drivers/staging/comedi/drivers/ni_pcidio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Comedi driver for National Instruments PCI-DIO-32HS
   4  *
   5  * COMEDI - Linux Control and Measurement Device Interface
   6  * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
   7  */
   8
   9 /*
  10  * Driver: ni_pcidio
  11  * Description: National Instruments PCI-DIO32HS, PCI-6533
  12  * Author: ds
  13  * Status: works
  14  * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
  15  *   [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
  16  *   [National Instruments] PCI-6534 (pci-6534)
  17  * Updated: Mon, 09 Jan 2012 14:27:23 +0000
  18  *
  19  * The DIO32HS board appears as one subdevice, with 32 channels. Each
  20  * channel is individually I/O configurable. The channel order is 0=A0,
  21  * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
  22  * digital I/O; no handshaking is supported.
  23  *
  24  * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
  25  *
  26  * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
  27  * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
  28  * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
  29  * trailing edge.
  30  *
  31  * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
  32  *
  33  * The PCI-6534 requires a firmware upload after power-up to work, the
  34  * firmware data and instructions for loading it with comedi_config
  35  * it are contained in the comedi_nonfree_firmware tarball available from
  36  * http://www.comedi.org
  37  */
  38
  39 #define USE_DMA
  40
  41 #include <linux/module.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/sched.h>
  45
  46 #include "../comedi_pci.h"
  47
  48 #include "mite.h"
  49
  50 /* defines for the PCI-DIO-32HS */
  51
  52 #define WINDOW_ADDRESS                  4       /* W */
  53 #define INTERRUPT_AND_WINDOW_STATUS     4       /* R */
  54 #define INT_STATUS_1                            BIT(0)
  55 #define INT_STATUS_2                            BIT(1)
  56 #define WINDOW_ADDRESS_STATUS_MASK              0x7c
  57
  58 #define MASTER_DMA_AND_INTERRUPT_CONTROL 5      /* W */
  59 #define INTERRUPT_LINE(x)                       ((x) & 3)
  60 #define OPEN_INT                                BIT(2)
  61 #define GROUP_STATUS                    5       /* R */
  62 #define DATA_LEFT                               BIT(0)
  63 #define REQ                                     BIT(2)
  64 #define STOP_TRIG                               BIT(3)
  65
  66 #define GROUP_1_FLAGS                   6       /* R */
  67 #define GROUP_2_FLAGS                   7       /* R */
  68 #define TRANSFER_READY                          BIT(0)
  69 #define COUNT_EXPIRED                           BIT(1)
  70 #define WAITED                                  BIT(5)
  71 #define PRIMARY_TC                              BIT(6)
  72 #define SECONDARY_TC                            BIT(7)
  73   /* #define SerialRose */
  74   /* #define ReqRose */
  75   /* #define Paused */
  76
  77 #define GROUP_1_FIRST_CLEAR             6       /* W */
  78 #define GROUP_2_FIRST_CLEAR             7       /* W */
  79 #define CLEAR_WAITED                            BIT(3)
  80 #define CLEAR_PRIMARY_TC                        BIT(4)
  81 #define CLEAR_SECONDARY_TC                      BIT(5)
  82 #define DMA_RESET                               BIT(6)
  83 #define FIFO_RESET                              BIT(7)
  84 #define CLEAR_ALL                               0xf8
  85
  86 #define GROUP_1_FIFO                    8       /* W */
  87 #define GROUP_2_FIFO                    12      /* W */
  88
  89 #define TRANSFER_COUNT                  20
  90 #define CHIP_ID_D                       24
  91 #define CHIP_ID_I                       25
  92 #define CHIP_ID_O                       26
  93 #define CHIP_VERSION                    27
  94 #define PORT_IO(x)                      (28 + (x))
  95 #define PORT_PIN_DIRECTIONS(x)          (32 + (x))
  96 #define PORT_PIN_MASK(x)                (36 + (x))
  97 #define PORT_PIN_POLARITIES(x)          (40 + (x))
  98
  99 #define MASTER_CLOCK_ROUTING            45
 100 #define RTSI_CLOCKING(x)                        (((x) & 3) << 4)
 101
 102 #define GROUP_1_SECOND_CLEAR            46      /* W */
 103 #define GROUP_2_SECOND_CLEAR            47      /* W */
 104 #define CLEAR_EXPIRED                           BIT(0)
 105
 106 #define PORT_PATTERN(x)                 (48 + (x))
 107
 108 #define DATA_PATH                       64
 109 #define FIFO_ENABLE_A           BIT(0)
 110 #define FIFO_ENABLE_B           BIT(1)
 111 #define FIFO_ENABLE_C           BIT(2)
 112 #define FIFO_ENABLE_D           BIT(3)
 113 #define FUNNELING(x)            (((x) & 3) << 4)
 114 #define GROUP_DIRECTION         BIT(7)
 115
 116 #define PROTOCOL_REGISTER_1             65
 117 #define OP_MODE                 PROTOCOL_REGISTER_1
 118 #define RUN_MODE(x)             ((x) & 7)
 119 #define NUMBERED                BIT(3)
 120
 121 #define PROTOCOL_REGISTER_2             66
 122 #define CLOCK_REG                       PROTOCOL_REGISTER_2
 123 #define CLOCK_LINE(x)           (((x) & 3) << 5)
 124 #define INVERT_STOP_TRIG                BIT(7)
 125 #define DATA_LATCHING(x)       (((x) & 3) << 5)
 126
 127 #define PROTOCOL_REGISTER_3             67
 128 #define SEQUENCE                        PROTOCOL_REGISTER_3
 129
 130 #define PROTOCOL_REGISTER_14            68      /* 16 bit */
 131 #define CLOCK_SPEED                     PROTOCOL_REGISTER_14
 132
 133 #define PROTOCOL_REGISTER_4             70
 134 #define REQ_REG                 PROTOCOL_REGISTER_4
 135 #define REQ_CONDITIONING(x)     (((x) & 7) << 3)
 136
 137 #define PROTOCOL_REGISTER_5             71
 138 #define BLOCK_MODE                      PROTOCOL_REGISTER_5
 139
 140 #define FIFO_Control                    72
 141 #define READY_LEVEL(x)          ((x) & 7)
 142
 143 #define PROTOCOL_REGISTER_6             73
 144 #define LINE_POLARITIES         PROTOCOL_REGISTER_6
 145 #define INVERT_ACK              BIT(0)
 146 #define INVERT_REQ              BIT(1)
 147 #define INVERT_CLOCK            BIT(2)
 148 #define INVERT_SERIAL           BIT(3)
 149 #define OPEN_ACK                BIT(4)
 150 #define OPEN_CLOCK              BIT(5)
 151
 152 #define PROTOCOL_REGISTER_7             74
 153 #define ACK_SER                 PROTOCOL_REGISTER_7
 154 #define ACK_LINE(x)             (((x) & 3) << 2)
 155 #define EXCHANGE_PINS           BIT(7)
 156
 157 #define INTERRUPT_CONTROL               75
 158 /* bits same as flags */
 159
 160 #define DMA_LINE_CONTROL_GROUP1         76
 161 #define DMA_LINE_CONTROL_GROUP2         108
 162
 163 /* channel zero is none */
 164 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
 165 {
 166         return channel & 0x3;
 167 }
 168
 169 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
 170 {
 171         return (channel << 2) & 0xc;
 172 }
 173
 174 #define TRANSFER_SIZE_CONTROL           77
 175 #define TRANSFER_WIDTH(x)       ((x) & 3)
 176 #define TRANSFER_LENGTH(x)      (((x) & 3) << 3)
 177 #define REQUIRE_R_LEVEL        BIT(5)
 178
 179 #define PROTOCOL_REGISTER_15            79
 180 #define DAQ_OPTIONS                     PROTOCOL_REGISTER_15
 181 #define START_SOURCE(x)                 ((x) & 0x3)
 182 #define INVERT_START                            BIT(2)
 183 #define STOP_SOURCE(x)                          (((x) & 0x3) << 3)
 184 #define REQ_START                               BIT(6)
 185 #define PRE_START                               BIT(7)
 186
 187 #define PATTERN_DETECTION               81
 188 #define DETECTION_METHOD                        BIT(0)
 189 #define INVERT_MATCH                            BIT(1)
 190 #define IE_PATTERN_DETECTION                    BIT(2)
 191
 192 #define PROTOCOL_REGISTER_9             82
 193 #define REQ_DELAY                       PROTOCOL_REGISTER_9
 194
 195 #define PROTOCOL_REGISTER_10            83
 196 #define REQ_NOT_DELAY                   PROTOCOL_REGISTER_10
 197
 198 #define PROTOCOL_REGISTER_11            84
 199 #define ACK_DELAY                       PROTOCOL_REGISTER_11
 200
 201 #define PROTOCOL_REGISTER_12            85
 202 #define ACK_NOT_DELAY                   PROTOCOL_REGISTER_12
 203
 204 #define PROTOCOL_REGISTER_13            86
 205 #define DATA_1_DELAY                    PROTOCOL_REGISTER_13
 206
 207 #define PROTOCOL_REGISTER_8             88      /* 32 bit */
 208 #define START_DELAY                     PROTOCOL_REGISTER_8
 209
 210 /* Firmware files for PCI-6524 */
 211 #define FW_PCI_6534_MAIN                "ni6534a.bin"
 212 #define FW_PCI_6534_SCARAB_DI           "niscrb01.bin"
 213 #define FW_PCI_6534_SCARAB_DO           "niscrb02.bin"
 214 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
 215 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
 216 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
 217
 218 enum pci_6534_firmware_registers {      /* 16 bit */
 219         Firmware_Control_Register = 0x100,
 220         Firmware_Status_Register = 0x104,
 221         Firmware_Data_Register = 0x108,
 222         Firmware_Mask_Register = 0x10c,
 223         Firmware_Debug_Register = 0x110,
 224 };
 225
 226 /* main fpga registers (32 bit)*/
 227 enum pci_6534_fpga_registers {
 228         FPGA_Control1_Register = 0x200,
 229         FPGA_Control2_Register = 0x204,
 230         FPGA_Irq_Mask_Register = 0x208,
 231         FPGA_Status_Register = 0x20c,
 232         FPGA_Signature_Register = 0x210,
 233         FPGA_SCALS_Counter_Register = 0x280,    /*write-clear */
 234         FPGA_SCAMS_Counter_Register = 0x284,    /*write-clear */
 235         FPGA_SCBLS_Counter_Register = 0x288,    /*write-clear */
 236         FPGA_SCBMS_Counter_Register = 0x28c,    /*write-clear */
 237         FPGA_Temp_Control_Register = 0x2a0,
 238         FPGA_DAR_Register = 0x2a8,
 239         FPGA_ELC_Read_Register = 0x2b8,
 240         FPGA_ELC_Write_Register = 0x2bc,
 241 };
 242
 243 enum FPGA_Control_Bits {
 244         FPGA_Enable_Bit = 0x8000,
 245 };
 246
 247 #define TIMER_BASE 50           /* nanoseconds */
 248
 249 #ifdef USE_DMA
 250 #define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC)
 251 #else
 252 #define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \
 253                 | PRIMARY_TC | SECONDARY_TC)
 254 #endif
 255
 256 enum nidio_boardid {
 257         BOARD_PCIDIO_32HS,
 258         BOARD_PXI6533,
 259         BOARD_PCI6534,
 260 };
 261
 262 struct nidio_board {
 263         const char *name;
 264         unsigned int uses_firmware:1;
 265         unsigned int dio_speed;
 266 };
 267
 268 static const struct nidio_board nidio_boards[] = {
 269         [BOARD_PCIDIO_32HS] = {
 270                 .name           = "pci-dio-32hs",
 271                 .dio_speed      = 50,
 272         },
 273         [BOARD_PXI6533] = {
 274                 .name           = "pxi-6533",
 275                 .dio_speed      = 50,
 276         },
 277         [BOARD_PCI6534] = {
 278                 .name           = "pci-6534",
 279                 .uses_firmware  = 1,
 280                 .dio_speed      = 50,
 281         },
 282 };
 283
 284 struct nidio96_private {
 285         struct mite *mite;
 286         int boardtype;
 287         int dio;
 288         unsigned short OP_MODEBits;
 289         struct mite_channel *di_mite_chan;
 290         struct mite_ring *di_mite_ring;
 291         spinlock_t mite_channel_lock;
 292 };
 293
 294 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
 295 {
 296         struct nidio96_private *devpriv = dev->private;
 297         unsigned long flags;
 298
 299         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 300         BUG_ON(devpriv->di_mite_chan);
 301         devpriv->di_mite_chan =
 302             mite_request_channel_in_range(devpriv->mite,
 303                                           devpriv->di_mite_ring, 1, 2);
 304         if (!devpriv->di_mite_chan) {
 305                 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 306                 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
 307                 return -EBUSY;
 308         }
 309         devpriv->di_mite_chan->dir = COMEDI_INPUT;
 310         writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
 311                secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
 312                dev->mmio + DMA_LINE_CONTROL_GROUP1);
 313         mmiowb();
 314         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 315         return 0;
 316 }
 317
 318 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
 319 {
 320         struct nidio96_private *devpriv = dev->private;
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 324         if (devpriv->di_mite_chan) {
 325                 mite_release_channel(devpriv->di_mite_chan);
 326                 devpriv->di_mite_chan = NULL;
 327                 writeb(primary_DMAChannel_bits(0) |
 328                        secondary_DMAChannel_bits(0),
 329                        dev->mmio + DMA_LINE_CONTROL_GROUP1);
 330                 mmiowb();
 331         }
 332         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 333 }
 334
 335 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
 336 {
 337         struct nidio96_private *devpriv = dev->private;
 338         int retval;
 339         unsigned long flags;
 340
 341         retval = ni_pcidio_request_di_mite_channel(dev);
 342         if (retval)
 343                 return retval;
 344
 345         /* write alloc the entire buffer */
 346         comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
 347
 348         spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
 349         if (devpriv->di_mite_chan) {
 350                 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
 351                 mite_dma_arm(devpriv->di_mite_chan);
 352         } else {
 353                 retval = -EIO;
 354         }
 355         spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
 356
 357         return retval;
 358 }
 359
 360 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
 361 {
 362         struct nidio96_private *devpriv = dev->private;
 363         unsigned long irq_flags;
 364         int count;
 365
 366         spin_lock_irqsave(&dev->spinlock, irq_flags);
 367         spin_lock(&devpriv->mite_channel_lock);
 368         if (devpriv->di_mite_chan)
 369                 mite_sync_dma(devpriv->di_mite_chan, s);
 370         spin_unlock(&devpriv->mite_channel_lock);
 371         count = comedi_buf_n_bytes_ready(s);
 372         spin_unlock_irqrestore(&dev->spinlock, irq_flags);
 373         return count;
 374 }
 375
 376 static irqreturn_t nidio_interrupt(int irq, void *d)
 377 {
 378         struct comedi_device *dev = d;
 379         struct nidio96_private *devpriv = dev->private;
 380         struct comedi_subdevice *s = dev->read_subdev;
 381         struct comedi_async *async = s->async;
 382         unsigned int auxdata;
 383         int flags;
 384         int status;
 385         int work = 0;
 386
 387         /* interrupcions parasites */
 388         if (!dev->attached) {
 389                 /* assume it's from another card */
 390                 return IRQ_NONE;
 391         }
 392
 393         /* Lock to avoid race with comedi_poll */
 394         spin_lock(&dev->spinlock);
 395
 396         status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
 397         flags = readb(dev->mmio + GROUP_1_FLAGS);
 398
 399         spin_lock(&devpriv->mite_channel_lock);
 400         if (devpriv->di_mite_chan) {
 401                 mite_ack_linkc(devpriv->di_mite_chan, s, false);
 402                 /* XXX need to byteswap sync'ed dma */
 403         }
 404         spin_unlock(&devpriv->mite_channel_lock);
 405
 406         while (status & DATA_LEFT) {
 407                 work++;
 408                 if (work > 20) {
 409                         dev_dbg(dev->class_dev, "too much work in interrupt\n");
 410                         writeb(0x00,
 411                                dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 412                         break;
 413                 }
 414
 415                 flags &= INT_EN;
 416
 417                 if (flags & TRANSFER_READY) {
 418                         while (flags & TRANSFER_READY) {
 419                                 work++;
 420                                 if (work > 100) {
 421                                         dev_dbg(dev->class_dev,
 422                                                 "too much work in interrupt\n");
 423                                         writeb(0x00, dev->mmio +
 424                                                MASTER_DMA_AND_INTERRUPT_CONTROL
 425                                               );
 426                                         goto out;
 427                                 }
 428                                 auxdata = readl(dev->mmio + GROUP_1_FIFO);
 429                                 comedi_buf_write_samples(s, &auxdata, 1);
 430                                 flags = readb(dev->mmio + GROUP_1_FLAGS);
 431                         }
 432                 }
 433
 434                 if (flags & COUNT_EXPIRED) {
 435                         writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
 436                         async->events |= COMEDI_CB_EOA;
 437
 438                         writeb(0x00, dev->mmio + OP_MODE);
 439                         break;
 440                 } else if (flags & WAITED) {
 441                         writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);
 442                         async->events |= COMEDI_CB_ERROR;
 443                         break;
 444                 } else if (flags & PRIMARY_TC) {
 445                         writeb(CLEAR_PRIMARY_TC,
 446                                dev->mmio + GROUP_1_FIRST_CLEAR);
 447                         async->events |= COMEDI_CB_EOA;
 448                 } else if (flags & SECONDARY_TC) {
 449                         writeb(CLEAR_SECONDARY_TC,
 450                                dev->mmio + GROUP_1_FIRST_CLEAR);
 451                         async->events |= COMEDI_CB_EOA;
 452                 }
 453
 454                 flags = readb(dev->mmio + GROUP_1_FLAGS);
 455                 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
 456         }
 457
 458 out:
 459         comedi_handle_events(dev, s);
 460 #if 0
 461         if (!tag)
 462                 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 463 #endif
 464
 465         spin_unlock(&dev->spinlock);
 466         return IRQ_HANDLED;
 467 }
 468
 469 static int ni_pcidio_insn_config(struct comedi_device *dev,
 470                                  struct comedi_subdevice *s,
 471                                  struct comedi_insn *insn,
 472                                  unsigned int *data)
 473 {
 474         int ret;
 475
 476         if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
 477                 const struct nidio_board *board = dev->board_ptr;
 478
 479                 /* we don't care about actual channels */
 480                 data[1] = board->dio_speed;
 481                 data[2] = 0;
 482                 return 0;
 483         }
 484
 485         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
 486         if (ret)
 487                 return ret;
 488
 489         writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
 490
 491         return insn->n;
 492 }
 493
 494 static int ni_pcidio_insn_bits(struct comedi_device *dev,
 495                                struct comedi_subdevice *s,
 496                                struct comedi_insn *insn,
 497                                unsigned int *data)
 498 {
 499         if (comedi_dio_update_state(s, data))
 500                 writel(s->state, dev->mmio + PORT_IO(0));
 501
 502         data[1] = readl(dev->mmio + PORT_IO(0));
 503
 504         return insn->n;
 505 }
 506
 507 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
 508 {
 509         int divider, base;
 510
 511         base = TIMER_BASE;
 512
 513         switch (flags & CMDF_ROUND_MASK) {
 514         case CMDF_ROUND_NEAREST:
 515         default:
 516                 divider = DIV_ROUND_CLOSEST(*nanosec, base);
 517                 break;
 518         case CMDF_ROUND_DOWN:
 519                 divider = (*nanosec) / base;
 520                 break;
 521         case CMDF_ROUND_UP:
 522                 divider = DIV_ROUND_UP(*nanosec, base);
 523                 break;
 524         }
 525
 526         *nanosec = base * divider;
 527         return divider;
 528 }
 529
 530 static int ni_pcidio_cmdtest(struct comedi_device *dev,
 531                              struct comedi_subdevice *s, struct comedi_cmd *cmd)
 532 {
 533         int err = 0;
 534         unsigned int arg;
 535
 536         /* Step 1 : check if triggers are trivially valid */
 537
 538         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
 539         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
 540                                         TRIG_TIMER | TRIG_EXT);
 541         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
 542         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 543         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
 544
 545         if (err)
 546                 return 1;
 547
 548         /* Step 2a : make sure trigger sources are unique */
 549
 550         err |= comedi_check_trigger_is_unique(cmd->start_src);
 551         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
 552         err |= comedi_check_trigger_is_unique(cmd->stop_src);
 553
 554         /* Step 2b : and mutually compatible */
 555
 556         if (err)
 557                 return 2;
 558
 559         /* Step 3: check if arguments are trivially valid */
 560
 561         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 562
 563 #define MAX_SPEED       (TIMER_BASE)    /* in nanoseconds */
 564
 565         if (cmd->scan_begin_src == TRIG_TIMER) {
 566                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
 567                                                     MAX_SPEED);
 568                 /* no minimum speed */
 569         } else {
 570                 /* TRIG_EXT */
 571                 /* should be level/edge, hi/lo specification here */
 572                 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
 573                         cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
 574                         err |= -EINVAL;
 575                 }
 576         }
 577
 578         err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 579         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 580                                            cmd->chanlist_len);
 581
 582         if (cmd->stop_src == TRIG_COUNT)
 583                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
 584         else    /* TRIG_NONE */
 585                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 586
 587         if (err)
 588                 return 3;
 589
 590         /* step 4: fix up any arguments */
 591
 592         if (cmd->scan_begin_src == TRIG_TIMER) {
 593                 arg = cmd->scan_begin_arg;
 594                 ni_pcidio_ns_to_timer(&arg, cmd->flags);
 595                 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
 596         }
 597
 598         if (err)
 599                 return 4;
 600
 601         return 0;
 602 }
 603
 604 static int ni_pcidio_inttrig(struct comedi_device *dev,
 605                              struct comedi_subdevice *s,
 606                              unsigned int trig_num)
 607 {
 608         struct nidio96_private *devpriv = dev->private;
 609         struct comedi_cmd *cmd = &s->async->cmd;
 610
 611         if (trig_num != cmd->start_arg)
 612                 return -EINVAL;
 613
 614         writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
 615         s->async->inttrig = NULL;
 616
 617         return 1;
 618 }
 619
 620 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
 621 {
 622         struct nidio96_private *devpriv = dev->private;
 623         struct comedi_cmd *cmd = &s->async->cmd;
 624
 625         /* XXX configure ports for input */
 626         writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
 627
 628         if (1) {
 629                 /* enable fifos A B C D */
 630                 writeb(0x0f, dev->mmio + DATA_PATH);
 631
 632                 /* set transfer width a 32 bits */
 633                 writeb(TRANSFER_WIDTH(0) | TRANSFER_LENGTH(0),
 634                        dev->mmio + TRANSFER_SIZE_CONTROL);
 635         } else {
 636                 writeb(0x03, dev->mmio + DATA_PATH);
 637                 writeb(TRANSFER_WIDTH(3) | TRANSFER_LENGTH(0),
 638                        dev->mmio + TRANSFER_SIZE_CONTROL);
 639         }
 640
 641         /* protocol configuration */
 642         if (cmd->scan_begin_src == TRIG_TIMER) {
 643                 /* page 4-5, "input with internal REQs" */
 644                 writeb(0, dev->mmio + OP_MODE);
 645                 writeb(0x00, dev->mmio + CLOCK_REG);
 646                 writeb(1, dev->mmio + SEQUENCE);
 647                 writeb(0x04, dev->mmio + REQ_REG);
 648                 writeb(4, dev->mmio + BLOCK_MODE);
 649                 writeb(3, dev->mmio + LINE_POLARITIES);
 650                 writeb(0xc0, dev->mmio + ACK_SER);
 651                 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
 652                                              CMDF_ROUND_NEAREST),
 653                        dev->mmio + START_DELAY);
 654                 writeb(1, dev->mmio + REQ_DELAY);
 655                 writeb(1, dev->mmio + REQ_NOT_DELAY);
 656                 writeb(1, dev->mmio + ACK_DELAY);
 657                 writeb(0x0b, dev->mmio + ACK_NOT_DELAY);
 658                 writeb(0x01, dev->mmio + DATA_1_DELAY);
 659                 /*
 660                  * manual, page 4-5:
 661                  * CLOCK_SPEED comment is incorrectly listed on DAQ_OPTIONS
 662                  */
 663                 writew(0, dev->mmio + CLOCK_SPEED);
 664                 writeb(0, dev->mmio + DAQ_OPTIONS);
 665         } else {
 666                 /* TRIG_EXT */
 667                 /* page 4-5, "input with external REQs" */
 668                 writeb(0, dev->mmio + OP_MODE);
 669                 writeb(0x00, dev->mmio + CLOCK_REG);
 670                 writeb(0, dev->mmio + SEQUENCE);
 671                 writeb(0x00, dev->mmio + REQ_REG);
 672                 writeb(4, dev->mmio + BLOCK_MODE);
 673                 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
 674                         writeb(0, dev->mmio + LINE_POLARITIES);
 675                 else                                    /* Trailing Edge */
 676                         writeb(2, dev->mmio + LINE_POLARITIES);
 677                 writeb(0x00, dev->mmio + ACK_SER);
 678                 writel(1, dev->mmio + START_DELAY);
 679                 writeb(1, dev->mmio + REQ_DELAY);
 680                 writeb(1, dev->mmio + REQ_NOT_DELAY);
 681                 writeb(1, dev->mmio + ACK_DELAY);
 682                 writeb(0x0C, dev->mmio + ACK_NOT_DELAY);
 683                 writeb(0x10, dev->mmio + DATA_1_DELAY);
 684                 writew(0, dev->mmio + CLOCK_SPEED);
 685                 writeb(0x60, dev->mmio + DAQ_OPTIONS);
 686         }
 687
 688         if (cmd->stop_src == TRIG_COUNT) {
 689                 writel(cmd->stop_arg,
 690                        dev->mmio + TRANSFER_COUNT);
 691         } else {
 692                 /* XXX */
 693         }
 694
 695 #ifdef USE_DMA
 696         writeb(CLEAR_PRIMARY_TC | CLEAR_SECONDARY_TC,
 697                dev->mmio + GROUP_1_FIRST_CLEAR);
 698
 699         {
 700                 int retval = setup_mite_dma(dev, s);
 701
 702                 if (retval)
 703                         return retval;
 704         }
 705 #else
 706         writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);
 707 #endif
 708         writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);
 709
 710         /* clear and enable interrupts */
 711         writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);
 712         /* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */
 713
 714         writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);
 715         writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 716
 717         if (cmd->stop_src == TRIG_NONE) {
 718                 devpriv->OP_MODEBits = DATA_LATCHING(0) | RUN_MODE(7);
 719         } else {                /* TRIG_TIMER */
 720                 devpriv->OP_MODEBits = NUMBERED | RUN_MODE(7);
 721         }
 722         if (cmd->start_src == TRIG_NOW) {
 723                 /* start */
 724                 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
 725                 s->async->inttrig = NULL;
 726         } else {
 727                 /* TRIG_INT */
 728                 s->async->inttrig = ni_pcidio_inttrig;
 729         }
 730
 731         return 0;
 732 }
 733
 734 static int ni_pcidio_cancel(struct comedi_device *dev,
 735                             struct comedi_subdevice *s)
 736 {
 737         writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 738         ni_pcidio_release_di_mite_channel(dev);
 739
 740         return 0;
 741 }
 742
 743 static int ni_pcidio_change(struct comedi_device *dev,
 744                             struct comedi_subdevice *s)
 745 {
 746         struct nidio96_private *devpriv = dev->private;
 747         int ret;
 748
 749         ret = mite_buf_change(devpriv->di_mite_ring, s);
 750         if (ret < 0)
 751                 return ret;
 752
 753         memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
 754
 755         return 0;
 756 }
 757
 758 static int pci_6534_load_fpga(struct comedi_device *dev,
 759                               const u8 *data, size_t data_len,
 760                               unsigned long context)
 761 {
 762         static const int timeout = 1000;
 763         int fpga_index = context;
 764         int i;
 765         size_t j;
 766
 767         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 768         writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
 769         for (i = 0;
 770              (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
 771              i < timeout; ++i) {
 772                 udelay(1);
 773         }
 774         if (i == timeout) {
 775                 dev_warn(dev->class_dev,
 776                          "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
 777                          fpga_index);
 778                 return -EIO;
 779         }
 780         writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
 781         for (i = 0;
 782              readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
 783              i < timeout; ++i) {
 784                 udelay(1);
 785         }
 786         if (i == timeout) {
 787                 dev_warn(dev->class_dev,
 788                          "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
 789                          fpga_index);
 790                 return -EIO;
 791         }
 792         for (j = 0; j + 1 < data_len;) {
 793                 unsigned int value = data[j++];
 794
 795                 value |= data[j++] << 8;
 796                 writew(value, dev->mmio + Firmware_Data_Register);
 797                 for (i = 0;
 798                      (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
 799                      && i < timeout; ++i) {
 800                         udelay(1);
 801                 }
 802                 if (i == timeout) {
 803                         dev_warn(dev->class_dev,
 804                                  "ni_pcidio: failed to load word into fpga %i\n",
 805                                  fpga_index);
 806                         return -EIO;
 807                 }
 808                 if (need_resched())
 809                         schedule();
 810         }
 811         writew(0x0, dev->mmio + Firmware_Control_Register);
 812         return 0;
 813 }
 814
 815 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
 816 {
 817         return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
 818 }
 819
 820 static int pci_6534_reset_fpgas(struct comedi_device *dev)
 821 {
 822         int ret;
 823         int i;
 824
 825         writew(0x0, dev->mmio + Firmware_Control_Register);
 826         for (i = 0; i < 3; ++i) {
 827                 ret = pci_6534_reset_fpga(dev, i);
 828                 if (ret < 0)
 829                         break;
 830         }
 831         writew(0x0, dev->mmio + Firmware_Mask_Register);
 832         return ret;
 833 }
 834
 835 static void pci_6534_init_main_fpga(struct comedi_device *dev)
 836 {
 837         writel(0, dev->mmio + FPGA_Control1_Register);
 838         writel(0, dev->mmio + FPGA_Control2_Register);
 839         writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
 840         writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
 841         writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
 842         writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
 843 }
 844
 845 static int pci_6534_upload_firmware(struct comedi_device *dev)
 846 {
 847         struct nidio96_private *devpriv = dev->private;
 848         static const char *const fw_file[3] = {
 849                 FW_PCI_6534_SCARAB_DI,  /* loaded into scarab A for DI */
 850                 FW_PCI_6534_SCARAB_DO,  /* loaded into scarab B for DO */
 851                 FW_PCI_6534_MAIN,       /* loaded into main FPGA */
 852         };
 853         int ret;
 854         int n;
 855
 856         ret = pci_6534_reset_fpgas(dev);
 857         if (ret < 0)
 858                 return ret;
 859         /* load main FPGA first, then the two scarabs */
 860         for (n = 2; n >= 0; n--) {
 861                 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
 862                                            fw_file[n],
 863                                            pci_6534_load_fpga, n);
 864                 if (ret == 0 && n == 2)
 865                         pci_6534_init_main_fpga(dev);
 866                 if (ret < 0)
 867                         break;
 868         }
 869         return ret;
 870 }
 871
 872 static void nidio_reset_board(struct comedi_device *dev)
 873 {
 874         writel(0, dev->mmio + PORT_IO(0));
 875         writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
 876         writel(0, dev->mmio + PORT_PIN_MASK(0));
 877
 878         /* disable interrupts on board */
 879         writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
 880 }
 881
 882 static int nidio_auto_attach(struct comedi_device *dev,
 883                              unsigned long context)
 884 {
 885         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 886         const struct nidio_board *board = NULL;
 887         struct nidio96_private *devpriv;
 888         struct comedi_subdevice *s;
 889         int ret;
 890         unsigned int irq;
 891
 892         if (context < ARRAY_SIZE(nidio_boards))
 893                 board = &nidio_boards[context];
 894         if (!board)
 895                 return -ENODEV;
 896         dev->board_ptr = board;
 897         dev->board_name = board->name;
 898
 899         ret = comedi_pci_enable(dev);
 900         if (ret)
 901                 return ret;
 902
 903         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 904         if (!devpriv)
 905                 return -ENOMEM;
 906
 907         spin_lock_init(&devpriv->mite_channel_lock);
 908
 909         devpriv->mite = mite_attach(dev, false);        /* use win0 */
 910         if (!devpriv->mite)
 911                 return -ENOMEM;
 912
 913         devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
 914         if (!devpriv->di_mite_ring)
 915                 return -ENOMEM;
 916
 917         if (board->uses_firmware) {
 918                 ret = pci_6534_upload_firmware(dev);
 919                 if (ret < 0)
 920                         return ret;
 921         }
 922
 923         nidio_reset_board(dev);
 924
 925         ret = comedi_alloc_subdevices(dev, 1);
 926         if (ret)
 927                 return ret;
 928
 929         dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
 930                  readb(dev->mmio + CHIP_VERSION));
 931
 932         s = &dev->subdevices[0];
 933
 934         dev->read_subdev = s;
 935         s->type = COMEDI_SUBD_DIO;
 936         s->subdev_flags =
 937                 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
 938                 SDF_CMD_READ;
 939         s->n_chan = 32;
 940         s->range_table = &range_digital;
 941         s->maxdata = 1;
 942         s->insn_config = &ni_pcidio_insn_config;
 943         s->insn_bits = &ni_pcidio_insn_bits;
 944         s->do_cmd = &ni_pcidio_cmd;
 945         s->do_cmdtest = &ni_pcidio_cmdtest;
 946         s->cancel = &ni_pcidio_cancel;
 947         s->len_chanlist = 32;   /* XXX */
 948         s->buf_change = &ni_pcidio_change;
 949         s->async_dma_dir = DMA_BIDIRECTIONAL;
 950         s->poll = &ni_pcidio_poll;
 951
 952         irq = pcidev->irq;
 953         if (irq) {
 954                 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
 955                                   dev->board_name, dev);
 956                 if (ret == 0)
 957                         dev->irq = irq;
 958         }
 959
 960         return 0;
 961 }
 962
 963 static void nidio_detach(struct comedi_device *dev)
 964 {
 965         struct nidio96_private *devpriv = dev->private;
 966
 967         if (dev->irq)
 968                 free_irq(dev->irq, dev);
 969         if (devpriv) {
 970                 if (devpriv->di_mite_ring) {
 971                         mite_free_ring(devpriv->di_mite_ring);
 972                         devpriv->di_mite_ring = NULL;
 973                 }
 974                 mite_detach(devpriv->mite);
 975         }
 976         if (dev->mmio)
 977                 iounmap(dev->mmio);
 978         comedi_pci_disable(dev);
 979 }
 980
 981 static struct comedi_driver ni_pcidio_driver = {
 982         .driver_name    = "ni_pcidio",
 983         .module         = THIS_MODULE,
 984         .auto_attach    = nidio_auto_attach,
 985         .detach         = nidio_detach,
 986 };
 987
 988 static int ni_pcidio_pci_probe(struct pci_dev *dev,
 989                                const struct pci_device_id *id)
 990 {
 991         return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
 992 }
 993
 994 static const struct pci_device_id ni_pcidio_pci_table[] = {
 995         { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
 996         { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
 997         { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
 998         { 0 }
 999 };
1000 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
1001
1002 static struct pci_driver ni_pcidio_pci_driver = {
1003         .name           = "ni_pcidio",
1004         .id_table       = ni_pcidio_pci_table,
1005         .probe          = ni_pcidio_pci_probe,
1006         .remove         = comedi_pci_auto_unconfig,
1007 };
1008 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1009
1010 MODULE_AUTHOR("Comedi http://www.comedi.org");
1011 MODULE_DESCRIPTION("Comedi low-level driver");
1012 MODULE_LICENSE("GPL");