drivers/staging/comedi/drivers/ni_tio.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Support for NI general purpose counters
   4  *
   5  * Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
   6  */
   7
   8 /*
   9  * Module: ni_tio
  10  * Description: National Instruments general purpose counters
  11  * Author: J.P. Mellor <jpmellor@rose-hulman.edu>,
  12  *         Herman.Bruyninckx@mech.kuleuven.ac.be,
  13  *         Wim.Meeussen@mech.kuleuven.ac.be,
  14  *         Klaas.Gadeyne@mech.kuleuven.ac.be,
  15  *         Frank Mori Hess <fmhess@users.sourceforge.net>
  16  * Updated: Thu Nov 16 09:50:32 EST 2006
  17  * Status: works
  18  *
  19  * This module is not used directly by end-users.  Rather, it
  20  * is used by other drivers (for example ni_660x and ni_pcimio)
  21  * to provide support for NI's general purpose counters.  It was
  22  * originally based on the counter code from ni_660x.c and
  23  * ni_mio_common.c.
  24  *
  25  * References:
  26  * DAQ 660x Register-Level Programmer Manual  (NI 370505A-01)
  27  * DAQ 6601/6602 User Manual (NI 322137B-01)
  28  * 340934b.pdf  DAQ-STC reference manual
  29  *
  30  * TODO: Support use of both banks X and Y
  31  */
  32
  33 #include <linux/module.h>
  34 #include <linux/slab.h>
  35
  36 #include "ni_tio_internal.h"
  37
  38 /*
  39  * clock sources for ni e and m series boards,
  40  * get bits with GI_SRC_SEL()
  41  */
  42 #define NI_M_TIMEBASE_1_CLK             0x0     /* 20MHz */
  43 #define NI_M_PFI_CLK(x)                 (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  44 #define NI_M_RTSI_CLK(x)                (((x) == 7) ? 0x1b : (0xb + (x)))
  45 #define NI_M_TIMEBASE_2_CLK             0x12    /* 100KHz */
  46 #define NI_M_NEXT_TC_CLK                0x13
  47 #define NI_M_NEXT_GATE_CLK              0x14    /* Gi_Src_SubSelect=0 */
  48 #define NI_M_PXI_STAR_TRIGGER_CLK       0x14    /* Gi_Src_SubSelect=1 */
  49 #define NI_M_PXI10_CLK                  0x1d
  50 #define NI_M_TIMEBASE_3_CLK             0x1e    /* 80MHz, Gi_Src_SubSelect=0 */
  51 #define NI_M_ANALOG_TRIGGER_OUT_CLK     0x1e    /* Gi_Src_SubSelect=1 */
  52 #define NI_M_LOGIC_LOW_CLK              0x1f
  53 #define NI_M_MAX_PFI_CHAN               15
  54 #define NI_M_MAX_RTSI_CHAN              7
  55
  56 /*
  57  * clock sources for ni_660x boards,
  58  * get bits with GI_SRC_SEL()
  59  */
  60 #define NI_660X_TIMEBASE_1_CLK          0x0     /* 20MHz */
  61 #define NI_660X_SRC_PIN_I_CLK           0x1
  62 #define NI_660X_SRC_PIN_CLK(x)          (0x2 + (x))
  63 #define NI_660X_NEXT_GATE_CLK           0xa
  64 #define NI_660X_RTSI_CLK(x)             (0xb + (x))
  65 #define NI_660X_TIMEBASE_2_CLK          0x12    /* 100KHz */
  66 #define NI_660X_NEXT_TC_CLK             0x13
  67 #define NI_660X_TIMEBASE_3_CLK          0x1e    /* 80MHz */
  68 #define NI_660X_LOGIC_LOW_CLK           0x1f
  69 #define NI_660X_MAX_SRC_PIN             7
  70 #define NI_660X_MAX_RTSI_CHAN           6
  71
  72 /* ni m series gate_select */
  73 #define NI_M_TIMESTAMP_MUX_GATE_SEL     0x0
  74 #define NI_M_PFI_GATE_SEL(x)            (((x) < 10) ? (1 + (x)) : (0xb + (x)))
  75 #define NI_M_RTSI_GATE_SEL(x)           (((x) == 7) ? 0x1b : (0xb + (x)))
  76 #define NI_M_AI_START2_GATE_SEL         0x12
  77 #define NI_M_PXI_STAR_TRIGGER_GATE_SEL  0x13
  78 #define NI_M_NEXT_OUT_GATE_SEL          0x14
  79 #define NI_M_AI_START1_GATE_SEL         0x1c
  80 #define NI_M_NEXT_SRC_GATE_SEL          0x1d
  81 #define NI_M_ANALOG_TRIG_OUT_GATE_SEL   0x1e
  82 #define NI_M_LOGIC_LOW_GATE_SEL         0x1f
  83
  84 /* ni_660x gate select */
  85 #define NI_660X_SRC_PIN_I_GATE_SEL      0x0
  86 #define NI_660X_GATE_PIN_I_GATE_SEL     0x1
  87 #define NI_660X_PIN_GATE_SEL(x)         (0x2 + (x))
  88 #define NI_660X_NEXT_SRC_GATE_SEL       0xa
  89 #define NI_660X_RTSI_GATE_SEL(x)        (0xb + (x))
  90 #define NI_660X_NEXT_OUT_GATE_SEL       0x14
  91 #define NI_660X_LOGIC_LOW_GATE_SEL      0x1f
  92 #define NI_660X_MAX_GATE_PIN            7
  93
  94 /* ni_660x second gate select */
  95 #define NI_660X_SRC_PIN_I_GATE2_SEL     0x0
  96 #define NI_660X_UD_PIN_I_GATE2_SEL      0x1
  97 #define NI_660X_UD_PIN_GATE2_SEL(x)     (0x2 + (x))
  98 #define NI_660X_NEXT_SRC_GATE2_SEL      0xa
  99 #define NI_660X_RTSI_GATE2_SEL(x)       (0xb + (x))
 100 #define NI_660X_NEXT_OUT_GATE2_SEL      0x14
 101 #define NI_660X_SELECTED_GATE2_SEL      0x1e
 102 #define NI_660X_LOGIC_LOW_GATE2_SEL     0x1f
 103 #define NI_660X_MAX_UP_DOWN_PIN         7
 104
 105 static inline unsigned int GI_PRESCALE_X2(enum ni_gpct_variant variant)
 106 {
 107         switch (variant) {
 108         case ni_gpct_variant_e_series:
 109         default:
 110                 return 0;
 111         case ni_gpct_variant_m_series:
 112                 return GI_M_PRESCALE_X2;
 113         case ni_gpct_variant_660x:
 114                 return GI_660X_PRESCALE_X2;
 115         }
 116 }
 117
 118 static inline unsigned int GI_PRESCALE_X8(enum ni_gpct_variant variant)
 119 {
 120         switch (variant) {
 121         case ni_gpct_variant_e_series:
 122         default:
 123                 return 0;
 124         case ni_gpct_variant_m_series:
 125                 return GI_M_PRESCALE_X8;
 126         case ni_gpct_variant_660x:
 127                 return GI_660X_PRESCALE_X8;
 128         }
 129 }
 130
 131 static bool ni_tio_has_gate2_registers(const struct ni_gpct_device *counter_dev)
 132 {
 133         switch (counter_dev->variant) {
 134         case ni_gpct_variant_e_series:
 135         default:
 136                 return false;
 137         case ni_gpct_variant_m_series:
 138         case ni_gpct_variant_660x:
 139                 return true;
 140         }
 141 }
 142
 143 /**
 144  * ni_tio_write() - Write a TIO register using the driver provided callback.
 145  * @counter: struct ni_gpct counter.
 146  * @value: the value to write
 147  * @reg: the register to write.
 148  */
 149 void ni_tio_write(struct ni_gpct *counter, unsigned int value,
 150                   enum ni_gpct_register reg)
 151 {
 152         if (reg < NITIO_NUM_REGS)
 153                 counter->counter_dev->write(counter, value, reg);
 154 }
 155 EXPORT_SYMBOL_GPL(ni_tio_write);
 156
 157 /**
 158  * ni_tio_read() - Read a TIO register using the driver provided callback.
 159  * @counter: struct ni_gpct counter.
 160  * @reg: the register to read.
 161  */
 162 unsigned int ni_tio_read(struct ni_gpct *counter, enum ni_gpct_register reg)
 163 {
 164         if (reg < NITIO_NUM_REGS)
 165                 return counter->counter_dev->read(counter, reg);
 166         return 0;
 167 }
 168 EXPORT_SYMBOL_GPL(ni_tio_read);
 169
 170 static void ni_tio_reset_count_and_disarm(struct ni_gpct *counter)
 171 {
 172         unsigned int cidx = counter->counter_index;
 173
 174         ni_tio_write(counter, GI_RESET(cidx), NITIO_RESET_REG(cidx));
 175 }
 176
 177 static int ni_tio_clock_period_ps(const struct ni_gpct *counter,
 178                                   unsigned int generic_clock_source,
 179                                   u64 *period_ps)
 180 {
 181         u64 clock_period_ps;
 182
 183         switch (generic_clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 184         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 185                 clock_period_ps = 50000;
 186                 break;
 187         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 188                 clock_period_ps = 10000000;
 189                 break;
 190         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 191                 clock_period_ps = 12500;
 192                 break;
 193         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 194                 clock_period_ps = 100000;
 195                 break;
 196         default:
 197                 /*
 198                  * clock period is specified by user with prescaling
 199                  * already taken into account.
 200                  */
 201                 *period_ps = counter->clock_period_ps;
 202                 return 0;
 203         }
 204
 205         switch (generic_clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 206         case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 207                 break;
 208         case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 209                 clock_period_ps *= 2;
 210                 break;
 211         case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 212                 clock_period_ps *= 8;
 213                 break;
 214         default:
 215                 return -EINVAL;
 216         }
 217         *period_ps = clock_period_ps;
 218         return 0;
 219 }
 220
 221 static void ni_tio_set_bits_transient(struct ni_gpct *counter,
 222                                       enum ni_gpct_register reg,
 223                                       unsigned int mask, unsigned int value,
 224                                       unsigned int transient)
 225 {
 226         struct ni_gpct_device *counter_dev = counter->counter_dev;
 227         unsigned int chip = counter->chip_index;
 228         unsigned long flags;
 229
 230         if (reg < NITIO_NUM_REGS && chip < counter_dev->num_chips) {
 231                 unsigned int *regs = counter_dev->regs[chip];
 232
 233                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 234                 regs[reg] &= ~mask;
 235                 regs[reg] |= (value & mask);
 236                 ni_tio_write(counter, regs[reg] | transient, reg);
 237                 mmiowb();
 238                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 239         }
 240 }
 241
 242 /**
 243  * ni_tio_set_bits() - Safely write a counter register.
 244  * @counter: struct ni_gpct counter.
 245  * @reg: the register to write.
 246  * @mask: the bits to change.
 247  * @value: the new bits value.
 248  *
 249  * Used to write to, and update the software copy, a register whose bits may
 250  * be twiddled in interrupt context, or whose software copy may be read in
 251  * interrupt context.
 252  */
 253 void ni_tio_set_bits(struct ni_gpct *counter, enum ni_gpct_register reg,
 254                      unsigned int mask, unsigned int value)
 255 {
 256         ni_tio_set_bits_transient(counter, reg, mask, value, 0x0);
 257 }
 258 EXPORT_SYMBOL_GPL(ni_tio_set_bits);
 259
 260 /**
 261  * ni_tio_get_soft_copy() - Safely read the software copy of a counter register.
 262  * @counter: struct ni_gpct counter.
 263  * @reg: the register to read.
 264  *
 265  * Used to get the software copy of a register whose bits might be modified
 266  * in interrupt context, or whose software copy might need to be read in
 267  * interrupt context.
 268  */
 269 unsigned int ni_tio_get_soft_copy(const struct ni_gpct *counter,
 270                                   enum ni_gpct_register reg)
 271 {
 272         struct ni_gpct_device *counter_dev = counter->counter_dev;
 273         unsigned int chip = counter->chip_index;
 274         unsigned int value = 0;
 275         unsigned long flags;
 276
 277         if (reg < NITIO_NUM_REGS && chip < counter_dev->num_chips) {
 278                 spin_lock_irqsave(&counter_dev->regs_lock, flags);
 279                 value = counter_dev->regs[chip][reg];
 280                 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
 281         }
 282         return value;
 283 }
 284 EXPORT_SYMBOL_GPL(ni_tio_get_soft_copy);
 285
 286 static unsigned int ni_tio_clock_src_modifiers(const struct ni_gpct *counter)
 287 {
 288         struct ni_gpct_device *counter_dev = counter->counter_dev;
 289         unsigned int cidx = counter->counter_index;
 290         unsigned int counting_mode_bits =
 291                 ni_tio_get_soft_copy(counter, NITIO_CNT_MODE_REG(cidx));
 292         unsigned int bits = 0;
 293
 294         if (ni_tio_get_soft_copy(counter, NITIO_INPUT_SEL_REG(cidx)) &
 295             GI_SRC_POL_INVERT)
 296                 bits |= NI_GPCT_INVERT_CLOCK_SRC_BIT;
 297         if (counting_mode_bits & GI_PRESCALE_X2(counter_dev->variant))
 298                 bits |= NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS;
 299         if (counting_mode_bits & GI_PRESCALE_X8(counter_dev->variant))
 300                 bits |= NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS;
 301         return bits;
 302 }
 303
 304 static int ni_m_series_clock_src_select(const struct ni_gpct *counter,
 305                                         unsigned int *clk_src)
 306 {
 307         struct ni_gpct_device *counter_dev = counter->counter_dev;
 308         unsigned int cidx = counter->counter_index;
 309         unsigned int chip = counter->chip_index;
 310         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 311         unsigned int clock_source = 0;
 312         unsigned int src;
 313         unsigned int i;
 314
 315         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 316                                                   NITIO_INPUT_SEL_REG(cidx)));
 317
 318         switch (src) {
 319         case NI_M_TIMEBASE_1_CLK:
 320                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 321                 break;
 322         case NI_M_TIMEBASE_2_CLK:
 323                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 324                 break;
 325         case NI_M_TIMEBASE_3_CLK:
 326                 if (counter_dev->regs[chip][second_gate_reg] & GI_SRC_SUBSEL)
 327                         clock_source =
 328                             NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS;
 329                 else
 330                         clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 331                 break;
 332         case NI_M_LOGIC_LOW_CLK:
 333                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 334                 break;
 335         case NI_M_NEXT_GATE_CLK:
 336                 if (counter_dev->regs[chip][second_gate_reg] & GI_SRC_SUBSEL)
 337                         clock_source = NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS;
 338                 else
 339                         clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 340                 break;
 341         case NI_M_PXI10_CLK:
 342                 clock_source = NI_GPCT_PXI10_CLOCK_SRC_BITS;
 343                 break;
 344         case NI_M_NEXT_TC_CLK:
 345                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 346                 break;
 347         default:
 348                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 349                         if (src == NI_M_RTSI_CLK(i)) {
 350                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 351                                 break;
 352                         }
 353                 }
 354                 if (i <= NI_M_MAX_RTSI_CHAN)
 355                         break;
 356                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 357                         if (src == NI_M_PFI_CLK(i)) {
 358                                 clock_source = NI_GPCT_PFI_CLOCK_SRC_BITS(i);
 359                                 break;
 360                         }
 361                 }
 362                 if (i <= NI_M_MAX_PFI_CHAN)
 363                         break;
 364                 return -EINVAL;
 365         }
 366         clock_source |= ni_tio_clock_src_modifiers(counter);
 367         *clk_src = clock_source;
 368         return 0;
 369 }
 370
 371 static int ni_660x_clock_src_select(const struct ni_gpct *counter,
 372                                     unsigned int *clk_src)
 373 {
 374         unsigned int clock_source = 0;
 375         unsigned int cidx = counter->counter_index;
 376         unsigned int src;
 377         unsigned int i;
 378
 379         src = GI_BITS_TO_SRC(ni_tio_get_soft_copy(counter,
 380                                                   NITIO_INPUT_SEL_REG(cidx)));
 381
 382         switch (src) {
 383         case NI_660X_TIMEBASE_1_CLK:
 384                 clock_source = NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS;
 385                 break;
 386         case NI_660X_TIMEBASE_2_CLK:
 387                 clock_source = NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS;
 388                 break;
 389         case NI_660X_TIMEBASE_3_CLK:
 390                 clock_source = NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS;
 391                 break;
 392         case NI_660X_LOGIC_LOW_CLK:
 393                 clock_source = NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS;
 394                 break;
 395         case NI_660X_SRC_PIN_I_CLK:
 396                 clock_source = NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS;
 397                 break;
 398         case NI_660X_NEXT_GATE_CLK:
 399                 clock_source = NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS;
 400                 break;
 401         case NI_660X_NEXT_TC_CLK:
 402                 clock_source = NI_GPCT_NEXT_TC_CLOCK_SRC_BITS;
 403                 break;
 404         default:
 405                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 406                         if (src == NI_660X_RTSI_CLK(i)) {
 407                                 clock_source = NI_GPCT_RTSI_CLOCK_SRC_BITS(i);
 408                                 break;
 409                         }
 410                 }
 411                 if (i <= NI_660X_MAX_RTSI_CHAN)
 412                         break;
 413                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 414                         if (src == NI_660X_SRC_PIN_CLK(i)) {
 415                                 clock_source =
 416                                     NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i);
 417                                 break;
 418                         }
 419                 }
 420                 if (i <= NI_660X_MAX_SRC_PIN)
 421                         break;
 422                 return -EINVAL;
 423         }
 424         clock_source |= ni_tio_clock_src_modifiers(counter);
 425         *clk_src = clock_source;
 426         return 0;
 427 }
 428
 429 static int ni_tio_generic_clock_src_select(const struct ni_gpct *counter,
 430                                            unsigned int *clk_src)
 431 {
 432         switch (counter->counter_dev->variant) {
 433         case ni_gpct_variant_e_series:
 434         case ni_gpct_variant_m_series:
 435         default:
 436                 return ni_m_series_clock_src_select(counter, clk_src);
 437         case ni_gpct_variant_660x:
 438                 return ni_660x_clock_src_select(counter, clk_src);
 439         }
 440 }
 441
 442 static void ni_tio_set_sync_mode(struct ni_gpct *counter)
 443 {
 444         struct ni_gpct_device *counter_dev = counter->counter_dev;
 445         unsigned int cidx = counter->counter_index;
 446         static const u64 min_normal_sync_period_ps = 25000;
 447         unsigned int mask = 0;
 448         unsigned int bits = 0;
 449         unsigned int reg;
 450         unsigned int mode;
 451         unsigned int clk_src = 0;
 452         u64 ps = 0;
 453         int ret;
 454         bool force_alt_sync;
 455
 456         /* only m series and 660x variants have counting mode registers */
 457         switch (counter_dev->variant) {
 458         case ni_gpct_variant_e_series:
 459         default:
 460                 return;
 461         case ni_gpct_variant_m_series:
 462                 mask = GI_M_ALT_SYNC;
 463                 break;
 464         case ni_gpct_variant_660x:
 465                 mask = GI_660X_ALT_SYNC;
 466                 break;
 467         }
 468
 469         reg = NITIO_CNT_MODE_REG(cidx);
 470         mode = ni_tio_get_soft_copy(counter, reg);
 471         switch (mode & GI_CNT_MODE_MASK) {
 472         case GI_CNT_MODE_QUADX1:
 473         case GI_CNT_MODE_QUADX2:
 474         case GI_CNT_MODE_QUADX4:
 475         case GI_CNT_MODE_SYNC_SRC:
 476                 force_alt_sync = true;
 477                 break;
 478         default:
 479                 force_alt_sync = false;
 480                 break;
 481         }
 482
 483         ret = ni_tio_generic_clock_src_select(counter, &clk_src);
 484         if (ret)
 485                 return;
 486         ret = ni_tio_clock_period_ps(counter, clk_src, &ps);
 487         if (ret)
 488                 return;
 489         /*
 490          * It's not clear what we should do if clock_period is unknown, so we
 491          * are not using the alt sync bit in that case.
 492          */
 493         if (force_alt_sync || (ps && ps < min_normal_sync_period_ps))
 494                 bits = mask;
 495
 496         ni_tio_set_bits(counter, reg, mask, bits);
 497 }
 498
 499 static int ni_tio_set_counter_mode(struct ni_gpct *counter, unsigned int mode)
 500 {
 501         struct ni_gpct_device *counter_dev = counter->counter_dev;
 502         unsigned int cidx = counter->counter_index;
 503         unsigned int mode_reg_mask;
 504         unsigned int mode_reg_values;
 505         unsigned int input_select_bits = 0;
 506         /* these bits map directly on to the mode register */
 507         static const unsigned int mode_reg_direct_mask =
 508             NI_GPCT_GATE_ON_BOTH_EDGES_BIT | NI_GPCT_EDGE_GATE_MODE_MASK |
 509             NI_GPCT_STOP_MODE_MASK | NI_GPCT_OUTPUT_MODE_MASK |
 510             NI_GPCT_HARDWARE_DISARM_MASK | NI_GPCT_LOADING_ON_TC_BIT |
 511             NI_GPCT_LOADING_ON_GATE_BIT | NI_GPCT_LOAD_B_SELECT_BIT;
 512
 513         mode_reg_mask = mode_reg_direct_mask | GI_RELOAD_SRC_SWITCHING;
 514         mode_reg_values = mode & mode_reg_direct_mask;
 515         switch (mode & NI_GPCT_RELOAD_SOURCE_MASK) {
 516         case NI_GPCT_RELOAD_SOURCE_FIXED_BITS:
 517                 break;
 518         case NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS:
 519                 mode_reg_values |= GI_RELOAD_SRC_SWITCHING;
 520                 break;
 521         case NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS:
 522                 input_select_bits |= GI_GATE_SEL_LOAD_SRC;
 523                 mode_reg_mask |= GI_GATING_MODE_MASK;
 524                 mode_reg_values |= GI_LEVEL_GATING;
 525                 break;
 526         default:
 527                 break;
 528         }
 529         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx),
 530                         mode_reg_mask, mode_reg_values);
 531
 532         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 533                 unsigned int bits = 0;
 534
 535                 bits |= GI_CNT_MODE(mode >> NI_GPCT_COUNTING_MODE_SHIFT);
 536                 bits |= GI_INDEX_PHASE((mode >> NI_GPCT_INDEX_PHASE_BITSHIFT));
 537                 if (mode & NI_GPCT_INDEX_ENABLE_BIT)
 538                         bits |= GI_INDEX_MODE;
 539                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 540                                 GI_CNT_MODE_MASK | GI_INDEX_PHASE_MASK |
 541                                 GI_INDEX_MODE, bits);
 542                 ni_tio_set_sync_mode(counter);
 543         }
 544
 545         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_CNT_DIR_MASK,
 546                         GI_CNT_DIR(mode >> NI_GPCT_COUNTING_DIRECTION_SHIFT));
 547
 548         if (mode & NI_GPCT_OR_GATE_BIT)
 549                 input_select_bits |= GI_OR_GATE;
 550         if (mode & NI_GPCT_INVERT_OUTPUT_BIT)
 551                 input_select_bits |= GI_OUTPUT_POL_INVERT;
 552         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 553                         GI_GATE_SEL_LOAD_SRC | GI_OR_GATE |
 554                         GI_OUTPUT_POL_INVERT, input_select_bits);
 555
 556         return 0;
 557 }
 558
 559 int ni_tio_arm(struct ni_gpct *counter, bool arm, unsigned int start_trigger)
 560 {
 561         struct ni_gpct_device *counter_dev = counter->counter_dev;
 562         unsigned int cidx = counter->counter_index;
 563         unsigned int transient_bits = 0;
 564
 565         if (arm) {
 566                 unsigned int mask = 0;
 567                 unsigned int bits = 0;
 568
 569                 /* only m series and 660x have counting mode registers */
 570                 switch (counter_dev->variant) {
 571                 case ni_gpct_variant_e_series:
 572                 default:
 573                         break;
 574                 case ni_gpct_variant_m_series:
 575                         mask = GI_M_HW_ARM_SEL_MASK;
 576                         break;
 577                 case ni_gpct_variant_660x:
 578                         mask = GI_660X_HW_ARM_SEL_MASK;
 579                         break;
 580                 }
 581
 582                 switch (start_trigger) {
 583                 case NI_GPCT_ARM_IMMEDIATE:
 584                         transient_bits |= GI_ARM;
 585                         break;
 586                 case NI_GPCT_ARM_PAIRED_IMMEDIATE:
 587                         transient_bits |= GI_ARM | GI_ARM_COPY;
 588                         break;
 589                 default:
 590                         /*
 591                          * for m series and 660x, pass-through the least
 592                          * significant bits so we can figure out what select
 593                          * later
 594                          */
 595                         if (mask && (start_trigger & NI_GPCT_ARM_UNKNOWN)) {
 596                                 bits |= GI_HW_ARM_ENA |
 597                                         (GI_HW_ARM_SEL(start_trigger) & mask);
 598                         } else {
 599                                 return -EINVAL;
 600                         }
 601                         break;
 602                 }
 603
 604                 if (mask)
 605                         ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 606                                         GI_HW_ARM_ENA | mask, bits);
 607         } else {
 608                 transient_bits |= GI_DISARM;
 609         }
 610         ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
 611                                   0, 0, transient_bits);
 612         return 0;
 613 }
 614 EXPORT_SYMBOL_GPL(ni_tio_arm);
 615
 616 static int ni_660x_clk_src(unsigned int clock_source, unsigned int *bits)
 617 {
 618         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 619         unsigned int ni_660x_clock;
 620         unsigned int i;
 621
 622         switch (clk_src) {
 623         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 624                 ni_660x_clock = NI_660X_TIMEBASE_1_CLK;
 625                 break;
 626         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 627                 ni_660x_clock = NI_660X_TIMEBASE_2_CLK;
 628                 break;
 629         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 630                 ni_660x_clock = NI_660X_TIMEBASE_3_CLK;
 631                 break;
 632         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 633                 ni_660x_clock = NI_660X_LOGIC_LOW_CLK;
 634                 break;
 635         case NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS:
 636                 ni_660x_clock = NI_660X_SRC_PIN_I_CLK;
 637                 break;
 638         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 639                 ni_660x_clock = NI_660X_NEXT_GATE_CLK;
 640                 break;
 641         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 642                 ni_660x_clock = NI_660X_NEXT_TC_CLK;
 643                 break;
 644         default:
 645                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 646                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 647                                 ni_660x_clock = NI_660X_RTSI_CLK(i);
 648                                 break;
 649                         }
 650                 }
 651                 if (i <= NI_660X_MAX_RTSI_CHAN)
 652                         break;
 653                 for (i = 0; i <= NI_660X_MAX_SRC_PIN; ++i) {
 654                         if (clk_src == NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(i)) {
 655                                 ni_660x_clock = NI_660X_SRC_PIN_CLK(i);
 656                                 break;
 657                         }
 658                 }
 659                 if (i <= NI_660X_MAX_SRC_PIN)
 660                         break;
 661                 return -EINVAL;
 662         }
 663         *bits = GI_SRC_SEL(ni_660x_clock);
 664         return 0;
 665 }
 666
 667 static int ni_m_clk_src(unsigned int clock_source, unsigned int *bits)
 668 {
 669         unsigned int clk_src = clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK;
 670         unsigned int ni_m_series_clock;
 671         unsigned int i;
 672
 673         switch (clk_src) {
 674         case NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS:
 675                 ni_m_series_clock = NI_M_TIMEBASE_1_CLK;
 676                 break;
 677         case NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS:
 678                 ni_m_series_clock = NI_M_TIMEBASE_2_CLK;
 679                 break;
 680         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 681                 ni_m_series_clock = NI_M_TIMEBASE_3_CLK;
 682                 break;
 683         case NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS:
 684                 ni_m_series_clock = NI_M_LOGIC_LOW_CLK;
 685                 break;
 686         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 687                 ni_m_series_clock = NI_M_NEXT_GATE_CLK;
 688                 break;
 689         case NI_GPCT_NEXT_TC_CLOCK_SRC_BITS:
 690                 ni_m_series_clock = NI_M_NEXT_TC_CLK;
 691                 break;
 692         case NI_GPCT_PXI10_CLOCK_SRC_BITS:
 693                 ni_m_series_clock = NI_M_PXI10_CLK;
 694                 break;
 695         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 696                 ni_m_series_clock = NI_M_PXI_STAR_TRIGGER_CLK;
 697                 break;
 698         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 699                 ni_m_series_clock = NI_M_ANALOG_TRIGGER_OUT_CLK;
 700                 break;
 701         default:
 702                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 703                         if (clk_src == NI_GPCT_RTSI_CLOCK_SRC_BITS(i)) {
 704                                 ni_m_series_clock = NI_M_RTSI_CLK(i);
 705                                 break;
 706                         }
 707                 }
 708                 if (i <= NI_M_MAX_RTSI_CHAN)
 709                         break;
 710                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 711                         if (clk_src == NI_GPCT_PFI_CLOCK_SRC_BITS(i)) {
 712                                 ni_m_series_clock = NI_M_PFI_CLK(i);
 713                                 break;
 714                         }
 715                 }
 716                 if (i <= NI_M_MAX_PFI_CHAN)
 717                         break;
 718                 return -EINVAL;
 719         }
 720         *bits = GI_SRC_SEL(ni_m_series_clock);
 721         return 0;
 722 };
 723
 724 static void ni_tio_set_source_subselect(struct ni_gpct *counter,
 725                                         unsigned int clock_source)
 726 {
 727         struct ni_gpct_device *counter_dev = counter->counter_dev;
 728         unsigned int cidx = counter->counter_index;
 729         unsigned int chip = counter->chip_index;
 730         unsigned int second_gate_reg = NITIO_GATE2_REG(cidx);
 731
 732         if (counter_dev->variant != ni_gpct_variant_m_series)
 733                 return;
 734         switch (clock_source & NI_GPCT_CLOCK_SRC_SELECT_MASK) {
 735                 /* Gi_Source_Subselect is zero */
 736         case NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS:
 737         case NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS:
 738                 counter_dev->regs[chip][second_gate_reg] &= ~GI_SRC_SUBSEL;
 739                 break;
 740                 /* Gi_Source_Subselect is one */
 741         case NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS:
 742         case NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS:
 743                 counter_dev->regs[chip][second_gate_reg] |= GI_SRC_SUBSEL;
 744                 break;
 745                 /* Gi_Source_Subselect doesn't matter */
 746         default:
 747                 return;
 748         }
 749         ni_tio_write(counter, counter_dev->regs[chip][second_gate_reg],
 750                      second_gate_reg);
 751 }
 752
 753 static int ni_tio_set_clock_src(struct ni_gpct *counter,
 754                                 unsigned int clock_source,
 755                                 unsigned int period_ns)
 756 {
 757         struct ni_gpct_device *counter_dev = counter->counter_dev;
 758         unsigned int cidx = counter->counter_index;
 759         unsigned int bits = 0;
 760         int ret;
 761
 762         switch (counter_dev->variant) {
 763         case ni_gpct_variant_660x:
 764                 ret = ni_660x_clk_src(clock_source, &bits);
 765                 break;
 766         case ni_gpct_variant_e_series:
 767         case ni_gpct_variant_m_series:
 768         default:
 769                 ret = ni_m_clk_src(clock_source, &bits);
 770                 break;
 771         }
 772         if (ret) {
 773                 struct comedi_device *dev = counter_dev->dev;
 774
 775                 dev_err(dev->class_dev, "invalid clock source 0x%x\n",
 776                         clock_source);
 777                 return ret;
 778         }
 779
 780         if (clock_source & NI_GPCT_INVERT_CLOCK_SRC_BIT)
 781                 bits |= GI_SRC_POL_INVERT;
 782         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx),
 783                         GI_SRC_SEL_MASK | GI_SRC_POL_INVERT, bits);
 784         ni_tio_set_source_subselect(counter, clock_source);
 785
 786         if (ni_tio_counting_mode_registers_present(counter_dev)) {
 787                 bits = 0;
 788                 switch (clock_source & NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK) {
 789                 case NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS:
 790                         break;
 791                 case NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS:
 792                         bits |= GI_PRESCALE_X2(counter_dev->variant);
 793                         break;
 794                 case NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS:
 795                         bits |= GI_PRESCALE_X8(counter_dev->variant);
 796                         break;
 797                 default:
 798                         return -EINVAL;
 799                 }
 800                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx),
 801                                 GI_PRESCALE_X2(counter_dev->variant) |
 802                                 GI_PRESCALE_X8(counter_dev->variant), bits);
 803         }
 804         counter->clock_period_ps = period_ns * 1000;
 805         ni_tio_set_sync_mode(counter);
 806         return 0;
 807 }
 808
 809 static int ni_tio_get_clock_src(struct ni_gpct *counter,
 810                                 unsigned int *clock_source,
 811                                 unsigned int *period_ns)
 812 {
 813         u64 temp64 = 0;
 814         int ret;
 815
 816         ret = ni_tio_generic_clock_src_select(counter, clock_source);
 817         if (ret)
 818                 return ret;
 819         ret = ni_tio_clock_period_ps(counter, *clock_source, &temp64);
 820         if (ret)
 821                 return ret;
 822         do_div(temp64, 1000);   /* ps to ns */
 823         *period_ns = temp64;
 824         return 0;
 825 }
 826
 827 static inline void ni_tio_set_gate_raw(struct ni_gpct *counter,
 828                                        unsigned int gate_source)
 829 {
 830         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(counter->counter_index),
 831                         GI_GATE_SEL_MASK, GI_GATE_SEL(gate_source));
 832 }
 833
 834 static inline void ni_tio_set_gate2_raw(struct ni_gpct *counter,
 835                                         unsigned int gate_source)
 836 {
 837         ni_tio_set_bits(counter, NITIO_GATE2_REG(counter->counter_index),
 838                         GI_GATE2_SEL_MASK, GI_GATE2_SEL(gate_source));
 839 }
 840
 841 /* Set the mode bits for gate. */
 842 static inline void ni_tio_set_gate_mode(struct ni_gpct *counter,
 843                                         unsigned int src)
 844 {
 845         unsigned int mode_bits = 0;
 846
 847         if (CR_CHAN(src) & NI_GPCT_DISABLED_GATE_SELECT) {
 848                 /*
 849                  * Allowing bitwise comparison here to allow non-zero raw
 850                  * register value to be used for channel when disabling.
 851                  */
 852                 mode_bits = GI_GATING_DISABLED;
 853         } else {
 854                 if (src & CR_INVERT)
 855                         mode_bits |= GI_GATE_POL_INVERT;
 856                 if (src & CR_EDGE)
 857                         mode_bits |= GI_RISING_EDGE_GATING;
 858                 else
 859                         mode_bits |= GI_LEVEL_GATING;
 860         }
 861         ni_tio_set_bits(counter, NITIO_MODE_REG(counter->counter_index),
 862                         GI_GATE_POL_INVERT | GI_GATING_MODE_MASK,
 863                         mode_bits);
 864 }
 865
 866 /*
 867  * Set the mode bits for gate2.
 868  *
 869  * Previously, the code this function represents did not actually write anything
 870  * to the register.  Rather, writing to this register was reserved for the code
 871  * ni ni_tio_set_gate2_raw.
 872  */
 873 static inline void ni_tio_set_gate2_mode(struct ni_gpct *counter,
 874                                          unsigned int src)
 875 {
 876         /*
 877          * The GI_GATE2_MODE bit was previously set in the code that also sets
 878          * the gate2 source.
 879          * We'll set mode bits _after_ source bits now, and thus, this function
 880          * will effectively enable the second gate after all bits are set.
 881          */
 882         unsigned int mode_bits = GI_GATE2_MODE;
 883
 884         if (CR_CHAN(src) & NI_GPCT_DISABLED_GATE_SELECT)
 885                 /*
 886                  * Allowing bitwise comparison here to allow non-zero raw
 887                  * register value to be used for channel when disabling.
 888                  */
 889                 mode_bits = GI_GATING_DISABLED;
 890         if (src & CR_INVERT)
 891                 mode_bits |= GI_GATE2_POL_INVERT;
 892
 893         ni_tio_set_bits(counter, NITIO_GATE2_REG(counter->counter_index),
 894                         GI_GATE2_POL_INVERT | GI_GATE2_MODE, mode_bits);
 895 }
 896
 897 static int ni_660x_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 898 {
 899         unsigned int chan = CR_CHAN(gate_source);
 900         unsigned int gate_sel;
 901         unsigned int i;
 902
 903         switch (chan) {
 904         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 905                 gate_sel = NI_660X_NEXT_SRC_GATE_SEL;
 906                 break;
 907         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 908         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 909         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 910         case NI_GPCT_GATE_PIN_i_GATE_SELECT:
 911                 gate_sel = chan & 0x1f;
 912                 break;
 913         default:
 914                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 915                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 916                                 gate_sel = chan & 0x1f;
 917                                 break;
 918                         }
 919                 }
 920                 if (i <= NI_660X_MAX_RTSI_CHAN)
 921                         break;
 922                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
 923                         if (chan == NI_GPCT_GATE_PIN_GATE_SELECT(i)) {
 924                                 gate_sel = chan & 0x1f;
 925                                 break;
 926                         }
 927                 }
 928                 if (i <= NI_660X_MAX_GATE_PIN)
 929                         break;
 930                 return -EINVAL;
 931         }
 932         ni_tio_set_gate_raw(counter, gate_sel);
 933         return 0;
 934 }
 935
 936 static int ni_m_set_gate(struct ni_gpct *counter, unsigned int gate_source)
 937 {
 938         unsigned int chan = CR_CHAN(gate_source);
 939         unsigned int gate_sel;
 940         unsigned int i;
 941
 942         switch (chan) {
 943         case NI_GPCT_TIMESTAMP_MUX_GATE_SELECT:
 944         case NI_GPCT_AI_START2_GATE_SELECT:
 945         case NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT:
 946         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 947         case NI_GPCT_AI_START1_GATE_SELECT:
 948         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 949         case NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT:
 950         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 951                 gate_sel = chan & 0x1f;
 952                 break;
 953         default:
 954                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
 955                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 956                                 gate_sel = chan & 0x1f;
 957                                 break;
 958                         }
 959                 }
 960                 if (i <= NI_M_MAX_RTSI_CHAN)
 961                         break;
 962                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
 963                         if (chan == NI_GPCT_PFI_GATE_SELECT(i)) {
 964                                 gate_sel = chan & 0x1f;
 965                                 break;
 966                         }
 967                 }
 968                 if (i <= NI_M_MAX_PFI_CHAN)
 969                         break;
 970                 return -EINVAL;
 971         }
 972         ni_tio_set_gate_raw(counter, gate_sel);
 973         return 0;
 974 }
 975
 976 static int ni_660x_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
 977 {
 978         unsigned int chan = CR_CHAN(gate_source);
 979         unsigned int gate2_sel;
 980         unsigned int i;
 981
 982         switch (chan) {
 983         case NI_GPCT_SOURCE_PIN_i_GATE_SELECT:
 984         case NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT:
 985         case NI_GPCT_SELECTED_GATE_GATE_SELECT:
 986         case NI_GPCT_NEXT_OUT_GATE_SELECT:
 987         case NI_GPCT_LOGIC_LOW_GATE_SELECT:
 988                 gate2_sel = chan & 0x1f;
 989                 break;
 990         case NI_GPCT_NEXT_SOURCE_GATE_SELECT:
 991                 gate2_sel = NI_660X_NEXT_SRC_GATE2_SEL;
 992                 break;
 993         default:
 994                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
 995                         if (chan == NI_GPCT_RTSI_GATE_SELECT(i)) {
 996                                 gate2_sel = chan & 0x1f;
 997                                 break;
 998                         }
 999                 }
1000                 if (i <= NI_660X_MAX_RTSI_CHAN)
1001                         break;
1002                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1003                         if (chan == NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i)) {
1004                                 gate2_sel = chan & 0x1f;
1005                                 break;
1006                         }
1007                 }
1008                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1009                         break;
1010                 return -EINVAL;
1011         }
1012         ni_tio_set_gate2_raw(counter, gate2_sel);
1013         return 0;
1014 }
1015
1016 static int ni_m_set_gate2(struct ni_gpct *counter, unsigned int gate_source)
1017 {
1018         /*
1019          * FIXME: We don't know what the m-series second gate codes are,
1020          * so we'll just pass the bits through for now.
1021          */
1022         ni_tio_set_gate2_raw(counter, gate_source);
1023         return 0;
1024 }
1025
1026 int ni_tio_set_gate_src_raw(struct ni_gpct *counter,
1027                             unsigned int gate, unsigned int src)
1028 {
1029         struct ni_gpct_device *counter_dev = counter->counter_dev;
1030
1031         switch (gate) {
1032         case 0:
1033                 /* 1.  start by disabling gate */
1034                 ni_tio_set_gate_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1035                 /* 2.  set the requested gate source */
1036                 ni_tio_set_gate_raw(counter, src);
1037                 /* 3.  reenable & set mode to starts things back up */
1038                 ni_tio_set_gate_mode(counter, src);
1039                 break;
1040         case 1:
1041                 if (!ni_tio_has_gate2_registers(counter_dev))
1042                         return -EINVAL;
1043
1044                 /* 1.  start by disabling gate */
1045                 ni_tio_set_gate2_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1046                 /* 2.  set the requested gate source */
1047                 ni_tio_set_gate2_raw(counter, src);
1048                 /* 3.  reenable & set mode to starts things back up */
1049                 ni_tio_set_gate2_mode(counter, src);
1050                 break;
1051         default:
1052                 return -EINVAL;
1053         }
1054         return 0;
1055 }
1056 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src_raw);
1057
1058 int ni_tio_set_gate_src(struct ni_gpct *counter,
1059                         unsigned int gate, unsigned int src)
1060 {
1061         struct ni_gpct_device *counter_dev = counter->counter_dev;
1062         /*
1063          * mask off disable flag.  This high bit still passes CR_CHAN.
1064          * Doing this allows one to both set the gate as disabled, but also
1065          * change the route value of the gate.
1066          */
1067         int chan = CR_CHAN(src) & (~NI_GPCT_DISABLED_GATE_SELECT);
1068         int ret;
1069
1070         switch (gate) {
1071         case 0:
1072                 /* 1.  start by disabling gate */
1073                 ni_tio_set_gate_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1074                 /* 2.  set the requested gate source */
1075                 switch (counter_dev->variant) {
1076                 case ni_gpct_variant_e_series:
1077                 case ni_gpct_variant_m_series:
1078                         ret = ni_m_set_gate(counter, chan);
1079                         break;
1080                 case ni_gpct_variant_660x:
1081                         ret = ni_660x_set_gate(counter, chan);
1082                         break;
1083                 default:
1084                         return -EINVAL;
1085                 }
1086                 if (ret)
1087                         return ret;
1088                 /* 3.  reenable & set mode to starts things back up */
1089                 ni_tio_set_gate_mode(counter, src);
1090                 break;
1091         case 1:
1092                 if (!ni_tio_has_gate2_registers(counter_dev))
1093                         return -EINVAL;
1094
1095                 /* 1.  start by disabling gate */
1096                 ni_tio_set_gate2_mode(counter, NI_GPCT_DISABLED_GATE_SELECT);
1097                 /* 2.  set the requested gate source */
1098                 switch (counter_dev->variant) {
1099                 case ni_gpct_variant_m_series:
1100                         ret = ni_m_set_gate2(counter, chan);
1101                         break;
1102                 case ni_gpct_variant_660x:
1103                         ret = ni_660x_set_gate2(counter, chan);
1104                         break;
1105                 default:
1106                         return -EINVAL;
1107                 }
1108                 if (ret)
1109                         return ret;
1110                 /* 3.  reenable & set mode to starts things back up */
1111                 ni_tio_set_gate2_mode(counter, src);
1112                 break;
1113         default:
1114                 return -EINVAL;
1115         }
1116         return 0;
1117 }
1118 EXPORT_SYMBOL_GPL(ni_tio_set_gate_src);
1119
1120 static int ni_tio_set_other_src(struct ni_gpct *counter, unsigned int index,
1121                                 unsigned int source)
1122 {
1123         struct ni_gpct_device *counter_dev = counter->counter_dev;
1124         unsigned int cidx = counter->counter_index;
1125         unsigned int chip = counter->chip_index;
1126         unsigned int abz_reg, shift, mask;
1127
1128         if (counter_dev->variant != ni_gpct_variant_m_series)
1129                 return -EINVAL;
1130
1131         abz_reg = NITIO_ABZ_REG(cidx);
1132
1133         /* allow for new device-global names */
1134         if (index == NI_GPCT_SOURCE_ENCODER_A ||
1135             (index >= NI_CtrA(0) && index <= NI_CtrA(-1))) {
1136                 shift = 10;
1137         } else if (index == NI_GPCT_SOURCE_ENCODER_B ||
1138             (index >= NI_CtrB(0) && index <= NI_CtrB(-1))) {
1139                 shift = 5;
1140         } else if (index == NI_GPCT_SOURCE_ENCODER_Z ||
1141             (index >= NI_CtrZ(0) && index <= NI_CtrZ(-1))) {
1142                 shift = 0;
1143         } else {
1144                 return -EINVAL;
1145         }
1146
1147         mask = 0x1f << shift;
1148         if (source > 0x1f)
1149                 source = 0x1f;  /* Disable gate */
1150
1151         counter_dev->regs[chip][abz_reg] &= ~mask;
1152         counter_dev->regs[chip][abz_reg] |= (source << shift) & mask;
1153         ni_tio_write(counter, counter_dev->regs[chip][abz_reg], abz_reg);
1154         return 0;
1155 }
1156
1157 static int ni_tio_get_other_src(struct ni_gpct *counter, unsigned int index,
1158                                 unsigned int *source)
1159 {
1160         struct ni_gpct_device *counter_dev = counter->counter_dev;
1161         unsigned int cidx = counter->counter_index;
1162         unsigned int abz_reg, shift, mask;
1163
1164         if (counter_dev->variant != ni_gpct_variant_m_series)
1165                 /* A,B,Z only valid for m-series */
1166                 return -EINVAL;
1167
1168         abz_reg = NITIO_ABZ_REG(cidx);
1169
1170         /* allow for new device-global names */
1171         if (index == NI_GPCT_SOURCE_ENCODER_A ||
1172             (index >= NI_CtrA(0) && index <= NI_CtrA(-1))) {
1173                 shift = 10;
1174         } else if (index == NI_GPCT_SOURCE_ENCODER_B ||
1175             (index >= NI_CtrB(0) && index <= NI_CtrB(-1))) {
1176                 shift = 5;
1177         } else if (index == NI_GPCT_SOURCE_ENCODER_Z ||
1178             (index >= NI_CtrZ(0) && index <= NI_CtrZ(-1))) {
1179                 shift = 0;
1180         } else {
1181                 return -EINVAL;
1182         }
1183
1184         mask = 0x1f;
1185
1186         *source = (ni_tio_get_soft_copy(counter, abz_reg) >> shift) & mask;
1187         return 0;
1188 }
1189
1190 static int ni_660x_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1191 {
1192         unsigned int source;
1193         unsigned int i;
1194
1195         switch (gate) {
1196         case NI_660X_SRC_PIN_I_GATE_SEL:
1197                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1198                 break;
1199         case NI_660X_GATE_PIN_I_GATE_SEL:
1200                 source = NI_GPCT_GATE_PIN_i_GATE_SELECT;
1201                 break;
1202         case NI_660X_NEXT_SRC_GATE_SEL:
1203                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1204                 break;
1205         case NI_660X_NEXT_OUT_GATE_SEL:
1206                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1207                 break;
1208         case NI_660X_LOGIC_LOW_GATE_SEL:
1209                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1210                 break;
1211         default:
1212                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1213                         if (gate == NI_660X_RTSI_GATE_SEL(i)) {
1214                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1215                                 break;
1216                         }
1217                 }
1218                 if (i <= NI_660X_MAX_RTSI_CHAN)
1219                         break;
1220                 for (i = 0; i <= NI_660X_MAX_GATE_PIN; ++i) {
1221                         if (gate == NI_660X_PIN_GATE_SEL(i)) {
1222                                 source = NI_GPCT_GATE_PIN_GATE_SELECT(i);
1223                                 break;
1224                         }
1225                 }
1226                 if (i <= NI_660X_MAX_GATE_PIN)
1227                         break;
1228                 return -EINVAL;
1229         }
1230         *src = source;
1231         return 0;
1232 }
1233
1234 static int ni_m_gate_to_generic_gate(unsigned int gate, unsigned int *src)
1235 {
1236         unsigned int source;
1237         unsigned int i;
1238
1239         switch (gate) {
1240         case NI_M_TIMESTAMP_MUX_GATE_SEL:
1241                 source = NI_GPCT_TIMESTAMP_MUX_GATE_SELECT;
1242                 break;
1243         case NI_M_AI_START2_GATE_SEL:
1244                 source = NI_GPCT_AI_START2_GATE_SELECT;
1245                 break;
1246         case NI_M_PXI_STAR_TRIGGER_GATE_SEL:
1247                 source = NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT;
1248                 break;
1249         case NI_M_NEXT_OUT_GATE_SEL:
1250                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1251                 break;
1252         case NI_M_AI_START1_GATE_SEL:
1253                 source = NI_GPCT_AI_START1_GATE_SELECT;
1254                 break;
1255         case NI_M_NEXT_SRC_GATE_SEL:
1256                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1257                 break;
1258         case NI_M_ANALOG_TRIG_OUT_GATE_SEL:
1259                 source = NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT;
1260                 break;
1261         case NI_M_LOGIC_LOW_GATE_SEL:
1262                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1263                 break;
1264         default:
1265                 for (i = 0; i <= NI_M_MAX_RTSI_CHAN; ++i) {
1266                         if (gate == NI_M_RTSI_GATE_SEL(i)) {
1267                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1268                                 break;
1269                         }
1270                 }
1271                 if (i <= NI_M_MAX_RTSI_CHAN)
1272                         break;
1273                 for (i = 0; i <= NI_M_MAX_PFI_CHAN; ++i) {
1274                         if (gate == NI_M_PFI_GATE_SEL(i)) {
1275                                 source = NI_GPCT_PFI_GATE_SELECT(i);
1276                                 break;
1277                         }
1278                 }
1279                 if (i <= NI_M_MAX_PFI_CHAN)
1280                         break;
1281                 return -EINVAL;
1282         }
1283         *src = source;
1284         return 0;
1285 }
1286
1287 static int ni_660x_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1288 {
1289         unsigned int source;
1290         unsigned int i;
1291
1292         switch (gate) {
1293         case NI_660X_SRC_PIN_I_GATE2_SEL:
1294                 source = NI_GPCT_SOURCE_PIN_i_GATE_SELECT;
1295                 break;
1296         case NI_660X_UD_PIN_I_GATE2_SEL:
1297                 source = NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT;
1298                 break;
1299         case NI_660X_NEXT_SRC_GATE2_SEL:
1300                 source = NI_GPCT_NEXT_SOURCE_GATE_SELECT;
1301                 break;
1302         case NI_660X_NEXT_OUT_GATE2_SEL:
1303                 source = NI_GPCT_NEXT_OUT_GATE_SELECT;
1304                 break;
1305         case NI_660X_SELECTED_GATE2_SEL:
1306                 source = NI_GPCT_SELECTED_GATE_GATE_SELECT;
1307                 break;
1308         case NI_660X_LOGIC_LOW_GATE2_SEL:
1309                 source = NI_GPCT_LOGIC_LOW_GATE_SELECT;
1310                 break;
1311         default:
1312                 for (i = 0; i <= NI_660X_MAX_RTSI_CHAN; ++i) {
1313                         if (gate == NI_660X_RTSI_GATE2_SEL(i)) {
1314                                 source = NI_GPCT_RTSI_GATE_SELECT(i);
1315                                 break;
1316                         }
1317                 }
1318                 if (i <= NI_660X_MAX_RTSI_CHAN)
1319                         break;
1320                 for (i = 0; i <= NI_660X_MAX_UP_DOWN_PIN; ++i) {
1321                         if (gate == NI_660X_UD_PIN_GATE2_SEL(i)) {
1322                                 source = NI_GPCT_UP_DOWN_PIN_GATE_SELECT(i);
1323                                 break;
1324                         }
1325                 }
1326                 if (i <= NI_660X_MAX_UP_DOWN_PIN)
1327                         break;
1328                 return -EINVAL;
1329         }
1330         *src = source;
1331         return 0;
1332 }
1333
1334 static int ni_m_gate2_to_generic_gate(unsigned int gate, unsigned int *src)
1335 {
1336         /*
1337          * FIXME: the second gate sources for the m series are undocumented,
1338          * so we just return the raw bits for now.
1339          */
1340         *src = gate;
1341         return 0;
1342 }
1343
1344 static inline unsigned int ni_tio_get_gate_mode(struct ni_gpct *counter)
1345 {
1346         unsigned int mode = ni_tio_get_soft_copy(
1347                 counter, NITIO_MODE_REG(counter->counter_index));
1348         unsigned int ret = 0;
1349
1350         if ((mode & GI_GATING_MODE_MASK) == GI_GATING_DISABLED)
1351                 ret |= NI_GPCT_DISABLED_GATE_SELECT;
1352         if (mode & GI_GATE_POL_INVERT)
1353                 ret |= CR_INVERT;
1354         if ((mode & GI_GATING_MODE_MASK) != GI_LEVEL_GATING)
1355                 ret |= CR_EDGE;
1356
1357         return ret;
1358 }
1359
1360 static inline unsigned int ni_tio_get_gate2_mode(struct ni_gpct *counter)
1361 {
1362         unsigned int mode = ni_tio_get_soft_copy(
1363                 counter, NITIO_GATE2_REG(counter->counter_index));
1364         unsigned int ret = 0;
1365
1366         if (!(mode & GI_GATE2_MODE))
1367                 ret |= NI_GPCT_DISABLED_GATE_SELECT;
1368         if (mode & GI_GATE2_POL_INVERT)
1369                 ret |= CR_INVERT;
1370
1371         return ret;
1372 }
1373
1374 static inline unsigned int ni_tio_get_gate_val(struct ni_gpct *counter)
1375 {
1376         return GI_BITS_TO_GATE(ni_tio_get_soft_copy(counter,
1377                 NITIO_INPUT_SEL_REG(counter->counter_index)));
1378 }
1379
1380 static inline unsigned int ni_tio_get_gate2_val(struct ni_gpct *counter)
1381 {
1382         return GI_BITS_TO_GATE2(ni_tio_get_soft_copy(counter,
1383                 NITIO_GATE2_REG(counter->counter_index)));
1384 }
1385
1386 static int ni_tio_get_gate_src(struct ni_gpct *counter, unsigned int gate_index,
1387                                unsigned int *gate_source)
1388 {
1389         unsigned int gate;
1390         int ret;
1391
1392         switch (gate_index) {
1393         case 0:
1394                 gate = ni_tio_get_gate_val(counter);
1395                 switch (counter->counter_dev->variant) {
1396                 case ni_gpct_variant_e_series:
1397                 case ni_gpct_variant_m_series:
1398                 default:
1399                         ret = ni_m_gate_to_generic_gate(gate, gate_source);
1400                         break;
1401                 case ni_gpct_variant_660x:
1402                         ret = ni_660x_gate_to_generic_gate(gate, gate_source);
1403                         break;
1404                 }
1405                 if (ret)
1406                         return ret;
1407                 *gate_source |= ni_tio_get_gate_mode(counter);
1408                 break;
1409         case 1:
1410                 gate = ni_tio_get_gate2_val(counter);
1411                 switch (counter->counter_dev->variant) {
1412                 case ni_gpct_variant_e_series:
1413                 case ni_gpct_variant_m_series:
1414                 default:
1415                         ret = ni_m_gate2_to_generic_gate(gate, gate_source);
1416                         break;
1417                 case ni_gpct_variant_660x:
1418                         ret = ni_660x_gate2_to_generic_gate(gate, gate_source);
1419                         break;
1420                 }
1421                 if (ret)
1422                         return ret;
1423                 *gate_source |= ni_tio_get_gate2_mode(counter);
1424                 break;
1425         default:
1426                 return -EINVAL;
1427         }
1428         return 0;
1429 }
1430
1431 static int ni_tio_get_gate_src_raw(struct ni_gpct *counter,
1432                                    unsigned int gate_index,
1433                                    unsigned int *gate_source)
1434 {
1435         switch (gate_index) {
1436         case 0:
1437                 *gate_source = ni_tio_get_gate_mode(counter)
1438                              | ni_tio_get_gate_val(counter);
1439                 break;
1440         case 1:
1441                 *gate_source = ni_tio_get_gate2_mode(counter)
1442                              | ni_tio_get_gate2_val(counter);
1443                 break;
1444         default:
1445                 return -EINVAL;
1446         }
1447         return 0;
1448 }
1449
1450 int ni_tio_insn_config(struct comedi_device *dev,
1451                        struct comedi_subdevice *s,
1452                        struct comedi_insn *insn,
1453                        unsigned int *data)
1454 {
1455         struct ni_gpct *counter = s->private;
1456         unsigned int cidx = counter->counter_index;
1457         unsigned int status;
1458         int ret = 0;
1459
1460         switch (data[0]) {
1461         case INSN_CONFIG_SET_COUNTER_MODE:
1462                 ret = ni_tio_set_counter_mode(counter, data[1]);
1463                 break;
1464         case INSN_CONFIG_ARM:
1465                 ret = ni_tio_arm(counter, true, data[1]);
1466                 break;
1467         case INSN_CONFIG_DISARM:
1468                 ret = ni_tio_arm(counter, false, 0);
1469                 break;
1470         case INSN_CONFIG_GET_COUNTER_STATUS:
1471                 data[1] = 0;
1472                 status = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1473                 if (status & GI_ARMED(cidx)) {
1474                         data[1] |= COMEDI_COUNTER_ARMED;
1475                         if (status & GI_COUNTING(cidx))
1476                                 data[1] |= COMEDI_COUNTER_COUNTING;
1477                 }
1478                 data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING;
1479                 break;
1480         case INSN_CONFIG_SET_CLOCK_SRC:
1481                 ret = ni_tio_set_clock_src(counter, data[1], data[2]);
1482                 break;
1483         case INSN_CONFIG_GET_CLOCK_SRC:
1484                 ret = ni_tio_get_clock_src(counter, &data[1], &data[2]);
1485                 break;
1486         case INSN_CONFIG_SET_GATE_SRC:
1487                 ret = ni_tio_set_gate_src(counter, data[1], data[2]);
1488                 break;
1489         case INSN_CONFIG_GET_GATE_SRC:
1490                 ret = ni_tio_get_gate_src(counter, data[1], &data[2]);
1491                 break;
1492         case INSN_CONFIG_SET_OTHER_SRC:
1493                 ret = ni_tio_set_other_src(counter, data[1], data[2]);
1494                 break;
1495         case INSN_CONFIG_RESET:
1496                 ni_tio_reset_count_and_disarm(counter);
1497                 break;
1498         default:
1499                 return -EINVAL;
1500         }
1501         return ret ? ret : insn->n;
1502 }
1503 EXPORT_SYMBOL_GPL(ni_tio_insn_config);
1504
1505 /**
1506  * Retrieves the register value of the current source of the output selector for
1507  * the given destination.
1508  *
1509  * If the terminal for the destination is not already configured as an output,
1510  * this function returns -EINVAL as error.
1511  *
1512  * Return: the register value of the destination output selector;
1513  *         -EINVAL if terminal is not configured for output.
1514  */
1515 int ni_tio_get_routing(struct ni_gpct_device *counter_dev, unsigned int dest)
1516 {
1517         /* we need to know the actual counter below... */
1518         int ctr_index = (dest - NI_COUNTER_NAMES_BASE) % NI_MAX_COUNTERS;
1519         struct ni_gpct *counter = &counter_dev->counters[ctr_index];
1520         int ret = 1;
1521         unsigned int reg;
1522
1523         if (dest >= NI_CtrA(0) && dest <= NI_CtrZ(-1)) {
1524                 ret = ni_tio_get_other_src(counter, dest, &reg);
1525         } else if (dest >= NI_CtrGate(0) && dest <= NI_CtrGate(-1)) {
1526                 ret = ni_tio_get_gate_src_raw(counter, 0, &reg);
1527         } else if (dest >= NI_CtrAux(0) && dest <= NI_CtrAux(-1)) {
1528                 ret = ni_tio_get_gate_src_raw(counter, 1, &reg);
1529         /*
1530          * This case is not possible through this interface.  A user must use
1531          * INSN_CONFIG_SET_CLOCK_SRC instead.
1532          * } else if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1)) {
1533          *      ret = ni_tio_set_clock_src(counter, &reg, &period_ns);
1534          */
1535         }
1536
1537         if (ret)
1538                 return -EINVAL;
1539
1540         return reg;
1541 }
1542 EXPORT_SYMBOL_GPL(ni_tio_get_routing);
1543
1544 /**
1545  * Sets the register value of the selector MUX for the given destination.
1546  * @counter_dev:Pointer to general counter device.
1547  * @destination:Device-global identifier of route destination.
1548  * @register_value:
1549  *              The first several bits of this value should store the desired
1550  *              value to write to the register.  All other bits are for
1551  *              transmitting information that modify the mode of the particular
1552  *              destination/gate.  These mode bits might include a bitwise or of
1553  *              CR_INVERT and CR_EDGE.  Note that the calling function should
1554  *              have already validated the correctness of this value.
1555  */
1556 int ni_tio_set_routing(struct ni_gpct_device *counter_dev, unsigned int dest,
1557                        unsigned int reg)
1558 {
1559         /* we need to know the actual counter below... */
1560         int ctr_index = (dest - NI_COUNTER_NAMES_BASE) % NI_MAX_COUNTERS;
1561         struct ni_gpct *counter = &counter_dev->counters[ctr_index];
1562         int ret;
1563
1564         if (dest >= NI_CtrA(0) && dest <= NI_CtrZ(-1)) {
1565                 ret = ni_tio_set_other_src(counter, dest, reg);
1566         } else if (dest >= NI_CtrGate(0) && dest <= NI_CtrGate(-1)) {
1567                 ret = ni_tio_set_gate_src_raw(counter, 0, reg);
1568         } else if (dest >= NI_CtrAux(0) && dest <= NI_CtrAux(-1)) {
1569                 ret = ni_tio_set_gate_src_raw(counter, 1, reg);
1570         /*
1571          * This case is not possible through this interface.  A user must use
1572          * INSN_CONFIG_SET_CLOCK_SRC instead.
1573          * } else if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1)) {
1574          *      ret = ni_tio_set_clock_src(counter, reg, period_ns);
1575          */
1576         } else {
1577                 return -EINVAL;
1578         }
1579
1580         return ret;
1581 }
1582 EXPORT_SYMBOL_GPL(ni_tio_set_routing);
1583
1584 /**
1585  * Sets the given destination MUX to its default value or disable it.
1586  *
1587  * Return: 0 if successful; -EINVAL if terminal is unknown.
1588  */
1589 int ni_tio_unset_routing(struct ni_gpct_device *counter_dev, unsigned int dest)
1590 {
1591         if (dest >= NI_GATES_NAMES_BASE && dest <= NI_GATES_NAMES_MAX)
1592                 /* Disable gate (via mode bits) and set to default 0-value */
1593                 return ni_tio_set_routing(counter_dev, dest,
1594                                           NI_GPCT_DISABLED_GATE_SELECT);
1595         /*
1596          * This case is not possible through this interface.  A user must use
1597          * INSN_CONFIG_SET_CLOCK_SRC instead.
1598          * if (dest >= NI_CtrSource(0) && dest <= NI_CtrSource(-1))
1599          *      return ni_tio_set_clock_src(counter, reg, period_ns);
1600          */
1601
1602         return -EINVAL;
1603 }
1604 EXPORT_SYMBOL_GPL(ni_tio_unset_routing);
1605
1606 static unsigned int ni_tio_read_sw_save_reg(struct comedi_device *dev,
1607                                             struct comedi_subdevice *s)
1608 {
1609         struct ni_gpct *counter = s->private;
1610         unsigned int cidx = counter->counter_index;
1611         unsigned int val;
1612
1613         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx), GI_SAVE_TRACE, 0);
1614         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1615                         GI_SAVE_TRACE, GI_SAVE_TRACE);
1616
1617         /*
1618          * The count doesn't get latched until the next clock edge, so it is
1619          * possible the count may change (once) while we are reading. Since
1620          * the read of the SW_Save_Reg isn't atomic (apparently even when it's
1621          * a 32 bit register according to 660x docs), we need to read twice
1622          * and make sure the reading hasn't changed. If it has, a third read
1623          * will be correct since the count value will definitely have latched
1624          * by then.
1625          */
1626         val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1627         if (val != ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx)))
1628                 val = ni_tio_read(counter, NITIO_SW_SAVE_REG(cidx));
1629
1630         return val;
1631 }
1632
1633 int ni_tio_insn_read(struct comedi_device *dev,
1634                      struct comedi_subdevice *s,
1635                      struct comedi_insn *insn,
1636                      unsigned int *data)
1637 {
1638         struct ni_gpct *counter = s->private;
1639         struct ni_gpct_device *counter_dev = counter->counter_dev;
1640         unsigned int channel = CR_CHAN(insn->chanspec);
1641         unsigned int cidx = counter->counter_index;
1642         unsigned int chip = counter->chip_index;
1643         int i;
1644
1645         for (i = 0; i < insn->n; i++) {
1646                 switch (channel) {
1647                 case 0:
1648                         data[i] = ni_tio_read_sw_save_reg(dev, s);
1649                         break;
1650                 case 1:
1651                         data[i] =
1652                             counter_dev->regs[chip][NITIO_LOADA_REG(cidx)];
1653                         break;
1654                 case 2:
1655                         data[i] =
1656                             counter_dev->regs[chip][NITIO_LOADB_REG(cidx)];
1657                         break;
1658                 }
1659         }
1660         return insn->n;
1661 }
1662 EXPORT_SYMBOL_GPL(ni_tio_insn_read);
1663
1664 static unsigned int ni_tio_next_load_register(struct ni_gpct *counter)
1665 {
1666         unsigned int cidx = counter->counter_index;
1667         unsigned int bits = ni_tio_read(counter, NITIO_SHARED_STATUS_REG(cidx));
1668
1669         return (bits & GI_NEXT_LOAD_SRC(cidx))
1670                         ? NITIO_LOADB_REG(cidx)
1671                         : NITIO_LOADA_REG(cidx);
1672 }
1673
1674 int ni_tio_insn_write(struct comedi_device *dev,
1675                       struct comedi_subdevice *s,
1676                       struct comedi_insn *insn,
1677                       unsigned int *data)
1678 {
1679         struct ni_gpct *counter = s->private;
1680         struct ni_gpct_device *counter_dev = counter->counter_dev;
1681         unsigned int channel = CR_CHAN(insn->chanspec);
1682         unsigned int cidx = counter->counter_index;
1683         unsigned int chip = counter->chip_index;
1684         unsigned int load_reg;
1685
1686         if (insn->n < 1)
1687                 return 0;
1688         switch (channel) {
1689         case 0:
1690                 /*
1691                  * Unsafe if counter is armed.
1692                  * Should probably check status and return -EBUSY if armed.
1693                  */
1694
1695                 /*
1696                  * Don't disturb load source select, just use whichever
1697                  * load register is already selected.
1698                  */
1699                 load_reg = ni_tio_next_load_register(counter);
1700                 ni_tio_write(counter, data[0], load_reg);
1701                 ni_tio_set_bits_transient(counter, NITIO_CMD_REG(cidx),
1702                                           0, 0, GI_LOAD);
1703                 /* restore load reg */
1704                 ni_tio_write(counter, counter_dev->regs[chip][load_reg],
1705                              load_reg);
1706                 break;
1707         case 1:
1708                 counter_dev->regs[chip][NITIO_LOADA_REG(cidx)] = data[0];
1709                 ni_tio_write(counter, data[0], NITIO_LOADA_REG(cidx));
1710                 break;
1711         case 2:
1712                 counter_dev->regs[chip][NITIO_LOADB_REG(cidx)] = data[0];
1713                 ni_tio_write(counter, data[0], NITIO_LOADB_REG(cidx));
1714                 break;
1715         default:
1716                 return -EINVAL;
1717         }
1718         return 0;
1719 }
1720 EXPORT_SYMBOL_GPL(ni_tio_insn_write);
1721
1722 void ni_tio_init_counter(struct ni_gpct *counter)
1723 {
1724         struct ni_gpct_device *counter_dev = counter->counter_dev;
1725         unsigned int cidx = counter->counter_index;
1726         unsigned int chip = counter->chip_index;
1727
1728         ni_tio_reset_count_and_disarm(counter);
1729
1730         /* initialize counter registers */
1731         counter_dev->regs[chip][NITIO_AUTO_INC_REG(cidx)] = 0x0;
1732         ni_tio_write(counter, 0x0, NITIO_AUTO_INC_REG(cidx));
1733
1734         ni_tio_set_bits(counter, NITIO_CMD_REG(cidx),
1735                         ~0, GI_SYNC_GATE);
1736
1737         ni_tio_set_bits(counter, NITIO_MODE_REG(cidx), ~0, 0);
1738
1739         counter_dev->regs[chip][NITIO_LOADA_REG(cidx)] = 0x0;
1740         ni_tio_write(counter, 0x0, NITIO_LOADA_REG(cidx));
1741
1742         counter_dev->regs[chip][NITIO_LOADB_REG(cidx)] = 0x0;
1743         ni_tio_write(counter, 0x0, NITIO_LOADB_REG(cidx));
1744
1745         ni_tio_set_bits(counter, NITIO_INPUT_SEL_REG(cidx), ~0, 0);
1746
1747         if (ni_tio_counting_mode_registers_present(counter_dev))
1748                 ni_tio_set_bits(counter, NITIO_CNT_MODE_REG(cidx), ~0, 0);
1749
1750         if (ni_tio_has_gate2_registers(counter_dev)) {
1751                 counter_dev->regs[chip][NITIO_GATE2_REG(cidx)] = 0x0;
1752                 ni_tio_write(counter, 0x0, NITIO_GATE2_REG(cidx));
1753         }
1754
1755         ni_tio_set_bits(counter, NITIO_DMA_CFG_REG(cidx), ~0, 0x0);
1756
1757         ni_tio_set_bits(counter, NITIO_INT_ENA_REG(cidx), ~0, 0x0);
1758 }
1759 EXPORT_SYMBOL_GPL(ni_tio_init_counter);
1760
1761 struct ni_gpct_device *
1762 ni_gpct_device_construct(struct comedi_device *dev,
1763                          void (*write)(struct ni_gpct *counter,
1764                                        unsigned int value,
1765                                        enum ni_gpct_register reg),
1766                          unsigned int (*read)(struct ni_gpct *counter,
1767                                               enum ni_gpct_register reg),
1768                          enum ni_gpct_variant variant,
1769                          unsigned int num_counters,
1770                          unsigned int counters_per_chip,
1771                          const struct ni_route_tables *routing_tables)
1772 {
1773         struct ni_gpct_device *counter_dev;
1774         struct ni_gpct *counter;
1775         unsigned int i;
1776
1777         if (num_counters == 0 || counters_per_chip == 0)
1778                 return NULL;
1779
1780         counter_dev = kzalloc(sizeof(*counter_dev), GFP_KERNEL);
1781         if (!counter_dev)
1782                 return NULL;
1783
1784         counter_dev->dev = dev;
1785         counter_dev->write = write;
1786         counter_dev->read = read;
1787         counter_dev->variant = variant;
1788         counter_dev->routing_tables = routing_tables;
1789
1790         spin_lock_init(&counter_dev->regs_lock);
1791
1792         counter_dev->num_counters = num_counters;
1793         counter_dev->num_chips = DIV_ROUND_UP(num_counters, counters_per_chip);
1794
1795         counter_dev->counters = kcalloc(num_counters, sizeof(*counter),
1796                                         GFP_KERNEL);
1797         counter_dev->regs = kcalloc(counter_dev->num_chips,
1798                                     sizeof(*counter_dev->regs), GFP_KERNEL);
1799         if (!counter_dev->regs || !counter_dev->counters) {
1800                 kfree(counter_dev->regs);
1801                 kfree(counter_dev->counters);
1802                 kfree(counter_dev);
1803                 return NULL;
1804         }
1805
1806         for (i = 0; i < num_counters; ++i) {
1807                 counter = &counter_dev->counters[i];
1808                 counter->counter_dev = counter_dev;
1809                 counter->chip_index = i / counters_per_chip;
1810                 counter->counter_index = i % counters_per_chip;
1811                 spin_lock_init(&counter->lock);
1812         }
1813
1814         return counter_dev;
1815 }
1816 EXPORT_SYMBOL_GPL(ni_gpct_device_construct);
1817
1818 void ni_gpct_device_destroy(struct ni_gpct_device *counter_dev)
1819 {
1820         if (!counter_dev)
1821                 return;
1822         kfree(counter_dev->regs);
1823         kfree(counter_dev->counters);
1824         kfree(counter_dev);
1825 }
1826 EXPORT_SYMBOL_GPL(ni_gpct_device_destroy);
1827
1828 static int __init ni_tio_init_module(void)
1829 {
1830         return 0;
1831 }
1832 module_init(ni_tio_init_module);
1833
1834 static void __exit ni_tio_cleanup_module(void)
1835 {
1836 }
1837 module_exit(ni_tio_cleanup_module);
1838
1839 MODULE_AUTHOR("Comedi <comedi@comedi.org>");
1840 MODULE_DESCRIPTION("Comedi support for NI general-purpose counters");
1841 MODULE_LICENSE("GPL");