drivers/staging/media/davinci_vpfe/dm365_ipipe_hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Inc
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation version 2.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * Contributors:
  15  *      Manjunath Hadli <manjunath.hadli@ti.com>
  16  *      Prabhakar Lad <prabhakar.lad@ti.com>
  17  */
  18
  19 #ifndef _DAVINCI_VPFE_DM365_IPIPE_HW_H
  20 #define _DAVINCI_VPFE_DM365_IPIPE_HW_H
  21
  22 #include "vpfe_mc_capture.h"
  23
  24 #define SET_LOW_ADDR     0x0000ffff
  25 #define SET_HIGH_ADDR    0xffff0000
  26
  27 /* Below are the internal tables */
  28 #define DPC_TB0_START_ADDR      0x8000
  29 #define DPC_TB1_START_ADDR      0x8400
  30
  31 #define GAMMA_R_START_ADDR      0xa800
  32 #define GAMMA_G_START_ADDR      0xb000
  33 #define GAMMA_B_START_ADDR      0xb800
  34
  35 /* RAM table addresses for edge enhancement correction*/
  36 #define YEE_TB_START_ADDR       0x8800
  37
  38 /* RAM table address for GBC LUT */
  39 #define GBCE_TB_START_ADDR      0x9000
  40
  41 /* RAM table for 3D NF LUT */
  42 #define D3L_TB0_START_ADDR      0x9800
  43 #define D3L_TB1_START_ADDR      0x9c00
  44 #define D3L_TB2_START_ADDR      0xa000
  45 #define D3L_TB3_START_ADDR      0xa400
  46
  47 /* IPIPE Register Offsets from the base address */
  48 #define IPIPE_SRC_EN            0x0000
  49 #define IPIPE_SRC_MODE          0x0004
  50 #define IPIPE_SRC_FMT           0x0008
  51 #define IPIPE_SRC_COL           0x000c
  52 #define IPIPE_SRC_VPS           0x0010
  53 #define IPIPE_SRC_VSZ           0x0014
  54 #define IPIPE_SRC_HPS           0x0018
  55 #define IPIPE_SRC_HSZ           0x001c
  56
  57 #define IPIPE_SEL_SBU           0x0020
  58
  59 #define IPIPE_DMA_STA           0x0024
  60 #define IPIPE_GCK_MMR           0x0028
  61 #define IPIPE_GCK_PIX           0x002c
  62 #define IPIPE_RESERVED0         0x0030
  63
  64 /* Defect Correction */
  65 #define DPC_LUT_EN              0x0034
  66 #define DPC_LUT_SEL             0x0038
  67 #define DPC_LUT_ADR             0x003c
  68 #define DPC_LUT_SIZ             0x0040
  69 #define DPC_OTF_EN              0x0044
  70 #define DPC_OTF_TYP             0x0048
  71 #define DPC_OTF_2D_THR_R        0x004c
  72 #define DPC_OTF_2D_THR_GR       0x0050
  73 #define DPC_OTF_2D_THR_GB       0x0054
  74 #define DPC_OTF_2D_THR_B        0x0058
  75 #define DPC_OTF_2C_THR_R        0x005c
  76 #define DPC_OTF_2C_THR_GR       0x0060
  77 #define DPC_OTF_2C_THR_GB       0x0064
  78 #define DPC_OTF_2C_THR_B        0x0068
  79 #define DPC_OTF_3_SHF           0x006c
  80 #define DPC_OTF_3D_THR          0x0070
  81 #define DPC_OTF_3D_SLP          0x0074
  82 #define DPC_OTF_3D_MIN          0x0078
  83 #define DPC_OTF_3D_MAX          0x007c
  84 #define DPC_OTF_3C_THR          0x0080
  85 #define DPC_OTF_3C_SLP          0x0084
  86 #define DPC_OTF_3C_MIN          0x0088
  87 #define DPC_OTF_3C_MAX          0x008c
  88
  89 /* Lense Shading Correction */
  90 #define LSC_VOFT                0x90
  91 #define LSC_VA2                 0x94
  92 #define LSC_VA1                 0x98
  93 #define LSC_VS                  0x9c
  94 #define LSC_HOFT                0xa0
  95 #define LSC_HA2                 0xa4
  96 #define LSC_HA1                 0xa8
  97 #define LSC_HS                  0xac
  98 #define LSC_GAIN_R              0xb0
  99 #define LSC_GAIN_GR             0xb4
 100 #define LSC_GAIN_GB             0xb8
 101 #define LSC_GAIN_B              0xbc
 102 #define LSC_OFT_R               0xc0
 103 #define LSC_OFT_GR              0xc4
 104 #define LSC_OFT_GB              0xc8
 105 #define LSC_OFT_B               0xcc
 106 #define LSC_SHF                 0xd0
 107 #define LSC_MAX                 0xd4
 108
 109 /* Noise Filter 1. Ofsets from start address given */
 110 #define D2F_1ST                 0xd8
 111 #define D2F_EN                  0x0
 112 #define D2F_TYP                 0x4
 113 #define D2F_THR                 0x8
 114 #define D2F_STR                 0x28
 115 #define D2F_SPR                 0x48
 116 #define D2F_EDG_MIN             0x68
 117 #define D2F_EDG_MAX             0x6c
 118
 119 /* Noise Filter 2 */
 120 #define D2F_2ND                 0x148
 121
 122 /* GIC */
 123 #define GIC_EN                  0x1b8
 124 #define GIC_TYP                 0x1bc
 125 #define GIC_GAN                 0x1c0
 126 #define GIC_NFGAN               0x1c4
 127 #define GIC_THR                 0x1c8
 128 #define GIC_SLP                 0x1cc
 129
 130 /* White Balance */
 131 #define WB2_OFT_R               0x1d0
 132 #define WB2_OFT_GR              0x1d4
 133 #define WB2_OFT_GB              0x1d8
 134 #define WB2_OFT_B               0x1dc
 135 #define WB2_WGN_R               0x1e0
 136 #define WB2_WGN_GR              0x1e4
 137 #define WB2_WGN_GB              0x1e8
 138 #define WB2_WGN_B               0x1ec
 139
 140 /* CFA interpolation */
 141 #define CFA_MODE                0x1f0
 142 #define CFA_2DIR_HPF_THR        0x1f4
 143 #define CFA_2DIR_HPF_SLP        0x1f8
 144 #define CFA_2DIR_MIX_THR        0x1fc
 145 #define CFA_2DIR_MIX_SLP        0x200
 146 #define CFA_2DIR_DIR_THR        0x204
 147 #define CFA_2DIR_DIR_SLP        0x208
 148 #define CFA_2DIR_NDWT           0x20c
 149 #define CFA_MONO_HUE_FRA        0x210
 150 #define CFA_MONO_EDG_THR        0x214
 151 #define CFA_MONO_THR_MIN        0x218
 152 #define CFA_MONO_THR_SLP        0x21c
 153 #define CFA_MONO_SLP_MIN        0x220
 154 #define CFA_MONO_SLP_SLP        0x224
 155 #define CFA_MONO_LPWT           0x228
 156
 157 /* RGB to RGB conversiona - 1st */
 158 #define RGB1_MUL_BASE           0x22c
 159 /* Offsets from base */
 160 #define RGB_MUL_RR              0x0
 161 #define RGB_MUL_GR              0x4
 162 #define RGB_MUL_BR              0x8
 163 #define RGB_MUL_RG              0xc
 164 #define RGB_MUL_GG              0x10
 165 #define RGB_MUL_BG              0x14
 166 #define RGB_MUL_RB              0x18
 167 #define RGB_MUL_GB              0x1c
 168 #define RGB_MUL_BB              0x20
 169 #define RGB_OFT_OR              0x24
 170 #define RGB_OFT_OG              0x28
 171 #define RGB_OFT_OB              0x2c
 172
 173 /* Gamma */
 174 #define GMM_CFG                 0x25c
 175
 176 /* RGB to RGB conversiona - 2nd */
 177 #define RGB2_MUL_BASE           0x260
 178
 179 /* 3D LUT */
 180 #define D3LUT_EN                0x290
 181
 182 /* RGB to YUV(YCbCr) conversion */
 183 #define YUV_ADJ                 0x294
 184 #define YUV_MUL_RY              0x298
 185 #define YUV_MUL_GY              0x29c
 186 #define YUV_MUL_BY              0x2a0
 187 #define YUV_MUL_RCB             0x2a4
 188 #define YUV_MUL_GCB             0x2a8
 189 #define YUV_MUL_BCB             0x2ac
 190 #define YUV_MUL_RCR             0x2b0
 191 #define YUV_MUL_GCR             0x2b4
 192 #define YUV_MUL_BCR             0x2b8
 193 #define YUV_OFT_Y               0x2bc
 194 #define YUV_OFT_CB              0x2c0
 195 #define YUV_OFT_CR              0x2c4
 196 #define YUV_PHS                 0x2c8
 197
 198 /* Global Brightness and Contrast */
 199 #define GBCE_EN                 0x2cc
 200 #define GBCE_TYP                0x2d0
 201
 202 /* Edge Enhancer */
 203 #define YEE_EN                  0x2d4
 204 #define YEE_TYP                 0x2d8
 205 #define YEE_SHF                 0x2dc
 206 #define YEE_MUL_00              0x2e0
 207 #define YEE_MUL_01              0x2e4
 208 #define YEE_MUL_02              0x2e8
 209 #define YEE_MUL_10              0x2ec
 210 #define YEE_MUL_11              0x2f0
 211 #define YEE_MUL_12              0x2f4
 212 #define YEE_MUL_20              0x2f8
 213 #define YEE_MUL_21              0x2fc
 214 #define YEE_MUL_22              0x300
 215 #define YEE_THR                 0x304
 216 #define YEE_E_GAN               0x308
 217 #define YEE_E_THR1              0x30c
 218 #define YEE_E_THR2              0x310
 219 #define YEE_G_GAN               0x314
 220 #define YEE_G_OFT               0x318
 221
 222 /* Chroma Artifact Reduction */
 223 #define CAR_EN                  0x31c
 224 #define CAR_TYP                 0x320
 225 #define CAR_SW                  0x324
 226 #define CAR_HPF_TYP             0x328
 227 #define CAR_HPF_SHF             0x32c
 228 #define CAR_HPF_THR             0x330
 229 #define CAR_GN1_GAN             0x334
 230 #define CAR_GN1_SHF             0x338
 231 #define CAR_GN1_MIN             0x33c
 232 #define CAR_GN2_GAN             0x340
 233 #define CAR_GN2_SHF             0x344
 234 #define CAR_GN2_MIN             0x348
 235
 236 /* Chroma Gain Suppression */
 237 #define CGS_EN                  0x34c
 238 #define CGS_GN1_L_THR           0x350
 239 #define CGS_GN1_L_GAN           0x354
 240 #define CGS_GN1_L_SHF           0x358
 241 #define CGS_GN1_L_MIN           0x35c
 242 #define CGS_GN1_H_THR           0x360
 243 #define CGS_GN1_H_GAN           0x364
 244 #define CGS_GN1_H_SHF           0x368
 245 #define CGS_GN1_H_MIN           0x36c
 246 #define CGS_GN2_L_THR           0x370
 247 #define CGS_GN2_L_GAN           0x374
 248 #define CGS_GN2_L_SHF           0x378
 249 #define CGS_GN2_L_MIN           0x37c
 250
 251 /* Resizer */
 252 #define RSZ_SRC_EN              0x0
 253 #define RSZ_SRC_MODE            0x4
 254 #define RSZ_SRC_FMT0            0x8
 255 #define RSZ_SRC_FMT1            0xc
 256 #define RSZ_SRC_VPS             0x10
 257 #define RSZ_SRC_VSZ             0x14
 258 #define RSZ_SRC_HPS             0x18
 259 #define RSZ_SRC_HSZ             0x1c
 260 #define RSZ_DMA_RZA             0x20
 261 #define RSZ_DMA_RZB             0x24
 262 #define RSZ_DMA_STA             0x28
 263 #define RSZ_GCK_MMR             0x2c
 264 #define RSZ_RESERVED0           0x30
 265 #define RSZ_GCK_SDR             0x34
 266 #define RSZ_IRQ_RZA             0x38
 267 #define RSZ_IRQ_RZB             0x3c
 268 #define RSZ_YUV_Y_MIN           0x40
 269 #define RSZ_YUV_Y_MAX           0x44
 270 #define RSZ_YUV_C_MIN           0x48
 271 #define RSZ_YUV_C_MAX           0x4c
 272 #define RSZ_YUV_PHS             0x50
 273 #define RSZ_SEQ                 0x54
 274
 275 /* Resizer Rescale Parameters */
 276 #define RSZ_EN_A                0x58
 277 #define RSZ_EN_B                0xe8
 278 /*
 279  * offset of the registers to be added with base register of
 280  * either RSZ0 or RSZ1
 281  */
 282 #define RSZ_MODE                0x4
 283 #define RSZ_420                 0x8
 284 #define RSZ_I_VPS               0xc
 285 #define RSZ_I_HPS               0x10
 286 #define RSZ_O_VSZ               0x14
 287 #define RSZ_O_HSZ               0x18
 288 #define RSZ_V_PHS_Y             0x1c
 289 #define RSZ_V_PHS_C             0x20
 290 #define RSZ_V_DIF               0x24
 291 #define RSZ_V_TYP               0x28
 292 #define RSZ_V_LPF               0x2c
 293 #define RSZ_H_PHS               0x30
 294 #define RSZ_H_PHS_ADJ           0x34
 295 #define RSZ_H_DIF               0x38
 296 #define RSZ_H_TYP               0x3c
 297 #define RSZ_H_LPF               0x40
 298 #define RSZ_DWN_EN              0x44
 299 #define RSZ_DWN_AV              0x48
 300
 301 /* Resizer RGB Conversion Parameters */
 302 #define RSZ_RGB_EN              0x4c
 303 #define RSZ_RGB_TYP             0x50
 304 #define RSZ_RGB_BLD             0x54
 305
 306 /* Resizer External Memory Parameters */
 307 #define RSZ_SDR_Y_BAD_H         0x58
 308 #define RSZ_SDR_Y_BAD_L         0x5c
 309 #define RSZ_SDR_Y_SAD_H         0x60
 310 #define RSZ_SDR_Y_SAD_L         0x64
 311 #define RSZ_SDR_Y_OFT           0x68
 312 #define RSZ_SDR_Y_PTR_S         0x6c
 313 #define RSZ_SDR_Y_PTR_E         0x70
 314 #define RSZ_SDR_C_BAD_H         0x74
 315 #define RSZ_SDR_C_BAD_L         0x78
 316 #define RSZ_SDR_C_SAD_H         0x7c
 317 #define RSZ_SDR_C_SAD_L         0x80
 318 #define RSZ_SDR_C_OFT           0x84
 319 #define RSZ_SDR_C_PTR_S         0x88
 320 #define RSZ_SDR_C_PTR_E         0x8c
 321
 322 /* Macro for resizer */
 323 #define RSZ_YUV_Y_MIN           0x40
 324 #define RSZ_YUV_Y_MAX           0x44
 325 #define RSZ_YUV_C_MIN           0x48
 326 #define RSZ_YUV_C_MAX           0x4c
 327
 328 #define IPIPE_GCK_MMR_DEFAULT   1
 329 #define IPIPE_GCK_PIX_DEFAULT   0xe
 330 #define RSZ_GCK_MMR_DEFAULT     1
 331 #define RSZ_GCK_SDR_DEFAULT     1
 332
 333 /* LUTDPC */
 334 #define LUTDPC_TBL_256_EN       0
 335 #define LUTDPC_INF_TBL_EN       1
 336 #define LUT_DPC_START_ADDR      0
 337 #define LUT_DPC_H_POS_MASK      0x1fff
 338 #define LUT_DPC_V_POS_MASK      0x1fff
 339 #define LUT_DPC_V_POS_SHIFT     13
 340 #define LUT_DPC_CORR_METH_SHIFT 26
 341 #define LUT_DPC_MAX_SIZE        256
 342 #define LUT_DPC_SIZE_MASK       0x3ff
 343
 344 /* OTFDPC */
 345 #define OTFDPC_DPC2_THR_MASK    0xfff
 346 #define OTF_DET_METHOD_SHIFT    1
 347 #define OTF_DPC3_0_SHF_MASK     3
 348 #define OTF_DPC3_0_THR_SHIFT    6
 349 #define OTF_DPC3_0_THR_MASK     0x3f
 350 #define OTF_DPC3_0_SLP_MASK     0x3f
 351 #define OTF_DPC3_0_DET_MASK     0xfff
 352 #define OTF_DPC3_0_CORR_MASK    0xfff
 353
 354 /* NF (D2F) */
 355 #define D2F_SPR_VAL_MASK                0x1f
 356 #define D2F_SPR_VAL_SHIFT               0
 357 #define D2F_SHFT_VAL_MASK               3
 358 #define D2F_SHFT_VAL_SHIFT              5
 359 #define D2F_SAMPLE_METH_SHIFT           7
 360 #define D2F_APPLY_LSC_GAIN_SHIFT        8
 361 #define D2F_USE_SPR_REG_VAL             0
 362 #define D2F_STR_VAL_MASK                0x1f
 363 #define D2F_THR_VAL_MASK                0x3ff
 364 #define D2F_EDGE_DET_THR_MASK           0x7ff
 365
 366 /* Green Imbalance Correction */
 367 #define GIC_TYP_SHIFT                   0
 368 #define GIC_THR_SEL_SHIFT               1
 369 #define GIC_APPLY_LSC_GAIN_SHIFT        2
 370 #define GIC_GAIN_MASK                   0xff
 371 #define GIC_THR_MASK                    0xfff
 372 #define GIC_SLOPE_MASK                  0xfff
 373 #define GIC_NFGAN_INT_MASK              7
 374 #define GIC_NFGAN_DECI_MASK             0x1f
 375
 376 /* WB */
 377 #define WB_OFFSET_MASK                  0xfff
 378 #define WB_GAIN_INT_MASK                0xf
 379 #define WB_GAIN_DECI_MASK               0x1ff
 380
 381 /* CFA */
 382 #define CFA_HPF_THR_2DIR_MASK           0x1fff
 383 #define CFA_HPF_SLOPE_2DIR_MASK         0x3ff
 384 #define CFA_HPF_MIX_THR_2DIR_MASK       0x1fff
 385 #define CFA_HPF_MIX_SLP_2DIR_MASK       0x3ff
 386 #define CFA_DIR_THR_2DIR_MASK           0x3ff
 387 #define CFA_DIR_SLP_2DIR_MASK           0x7f
 388 #define CFA_ND_WT_2DIR_MASK             0x3f
 389 #define CFA_DAA_HUE_FRA_MASK            0x3f
 390 #define CFA_DAA_EDG_THR_MASK            0xff
 391 #define CFA_DAA_THR_MIN_MASK            0x3ff
 392 #define CFA_DAA_THR_SLP_MASK            0x3ff
 393 #define CFA_DAA_SLP_MIN_MASK            0x3ff
 394 #define CFA_DAA_SLP_SLP_MASK            0x3ff
 395 #define CFA_DAA_LP_WT_MASK              0x3f
 396
 397 /* RGB2RGB */
 398 #define RGB2RGB_1_OFST_MASK             0x1fff
 399 #define RGB2RGB_1_GAIN_INT_MASK         0xf
 400 #define RGB2RGB_GAIN_DECI_MASK          0xff
 401 #define RGB2RGB_2_OFST_MASK             0x7ff
 402 #define RGB2RGB_2_GAIN_INT_MASK         0x7
 403
 404 /* Gamma */
 405 #define GAMMA_BYPR_SHIFT                0
 406 #define GAMMA_BYPG_SHIFT                1
 407 #define GAMMA_BYPB_SHIFT                2
 408 #define GAMMA_TBL_SEL_SHIFT             4
 409 #define GAMMA_TBL_SIZE_SHIFT            5
 410 #define GAMMA_MASK                      0x3ff
 411 #define GAMMA_SHIFT                     10
 412
 413 /* 3D LUT */
 414 #define D3_LUT_ENTRY_MASK               0x3ff
 415 #define D3_LUT_ENTRY_R_SHIFT            20
 416 #define D3_LUT_ENTRY_G_SHIFT            10
 417 #define D3_LUT_ENTRY_B_SHIFT            0
 418
 419 /* Lumina adj */
 420 #define LUM_ADJ_CONTR_SHIFT             0
 421 #define LUM_ADJ_BRIGHT_SHIFT            8
 422
 423 /* RGB2YCbCr */
 424 #define RGB2YCBCR_OFST_MASK             0x7ff
 425 #define RGB2YCBCR_COEF_INT_MASK         0xf
 426 #define RGB2YCBCR_COEF_DECI_MASK        0xff
 427
 428 /* GBCE */
 429 #define GBCE_Y_VAL_MASK                 0xff
 430 #define GBCE_GAIN_VAL_MASK              0x3ff
 431 #define GBCE_ENTRY_SHIFT                10
 432
 433 /* Edge Enhancements */
 434 #define YEE_HALO_RED_EN_SHIFT           1
 435 #define YEE_HPF_SHIFT_MASK              0xf
 436 #define YEE_COEF_MASK                   0x3ff
 437 #define YEE_THR_MASK                    0x3f
 438 #define YEE_ES_GAIN_MASK                0xfff
 439 #define YEE_ES_THR1_MASK                0xfff
 440 #define YEE_ENTRY_SHIFT                 9
 441 #define YEE_ENTRY_MASK                  0x1ff
 442
 443 /* CAR */
 444 #define CAR_MF_THR                      0xff
 445 #define CAR_SW1_SHIFT                   8
 446 #define CAR_GAIN1_SHFT_MASK             7
 447 #define CAR_GAIN_MIN_MASK               0x1ff
 448 #define CAR_GAIN2_SHFT_MASK             0xf
 449 #define CAR_HPF_SHIFT_MASK              3
 450
 451 /* CGS */
 452 #define CAR_SHIFT_MASK                  3
 453
 454 /* Resizer */
 455 #define RSZ_BYPASS_SHIFT                1
 456 #define RSZ_SRC_IMG_FMT_SHIFT           1
 457 #define RSZ_SRC_Y_C_SEL_SHIFT           2
 458 #define IPIPE_RSZ_VPS_MASK              0xffff
 459 #define IPIPE_RSZ_HPS_MASK              0xffff
 460 #define IPIPE_RSZ_VSZ_MASK              0x1fff
 461 #define IPIPE_RSZ_HSZ_MASK              0x1fff
 462 #define RSZ_HPS_MASK                    0x1fff
 463 #define RSZ_VPS_MASK                    0x1fff
 464 #define RSZ_O_HSZ_MASK                  0x1fff
 465 #define RSZ_O_VSZ_MASK                  0x1fff
 466 #define RSZ_V_PHS_MASK                  0x3fff
 467 #define RSZ_V_DIF_MASK                  0x3fff
 468
 469 #define RSZA_H_FLIP_SHIFT               0
 470 #define RSZA_V_FLIP_SHIFT               1
 471 #define RSZB_H_FLIP_SHIFT               2
 472 #define RSZB_V_FLIP_SHIFT               3
 473 #define RSZ_A                           0
 474 #define RSZ_B                           1
 475 #define RSZ_CEN_SHIFT                   1
 476 #define RSZ_YEN_SHIFT                   0
 477 #define RSZ_TYP_Y_SHIFT                 0
 478 #define RSZ_TYP_C_SHIFT                 1
 479 #define RSZ_LPF_INT_MASK                0x3f
 480 #define RSZ_LPF_INT_C_SHIFT             6
 481 #define RSZ_H_PHS_MASK                  0x3fff
 482 #define RSZ_H_DIF_MASK                  0x3fff
 483 #define RSZ_DIFF_DOWN_THR               256
 484 #define RSZ_DWN_SCALE_AV_SZ_V_SHIFT     3
 485 #define RSZ_DWN_SCALE_AV_SZ_MASK        7
 486 #define RSZ_RGB_MSK1_SHIFT              2
 487 #define RSZ_RGB_MSK0_SHIFT              1
 488 #define RSZ_RGB_TYP_SHIFT               0
 489 #define RSZ_RGB_ALPHA_MASK              0xff
 490
 491 static inline u32 regr_ip(void __iomem *addr, u32 offset)
 492 {
 493         return readl(addr + offset);
 494 }
 495
 496 static inline void regw_ip(void __iomem *addr, u32 val, u32 offset)
 497 {
 498         writel(val, addr + offset);
 499 }
 500
 501 static inline u32 w_ip_table(void __iomem *addr, u32 val, u32 offset)
 502 {
 503         writel(val, addr + offset);
 504
 505         return val;
 506 }
 507
 508 static inline u32 regr_rsz(void __iomem *addr, u32 offset)
 509 {
 510         return readl(addr + offset);
 511 }
 512
 513 static inline u32 regw_rsz(void __iomem *addr, u32 val, u32 offset)
 514 {
 515         writel(val, addr + offset);
 516
 517         return val;
 518 }
 519
 520 int config_ipipe_hw(struct vpfe_ipipe_device *ipipe);
 521 int resizer_set_outaddr(void __iomem *rsz_base, struct resizer_params *params,
 522                         int resize_no, unsigned int address);
 523 int rsz_enable(void __iomem *rsz_base, int rsz_id, int enable);
 524 void rsz_src_enable(void __iomem *rsz_base, int enable);
 525 void rsz_set_in_pix_format(unsigned char y_c);
 526 int config_rsz_hw(struct vpfe_resizer_device *resizer,
 527                   struct resizer_params *config);
 528 void ipipe_set_d2f_regs(void __iomem *base_addr, unsigned int id,
 529         struct vpfe_ipipe_nf *noise_filter);
 530 void ipipe_set_rgb2rgb_regs(void __iomem *base_addr, unsigned int id,
 531         struct vpfe_ipipe_rgb2rgb *rgb);
 532 void ipipe_set_yuv422_conv_regs(void __iomem *base_addr,
 533         struct vpfe_ipipe_yuv422_conv *conv);
 534 void ipipe_set_lum_adj_regs(void __iomem *base_addr,
 535         struct ipipe_lum_adj *lum_adj);
 536 void ipipe_set_rgb2ycbcr_regs(void __iomem *base_addr,
 537         struct vpfe_ipipe_rgb2yuv *yuv);
 538 void ipipe_set_lutdpc_regs(void __iomem *base_addr,
 539         void __iomem *isp5_base_addr, struct vpfe_ipipe_lutdpc *lutdpc);
 540 void ipipe_set_otfdpc_regs(void __iomem *base_addr,
 541         struct vpfe_ipipe_otfdpc *otfdpc);
 542 void ipipe_set_3d_lut_regs(void __iomem *base_addr,
 543         void __iomem *isp5_base_addr, struct vpfe_ipipe_3d_lut *lut_3d);
 544 void ipipe_set_gamma_regs(void __iomem *base_addr,
 545         void __iomem *isp5_base_addr, struct vpfe_ipipe_gamma *gamma);
 546 void ipipe_set_ee_regs(void __iomem *base_addr,
 547         void __iomem *isp5_base_addr, struct vpfe_ipipe_yee *ee);
 548 void ipipe_set_gbce_regs(void __iomem *base_addr,
 549         void __iomem *isp5_base_addr, struct vpfe_ipipe_gbce *gbce);
 550 void ipipe_set_gic_regs(void __iomem *base_addr, struct vpfe_ipipe_gic *gic);
 551 void ipipe_set_cfa_regs(void __iomem *base_addr, struct vpfe_ipipe_cfa *cfa);
 552 void ipipe_set_car_regs(void __iomem *base_addr, struct vpfe_ipipe_car *car);
 553 void ipipe_set_cgs_regs(void __iomem *base_addr, struct vpfe_ipipe_cgs *cgs);
 554 void ipipe_set_wb_regs(void __iomem *base_addr, struct vpfe_ipipe_wb *wb);
 555
 556 #endif          /* _DAVINCI_VPFE_DM365_IPIPE_HW_H */