drivers/staging/media/hantro/rk3399_vpu_hw.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Hantro VPU codec driver
   4  *
   5  * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
   6  *      Jeffy Chen <jeffy.chen@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10
  11 #include "hantro.h"
  12 #include "hantro_jpeg.h"
  13 #include "rk3399_vpu_regs.h"
  14
  15 #define RK3399_ACLK_MAX_FREQ (400 * 1000 * 1000)
  16
  17 /*
  18  * Supported formats.
  19  */
  20
  21 static const struct hantro_fmt rk3399_vpu_enc_fmts[] = {
  22         {
  23                 .fourcc = V4L2_PIX_FMT_YUV420M,
  24                 .codec_mode = HANTRO_MODE_NONE,
  25                 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420P,
  26         },
  27         {
  28                 .fourcc = V4L2_PIX_FMT_NV12M,
  29                 .codec_mode = HANTRO_MODE_NONE,
  30                 .enc_fmt = RK3288_VPU_ENC_FMT_YUV420SP,
  31         },
  32         {
  33                 .fourcc = V4L2_PIX_FMT_YUYV,
  34                 .codec_mode = HANTRO_MODE_NONE,
  35                 .enc_fmt = RK3288_VPU_ENC_FMT_YUYV422,
  36         },
  37         {
  38                 .fourcc = V4L2_PIX_FMT_UYVY,
  39                 .codec_mode = HANTRO_MODE_NONE,
  40                 .enc_fmt = RK3288_VPU_ENC_FMT_UYVY422,
  41         },
  42         {
  43                 .fourcc = V4L2_PIX_FMT_JPEG,
  44                 .codec_mode = HANTRO_MODE_JPEG_ENC,
  45                 .max_depth = 2,
  46                 .header_size = JPEG_HEADER_SIZE,
  47                 .frmsize = {
  48                         .min_width = 96,
  49                         .max_width = 8192,
  50                         .step_width = JPEG_MB_DIM,
  51                         .min_height = 32,
  52                         .max_height = 8192,
  53                         .step_height = JPEG_MB_DIM,
  54                 },
  55         },
  56 };
  57
  58 static const struct hantro_fmt rk3399_vpu_dec_fmts[] = {
  59         {
  60                 .fourcc = V4L2_PIX_FMT_NV12,
  61                 .codec_mode = HANTRO_MODE_NONE,
  62         },
  63         {
  64                 .fourcc = V4L2_PIX_FMT_MPEG2_SLICE,
  65                 .codec_mode = HANTRO_MODE_MPEG2_DEC,
  66                 .max_depth = 2,
  67                 .frmsize = {
  68                         .min_width = 48,
  69                         .max_width = 1920,
  70                         .step_width = MPEG2_MB_DIM,
  71                         .min_height = 48,
  72                         .max_height = 1088,
  73                         .step_height = MPEG2_MB_DIM,
  74                 },
  75         },
  76 };
  77
  78 static irqreturn_t rk3399_vepu_irq(int irq, void *dev_id)
  79 {
  80         struct hantro_dev *vpu = dev_id;
  81         enum vb2_buffer_state state;
  82         u32 status, bytesused;
  83
  84         status = vepu_read(vpu, VEPU_REG_INTERRUPT);
  85         bytesused = vepu_read(vpu, VEPU_REG_STR_BUF_LIMIT) / 8;
  86         state = (status & VEPU_REG_INTERRUPT_FRAME_READY) ?
  87                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
  88
  89         vepu_write(vpu, 0, VEPU_REG_INTERRUPT);
  90         vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
  91
  92         hantro_irq_done(vpu, bytesused, state);
  93
  94         return IRQ_HANDLED;
  95 }
  96
  97 static irqreturn_t rk3399_vdpu_irq(int irq, void *dev_id)
  98 {
  99         struct hantro_dev *vpu = dev_id;
 100         enum vb2_buffer_state state;
 101         u32 status;
 102
 103         status = vdpu_read(vpu, VDPU_REG_INTERRUPT);
 104         state = (status & VDPU_REG_INTERRUPT_DEC_IRQ) ?
 105                 VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR;
 106
 107         vdpu_write(vpu, 0, VDPU_REG_INTERRUPT);
 108         vdpu_write(vpu, 0, VDPU_REG_AXI_CTRL);
 109
 110         hantro_irq_done(vpu, 0, state);
 111
 112         return IRQ_HANDLED;
 113 }
 114
 115 static int rk3399_vpu_hw_init(struct hantro_dev *vpu)
 116 {
 117         /* Bump ACLK to max. possible freq. to improve performance. */
 118         clk_set_rate(vpu->clocks[0].clk, RK3399_ACLK_MAX_FREQ);
 119         return 0;
 120 }
 121
 122 static void rk3399_vpu_enc_reset(struct hantro_ctx *ctx)
 123 {
 124         struct hantro_dev *vpu = ctx->dev;
 125
 126         vepu_write(vpu, VEPU_REG_INTERRUPT_DIS_BIT, VEPU_REG_INTERRUPT);
 127         vepu_write(vpu, 0, VEPU_REG_ENCODE_START);
 128         vepu_write(vpu, 0, VEPU_REG_AXI_CTRL);
 129 }
 130
 131 static void rk3399_vpu_dec_reset(struct hantro_ctx *ctx)
 132 {
 133         struct hantro_dev *vpu = ctx->dev;
 134
 135         vdpu_write(vpu, VDPU_REG_INTERRUPT_DEC_IRQ_DIS, VDPU_REG_INTERRUPT);
 136         vdpu_write(vpu, 0, VDPU_REG_EN_FLAGS);
 137         vdpu_write(vpu, 1, VDPU_REG_SOFT_RESET);
 138 }
 139
 140 /*
 141  * Supported codec ops.
 142  */
 143
 144 static const struct hantro_codec_ops rk3399_vpu_codec_ops[] = {
 145         [HANTRO_MODE_JPEG_ENC] = {
 146                 .run = rk3399_vpu_jpeg_enc_run,
 147                 .reset = rk3399_vpu_enc_reset,
 148                 .init = hantro_jpeg_enc_init,
 149                 .exit = hantro_jpeg_enc_exit,
 150         },
 151         [HANTRO_MODE_MPEG2_DEC] = {
 152                 .run = rk3399_vpu_mpeg2_dec_run,
 153                 .reset = rk3399_vpu_dec_reset,
 154                 .init = hantro_mpeg2_dec_init,
 155                 .exit = hantro_mpeg2_dec_exit,
 156         },
 157 };
 158
 159 /*
 160  * VPU variant.
 161  */
 162
 163 static const struct hantro_irq rk3399_irqs[] = {
 164         { "vepu", rk3399_vepu_irq },
 165         { "vdpu", rk3399_vdpu_irq },
 166 };
 167
 168 static const char * const rk3399_clk_names[] = {
 169         "aclk", "hclk"
 170 };
 171
 172 const struct hantro_variant rk3399_vpu_variant = {
 173         .enc_offset = 0x0,
 174         .enc_fmts = rk3399_vpu_enc_fmts,
 175         .num_enc_fmts = ARRAY_SIZE(rk3399_vpu_enc_fmts),
 176         .dec_offset = 0x400,
 177         .dec_fmts = rk3399_vpu_dec_fmts,
 178         .num_dec_fmts = ARRAY_SIZE(rk3399_vpu_dec_fmts),
 179         .codec = HANTRO_JPEG_ENCODER | HANTRO_MPEG2_DECODER,
 180         .codec_ops = rk3399_vpu_codec_ops,
 181         .irqs = rk3399_irqs,
 182         .num_irqs = ARRAY_SIZE(rk3399_irqs),
 183         .init = rk3399_vpu_hw_init,
 184         .clk_names = rk3399_clk_names,
 185         .num_clocks = ARRAY_SIZE(rk3399_clk_names)
 186 };