1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 - 2018 Intel Corporation
4 * Copyright 2017 Google LLC
6 * Based on Intel IPU4 driver.
10 #include <linux/delay.h>
11 #include <linux/interrupt.h>
12 #include <linux/module.h>
13 #include <linux/pm_runtime.h>
16 #include "ipu3-dmamap.h"
19 #define IMGU_PCI_ID 0x1919
20 #define IMGU_PCI_BAR 0
21 #define IMGU_DMA_MASK DMA_BIT_MASK(39)
22 #define IMGU_MAX_QUEUE_DEPTH (2 + 2)
25 * pre-allocated buffer size for IMGU dummy buffers. Those
26 * values should be tuned to big enough to avoid buffer
27 * re-allocation when streaming to lower streaming latency.
29 #define CSS_QUEUE_IN_BUF_SIZE 0
30 #define CSS_QUEUE_PARAMS_BUF_SIZE 0
31 #define CSS_QUEUE_OUT_BUF_SIZE (4160 * 3120 * 12 / 8)
32 #define CSS_QUEUE_VF_BUF_SIZE (1920 * 1080 * 12 / 8)
33 #define CSS_QUEUE_STAT_3A_BUF_SIZE sizeof(struct ipu3_uapi_stats_3a)
35 static const size_t css_queue_buf_size_map[IPU3_CSS_QUEUES] = {
36 [IPU3_CSS_QUEUE_IN] = CSS_QUEUE_IN_BUF_SIZE,
37 [IPU3_CSS_QUEUE_PARAMS] = CSS_QUEUE_PARAMS_BUF_SIZE,
38 [IPU3_CSS_QUEUE_OUT] = CSS_QUEUE_OUT_BUF_SIZE,
39 [IPU3_CSS_QUEUE_VF] = CSS_QUEUE_VF_BUF_SIZE,
40 [IPU3_CSS_QUEUE_STAT_3A] = CSS_QUEUE_STAT_3A_BUF_SIZE,
43 static const struct imgu_node_mapping imgu_node_map[IMGU_NODE_NUM] = {
44 [IMGU_NODE_IN] = {IPU3_CSS_QUEUE_IN, "input"},
45 [IMGU_NODE_PARAMS] = {IPU3_CSS_QUEUE_PARAMS, "parameters"},
46 [IMGU_NODE_OUT] = {IPU3_CSS_QUEUE_OUT, "output"},
47 [IMGU_NODE_VF] = {IPU3_CSS_QUEUE_VF, "viewfinder"},
48 [IMGU_NODE_STAT_3A] = {IPU3_CSS_QUEUE_STAT_3A, "3a stat"},
51 unsigned int imgu_node_to_queue(unsigned int node)
53 return imgu_node_map[node].css_queue;
56 unsigned int imgu_map_node(struct imgu_device *imgu, unsigned int css_queue)
60 for (i = 0; i < IMGU_NODE_NUM; i++)
61 if (imgu_node_map[i].css_queue == css_queue)
67 /**************** Dummy buffers ****************/
69 static void imgu_dummybufs_cleanup(struct imgu_device *imgu, unsigned int pipe)
72 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
74 for (i = 0; i < IPU3_CSS_QUEUES; i++)
75 ipu3_dmamap_free(imgu,
76 &imgu_pipe->queues[i].dmap);
79 static int imgu_dummybufs_preallocate(struct imgu_device *imgu,
84 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
86 for (i = 0; i < IPU3_CSS_QUEUES; i++) {
87 size = css_queue_buf_size_map[i];
89 * Do not enable dummy buffers for master queue,
90 * always require that real buffers from user are
93 if (i == IMGU_QUEUE_MASTER || size == 0)
96 if (!ipu3_dmamap_alloc(imgu,
97 &imgu_pipe->queues[i].dmap, size)) {
98 imgu_dummybufs_cleanup(imgu, pipe);
106 static int imgu_dummybufs_init(struct imgu_device *imgu, unsigned int pipe)
108 const struct v4l2_pix_format_mplane *mpix;
109 const struct v4l2_meta_format *meta;
110 unsigned int i, k, node;
112 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
114 /* Allocate a dummy buffer for each queue where buffer is optional */
115 for (i = 0; i < IPU3_CSS_QUEUES; i++) {
116 node = imgu_map_node(imgu, i);
117 if (!imgu_pipe->queue_enabled[node] || i == IMGU_QUEUE_MASTER)
120 if (!imgu_pipe->nodes[IMGU_NODE_VF].enabled &&
121 i == IPU3_CSS_QUEUE_VF)
123 * Do not enable dummy buffers for VF if it is not
124 * requested by the user.
128 meta = &imgu_pipe->nodes[node].vdev_fmt.fmt.meta;
129 mpix = &imgu_pipe->nodes[node].vdev_fmt.fmt.pix_mp;
131 if (node == IMGU_NODE_STAT_3A || node == IMGU_NODE_PARAMS)
132 size = meta->buffersize;
134 size = mpix->plane_fmt[0].sizeimage;
136 if (ipu3_css_dma_buffer_resize(imgu,
137 &imgu_pipe->queues[i].dmap,
139 imgu_dummybufs_cleanup(imgu, pipe);
143 for (k = 0; k < IMGU_MAX_QUEUE_DEPTH; k++)
144 ipu3_css_buf_init(&imgu_pipe->queues[i].dummybufs[k], i,
145 imgu_pipe->queues[i].dmap.daddr);
151 /* May be called from atomic context */
152 static struct ipu3_css_buffer *imgu_dummybufs_get(struct imgu_device *imgu,
153 int queue, unsigned int pipe)
156 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
158 /* dummybufs are not allocated for master q */
159 if (queue == IPU3_CSS_QUEUE_IN)
162 if (WARN_ON(!imgu_pipe->queues[queue].dmap.vaddr))
163 /* Buffer should not be allocated here */
166 for (i = 0; i < IMGU_MAX_QUEUE_DEPTH; i++)
167 if (ipu3_css_buf_state(&imgu_pipe->queues[queue].dummybufs[i]) !=
168 IPU3_CSS_BUFFER_QUEUED)
171 if (i == IMGU_MAX_QUEUE_DEPTH)
174 ipu3_css_buf_init(&imgu_pipe->queues[queue].dummybufs[i], queue,
175 imgu_pipe->queues[queue].dmap.daddr);
177 return &imgu_pipe->queues[queue].dummybufs[i];
180 /* Check if given buffer is a dummy buffer */
181 static bool imgu_dummybufs_check(struct imgu_device *imgu,
182 struct ipu3_css_buffer *buf,
186 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
188 for (i = 0; i < IMGU_MAX_QUEUE_DEPTH; i++)
189 if (buf == &imgu_pipe->queues[buf->queue].dummybufs[i])
192 return i < IMGU_MAX_QUEUE_DEPTH;
195 static void imgu_buffer_done(struct imgu_device *imgu, struct vb2_buffer *vb,
196 enum vb2_buffer_state state)
198 mutex_lock(&imgu->lock);
199 imgu_v4l2_buffer_done(vb, state);
200 mutex_unlock(&imgu->lock);
203 static struct ipu3_css_buffer *imgu_queue_getbuf(struct imgu_device *imgu,
207 struct imgu_buffer *buf;
208 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
210 if (WARN_ON(node >= IMGU_NODE_NUM))
213 /* Find first free buffer from the node */
214 list_for_each_entry(buf, &imgu_pipe->nodes[node].buffers, vid_buf.list) {
215 if (ipu3_css_buf_state(&buf->css_buf) == IPU3_CSS_BUFFER_NEW)
216 return &buf->css_buf;
219 /* There were no free buffers, try to return a dummy buffer */
220 return imgu_dummybufs_get(imgu, imgu_node_map[node].css_queue, pipe);
224 * Queue as many buffers to CSS as possible. If all buffers don't fit into
225 * CSS buffer queues, they remain unqueued and will be queued later.
227 int imgu_queue_buffers(struct imgu_device *imgu, bool initial, unsigned int pipe)
231 struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
233 if (!ipu3_css_is_streaming(&imgu->css))
236 dev_dbg(&imgu->pci_dev->dev, "Queue buffers to pipe %d", pipe);
237 mutex_lock(&imgu->lock);
239 /* Buffer set is queued to FW only when input buffer is ready */
240 for (node = IMGU_NODE_NUM - 1;
241 imgu_queue_getbuf(imgu, IMGU_NODE_IN, pipe);
242 node = node ? node - 1 : IMGU_NODE_NUM - 1) {
244 if (node == IMGU_NODE_VF &&
245 !imgu_pipe->nodes[IMGU_NODE_VF].enabled) {
246 dev_warn(&imgu->pci_dev->dev,
247 "Vf not enabled, ignore queue");
249 } else if (imgu_pipe->queue_enabled[node]) {
250 struct ipu3_css_buffer *buf =
251 imgu_queue_getbuf(imgu, node, pipe);
252 struct imgu_buffer *ibuf = NULL;
258 r = ipu3_css_buf_queue(&imgu->css, pipe, buf);
261 dummy = imgu_dummybufs_check(imgu, buf, pipe);
263 ibuf = container_of(buf, struct imgu_buffer,
265 dev_dbg(&imgu->pci_dev->dev,
266 "queue %s %s buffer %u to css da: 0x%08x\n",
267 dummy ? "dummy" : "user",
268 imgu_node_map[node].name,
269 dummy ? 0 : ibuf->vid_buf.vbb.vb2_buf.index,
273 mutex_unlock(&imgu->lock);
275 if (r && r != -EBUSY)
282 * On error, mark all buffers as failed which are not
285 dev_err(&imgu->pci_dev->dev,
286 "failed to queue buffer to CSS on queue %i (%d)\n",
290 /* If we were called from streamon(), no need to finish bufs */
293 for (node = 0; node < IMGU_NODE_NUM; node++) {
294 struct imgu_buffer *buf, *buf0;
296 if (!imgu_pipe->queue_enabled[node])
297 continue; /* Skip disabled queues */
299 mutex_lock(&imgu->lock);
300 list_for_each_entry_safe(buf, buf0,
301 &imgu_pipe->nodes[node].buffers,
303 if (ipu3_css_buf_state(&buf->css_buf) ==
304 IPU3_CSS_BUFFER_QUEUED)
305 continue; /* Was already queued, skip */
307 imgu_v4l2_buffer_done(&buf->vid_buf.vbb.vb2_buf,
308 VB2_BUF_STATE_ERROR);
310 mutex_unlock(&imgu->lock);
316 static int imgu_powerup(struct imgu_device *imgu)
320 r = ipu3_css_set_powerup(&imgu->pci_dev->dev, imgu->base);
324 ipu3_mmu_resume(imgu->mmu);
328 static void imgu_powerdown(struct imgu_device *imgu)
330 ipu3_mmu_suspend(imgu->mmu);
331 ipu3_css_set_powerdown(&imgu->pci_dev->dev, imgu->base);
334 int imgu_s_stream(struct imgu_device *imgu, int enable)
336 struct device *dev = &imgu->pci_dev->dev;
341 dev_dbg(dev, "stream off\n");
342 /* Block new buffers to be queued to CSS. */
343 atomic_set(&imgu->qbuf_barrier, 1);
344 ipu3_css_stop_streaming(&imgu->css);
345 synchronize_irq(imgu->pci_dev->irq);
346 atomic_set(&imgu->qbuf_barrier, 0);
347 imgu_powerdown(imgu);
348 pm_runtime_put(&imgu->pci_dev->dev);
354 r = pm_runtime_get_sync(dev);
356 dev_err(dev, "failed to set imgu power\n");
361 r = imgu_powerup(imgu);
363 dev_err(dev, "failed to power up imgu\n");
368 /* Start CSS streaming */
369 r = ipu3_css_start_streaming(&imgu->css);
371 dev_err(dev, "failed to start css streaming (%d)", r);
372 goto fail_start_streaming;
375 for_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM) {
376 /* Initialize dummy buffers */
377 r = imgu_dummybufs_init(imgu, pipe);
379 dev_err(dev, "failed to initialize dummy buffers (%d)", r);
383 /* Queue as many buffers from queue as possible */
384 r = imgu_queue_buffers(imgu, true, pipe);
386 dev_err(dev, "failed to queue initial buffers (%d)", r);
393 for_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM)
394 imgu_dummybufs_cleanup(imgu, pipe);
396 ipu3_css_stop_streaming(&imgu->css);
397 fail_start_streaming:
403 static int imgu_video_nodes_init(struct imgu_device *imgu)
405 struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES] = { NULL };
406 struct v4l2_rect *rects[IPU3_CSS_RECTS] = { NULL };
407 struct imgu_media_pipe *imgu_pipe;
411 imgu->buf_struct_size = sizeof(struct imgu_buffer);
413 for (j = 0; j < IMGU_MAX_PIPE_NUM; j++) {
414 imgu_pipe = &imgu->imgu_pipe[j];
416 for (i = 0; i < IMGU_NODE_NUM; i++) {
417 imgu_pipe->nodes[i].name = imgu_node_map[i].name;
418 imgu_pipe->nodes[i].output = i < IMGU_QUEUE_FIRST_INPUT;
419 imgu_pipe->nodes[i].enabled = false;
421 if (i != IMGU_NODE_PARAMS && i != IMGU_NODE_STAT_3A)
422 fmts[imgu_node_map[i].css_queue] =
423 &imgu_pipe->nodes[i].vdev_fmt.fmt.pix_mp;
424 atomic_set(&imgu_pipe->nodes[i].sequence, 0);
428 r = imgu_v4l2_register(imgu);
432 /* Set initial formats and initialize formats of video nodes */
433 for (j = 0; j < IMGU_MAX_PIPE_NUM; j++) {
434 imgu_pipe = &imgu->imgu_pipe[j];
436 rects[IPU3_CSS_RECT_EFFECTIVE] = &imgu_pipe->imgu_sd.rect.eff;
437 rects[IPU3_CSS_RECT_BDS] = &imgu_pipe->imgu_sd.rect.bds;
438 ipu3_css_fmt_set(&imgu->css, fmts, rects, j);
440 /* Pre-allocate dummy buffers */
441 r = imgu_dummybufs_preallocate(imgu, j);
443 dev_err(&imgu->pci_dev->dev,
444 "failed to pre-allocate dummy buffers (%d)", r);
452 for (j = 0; j < IMGU_MAX_PIPE_NUM; j++)
453 imgu_dummybufs_cleanup(imgu, j);
455 imgu_v4l2_unregister(imgu);
460 static void imgu_video_nodes_exit(struct imgu_device *imgu)
464 for (i = 0; i < IMGU_MAX_PIPE_NUM; i++)
465 imgu_dummybufs_cleanup(imgu, i);
467 imgu_v4l2_unregister(imgu);
470 /**************** PCI interface ****************/
472 static irqreturn_t imgu_isr_threaded(int irq, void *imgu_ptr)
474 struct imgu_device *imgu = imgu_ptr;
475 struct imgu_media_pipe *imgu_pipe;
478 /* Dequeue / queue buffers */
480 u64 ns = ktime_get_ns();
481 struct ipu3_css_buffer *b;
482 struct imgu_buffer *buf = NULL;
483 unsigned int node, pipe;
487 mutex_lock(&imgu->lock);
488 b = ipu3_css_buf_dequeue(&imgu->css);
489 mutex_unlock(&imgu->lock);
490 } while (PTR_ERR(b) == -EAGAIN);
493 if (PTR_ERR(b) != -EBUSY) /* All done */
494 dev_err(&imgu->pci_dev->dev,
495 "failed to dequeue buffers (%ld)\n",
500 node = imgu_map_node(imgu, b->queue);
502 dummy = imgu_dummybufs_check(imgu, b, pipe);
504 buf = container_of(b, struct imgu_buffer, css_buf);
505 dev_dbg(&imgu->pci_dev->dev,
506 "dequeue %s %s buffer %d daddr 0x%x from css\n",
507 dummy ? "dummy" : "user",
508 imgu_node_map[node].name,
509 dummy ? 0 : buf->vid_buf.vbb.vb2_buf.index,
513 /* It was a dummy buffer, skip it */
516 /* Fill vb2 buffer entries and tell it's ready */
517 imgu_pipe = &imgu->imgu_pipe[pipe];
518 if (!imgu_pipe->nodes[node].output) {
519 buf->vid_buf.vbb.vb2_buf.timestamp = ns;
520 buf->vid_buf.vbb.field = V4L2_FIELD_NONE;
521 buf->vid_buf.vbb.sequence =
523 &imgu_pipe->nodes[node].sequence);
524 dev_dbg(&imgu->pci_dev->dev, "vb2 buffer sequence %d",
525 buf->vid_buf.vbb.sequence);
527 imgu_buffer_done(imgu, &buf->vid_buf.vbb.vb2_buf,
528 ipu3_css_buf_state(&buf->css_buf) ==
529 IPU3_CSS_BUFFER_DONE ?
531 VB2_BUF_STATE_ERROR);
532 mutex_lock(&imgu->lock);
533 if (ipu3_css_queue_empty(&imgu->css))
534 wake_up_all(&imgu->buf_drain_wq);
535 mutex_unlock(&imgu->lock);
539 * Try to queue more buffers for CSS.
540 * qbuf_barrier is used to disable new buffers
541 * to be queued to CSS.
543 if (!atomic_read(&imgu->qbuf_barrier))
544 for_each_set_bit(p, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM)
545 imgu_queue_buffers(imgu, false, p);
550 static irqreturn_t imgu_isr(int irq, void *imgu_ptr)
552 struct imgu_device *imgu = imgu_ptr;
554 /* acknowledge interruption */
555 if (ipu3_css_irq_ack(&imgu->css) < 0)
558 return IRQ_WAKE_THREAD;
561 static int imgu_pci_config_setup(struct pci_dev *dev)
564 int r = pci_enable_msi(dev);
567 dev_err(&dev->dev, "failed to enable MSI (%d)\n", r);
571 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
572 pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
573 PCI_COMMAND_INTX_DISABLE;
574 pci_write_config_word(dev, PCI_COMMAND, pci_command);
579 static int imgu_pci_probe(struct pci_dev *pci_dev,
580 const struct pci_device_id *id)
582 struct imgu_device *imgu;
584 unsigned long phys_len;
585 void __iomem *const *iomap;
588 imgu = devm_kzalloc(&pci_dev->dev, sizeof(*imgu), GFP_KERNEL);
592 imgu->pci_dev = pci_dev;
594 r = pcim_enable_device(pci_dev);
596 dev_err(&pci_dev->dev, "failed to enable device (%d)\n", r);
600 dev_info(&pci_dev->dev, "device 0x%x (rev: 0x%x)\n",
601 pci_dev->device, pci_dev->revision);
603 phys = pci_resource_start(pci_dev, IMGU_PCI_BAR);
604 phys_len = pci_resource_len(pci_dev, IMGU_PCI_BAR);
606 r = pcim_iomap_regions(pci_dev, 1 << IMGU_PCI_BAR, pci_name(pci_dev));
608 dev_err(&pci_dev->dev, "failed to remap I/O memory (%d)\n", r);
611 dev_info(&pci_dev->dev, "physical base address %pap, %lu bytes\n",
614 iomap = pcim_iomap_table(pci_dev);
616 dev_err(&pci_dev->dev, "failed to iomap table\n");
620 imgu->base = iomap[IMGU_PCI_BAR];
622 pci_set_drvdata(pci_dev, imgu);
624 pci_set_master(pci_dev);
626 r = dma_coerce_mask_and_coherent(&pci_dev->dev, IMGU_DMA_MASK);
628 dev_err(&pci_dev->dev, "failed to set DMA mask (%d)\n", r);
632 r = imgu_pci_config_setup(pci_dev);
636 mutex_init(&imgu->lock);
637 atomic_set(&imgu->qbuf_barrier, 0);
638 init_waitqueue_head(&imgu->buf_drain_wq);
640 r = ipu3_css_set_powerup(&pci_dev->dev, imgu->base);
642 dev_err(&pci_dev->dev,
643 "failed to power up CSS (%d)\n", r);
644 goto out_mutex_destroy;
647 imgu->mmu = ipu3_mmu_init(&pci_dev->dev, imgu->base);
648 if (IS_ERR(imgu->mmu)) {
649 r = PTR_ERR(imgu->mmu);
650 dev_err(&pci_dev->dev, "failed to initialize MMU (%d)\n", r);
651 goto out_css_powerdown;
654 r = ipu3_dmamap_init(imgu);
656 dev_err(&pci_dev->dev,
657 "failed to initialize DMA mapping (%d)\n", r);
661 /* ISP programming */
662 r = ipu3_css_init(&pci_dev->dev, &imgu->css, imgu->base, phys_len);
664 dev_err(&pci_dev->dev, "failed to initialize CSS (%d)\n", r);
665 goto out_dmamap_exit;
668 /* v4l2 sub-device registration */
669 r = imgu_video_nodes_init(imgu);
671 dev_err(&pci_dev->dev, "failed to create V4L2 devices (%d)\n",
673 goto out_css_cleanup;
676 r = devm_request_threaded_irq(&pci_dev->dev, pci_dev->irq,
677 imgu_isr, imgu_isr_threaded,
678 IRQF_SHARED, IMGU_NAME, imgu);
680 dev_err(&pci_dev->dev, "failed to request IRQ (%d)\n", r);
684 pm_runtime_put_noidle(&pci_dev->dev);
685 pm_runtime_allow(&pci_dev->dev);
690 imgu_video_nodes_exit(imgu);
692 ipu3_css_cleanup(&imgu->css);
694 ipu3_dmamap_exit(imgu);
696 ipu3_mmu_exit(imgu->mmu);
698 ipu3_css_set_powerdown(&pci_dev->dev, imgu->base);
700 mutex_destroy(&imgu->lock);
705 static void imgu_pci_remove(struct pci_dev *pci_dev)
707 struct imgu_device *imgu = pci_get_drvdata(pci_dev);
709 pm_runtime_forbid(&pci_dev->dev);
710 pm_runtime_get_noresume(&pci_dev->dev);
712 imgu_video_nodes_exit(imgu);
713 ipu3_css_cleanup(&imgu->css);
714 ipu3_css_set_powerdown(&pci_dev->dev, imgu->base);
715 ipu3_dmamap_exit(imgu);
716 ipu3_mmu_exit(imgu->mmu);
717 mutex_destroy(&imgu->lock);
720 static int __maybe_unused imgu_suspend(struct device *dev)
722 struct pci_dev *pci_dev = to_pci_dev(dev);
723 struct imgu_device *imgu = pci_get_drvdata(pci_dev);
725 dev_dbg(dev, "enter %s\n", __func__);
726 imgu->suspend_in_stream = ipu3_css_is_streaming(&imgu->css);
727 if (!imgu->suspend_in_stream)
729 /* Block new buffers to be queued to CSS. */
730 atomic_set(&imgu->qbuf_barrier, 1);
732 * Wait for currently running irq handler to be done so that
733 * no new buffers will be queued to fw later.
735 synchronize_irq(pci_dev->irq);
736 /* Wait until all buffers in CSS are done. */
737 if (!wait_event_timeout(imgu->buf_drain_wq,
738 ipu3_css_queue_empty(&imgu->css), msecs_to_jiffies(1000)))
739 dev_err(dev, "wait buffer drain timeout.\n");
741 ipu3_css_stop_streaming(&imgu->css);
742 atomic_set(&imgu->qbuf_barrier, 0);
743 imgu_powerdown(imgu);
744 pm_runtime_force_suspend(dev);
746 dev_dbg(dev, "leave %s\n", __func__);
750 static int __maybe_unused imgu_resume(struct device *dev)
752 struct pci_dev *pci_dev = to_pci_dev(dev);
753 struct imgu_device *imgu = pci_get_drvdata(pci_dev);
757 dev_dbg(dev, "enter %s\n", __func__);
759 if (!imgu->suspend_in_stream)
762 pm_runtime_force_resume(dev);
764 r = imgu_powerup(imgu);
766 dev_err(dev, "failed to power up imgu\n");
770 /* Start CSS streaming */
771 r = ipu3_css_start_streaming(&imgu->css);
773 dev_err(dev, "failed to resume css streaming (%d)", r);
777 for_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM) {
778 r = imgu_queue_buffers(imgu, true, pipe);
780 dev_err(dev, "failed to queue buffers to pipe %d (%d)",
785 dev_dbg(dev, "leave %s\n", __func__);
791 * PCI rpm framework checks the existence of driver rpm callbacks.
792 * Place a dummy callback here to avoid rpm going into error state.
794 static int imgu_rpm_dummy_cb(struct device *dev)
799 static const struct dev_pm_ops imgu_pm_ops = {
800 SET_RUNTIME_PM_OPS(&imgu_rpm_dummy_cb, &imgu_rpm_dummy_cb, NULL)
801 SET_SYSTEM_SLEEP_PM_OPS(&imgu_suspend, &imgu_resume)
804 static const struct pci_device_id imgu_pci_tbl[] = {
805 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, IMGU_PCI_ID) },
809 MODULE_DEVICE_TABLE(pci, imgu_pci_tbl);
811 static struct pci_driver imgu_pci_driver = {
813 .id_table = imgu_pci_tbl,
814 .probe = imgu_pci_probe,
815 .remove = imgu_pci_remove,
821 module_pci_driver(imgu_pci_driver);
823 MODULE_AUTHOR("Tuukka Toivonen <tuukka.toivonen@intel.com>");
824 MODULE_AUTHOR("Tianshu Qiu <tian.shu.qiu@intel.com>");
825 MODULE_AUTHOR("Jian Xu Zheng <jian.xu.zheng@intel.com>");
826 MODULE_AUTHOR("Yuning Pu <yuning.pu@intel.com>");
827 MODULE_AUTHOR("Yong Zhi <yong.zhi@intel.com>");
828 MODULE_LICENSE("GPL v2");
829 MODULE_DESCRIPTION("Intel ipu3_imgu PCI driver");