drivers/staging/media/ipu3/ipu3.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 - 2018 Intel Corporation
   4  * Copyright 2017 Google LLC
   5  *
   6  * Based on Intel IPU4 driver.
   7  *
   8  */
   9
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/module.h>
  13 #include <linux/pm_runtime.h>
  14
  15 #include "ipu3.h"
  16 #include "ipu3-dmamap.h"
  17 #include "ipu3-mmu.h"
  18
  19 #define IMGU_PCI_ID                     0x1919
  20 #define IMGU_PCI_BAR                    0
  21 #define IMGU_DMA_MASK                   DMA_BIT_MASK(39)
  22 #define IMGU_MAX_QUEUE_DEPTH            (2 + 2)
  23
  24 /*
  25  * pre-allocated buffer size for IMGU dummy buffers. Those
  26  * values should be tuned to big enough to avoid buffer
  27  * re-allocation when streaming to lower streaming latency.
  28  */
  29 #define CSS_QUEUE_IN_BUF_SIZE           0
  30 #define CSS_QUEUE_PARAMS_BUF_SIZE       0
  31 #define CSS_QUEUE_OUT_BUF_SIZE          (4160 * 3120 * 12 / 8)
  32 #define CSS_QUEUE_VF_BUF_SIZE           (1920 * 1080 * 12 / 8)
  33 #define CSS_QUEUE_STAT_3A_BUF_SIZE      sizeof(struct ipu3_uapi_stats_3a)
  34
  35 static const size_t css_queue_buf_size_map[IPU3_CSS_QUEUES] = {
  36         [IPU3_CSS_QUEUE_IN] = CSS_QUEUE_IN_BUF_SIZE,
  37         [IPU3_CSS_QUEUE_PARAMS] = CSS_QUEUE_PARAMS_BUF_SIZE,
  38         [IPU3_CSS_QUEUE_OUT] = CSS_QUEUE_OUT_BUF_SIZE,
  39         [IPU3_CSS_QUEUE_VF] = CSS_QUEUE_VF_BUF_SIZE,
  40         [IPU3_CSS_QUEUE_STAT_3A] = CSS_QUEUE_STAT_3A_BUF_SIZE,
  41 };
  42
  43 static const struct imgu_node_mapping imgu_node_map[IMGU_NODE_NUM] = {
  44         [IMGU_NODE_IN] = {IPU3_CSS_QUEUE_IN, "input"},
  45         [IMGU_NODE_PARAMS] = {IPU3_CSS_QUEUE_PARAMS, "parameters"},
  46         [IMGU_NODE_OUT] = {IPU3_CSS_QUEUE_OUT, "output"},
  47         [IMGU_NODE_VF] = {IPU3_CSS_QUEUE_VF, "viewfinder"},
  48         [IMGU_NODE_STAT_3A] = {IPU3_CSS_QUEUE_STAT_3A, "3a stat"},
  49 };
  50
  51 unsigned int imgu_node_to_queue(unsigned int node)
  52 {
  53         return imgu_node_map[node].css_queue;
  54 }
  55
  56 unsigned int imgu_map_node(struct imgu_device *imgu, unsigned int css_queue)
  57 {
  58         unsigned int i;
  59
  60         for (i = 0; i < IMGU_NODE_NUM; i++)
  61                 if (imgu_node_map[i].css_queue == css_queue)
  62                         break;
  63
  64         return i;
  65 }
  66
  67 /**************** Dummy buffers ****************/
  68
  69 static void imgu_dummybufs_cleanup(struct imgu_device *imgu, unsigned int pipe)
  70 {
  71         unsigned int i;
  72         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
  73
  74         for (i = 0; i < IPU3_CSS_QUEUES; i++)
  75                 ipu3_dmamap_free(imgu,
  76                                  &imgu_pipe->queues[i].dmap);
  77 }
  78
  79 static int imgu_dummybufs_preallocate(struct imgu_device *imgu,
  80                                       unsigned int pipe)
  81 {
  82         unsigned int i;
  83         size_t size;
  84         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
  85
  86         for (i = 0; i < IPU3_CSS_QUEUES; i++) {
  87                 size = css_queue_buf_size_map[i];
  88                 /*
  89                  * Do not enable dummy buffers for master queue,
  90                  * always require that real buffers from user are
  91                  * available.
  92                  */
  93                 if (i == IMGU_QUEUE_MASTER || size == 0)
  94                         continue;
  95
  96                 if (!ipu3_dmamap_alloc(imgu,
  97                                        &imgu_pipe->queues[i].dmap, size)) {
  98                         imgu_dummybufs_cleanup(imgu, pipe);
  99                         return -ENOMEM;
 100                 }
 101         }
 102
 103         return 0;
 104 }
 105
 106 static int imgu_dummybufs_init(struct imgu_device *imgu, unsigned int pipe)
 107 {
 108         const struct v4l2_pix_format_mplane *mpix;
 109         const struct v4l2_meta_format   *meta;
 110         unsigned int i, k, node;
 111         size_t size;
 112         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
 113
 114         /* Allocate a dummy buffer for each queue where buffer is optional */
 115         for (i = 0; i < IPU3_CSS_QUEUES; i++) {
 116                 node = imgu_map_node(imgu, i);
 117                 if (!imgu_pipe->queue_enabled[node] || i == IMGU_QUEUE_MASTER)
 118                         continue;
 119
 120                 if (!imgu_pipe->nodes[IMGU_NODE_VF].enabled &&
 121                     i == IPU3_CSS_QUEUE_VF)
 122                         /*
 123                          * Do not enable dummy buffers for VF if it is not
 124                          * requested by the user.
 125                          */
 126                         continue;
 127
 128                 meta = &imgu_pipe->nodes[node].vdev_fmt.fmt.meta;
 129                 mpix = &imgu_pipe->nodes[node].vdev_fmt.fmt.pix_mp;
 130
 131                 if (node == IMGU_NODE_STAT_3A || node == IMGU_NODE_PARAMS)
 132                         size = meta->buffersize;
 133                 else
 134                         size = mpix->plane_fmt[0].sizeimage;
 135
 136                 if (ipu3_css_dma_buffer_resize(imgu,
 137                                                &imgu_pipe->queues[i].dmap,
 138                                                size)) {
 139                         imgu_dummybufs_cleanup(imgu, pipe);
 140                         return -ENOMEM;
 141                 }
 142
 143                 for (k = 0; k < IMGU_MAX_QUEUE_DEPTH; k++)
 144                         ipu3_css_buf_init(&imgu_pipe->queues[i].dummybufs[k], i,
 145                                           imgu_pipe->queues[i].dmap.daddr);
 146         }
 147
 148         return 0;
 149 }
 150
 151 /* May be called from atomic context */
 152 static struct ipu3_css_buffer *imgu_dummybufs_get(struct imgu_device *imgu,
 153                                                    int queue, unsigned int pipe)
 154 {
 155         unsigned int i;
 156         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
 157
 158         /* dummybufs are not allocated for master q */
 159         if (queue == IPU3_CSS_QUEUE_IN)
 160                 return NULL;
 161
 162         if (WARN_ON(!imgu_pipe->queues[queue].dmap.vaddr))
 163                 /* Buffer should not be allocated here */
 164                 return NULL;
 165
 166         for (i = 0; i < IMGU_MAX_QUEUE_DEPTH; i++)
 167                 if (ipu3_css_buf_state(&imgu_pipe->queues[queue].dummybufs[i]) !=
 168                         IPU3_CSS_BUFFER_QUEUED)
 169                         break;
 170
 171         if (i == IMGU_MAX_QUEUE_DEPTH)
 172                 return NULL;
 173
 174         ipu3_css_buf_init(&imgu_pipe->queues[queue].dummybufs[i], queue,
 175                           imgu_pipe->queues[queue].dmap.daddr);
 176
 177         return &imgu_pipe->queues[queue].dummybufs[i];
 178 }
 179
 180 /* Check if given buffer is a dummy buffer */
 181 static bool imgu_dummybufs_check(struct imgu_device *imgu,
 182                                  struct ipu3_css_buffer *buf,
 183                                  unsigned int pipe)
 184 {
 185         unsigned int i;
 186         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
 187
 188         for (i = 0; i < IMGU_MAX_QUEUE_DEPTH; i++)
 189                 if (buf == &imgu_pipe->queues[buf->queue].dummybufs[i])
 190                         break;
 191
 192         return i < IMGU_MAX_QUEUE_DEPTH;
 193 }
 194
 195 static void imgu_buffer_done(struct imgu_device *imgu, struct vb2_buffer *vb,
 196                              enum vb2_buffer_state state)
 197 {
 198         mutex_lock(&imgu->lock);
 199         imgu_v4l2_buffer_done(vb, state);
 200         mutex_unlock(&imgu->lock);
 201 }
 202
 203 static struct ipu3_css_buffer *imgu_queue_getbuf(struct imgu_device *imgu,
 204                                                  unsigned int node,
 205                                                  unsigned int pipe)
 206 {
 207         struct imgu_buffer *buf;
 208         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
 209
 210         if (WARN_ON(node >= IMGU_NODE_NUM))
 211                 return NULL;
 212
 213         /* Find first free buffer from the node */
 214         list_for_each_entry(buf, &imgu_pipe->nodes[node].buffers, vid_buf.list) {
 215                 if (ipu3_css_buf_state(&buf->css_buf) == IPU3_CSS_BUFFER_NEW)
 216                         return &buf->css_buf;
 217         }
 218
 219         /* There were no free buffers, try to return a dummy buffer */
 220         return imgu_dummybufs_get(imgu, imgu_node_map[node].css_queue, pipe);
 221 }
 222
 223 /*
 224  * Queue as many buffers to CSS as possible. If all buffers don't fit into
 225  * CSS buffer queues, they remain unqueued and will be queued later.
 226  */
 227 int imgu_queue_buffers(struct imgu_device *imgu, bool initial, unsigned int pipe)
 228 {
 229         unsigned int node;
 230         int r = 0;
 231         struct imgu_media_pipe *imgu_pipe = &imgu->imgu_pipe[pipe];
 232
 233         if (!ipu3_css_is_streaming(&imgu->css))
 234                 return 0;
 235
 236         dev_dbg(&imgu->pci_dev->dev, "Queue buffers to pipe %d", pipe);
 237         mutex_lock(&imgu->lock);
 238
 239         /* Buffer set is queued to FW only when input buffer is ready */
 240         for (node = IMGU_NODE_NUM - 1;
 241              imgu_queue_getbuf(imgu, IMGU_NODE_IN, pipe);
 242              node = node ? node - 1 : IMGU_NODE_NUM - 1) {
 243
 244                 if (node == IMGU_NODE_VF &&
 245                     !imgu_pipe->nodes[IMGU_NODE_VF].enabled) {
 246                         dev_warn(&imgu->pci_dev->dev,
 247                                  "Vf not enabled, ignore queue");
 248                         continue;
 249                 } else if (imgu_pipe->queue_enabled[node]) {
 250                         struct ipu3_css_buffer *buf =
 251                                 imgu_queue_getbuf(imgu, node, pipe);
 252                         struct imgu_buffer *ibuf = NULL;
 253                         bool dummy;
 254
 255                         if (!buf)
 256                                 break;
 257
 258                         r = ipu3_css_buf_queue(&imgu->css, pipe, buf);
 259                         if (r)
 260                                 break;
 261                         dummy = imgu_dummybufs_check(imgu, buf, pipe);
 262                         if (!dummy)
 263                                 ibuf = container_of(buf, struct imgu_buffer,
 264                                                     css_buf);
 265                         dev_dbg(&imgu->pci_dev->dev,
 266                                 "queue %s %s buffer %u to css da: 0x%08x\n",
 267                                 dummy ? "dummy" : "user",
 268                                 imgu_node_map[node].name,
 269                                 dummy ? 0 : ibuf->vid_buf.vbb.vb2_buf.index,
 270                                 (u32)buf->daddr);
 271                 }
 272         }
 273         mutex_unlock(&imgu->lock);
 274
 275         if (r && r != -EBUSY)
 276                 goto failed;
 277
 278         return 0;
 279
 280 failed:
 281         /*
 282          * On error, mark all buffers as failed which are not
 283          * yet queued to CSS
 284          */
 285         dev_err(&imgu->pci_dev->dev,
 286                 "failed to queue buffer to CSS on queue %i (%d)\n",
 287                 node, r);
 288
 289         if (initial)
 290                 /* If we were called from streamon(), no need to finish bufs */
 291                 return r;
 292
 293         for (node = 0; node < IMGU_NODE_NUM; node++) {
 294                 struct imgu_buffer *buf, *buf0;
 295
 296                 if (!imgu_pipe->queue_enabled[node])
 297                         continue;       /* Skip disabled queues */
 298
 299                 mutex_lock(&imgu->lock);
 300                 list_for_each_entry_safe(buf, buf0,
 301                                          &imgu_pipe->nodes[node].buffers,
 302                                          vid_buf.list) {
 303                         if (ipu3_css_buf_state(&buf->css_buf) ==
 304                             IPU3_CSS_BUFFER_QUEUED)
 305                                 continue;       /* Was already queued, skip */
 306
 307                         imgu_v4l2_buffer_done(&buf->vid_buf.vbb.vb2_buf,
 308                                               VB2_BUF_STATE_ERROR);
 309                 }
 310                 mutex_unlock(&imgu->lock);
 311         }
 312
 313         return r;
 314 }
 315
 316 static int imgu_powerup(struct imgu_device *imgu)
 317 {
 318         int r;
 319
 320         r = ipu3_css_set_powerup(&imgu->pci_dev->dev, imgu->base);
 321         if (r)
 322                 return r;
 323
 324         ipu3_mmu_resume(imgu->mmu);
 325         return 0;
 326 }
 327
 328 static void imgu_powerdown(struct imgu_device *imgu)
 329 {
 330         ipu3_mmu_suspend(imgu->mmu);
 331         ipu3_css_set_powerdown(&imgu->pci_dev->dev, imgu->base);
 332 }
 333
 334 int imgu_s_stream(struct imgu_device *imgu, int enable)
 335 {
 336         struct device *dev = &imgu->pci_dev->dev;
 337         int r, pipe;
 338
 339         if (!enable) {
 340                 /* Stop streaming */
 341                 dev_dbg(dev, "stream off\n");
 342                 /* Block new buffers to be queued to CSS. */
 343                 atomic_set(&imgu->qbuf_barrier, 1);
 344                 ipu3_css_stop_streaming(&imgu->css);
 345                 synchronize_irq(imgu->pci_dev->irq);
 346                 atomic_set(&imgu->qbuf_barrier, 0);
 347                 imgu_powerdown(imgu);
 348                 pm_runtime_put(&imgu->pci_dev->dev);
 349
 350                 return 0;
 351         }
 352
 353         /* Set Power */
 354         r = pm_runtime_get_sync(dev);
 355         if (r < 0) {
 356                 dev_err(dev, "failed to set imgu power\n");
 357                 pm_runtime_put(dev);
 358                 return r;
 359         }
 360
 361         r = imgu_powerup(imgu);
 362         if (r) {
 363                 dev_err(dev, "failed to power up imgu\n");
 364                 pm_runtime_put(dev);
 365                 return r;
 366         }
 367
 368         /* Start CSS streaming */
 369         r = ipu3_css_start_streaming(&imgu->css);
 370         if (r) {
 371                 dev_err(dev, "failed to start css streaming (%d)", r);
 372                 goto fail_start_streaming;
 373         }
 374
 375         for_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM) {
 376                 /* Initialize dummy buffers */
 377                 r = imgu_dummybufs_init(imgu, pipe);
 378                 if (r) {
 379                         dev_err(dev, "failed to initialize dummy buffers (%d)", r);
 380                         goto fail_dummybufs;
 381                 }
 382
 383                 /* Queue as many buffers from queue as possible */
 384                 r = imgu_queue_buffers(imgu, true, pipe);
 385                 if (r) {
 386                         dev_err(dev, "failed to queue initial buffers (%d)", r);
 387                         goto fail_queueing;
 388                 }
 389         }
 390
 391         return 0;
 392 fail_queueing:
 393         for_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM)
 394                 imgu_dummybufs_cleanup(imgu, pipe);
 395 fail_dummybufs:
 396         ipu3_css_stop_streaming(&imgu->css);
 397 fail_start_streaming:
 398         pm_runtime_put(dev);
 399
 400         return r;
 401 }
 402
 403 static int imgu_video_nodes_init(struct imgu_device *imgu)
 404 {
 405         struct v4l2_pix_format_mplane *fmts[IPU3_CSS_QUEUES] = { NULL };
 406         struct v4l2_rect *rects[IPU3_CSS_RECTS] = { NULL };
 407         struct imgu_media_pipe *imgu_pipe;
 408         unsigned int i, j;
 409         int r;
 410
 411         imgu->buf_struct_size = sizeof(struct imgu_buffer);
 412
 413         for (j = 0; j < IMGU_MAX_PIPE_NUM; j++) {
 414                 imgu_pipe = &imgu->imgu_pipe[j];
 415
 416                 for (i = 0; i < IMGU_NODE_NUM; i++) {
 417                         imgu_pipe->nodes[i].name = imgu_node_map[i].name;
 418                         imgu_pipe->nodes[i].output = i < IMGU_QUEUE_FIRST_INPUT;
 419                         imgu_pipe->nodes[i].enabled = false;
 420
 421                         if (i != IMGU_NODE_PARAMS && i != IMGU_NODE_STAT_3A)
 422                                 fmts[imgu_node_map[i].css_queue] =
 423                                         &imgu_pipe->nodes[i].vdev_fmt.fmt.pix_mp;
 424                         atomic_set(&imgu_pipe->nodes[i].sequence, 0);
 425                 }
 426         }
 427
 428         r = imgu_v4l2_register(imgu);
 429         if (r)
 430                 return r;
 431
 432         /* Set initial formats and initialize formats of video nodes */
 433         for (j = 0; j < IMGU_MAX_PIPE_NUM; j++) {
 434                 imgu_pipe = &imgu->imgu_pipe[j];
 435
 436                 rects[IPU3_CSS_RECT_EFFECTIVE] = &imgu_pipe->imgu_sd.rect.eff;
 437                 rects[IPU3_CSS_RECT_BDS] = &imgu_pipe->imgu_sd.rect.bds;
 438                 ipu3_css_fmt_set(&imgu->css, fmts, rects, j);
 439
 440                 /* Pre-allocate dummy buffers */
 441                 r = imgu_dummybufs_preallocate(imgu, j);
 442                 if (r) {
 443                         dev_err(&imgu->pci_dev->dev,
 444                                 "failed to pre-allocate dummy buffers (%d)", r);
 445                         goto out_cleanup;
 446                 }
 447         }
 448
 449         return 0;
 450
 451 out_cleanup:
 452         for (j = 0; j < IMGU_MAX_PIPE_NUM; j++)
 453                 imgu_dummybufs_cleanup(imgu, j);
 454
 455         imgu_v4l2_unregister(imgu);
 456
 457         return r;
 458 }
 459
 460 static void imgu_video_nodes_exit(struct imgu_device *imgu)
 461 {
 462         int i;
 463
 464         for (i = 0; i < IMGU_MAX_PIPE_NUM; i++)
 465                 imgu_dummybufs_cleanup(imgu, i);
 466
 467         imgu_v4l2_unregister(imgu);
 468 }
 469
 470 /**************** PCI interface ****************/
 471
 472 static irqreturn_t imgu_isr_threaded(int irq, void *imgu_ptr)
 473 {
 474         struct imgu_device *imgu = imgu_ptr;
 475         struct imgu_media_pipe *imgu_pipe;
 476         int p;
 477
 478         /* Dequeue / queue buffers */
 479         do {
 480                 u64 ns = ktime_get_ns();
 481                 struct ipu3_css_buffer *b;
 482                 struct imgu_buffer *buf = NULL;
 483                 unsigned int node, pipe;
 484                 bool dummy;
 485
 486                 do {
 487                         mutex_lock(&imgu->lock);
 488                         b = ipu3_css_buf_dequeue(&imgu->css);
 489                         mutex_unlock(&imgu->lock);
 490                 } while (PTR_ERR(b) == -EAGAIN);
 491
 492                 if (IS_ERR_OR_NULL(b)) {
 493                         if (!b || PTR_ERR(b) == -EBUSY) /* All done */
 494                                 break;
 495                         dev_err(&imgu->pci_dev->dev,
 496                                 "failed to dequeue buffers (%ld)\n",
 497                                 PTR_ERR(b));
 498                         break;
 499                 }
 500
 501                 node = imgu_map_node(imgu, b->queue);
 502                 pipe = b->pipe;
 503                 dummy = imgu_dummybufs_check(imgu, b, pipe);
 504                 if (!dummy)
 505                         buf = container_of(b, struct imgu_buffer, css_buf);
 506                 dev_dbg(&imgu->pci_dev->dev,
 507                         "dequeue %s %s buffer %d daddr 0x%x from css\n",
 508                         dummy ? "dummy" : "user",
 509                         imgu_node_map[node].name,
 510                         dummy ? 0 : buf->vid_buf.vbb.vb2_buf.index,
 511                         (u32)b->daddr);
 512
 513                 if (dummy)
 514                         /* It was a dummy buffer, skip it */
 515                         continue;
 516
 517                 /* Fill vb2 buffer entries and tell it's ready */
 518                 imgu_pipe = &imgu->imgu_pipe[pipe];
 519                 if (!imgu_pipe->nodes[node].output) {
 520                         buf->vid_buf.vbb.vb2_buf.timestamp = ns;
 521                         buf->vid_buf.vbb.field = V4L2_FIELD_NONE;
 522                         buf->vid_buf.vbb.sequence =
 523                                 atomic_inc_return(
 524                                 &imgu_pipe->nodes[node].sequence);
 525                         dev_dbg(&imgu->pci_dev->dev, "vb2 buffer sequence %d",
 526                                 buf->vid_buf.vbb.sequence);
 527                 }
 528                 imgu_buffer_done(imgu, &buf->vid_buf.vbb.vb2_buf,
 529                                  ipu3_css_buf_state(&buf->css_buf) ==
 530                                                     IPU3_CSS_BUFFER_DONE ?
 531                                                     VB2_BUF_STATE_DONE :
 532                                                     VB2_BUF_STATE_ERROR);
 533                 mutex_lock(&imgu->lock);
 534                 if (ipu3_css_queue_empty(&imgu->css))
 535                         wake_up_all(&imgu->buf_drain_wq);
 536                 mutex_unlock(&imgu->lock);
 537         } while (1);
 538
 539         /*
 540          * Try to queue more buffers for CSS.
 541          * qbuf_barrier is used to disable new buffers
 542          * to be queued to CSS.
 543          */
 544         if (!atomic_read(&imgu->qbuf_barrier))
 545                 for_each_set_bit(p, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM)
 546                         imgu_queue_buffers(imgu, false, p);
 547
 548         return IRQ_HANDLED;
 549 }
 550
 551 static irqreturn_t imgu_isr(int irq, void *imgu_ptr)
 552 {
 553         struct imgu_device *imgu = imgu_ptr;
 554
 555         /* acknowledge interruption */
 556         if (ipu3_css_irq_ack(&imgu->css) < 0)
 557                 return IRQ_NONE;
 558
 559         return IRQ_WAKE_THREAD;
 560 }
 561
 562 static int imgu_pci_config_setup(struct pci_dev *dev)
 563 {
 564         u16 pci_command;
 565         int r = pci_enable_msi(dev);
 566
 567         if (r) {
 568                 dev_err(&dev->dev, "failed to enable MSI (%d)\n", r);
 569                 return r;
 570         }
 571
 572         pci_read_config_word(dev, PCI_COMMAND, &pci_command);
 573         pci_command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 574                         PCI_COMMAND_INTX_DISABLE;
 575         pci_write_config_word(dev, PCI_COMMAND, pci_command);
 576
 577         return 0;
 578 }
 579
 580 static int imgu_pci_probe(struct pci_dev *pci_dev,
 581                           const struct pci_device_id *id)
 582 {
 583         struct imgu_device *imgu;
 584         phys_addr_t phys;
 585         unsigned long phys_len;
 586         void __iomem *const *iomap;
 587         int r;
 588
 589         imgu = devm_kzalloc(&pci_dev->dev, sizeof(*imgu), GFP_KERNEL);
 590         if (!imgu)
 591                 return -ENOMEM;
 592
 593         imgu->pci_dev = pci_dev;
 594
 595         r = pcim_enable_device(pci_dev);
 596         if (r) {
 597                 dev_err(&pci_dev->dev, "failed to enable device (%d)\n", r);
 598                 return r;
 599         }
 600
 601         dev_info(&pci_dev->dev, "device 0x%x (rev: 0x%x)\n",
 602                  pci_dev->device, pci_dev->revision);
 603
 604         phys = pci_resource_start(pci_dev, IMGU_PCI_BAR);
 605         phys_len = pci_resource_len(pci_dev, IMGU_PCI_BAR);
 606
 607         r = pcim_iomap_regions(pci_dev, 1 << IMGU_PCI_BAR, pci_name(pci_dev));
 608         if (r) {
 609                 dev_err(&pci_dev->dev, "failed to remap I/O memory (%d)\n", r);
 610                 return r;
 611         }
 612         dev_info(&pci_dev->dev, "physical base address %pap, %lu bytes\n",
 613                  &phys, phys_len);
 614
 615         iomap = pcim_iomap_table(pci_dev);
 616         if (!iomap) {
 617                 dev_err(&pci_dev->dev, "failed to iomap table\n");
 618                 return -ENODEV;
 619         }
 620
 621         imgu->base = iomap[IMGU_PCI_BAR];
 622
 623         pci_set_drvdata(pci_dev, imgu);
 624
 625         pci_set_master(pci_dev);
 626
 627         r = dma_coerce_mask_and_coherent(&pci_dev->dev, IMGU_DMA_MASK);
 628         if (r) {
 629                 dev_err(&pci_dev->dev, "failed to set DMA mask (%d)\n", r);
 630                 return -ENODEV;
 631         }
 632
 633         r = imgu_pci_config_setup(pci_dev);
 634         if (r)
 635                 return r;
 636
 637         mutex_init(&imgu->lock);
 638         atomic_set(&imgu->qbuf_barrier, 0);
 639         init_waitqueue_head(&imgu->buf_drain_wq);
 640
 641         r = ipu3_css_set_powerup(&pci_dev->dev, imgu->base);
 642         if (r) {
 643                 dev_err(&pci_dev->dev,
 644                         "failed to power up CSS (%d)\n", r);
 645                 goto out_mutex_destroy;
 646         }
 647
 648         imgu->mmu = ipu3_mmu_init(&pci_dev->dev, imgu->base);
 649         if (IS_ERR(imgu->mmu)) {
 650                 r = PTR_ERR(imgu->mmu);
 651                 dev_err(&pci_dev->dev, "failed to initialize MMU (%d)\n", r);
 652                 goto out_css_powerdown;
 653         }
 654
 655         r = ipu3_dmamap_init(imgu);
 656         if (r) {
 657                 dev_err(&pci_dev->dev,
 658                         "failed to initialize DMA mapping (%d)\n", r);
 659                 goto out_mmu_exit;
 660         }
 661
 662         /* ISP programming */
 663         r = ipu3_css_init(&pci_dev->dev, &imgu->css, imgu->base, phys_len);
 664         if (r) {
 665                 dev_err(&pci_dev->dev, "failed to initialize CSS (%d)\n", r);
 666                 goto out_dmamap_exit;
 667         }
 668
 669         /* v4l2 sub-device registration */
 670         r = imgu_video_nodes_init(imgu);
 671         if (r) {
 672                 dev_err(&pci_dev->dev, "failed to create V4L2 devices (%d)\n",
 673                         r);
 674                 goto out_css_cleanup;
 675         }
 676
 677         r = devm_request_threaded_irq(&pci_dev->dev, pci_dev->irq,
 678                                       imgu_isr, imgu_isr_threaded,
 679                                       IRQF_SHARED, IMGU_NAME, imgu);
 680         if (r) {
 681                 dev_err(&pci_dev->dev, "failed to request IRQ (%d)\n", r);
 682                 goto out_video_exit;
 683         }
 684
 685         pm_runtime_put_noidle(&pci_dev->dev);
 686         pm_runtime_allow(&pci_dev->dev);
 687
 688         return 0;
 689
 690 out_video_exit:
 691         imgu_video_nodes_exit(imgu);
 692 out_css_cleanup:
 693         ipu3_css_cleanup(&imgu->css);
 694 out_dmamap_exit:
 695         ipu3_dmamap_exit(imgu);
 696 out_mmu_exit:
 697         ipu3_mmu_exit(imgu->mmu);
 698 out_css_powerdown:
 699         ipu3_css_set_powerdown(&pci_dev->dev, imgu->base);
 700 out_mutex_destroy:
 701         mutex_destroy(&imgu->lock);
 702
 703         return r;
 704 }
 705
 706 static void imgu_pci_remove(struct pci_dev *pci_dev)
 707 {
 708         struct imgu_device *imgu = pci_get_drvdata(pci_dev);
 709
 710         pm_runtime_forbid(&pci_dev->dev);
 711         pm_runtime_get_noresume(&pci_dev->dev);
 712
 713         imgu_video_nodes_exit(imgu);
 714         ipu3_css_cleanup(&imgu->css);
 715         ipu3_css_set_powerdown(&pci_dev->dev, imgu->base);
 716         ipu3_dmamap_exit(imgu);
 717         ipu3_mmu_exit(imgu->mmu);
 718         mutex_destroy(&imgu->lock);
 719 }
 720
 721 static int __maybe_unused imgu_suspend(struct device *dev)
 722 {
 723         struct pci_dev *pci_dev = to_pci_dev(dev);
 724         struct imgu_device *imgu = pci_get_drvdata(pci_dev);
 725
 726         dev_dbg(dev, "enter %s\n", __func__);
 727         imgu->suspend_in_stream = ipu3_css_is_streaming(&imgu->css);
 728         if (!imgu->suspend_in_stream)
 729                 goto out;
 730         /* Block new buffers to be queued to CSS. */
 731         atomic_set(&imgu->qbuf_barrier, 1);
 732         /*
 733          * Wait for currently running irq handler to be done so that
 734          * no new buffers will be queued to fw later.
 735          */
 736         synchronize_irq(pci_dev->irq);
 737         /* Wait until all buffers in CSS are done. */
 738         if (!wait_event_timeout(imgu->buf_drain_wq,
 739             ipu3_css_queue_empty(&imgu->css), msecs_to_jiffies(1000)))
 740                 dev_err(dev, "wait buffer drain timeout.\n");
 741
 742         ipu3_css_stop_streaming(&imgu->css);
 743         atomic_set(&imgu->qbuf_barrier, 0);
 744         imgu_powerdown(imgu);
 745         pm_runtime_force_suspend(dev);
 746 out:
 747         dev_dbg(dev, "leave %s\n", __func__);
 748         return 0;
 749 }
 750
 751 static int __maybe_unused imgu_resume(struct device *dev)
 752 {
 753         struct pci_dev *pci_dev = to_pci_dev(dev);
 754         struct imgu_device *imgu = pci_get_drvdata(pci_dev);
 755         int r = 0;
 756         unsigned int pipe;
 757
 758         dev_dbg(dev, "enter %s\n", __func__);
 759
 760         if (!imgu->suspend_in_stream)
 761                 goto out;
 762
 763         pm_runtime_force_resume(dev);
 764
 765         r = imgu_powerup(imgu);
 766         if (r) {
 767                 dev_err(dev, "failed to power up imgu\n");
 768                 goto out;
 769         }
 770
 771         /* Start CSS streaming */
 772         r = ipu3_css_start_streaming(&imgu->css);
 773         if (r) {
 774                 dev_err(dev, "failed to resume css streaming (%d)", r);
 775                 goto out;
 776         }
 777
 778         for_each_set_bit(pipe, imgu->css.enabled_pipes, IMGU_MAX_PIPE_NUM) {
 779                 r = imgu_queue_buffers(imgu, true, pipe);
 780                 if (r)
 781                         dev_err(dev, "failed to queue buffers to pipe %d (%d)",
 782                                 pipe, r);
 783         }
 784
 785 out:
 786         dev_dbg(dev, "leave %s\n", __func__);
 787
 788         return r;
 789 }
 790
 791 /*
 792  * PCI rpm framework checks the existence of driver rpm callbacks.
 793  * Place a dummy callback here to avoid rpm going into error state.
 794  */
 795 static int imgu_rpm_dummy_cb(struct device *dev)
 796 {
 797         return 0;
 798 }
 799
 800 static const struct dev_pm_ops imgu_pm_ops = {
 801         SET_RUNTIME_PM_OPS(&imgu_rpm_dummy_cb, &imgu_rpm_dummy_cb, NULL)
 802         SET_SYSTEM_SLEEP_PM_OPS(&imgu_suspend, &imgu_resume)
 803 };
 804
 805 static const struct pci_device_id imgu_pci_tbl[] = {
 806         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, IMGU_PCI_ID) },
 807         { 0, }
 808 };
 809
 810 MODULE_DEVICE_TABLE(pci, imgu_pci_tbl);
 811
 812 static struct pci_driver imgu_pci_driver = {
 813         .name = IMGU_NAME,
 814         .id_table = imgu_pci_tbl,
 815         .probe = imgu_pci_probe,
 816         .remove = imgu_pci_remove,
 817         .driver = {
 818                 .pm = &imgu_pm_ops,
 819         },
 820 };
 821
 822 module_pci_driver(imgu_pci_driver);
 823
 824 MODULE_AUTHOR("Tuukka Toivonen <tuukka.toivonen@intel.com>");
 825 MODULE_AUTHOR("Tianshu Qiu <tian.shu.qiu@intel.com>");
 826 MODULE_AUTHOR("Jian Xu Zheng <jian.xu.zheng@intel.com>");
 827 MODULE_AUTHOR("Yuning Pu <yuning.pu@intel.com>");
 828 MODULE_AUTHOR("Yong Zhi <yong.zhi@intel.com>");
 829 MODULE_LICENSE("GPL v2");
 830 MODULE_DESCRIPTION("Intel ipu3_imgu PCI driver");