]> asedeno.scripts.mit.edu Git - linux.git/blob - drivers/staging/octeon/octeon-stubs.h
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux.git] / drivers / staging / octeon / octeon-stubs.h
1 #define CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE        512
2
3 #ifndef XKPHYS_TO_PHYS
4 # define XKPHYS_TO_PHYS(p)                      (p)
5 #endif
6
7 #define OCTEON_IRQ_WORKQ0 0
8 #define OCTEON_IRQ_RML 0
9 #define OCTEON_IRQ_TIMER1 0
10 #define OCTEON_IS_MODEL(x) 0
11 #define octeon_has_feature(x)   0
12 #define octeon_get_clock_rate() 0
13
14 #define CVMX_SYNCIOBDMA         do { } while(0)
15
16 #define CVMX_HELPER_INPUT_TAG_TYPE      0
17 #define CVMX_HELPER_FIRST_MBUFF_SKIP    7
18 #define CVMX_FAU_REG_END                (2048)
19 #define CVMX_FPA_OUTPUT_BUFFER_POOL         (2)
20 #define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE    16
21 #define CVMX_FPA_PACKET_POOL                (0)
22 #define CVMX_FPA_PACKET_POOL_SIZE           16
23 #define CVMX_FPA_WQE_POOL                   (1)
24 #define CVMX_FPA_WQE_POOL_SIZE              16
25 #define CVMX_GMXX_RXX_ADR_CAM_EN(a, b)  ((a)+(b))
26 #define CVMX_GMXX_RXX_ADR_CTL(a, b)     ((a)+(b))
27 #define CVMX_GMXX_PRTX_CFG(a, b)        ((a)+(b))
28 #define CVMX_GMXX_RXX_FRM_MAX(a, b)     ((a)+(b))
29 #define CVMX_GMXX_RXX_JABBER(a, b)      ((a)+(b))
30 #define CVMX_IPD_CTL_STATUS             0
31 #define CVMX_PIP_FRM_LEN_CHKX(a)        (a)
32 #define CVMX_PIP_NUM_INPUT_PORTS        1
33 #define CVMX_SCR_SCRATCH                0
34 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0     2
35 #define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1     2
36 #define CVMX_IPD_SUB_PORT_FCS           0
37 #define CVMX_SSO_WQ_IQ_DIS              0
38 #define CVMX_SSO_WQ_INT                 0
39 #define CVMX_POW_WQ_INT                 0
40 #define CVMX_SSO_WQ_INT_PC              0
41 #define CVMX_NPI_RSL_INT_BLOCKS         0
42 #define CVMX_POW_WQ_INT_PC              0
43
44 union cvmx_pip_wqe_word2 {
45         uint64_t u64;
46         struct {
47                 uint64_t bufs:8;
48                 uint64_t ip_offset:8;
49                 uint64_t vlan_valid:1;
50                 uint64_t vlan_stacked:1;
51                 uint64_t unassigned:1;
52                 uint64_t vlan_cfi:1;
53                 uint64_t vlan_id:12;
54                 uint64_t pr:4;
55                 uint64_t unassigned2:8;
56                 uint64_t dec_ipcomp:1;
57                 uint64_t tcp_or_udp:1;
58                 uint64_t dec_ipsec:1;
59                 uint64_t is_v6:1;
60                 uint64_t software:1;
61                 uint64_t L4_error:1;
62                 uint64_t is_frag:1;
63                 uint64_t IP_exc:1;
64                 uint64_t is_bcast:1;
65                 uint64_t is_mcast:1;
66                 uint64_t not_IP:1;
67                 uint64_t rcv_error:1;
68                 uint64_t err_code:8;
69         } s;
70         struct {
71                 uint64_t bufs:8;
72                 uint64_t ip_offset:8;
73                 uint64_t vlan_valid:1;
74                 uint64_t vlan_stacked:1;
75                 uint64_t unassigned:1;
76                 uint64_t vlan_cfi:1;
77                 uint64_t vlan_id:12;
78                 uint64_t port:12;
79                 uint64_t dec_ipcomp:1;
80                 uint64_t tcp_or_udp:1;
81                 uint64_t dec_ipsec:1;
82                 uint64_t is_v6:1;
83                 uint64_t software:1;
84                 uint64_t L4_error:1;
85                 uint64_t is_frag:1;
86                 uint64_t IP_exc:1;
87                 uint64_t is_bcast:1;
88                 uint64_t is_mcast:1;
89                 uint64_t not_IP:1;
90                 uint64_t rcv_error:1;
91                 uint64_t err_code:8;
92         } s_cn68xx;
93
94         struct {
95                 uint64_t unused1:16;
96                 uint64_t vlan:16;
97                 uint64_t unused2:32;
98         } svlan;
99         struct {
100                 uint64_t bufs:8;
101                 uint64_t unused:8;
102                 uint64_t vlan_valid:1;
103                 uint64_t vlan_stacked:1;
104                 uint64_t unassigned:1;
105                 uint64_t vlan_cfi:1;
106                 uint64_t vlan_id:12;
107                 uint64_t pr:4;
108                 uint64_t unassigned2:12;
109                 uint64_t software:1;
110                 uint64_t unassigned3:1;
111                 uint64_t is_rarp:1;
112                 uint64_t is_arp:1;
113                 uint64_t is_bcast:1;
114                 uint64_t is_mcast:1;
115                 uint64_t not_IP:1;
116                 uint64_t rcv_error:1;
117                 uint64_t err_code:8;
118         } snoip;
119
120 };
121
122 union cvmx_pip_wqe_word0 {
123         struct {
124                 uint64_t next_ptr:40;
125                 uint8_t unused;
126                 __wsum hw_chksum;
127         } cn38xx;
128         struct {
129                 uint64_t pknd:6;        /* 0..5 */
130                 uint64_t unused2:2;     /* 6..7 */
131                 uint64_t bpid:6;        /* 8..13 */
132                 uint64_t unused1:18;    /* 14..31 */
133                 uint64_t l2ptr:8;       /* 32..39 */
134                 uint64_t l3ptr:8;       /* 40..47 */
135                 uint64_t unused0:8;     /* 48..55 */
136                 uint64_t l4ptr:8;       /* 56..63 */
137         } cn68xx;
138 };
139
140 union cvmx_wqe_word0 {
141         uint64_t u64;
142         union cvmx_pip_wqe_word0 pip;
143 };
144
145 union cvmx_wqe_word1 {
146         uint64_t u64;
147         struct {
148                 uint64_t tag:32;
149                 uint64_t tag_type:2;
150                 uint64_t varies:14;
151                 uint64_t len:16;
152         };
153         struct {
154                 uint64_t tag:32;
155                 uint64_t tag_type:2;
156                 uint64_t zero_2:3;
157                 uint64_t grp:6;
158                 uint64_t zero_1:1;
159                 uint64_t qos:3;
160                 uint64_t zero_0:1;
161                 uint64_t len:16;
162         } cn68xx;
163         struct {
164                 uint64_t tag:32;
165                 uint64_t tag_type:2;
166                 uint64_t zero_2:1;
167                 uint64_t grp:4;
168                 uint64_t qos:3;
169                 uint64_t ipprt:6;
170                 uint64_t len:16;
171         } cn38xx;
172 };
173
174 union cvmx_buf_ptr {
175         void *ptr;
176         uint64_t u64;
177         struct {
178                 uint64_t i:1;
179                 uint64_t back:4;
180                 uint64_t pool:3;
181                 uint64_t size:16;
182                 uint64_t addr:40;
183         } s;
184 };
185
186 struct cvmx_wqe {
187         union cvmx_wqe_word0 word0;
188         union cvmx_wqe_word1 word1;
189         union cvmx_pip_wqe_word2 word2;
190         union cvmx_buf_ptr packet_ptr;
191         uint8_t packet_data[96];
192 };
193
194 union cvmx_helper_link_info {
195         uint64_t u64;
196         struct {
197                 uint64_t reserved_20_63:44;
198                 uint64_t link_up:1;         /**< Is the physical link up? */
199                 uint64_t full_duplex:1;     /**< 1 if the link is full duplex */
200                 uint64_t speed:18;          /**< Speed of the link in Mbps */
201         } s;
202 };
203
204 enum cvmx_fau_reg_32 {
205         CVMX_FAU_REG_32_START   = 0,
206 };
207
208 enum cvmx_fau_op_size {
209         CVMX_FAU_OP_SIZE_8 = 0,
210         CVMX_FAU_OP_SIZE_16 = 1,
211         CVMX_FAU_OP_SIZE_32 = 2,
212         CVMX_FAU_OP_SIZE_64 = 3
213 };
214
215 typedef enum {
216         CVMX_SPI_MODE_UNKNOWN = 0,
217         CVMX_SPI_MODE_TX_HALFPLEX = 1,
218         CVMX_SPI_MODE_RX_HALFPLEX = 2,
219         CVMX_SPI_MODE_DUPLEX = 3
220 } cvmx_spi_mode_t;
221
222 typedef enum {
223         CVMX_HELPER_INTERFACE_MODE_DISABLED,
224         CVMX_HELPER_INTERFACE_MODE_RGMII,
225         CVMX_HELPER_INTERFACE_MODE_GMII,
226         CVMX_HELPER_INTERFACE_MODE_SPI,
227         CVMX_HELPER_INTERFACE_MODE_PCIE,
228         CVMX_HELPER_INTERFACE_MODE_XAUI,
229         CVMX_HELPER_INTERFACE_MODE_SGMII,
230         CVMX_HELPER_INTERFACE_MODE_PICMG,
231         CVMX_HELPER_INTERFACE_MODE_NPI,
232         CVMX_HELPER_INTERFACE_MODE_LOOP,
233 } cvmx_helper_interface_mode_t;
234
235 typedef enum {
236         CVMX_POW_WAIT = 1,
237         CVMX_POW_NO_WAIT = 0,
238 } cvmx_pow_wait_t;
239
240 typedef enum {
241         CVMX_PKO_LOCK_NONE = 0,
242         CVMX_PKO_LOCK_ATOMIC_TAG = 1,
243         CVMX_PKO_LOCK_CMD_QUEUE = 2,
244 } cvmx_pko_lock_t;
245
246 typedef enum {
247         CVMX_PKO_SUCCESS,
248         CVMX_PKO_INVALID_PORT,
249         CVMX_PKO_INVALID_QUEUE,
250         CVMX_PKO_INVALID_PRIORITY,
251         CVMX_PKO_NO_MEMORY,
252         CVMX_PKO_PORT_ALREADY_SETUP,
253         CVMX_PKO_CMD_QUEUE_INIT_ERROR
254 } cvmx_pko_status_t;
255
256 enum cvmx_pow_tag_type {
257         CVMX_POW_TAG_TYPE_ORDERED   = 0L,
258         CVMX_POW_TAG_TYPE_ATOMIC    = 1L,
259         CVMX_POW_TAG_TYPE_NULL      = 2L,
260         CVMX_POW_TAG_TYPE_NULL_NULL = 3L
261 };
262
263 union cvmx_ipd_ctl_status {
264         uint64_t u64;
265         struct cvmx_ipd_ctl_status_s {
266                 uint64_t reserved_18_63:46;
267                 uint64_t use_sop:1;
268                 uint64_t rst_done:1;
269                 uint64_t clken:1;
270                 uint64_t no_wptr:1;
271                 uint64_t pq_apkt:1;
272                 uint64_t pq_nabuf:1;
273                 uint64_t ipd_full:1;
274                 uint64_t pkt_off:1;
275                 uint64_t len_m8:1;
276                 uint64_t reset:1;
277                 uint64_t addpkt:1;
278                 uint64_t naddbuf:1;
279                 uint64_t pkt_lend:1;
280                 uint64_t wqe_lend:1;
281                 uint64_t pbp_en:1;
282                 uint64_t opc_mode:2;
283                 uint64_t ipd_en:1;
284         } s;
285         struct cvmx_ipd_ctl_status_cn30xx {
286                 uint64_t reserved_10_63:54;
287                 uint64_t len_m8:1;
288                 uint64_t reset:1;
289                 uint64_t addpkt:1;
290                 uint64_t naddbuf:1;
291                 uint64_t pkt_lend:1;
292                 uint64_t wqe_lend:1;
293                 uint64_t pbp_en:1;
294                 uint64_t opc_mode:2;
295                 uint64_t ipd_en:1;
296         } cn30xx;
297         struct cvmx_ipd_ctl_status_cn38xxp2 {
298                 uint64_t reserved_9_63:55;
299                 uint64_t reset:1;
300                 uint64_t addpkt:1;
301                 uint64_t naddbuf:1;
302                 uint64_t pkt_lend:1;
303                 uint64_t wqe_lend:1;
304                 uint64_t pbp_en:1;
305                 uint64_t opc_mode:2;
306                 uint64_t ipd_en:1;
307         } cn38xxp2;
308         struct cvmx_ipd_ctl_status_cn50xx {
309                 uint64_t reserved_15_63:49;
310                 uint64_t no_wptr:1;
311                 uint64_t pq_apkt:1;
312                 uint64_t pq_nabuf:1;
313                 uint64_t ipd_full:1;
314                 uint64_t pkt_off:1;
315                 uint64_t len_m8:1;
316                 uint64_t reset:1;
317                 uint64_t addpkt:1;
318                 uint64_t naddbuf:1;
319                 uint64_t pkt_lend:1;
320                 uint64_t wqe_lend:1;
321                 uint64_t pbp_en:1;
322                 uint64_t opc_mode:2;
323                 uint64_t ipd_en:1;
324         } cn50xx;
325         struct cvmx_ipd_ctl_status_cn58xx {
326                 uint64_t reserved_12_63:52;
327                 uint64_t ipd_full:1;
328                 uint64_t pkt_off:1;
329                 uint64_t len_m8:1;
330                 uint64_t reset:1;
331                 uint64_t addpkt:1;
332                 uint64_t naddbuf:1;
333                 uint64_t pkt_lend:1;
334                 uint64_t wqe_lend:1;
335                 uint64_t pbp_en:1;
336                 uint64_t opc_mode:2;
337                 uint64_t ipd_en:1;
338         } cn58xx;
339         struct cvmx_ipd_ctl_status_cn63xxp1 {
340                 uint64_t reserved_16_63:48;
341                 uint64_t clken:1;
342                 uint64_t no_wptr:1;
343                 uint64_t pq_apkt:1;
344                 uint64_t pq_nabuf:1;
345                 uint64_t ipd_full:1;
346                 uint64_t pkt_off:1;
347                 uint64_t len_m8:1;
348                 uint64_t reset:1;
349                 uint64_t addpkt:1;
350                 uint64_t naddbuf:1;
351                 uint64_t pkt_lend:1;
352                 uint64_t wqe_lend:1;
353                 uint64_t pbp_en:1;
354                 uint64_t opc_mode:2;
355                 uint64_t ipd_en:1;
356         } cn63xxp1;
357 };
358
359 union cvmx_ipd_sub_port_fcs {
360         uint64_t u64;
361         struct cvmx_ipd_sub_port_fcs_s {
362                 uint64_t port_bit:32;
363                 uint64_t reserved_32_35:4;
364                 uint64_t port_bit2:4;
365                 uint64_t reserved_40_63:24;
366         } s;
367         struct cvmx_ipd_sub_port_fcs_cn30xx {
368                 uint64_t port_bit:3;
369                 uint64_t reserved_3_63:61;
370         } cn30xx;
371         struct cvmx_ipd_sub_port_fcs_cn38xx {
372                 uint64_t port_bit:32;
373                 uint64_t reserved_32_63:32;
374         } cn38xx;
375 };
376
377 union cvmx_ipd_sub_port_qos_cnt {
378         uint64_t u64;
379         struct cvmx_ipd_sub_port_qos_cnt_s {
380                 uint64_t cnt:32;
381                 uint64_t port_qos:9;
382                 uint64_t reserved_41_63:23;
383         } s;
384 };
385 typedef struct {
386         uint32_t dropped_octets;
387         uint32_t dropped_packets;
388         uint32_t pci_raw_packets;
389         uint32_t octets;
390         uint32_t packets;
391         uint32_t multicast_packets;
392         uint32_t broadcast_packets;
393         uint32_t len_64_packets;
394         uint32_t len_65_127_packets;
395         uint32_t len_128_255_packets;
396         uint32_t len_256_511_packets;
397         uint32_t len_512_1023_packets;
398         uint32_t len_1024_1518_packets;
399         uint32_t len_1519_max_packets;
400         uint32_t fcs_align_err_packets;
401         uint32_t runt_packets;
402         uint32_t runt_crc_packets;
403         uint32_t oversize_packets;
404         uint32_t oversize_crc_packets;
405         uint32_t inb_packets;
406         uint64_t inb_octets;
407         uint16_t inb_errors;
408 } cvmx_pip_port_status_t;
409
410 typedef struct {
411         uint32_t packets;
412         uint64_t octets;
413         uint64_t doorbell;
414 } cvmx_pko_port_status_t;
415
416 union cvmx_pip_frm_len_chkx {
417         uint64_t u64;
418         struct cvmx_pip_frm_len_chkx_s {
419                 uint64_t reserved_32_63:32;
420                 uint64_t maxlen:16;
421                 uint64_t minlen:16;
422         } s;
423 };
424
425 union cvmx_gmxx_rxx_frm_ctl {
426         uint64_t u64;
427         struct cvmx_gmxx_rxx_frm_ctl_s {
428                 uint64_t pre_chk:1;
429                 uint64_t pre_strp:1;
430                 uint64_t ctl_drp:1;
431                 uint64_t ctl_bck:1;
432                 uint64_t ctl_mcst:1;
433                 uint64_t ctl_smac:1;
434                 uint64_t pre_free:1;
435                 uint64_t vlan_len:1;
436                 uint64_t pad_len:1;
437                 uint64_t pre_align:1;
438                 uint64_t null_dis:1;
439                 uint64_t reserved_11_11:1;
440                 uint64_t ptp_mode:1;
441                 uint64_t reserved_13_63:51;
442         } s;
443         struct cvmx_gmxx_rxx_frm_ctl_cn30xx {
444                 uint64_t pre_chk:1;
445                 uint64_t pre_strp:1;
446                 uint64_t ctl_drp:1;
447                 uint64_t ctl_bck:1;
448                 uint64_t ctl_mcst:1;
449                 uint64_t ctl_smac:1;
450                 uint64_t pre_free:1;
451                 uint64_t vlan_len:1;
452                 uint64_t pad_len:1;
453                 uint64_t reserved_9_63:55;
454         } cn30xx;
455         struct cvmx_gmxx_rxx_frm_ctl_cn31xx {
456                 uint64_t pre_chk:1;
457                 uint64_t pre_strp:1;
458                 uint64_t ctl_drp:1;
459                 uint64_t ctl_bck:1;
460                 uint64_t ctl_mcst:1;
461                 uint64_t ctl_smac:1;
462                 uint64_t pre_free:1;
463                 uint64_t vlan_len:1;
464                 uint64_t reserved_8_63:56;
465         } cn31xx;
466         struct cvmx_gmxx_rxx_frm_ctl_cn50xx {
467                 uint64_t pre_chk:1;
468                 uint64_t pre_strp:1;
469                 uint64_t ctl_drp:1;
470                 uint64_t ctl_bck:1;
471                 uint64_t ctl_mcst:1;
472                 uint64_t ctl_smac:1;
473                 uint64_t pre_free:1;
474                 uint64_t reserved_7_8:2;
475                 uint64_t pre_align:1;
476                 uint64_t null_dis:1;
477                 uint64_t reserved_11_63:53;
478         } cn50xx;
479         struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 {
480                 uint64_t pre_chk:1;
481                 uint64_t pre_strp:1;
482                 uint64_t ctl_drp:1;
483                 uint64_t ctl_bck:1;
484                 uint64_t ctl_mcst:1;
485                 uint64_t ctl_smac:1;
486                 uint64_t pre_free:1;
487                 uint64_t reserved_7_8:2;
488                 uint64_t pre_align:1;
489                 uint64_t reserved_10_63:54;
490         } cn56xxp1;
491         struct cvmx_gmxx_rxx_frm_ctl_cn58xx {
492                 uint64_t pre_chk:1;
493                 uint64_t pre_strp:1;
494                 uint64_t ctl_drp:1;
495                 uint64_t ctl_bck:1;
496                 uint64_t ctl_mcst:1;
497                 uint64_t ctl_smac:1;
498                 uint64_t pre_free:1;
499                 uint64_t vlan_len:1;
500                 uint64_t pad_len:1;
501                 uint64_t pre_align:1;
502                 uint64_t null_dis:1;
503                 uint64_t reserved_11_63:53;
504         } cn58xx;
505         struct cvmx_gmxx_rxx_frm_ctl_cn61xx {
506                 uint64_t pre_chk:1;
507                 uint64_t pre_strp:1;
508                 uint64_t ctl_drp:1;
509                 uint64_t ctl_bck:1;
510                 uint64_t ctl_mcst:1;
511                 uint64_t ctl_smac:1;
512                 uint64_t pre_free:1;
513                 uint64_t reserved_7_8:2;
514                 uint64_t pre_align:1;
515                 uint64_t null_dis:1;
516                 uint64_t reserved_11_11:1;
517                 uint64_t ptp_mode:1;
518                 uint64_t reserved_13_63:51;
519         } cn61xx;
520 };
521
522 union cvmx_gmxx_rxx_int_reg {
523         uint64_t u64;
524         struct cvmx_gmxx_rxx_int_reg_s {
525                 uint64_t minerr:1;
526                 uint64_t carext:1;
527                 uint64_t maxerr:1;
528                 uint64_t jabber:1;
529                 uint64_t fcserr:1;
530                 uint64_t alnerr:1;
531                 uint64_t lenerr:1;
532                 uint64_t rcverr:1;
533                 uint64_t skperr:1;
534                 uint64_t niberr:1;
535                 uint64_t ovrerr:1;
536                 uint64_t pcterr:1;
537                 uint64_t rsverr:1;
538                 uint64_t falerr:1;
539                 uint64_t coldet:1;
540                 uint64_t ifgerr:1;
541                 uint64_t phy_link:1;
542                 uint64_t phy_spd:1;
543                 uint64_t phy_dupx:1;
544                 uint64_t pause_drp:1;
545                 uint64_t loc_fault:1;
546                 uint64_t rem_fault:1;
547                 uint64_t bad_seq:1;
548                 uint64_t bad_term:1;
549                 uint64_t unsop:1;
550                 uint64_t uneop:1;
551                 uint64_t undat:1;
552                 uint64_t hg2fld:1;
553                 uint64_t hg2cc:1;
554                 uint64_t reserved_29_63:35;
555         } s;
556         struct cvmx_gmxx_rxx_int_reg_cn30xx {
557                 uint64_t minerr:1;
558                 uint64_t carext:1;
559                 uint64_t maxerr:1;
560                 uint64_t jabber:1;
561                 uint64_t fcserr:1;
562                 uint64_t alnerr:1;
563                 uint64_t lenerr:1;
564                 uint64_t rcverr:1;
565                 uint64_t skperr:1;
566                 uint64_t niberr:1;
567                 uint64_t ovrerr:1;
568                 uint64_t pcterr:1;
569                 uint64_t rsverr:1;
570                 uint64_t falerr:1;
571                 uint64_t coldet:1;
572                 uint64_t ifgerr:1;
573                 uint64_t phy_link:1;
574                 uint64_t phy_spd:1;
575                 uint64_t phy_dupx:1;
576                 uint64_t reserved_19_63:45;
577         } cn30xx;
578         struct cvmx_gmxx_rxx_int_reg_cn50xx {
579                 uint64_t reserved_0_0:1;
580                 uint64_t carext:1;
581                 uint64_t reserved_2_2:1;
582                 uint64_t jabber:1;
583                 uint64_t fcserr:1;
584                 uint64_t alnerr:1;
585                 uint64_t reserved_6_6:1;
586                 uint64_t rcverr:1;
587                 uint64_t skperr:1;
588                 uint64_t niberr:1;
589                 uint64_t ovrerr:1;
590                 uint64_t pcterr:1;
591                 uint64_t rsverr:1;
592                 uint64_t falerr:1;
593                 uint64_t coldet:1;
594                 uint64_t ifgerr:1;
595                 uint64_t phy_link:1;
596                 uint64_t phy_spd:1;
597                 uint64_t phy_dupx:1;
598                 uint64_t pause_drp:1;
599                 uint64_t reserved_20_63:44;
600         } cn50xx;
601         struct cvmx_gmxx_rxx_int_reg_cn52xx {
602                 uint64_t reserved_0_0:1;
603                 uint64_t carext:1;
604                 uint64_t reserved_2_2:1;
605                 uint64_t jabber:1;
606                 uint64_t fcserr:1;
607                 uint64_t reserved_5_6:2;
608                 uint64_t rcverr:1;
609                 uint64_t skperr:1;
610                 uint64_t reserved_9_9:1;
611                 uint64_t ovrerr:1;
612                 uint64_t pcterr:1;
613                 uint64_t rsverr:1;
614                 uint64_t falerr:1;
615                 uint64_t coldet:1;
616                 uint64_t ifgerr:1;
617                 uint64_t reserved_16_18:3;
618                 uint64_t pause_drp:1;
619                 uint64_t loc_fault:1;
620                 uint64_t rem_fault:1;
621                 uint64_t bad_seq:1;
622                 uint64_t bad_term:1;
623                 uint64_t unsop:1;
624                 uint64_t uneop:1;
625                 uint64_t undat:1;
626                 uint64_t hg2fld:1;
627                 uint64_t hg2cc:1;
628                 uint64_t reserved_29_63:35;
629         } cn52xx;
630         struct cvmx_gmxx_rxx_int_reg_cn56xxp1 {
631                 uint64_t reserved_0_0:1;
632                 uint64_t carext:1;
633                 uint64_t reserved_2_2:1;
634                 uint64_t jabber:1;
635                 uint64_t fcserr:1;
636                 uint64_t reserved_5_6:2;
637                 uint64_t rcverr:1;
638                 uint64_t skperr:1;
639                 uint64_t reserved_9_9:1;
640                 uint64_t ovrerr:1;
641                 uint64_t pcterr:1;
642                 uint64_t rsverr:1;
643                 uint64_t falerr:1;
644                 uint64_t coldet:1;
645                 uint64_t ifgerr:1;
646                 uint64_t reserved_16_18:3;
647                 uint64_t pause_drp:1;
648                 uint64_t loc_fault:1;
649                 uint64_t rem_fault:1;
650                 uint64_t bad_seq:1;
651                 uint64_t bad_term:1;
652                 uint64_t unsop:1;
653                 uint64_t uneop:1;
654                 uint64_t undat:1;
655                 uint64_t reserved_27_63:37;
656         } cn56xxp1;
657         struct cvmx_gmxx_rxx_int_reg_cn58xx {
658                 uint64_t minerr:1;
659                 uint64_t carext:1;
660                 uint64_t maxerr:1;
661                 uint64_t jabber:1;
662                 uint64_t fcserr:1;
663                 uint64_t alnerr:1;
664                 uint64_t lenerr:1;
665                 uint64_t rcverr:1;
666                 uint64_t skperr:1;
667                 uint64_t niberr:1;
668                 uint64_t ovrerr:1;
669                 uint64_t pcterr:1;
670                 uint64_t rsverr:1;
671                 uint64_t falerr:1;
672                 uint64_t coldet:1;
673                 uint64_t ifgerr:1;
674                 uint64_t phy_link:1;
675                 uint64_t phy_spd:1;
676                 uint64_t phy_dupx:1;
677                 uint64_t pause_drp:1;
678                 uint64_t reserved_20_63:44;
679         } cn58xx;
680         struct cvmx_gmxx_rxx_int_reg_cn61xx {
681                 uint64_t minerr:1;
682                 uint64_t carext:1;
683                 uint64_t reserved_2_2:1;
684                 uint64_t jabber:1;
685                 uint64_t fcserr:1;
686                 uint64_t reserved_5_6:2;
687                 uint64_t rcverr:1;
688                 uint64_t skperr:1;
689                 uint64_t reserved_9_9:1;
690                 uint64_t ovrerr:1;
691                 uint64_t pcterr:1;
692                 uint64_t rsverr:1;
693                 uint64_t falerr:1;
694                 uint64_t coldet:1;
695                 uint64_t ifgerr:1;
696                 uint64_t reserved_16_18:3;
697                 uint64_t pause_drp:1;
698                 uint64_t loc_fault:1;
699                 uint64_t rem_fault:1;
700                 uint64_t bad_seq:1;
701                 uint64_t bad_term:1;
702                 uint64_t unsop:1;
703                 uint64_t uneop:1;
704                 uint64_t undat:1;
705                 uint64_t hg2fld:1;
706                 uint64_t hg2cc:1;
707                 uint64_t reserved_29_63:35;
708         } cn61xx;
709 };
710
711 union cvmx_gmxx_prtx_cfg {
712         uint64_t u64;
713         struct cvmx_gmxx_prtx_cfg_s {
714                 uint64_t reserved_22_63:42;
715                 uint64_t pknd:6;
716                 uint64_t reserved_14_15:2;
717                 uint64_t tx_idle:1;
718                 uint64_t rx_idle:1;
719                 uint64_t reserved_9_11:3;
720                 uint64_t speed_msb:1;
721                 uint64_t reserved_4_7:4;
722                 uint64_t slottime:1;
723                 uint64_t duplex:1;
724                 uint64_t speed:1;
725                 uint64_t en:1;
726         } s;
727         struct cvmx_gmxx_prtx_cfg_cn30xx {
728                 uint64_t reserved_4_63:60;
729                 uint64_t slottime:1;
730                 uint64_t duplex:1;
731                 uint64_t speed:1;
732                 uint64_t en:1;
733         } cn30xx;
734         struct cvmx_gmxx_prtx_cfg_cn52xx {
735                 uint64_t reserved_14_63:50;
736                 uint64_t tx_idle:1;
737                 uint64_t rx_idle:1;
738                 uint64_t reserved_9_11:3;
739                 uint64_t speed_msb:1;
740                 uint64_t reserved_4_7:4;
741                 uint64_t slottime:1;
742                 uint64_t duplex:1;
743                 uint64_t speed:1;
744                 uint64_t en:1;
745         } cn52xx;
746 };
747
748 union cvmx_gmxx_rxx_adr_ctl {
749         uint64_t u64;
750         struct cvmx_gmxx_rxx_adr_ctl_s {
751                 uint64_t reserved_4_63:60;
752                 uint64_t cam_mode:1;
753                 uint64_t mcst:2;
754                 uint64_t bcst:1;
755         } s;
756 };
757
758 union cvmx_pip_prt_tagx {
759         uint64_t u64;
760         struct cvmx_pip_prt_tagx_s {
761                 uint64_t reserved_54_63:10;
762                 uint64_t portadd_en:1;
763                 uint64_t inc_hwchk:1;
764                 uint64_t reserved_50_51:2;
765                 uint64_t grptagbase_msb:2;
766                 uint64_t reserved_46_47:2;
767                 uint64_t grptagmask_msb:2;
768                 uint64_t reserved_42_43:2;
769                 uint64_t grp_msb:2;
770                 uint64_t grptagbase:4;
771                 uint64_t grptagmask:4;
772                 uint64_t grptag:1;
773                 uint64_t grptag_mskip:1;
774                 uint64_t tag_mode:2;
775                 uint64_t inc_vs:2;
776                 uint64_t inc_vlan:1;
777                 uint64_t inc_prt_flag:1;
778                 uint64_t ip6_dprt_flag:1;
779                 uint64_t ip4_dprt_flag:1;
780                 uint64_t ip6_sprt_flag:1;
781                 uint64_t ip4_sprt_flag:1;
782                 uint64_t ip6_nxth_flag:1;
783                 uint64_t ip4_pctl_flag:1;
784                 uint64_t ip6_dst_flag:1;
785                 uint64_t ip4_dst_flag:1;
786                 uint64_t ip6_src_flag:1;
787                 uint64_t ip4_src_flag:1;
788                 uint64_t tcp6_tag_type:2;
789                 uint64_t tcp4_tag_type:2;
790                 uint64_t ip6_tag_type:2;
791                 uint64_t ip4_tag_type:2;
792                 uint64_t non_tag_type:2;
793                 uint64_t grp:4;
794         } s;
795         struct cvmx_pip_prt_tagx_cn30xx {
796                 uint64_t reserved_40_63:24;
797                 uint64_t grptagbase:4;
798                 uint64_t grptagmask:4;
799                 uint64_t grptag:1;
800                 uint64_t reserved_30_30:1;
801                 uint64_t tag_mode:2;
802                 uint64_t inc_vs:2;
803                 uint64_t inc_vlan:1;
804                 uint64_t inc_prt_flag:1;
805                 uint64_t ip6_dprt_flag:1;
806                 uint64_t ip4_dprt_flag:1;
807                 uint64_t ip6_sprt_flag:1;
808                 uint64_t ip4_sprt_flag:1;
809                 uint64_t ip6_nxth_flag:1;
810                 uint64_t ip4_pctl_flag:1;
811                 uint64_t ip6_dst_flag:1;
812                 uint64_t ip4_dst_flag:1;
813                 uint64_t ip6_src_flag:1;
814                 uint64_t ip4_src_flag:1;
815                 uint64_t tcp6_tag_type:2;
816                 uint64_t tcp4_tag_type:2;
817                 uint64_t ip6_tag_type:2;
818                 uint64_t ip4_tag_type:2;
819                 uint64_t non_tag_type:2;
820                 uint64_t grp:4;
821         } cn30xx;
822         struct cvmx_pip_prt_tagx_cn50xx {
823                 uint64_t reserved_40_63:24;
824                 uint64_t grptagbase:4;
825                 uint64_t grptagmask:4;
826                 uint64_t grptag:1;
827                 uint64_t grptag_mskip:1;
828                 uint64_t tag_mode:2;
829                 uint64_t inc_vs:2;
830                 uint64_t inc_vlan:1;
831                 uint64_t inc_prt_flag:1;
832                 uint64_t ip6_dprt_flag:1;
833                 uint64_t ip4_dprt_flag:1;
834                 uint64_t ip6_sprt_flag:1;
835                 uint64_t ip4_sprt_flag:1;
836                 uint64_t ip6_nxth_flag:1;
837                 uint64_t ip4_pctl_flag:1;
838                 uint64_t ip6_dst_flag:1;
839                 uint64_t ip4_dst_flag:1;
840                 uint64_t ip6_src_flag:1;
841                 uint64_t ip4_src_flag:1;
842                 uint64_t tcp6_tag_type:2;
843                 uint64_t tcp4_tag_type:2;
844                 uint64_t ip6_tag_type:2;
845                 uint64_t ip4_tag_type:2;
846                 uint64_t non_tag_type:2;
847                 uint64_t grp:4;
848         } cn50xx;
849 };
850
851 union cvmx_spxx_int_reg {
852         uint64_t u64;
853         struct cvmx_spxx_int_reg_s {
854                 uint64_t reserved_32_63:32;
855                 uint64_t spf:1;
856                 uint64_t reserved_12_30:19;
857                 uint64_t calerr:1;
858                 uint64_t syncerr:1;
859                 uint64_t diperr:1;
860                 uint64_t tpaovr:1;
861                 uint64_t rsverr:1;
862                 uint64_t drwnng:1;
863                 uint64_t clserr:1;
864                 uint64_t spiovr:1;
865                 uint64_t reserved_2_3:2;
866                 uint64_t abnorm:1;
867                 uint64_t prtnxa:1;
868         } s;
869 };
870
871 union cvmx_spxx_int_msk {
872         uint64_t u64;
873         struct cvmx_spxx_int_msk_s {
874                 uint64_t reserved_12_63:52;
875                 uint64_t calerr:1;
876                 uint64_t syncerr:1;
877                 uint64_t diperr:1;
878                 uint64_t tpaovr:1;
879                 uint64_t rsverr:1;
880                 uint64_t drwnng:1;
881                 uint64_t clserr:1;
882                 uint64_t spiovr:1;
883                 uint64_t reserved_2_3:2;
884                 uint64_t abnorm:1;
885                 uint64_t prtnxa:1;
886         } s;
887 };
888
889 union cvmx_pow_wq_int {
890         uint64_t u64;
891         struct cvmx_pow_wq_int_s {
892                 uint64_t wq_int:16;
893                 uint64_t iq_dis:16;
894                 uint64_t reserved_32_63:32;
895         } s;
896 };
897
898 union cvmx_sso_wq_int_thrx {
899         uint64_t u64;
900         struct {
901                 uint64_t iq_thr:12;
902                 uint64_t reserved_12_13:2;
903                 uint64_t ds_thr:12;
904                 uint64_t reserved_26_27:2;
905                 uint64_t tc_thr:4;
906                 uint64_t tc_en:1;
907                 uint64_t reserved_33_63:31;
908         } s;
909 };
910
911 union cvmx_stxx_int_reg {
912         uint64_t u64;
913         struct cvmx_stxx_int_reg_s {
914                 uint64_t reserved_9_63:55;
915                 uint64_t syncerr:1;
916                 uint64_t frmerr:1;
917                 uint64_t unxfrm:1;
918                 uint64_t nosync:1;
919                 uint64_t diperr:1;
920                 uint64_t datovr:1;
921                 uint64_t ovrbst:1;
922                 uint64_t calpar1:1;
923                 uint64_t calpar0:1;
924         } s;
925 };
926
927 union cvmx_stxx_int_msk {
928         uint64_t u64;
929         struct cvmx_stxx_int_msk_s {
930                 uint64_t reserved_8_63:56;
931                 uint64_t frmerr:1;
932                 uint64_t unxfrm:1;
933                 uint64_t nosync:1;
934                 uint64_t diperr:1;
935                 uint64_t datovr:1;
936                 uint64_t ovrbst:1;
937                 uint64_t calpar1:1;
938                 uint64_t calpar0:1;
939         } s;
940 };
941
942 union cvmx_pow_wq_int_pc {
943         uint64_t u64;
944         struct cvmx_pow_wq_int_pc_s {
945                 uint64_t reserved_0_7:8;
946                 uint64_t pc_thr:20;
947                 uint64_t reserved_28_31:4;
948                 uint64_t pc:28;
949                 uint64_t reserved_60_63:4;
950         } s;
951 };
952
953 union cvmx_pow_wq_int_thrx {
954         uint64_t u64;
955         struct cvmx_pow_wq_int_thrx_s {
956                 uint64_t reserved_29_63:35;
957                 uint64_t tc_en:1;
958                 uint64_t tc_thr:4;
959                 uint64_t reserved_23_23:1;
960                 uint64_t ds_thr:11;
961                 uint64_t reserved_11_11:1;
962                 uint64_t iq_thr:11;
963         } s;
964         struct cvmx_pow_wq_int_thrx_cn30xx {
965                 uint64_t reserved_29_63:35;
966                 uint64_t tc_en:1;
967                 uint64_t tc_thr:4;
968                 uint64_t reserved_18_23:6;
969                 uint64_t ds_thr:6;
970                 uint64_t reserved_6_11:6;
971                 uint64_t iq_thr:6;
972         } cn30xx;
973         struct cvmx_pow_wq_int_thrx_cn31xx {
974                 uint64_t reserved_29_63:35;
975                 uint64_t tc_en:1;
976                 uint64_t tc_thr:4;
977                 uint64_t reserved_20_23:4;
978                 uint64_t ds_thr:8;
979                 uint64_t reserved_8_11:4;
980                 uint64_t iq_thr:8;
981         } cn31xx;
982         struct cvmx_pow_wq_int_thrx_cn52xx {
983                 uint64_t reserved_29_63:35;
984                 uint64_t tc_en:1;
985                 uint64_t tc_thr:4;
986                 uint64_t reserved_21_23:3;
987                 uint64_t ds_thr:9;
988                 uint64_t reserved_9_11:3;
989                 uint64_t iq_thr:9;
990         } cn52xx;
991         struct cvmx_pow_wq_int_thrx_cn63xx {
992                 uint64_t reserved_29_63:35;
993                 uint64_t tc_en:1;
994                 uint64_t tc_thr:4;
995                 uint64_t reserved_22_23:2;
996                 uint64_t ds_thr:10;
997                 uint64_t reserved_10_11:2;
998                 uint64_t iq_thr:10;
999         } cn63xx;
1000 };
1001
1002 union cvmx_npi_rsl_int_blocks {
1003         uint64_t u64;
1004         struct cvmx_npi_rsl_int_blocks_s {
1005                 uint64_t reserved_32_63:32;
1006                 uint64_t rint_31:1;
1007                 uint64_t iob:1;
1008                 uint64_t reserved_28_29:2;
1009                 uint64_t rint_27:1;
1010                 uint64_t rint_26:1;
1011                 uint64_t rint_25:1;
1012                 uint64_t rint_24:1;
1013                 uint64_t asx1:1;
1014                 uint64_t asx0:1;
1015                 uint64_t rint_21:1;
1016                 uint64_t pip:1;
1017                 uint64_t spx1:1;
1018                 uint64_t spx0:1;
1019                 uint64_t lmc:1;
1020                 uint64_t l2c:1;
1021                 uint64_t rint_15:1;
1022                 uint64_t reserved_13_14:2;
1023                 uint64_t pow:1;
1024                 uint64_t tim:1;
1025                 uint64_t pko:1;
1026                 uint64_t ipd:1;
1027                 uint64_t rint_8:1;
1028                 uint64_t zip:1;
1029                 uint64_t dfa:1;
1030                 uint64_t fpa:1;
1031                 uint64_t key:1;
1032                 uint64_t npi:1;
1033                 uint64_t gmx1:1;
1034                 uint64_t gmx0:1;
1035                 uint64_t mio:1;
1036         } s;
1037         struct cvmx_npi_rsl_int_blocks_cn30xx {
1038                 uint64_t reserved_32_63:32;
1039                 uint64_t rint_31:1;
1040                 uint64_t iob:1;
1041                 uint64_t rint_29:1;
1042                 uint64_t rint_28:1;
1043                 uint64_t rint_27:1;
1044                 uint64_t rint_26:1;
1045                 uint64_t rint_25:1;
1046                 uint64_t rint_24:1;
1047                 uint64_t asx1:1;
1048                 uint64_t asx0:1;
1049                 uint64_t rint_21:1;
1050                 uint64_t pip:1;
1051                 uint64_t spx1:1;
1052                 uint64_t spx0:1;
1053                 uint64_t lmc:1;
1054                 uint64_t l2c:1;
1055                 uint64_t rint_15:1;
1056                 uint64_t rint_14:1;
1057                 uint64_t usb:1;
1058                 uint64_t pow:1;
1059                 uint64_t tim:1;
1060                 uint64_t pko:1;
1061                 uint64_t ipd:1;
1062                 uint64_t rint_8:1;
1063                 uint64_t zip:1;
1064                 uint64_t dfa:1;
1065                 uint64_t fpa:1;
1066                 uint64_t key:1;
1067                 uint64_t npi:1;
1068                 uint64_t gmx1:1;
1069                 uint64_t gmx0:1;
1070                 uint64_t mio:1;
1071         } cn30xx;
1072         struct cvmx_npi_rsl_int_blocks_cn38xx {
1073                 uint64_t reserved_32_63:32;
1074                 uint64_t rint_31:1;
1075                 uint64_t iob:1;
1076                 uint64_t rint_29:1;
1077                 uint64_t rint_28:1;
1078                 uint64_t rint_27:1;
1079                 uint64_t rint_26:1;
1080                 uint64_t rint_25:1;
1081                 uint64_t rint_24:1;
1082                 uint64_t asx1:1;
1083                 uint64_t asx0:1;
1084                 uint64_t rint_21:1;
1085                 uint64_t pip:1;
1086                 uint64_t spx1:1;
1087                 uint64_t spx0:1;
1088                 uint64_t lmc:1;
1089                 uint64_t l2c:1;
1090                 uint64_t rint_15:1;
1091                 uint64_t rint_14:1;
1092                 uint64_t rint_13:1;
1093                 uint64_t pow:1;
1094                 uint64_t tim:1;
1095                 uint64_t pko:1;
1096                 uint64_t ipd:1;
1097                 uint64_t rint_8:1;
1098                 uint64_t zip:1;
1099                 uint64_t dfa:1;
1100                 uint64_t fpa:1;
1101                 uint64_t key:1;
1102                 uint64_t npi:1;
1103                 uint64_t gmx1:1;
1104                 uint64_t gmx0:1;
1105                 uint64_t mio:1;
1106         } cn38xx;
1107         struct cvmx_npi_rsl_int_blocks_cn50xx {
1108                 uint64_t reserved_31_63:33;
1109                 uint64_t iob:1;
1110                 uint64_t lmc1:1;
1111                 uint64_t agl:1;
1112                 uint64_t reserved_24_27:4;
1113                 uint64_t asx1:1;
1114                 uint64_t asx0:1;
1115                 uint64_t reserved_21_21:1;
1116                 uint64_t pip:1;
1117                 uint64_t spx1:1;
1118                 uint64_t spx0:1;
1119                 uint64_t lmc:1;
1120                 uint64_t l2c:1;
1121                 uint64_t reserved_15_15:1;
1122                 uint64_t rad:1;
1123                 uint64_t usb:1;
1124                 uint64_t pow:1;
1125                 uint64_t tim:1;
1126                 uint64_t pko:1;
1127                 uint64_t ipd:1;
1128                 uint64_t reserved_8_8:1;
1129                 uint64_t zip:1;
1130                 uint64_t dfa:1;
1131                 uint64_t fpa:1;
1132                 uint64_t key:1;
1133                 uint64_t npi:1;
1134                 uint64_t gmx1:1;
1135                 uint64_t gmx0:1;
1136                 uint64_t mio:1;
1137         } cn50xx;
1138 };
1139
1140 union cvmx_pko_command_word0 {
1141         uint64_t u64;
1142         struct {
1143                 uint64_t total_bytes:16;
1144                 uint64_t segs:6;
1145                 uint64_t dontfree:1;
1146                 uint64_t ignore_i:1;
1147                 uint64_t ipoffp1:7;
1148                 uint64_t gather:1;
1149                 uint64_t rsp:1;
1150                 uint64_t wqp:1;
1151                 uint64_t n2:1;
1152                 uint64_t le:1;
1153                 uint64_t reg0:11;
1154                 uint64_t subone0:1;
1155                 uint64_t reg1:11;
1156                 uint64_t subone1:1;
1157                 uint64_t size0:2;
1158                 uint64_t size1:2;
1159         } s;
1160 };
1161
1162 union cvmx_ciu_timx {
1163         uint64_t u64;
1164         struct cvmx_ciu_timx_s {
1165                 uint64_t reserved_37_63:27;
1166                 uint64_t one_shot:1;
1167                 uint64_t len:36;
1168         } s;
1169 };
1170
1171 union cvmx_gmxx_rxx_rx_inbnd {
1172         uint64_t u64;
1173         struct cvmx_gmxx_rxx_rx_inbnd_s {
1174                 uint64_t status:1;
1175                 uint64_t speed:2;
1176                 uint64_t duplex:1;
1177                 uint64_t reserved_4_63:60;
1178         } s;
1179 };
1180
1181 static inline int32_t cvmx_fau_fetch_and_add32(enum cvmx_fau_reg_32 reg,
1182                                                int32_t value)
1183 {
1184         return value;
1185 }
1186
1187 static inline void cvmx_fau_atomic_add32(enum cvmx_fau_reg_32 reg,
1188                                          int32_t value)
1189 { }
1190
1191 static inline void cvmx_fau_atomic_write32(enum cvmx_fau_reg_32 reg,
1192                                            int32_t value)
1193 { }
1194
1195 static inline uint64_t cvmx_scratch_read64(uint64_t address)
1196 {
1197         return 0;
1198 }
1199
1200 static inline void cvmx_scratch_write64(uint64_t address, uint64_t value)
1201 { }
1202
1203 static inline int cvmx_wqe_get_grp(struct cvmx_wqe *work)
1204 {
1205         return 0;
1206 }
1207
1208 static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
1209 {
1210         return (void *)(uintptr_t)(physical_address);
1211 }
1212
1213 static inline uint64_t cvmx_ptr_to_phys(void *ptr)
1214 {
1215         return (unsigned long)ptr;
1216 }
1217
1218 static inline int cvmx_helper_get_interface_num(int ipd_port)
1219 {
1220         return ipd_port;
1221 }
1222
1223 static inline int cvmx_helper_get_interface_index_num(int ipd_port)
1224 {
1225         return ipd_port;
1226 }
1227
1228 static inline void cvmx_fpa_enable(void)
1229 { }
1230
1231 static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
1232 {
1233         return 0;
1234 }
1235
1236 static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
1237 { }
1238
1239 static inline int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1240 {
1241         return 0;
1242 }
1243
1244 static inline void *cvmx_fpa_alloc(uint64_t pool)
1245 {
1246         return NULL;
1247 }
1248
1249 static inline void cvmx_fpa_free(void *ptr, uint64_t pool,
1250                                  uint64_t num_cache_lines)
1251 { }
1252
1253 static inline int octeon_is_simulation(void)
1254 {
1255         return 1;
1256 }
1257
1258 static inline void cvmx_pip_get_port_status(uint64_t port_num, uint64_t clear,
1259                                             cvmx_pip_port_status_t *status)
1260 { }
1261
1262 static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
1263                                             cvmx_pko_port_status_t *status)
1264 { }
1265
1266 static inline cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int
1267                                                                    interface)
1268 {
1269         return 0;
1270 }
1271
1272 static inline union cvmx_helper_link_info cvmx_helper_link_get(int ipd_port)
1273 {
1274         union cvmx_helper_link_info ret = { .u64 = 0 };
1275
1276         return ret;
1277 }
1278
1279 static inline int cvmx_helper_link_set(int ipd_port,
1280                                        union cvmx_helper_link_info link_info)
1281 {
1282         return 0;
1283 }
1284
1285 static inline int cvmx_helper_initialize_packet_io_global(void)
1286 {
1287         return 0;
1288 }
1289
1290 static inline int cvmx_helper_get_number_of_interfaces(void)
1291 {
1292         return 2;
1293 }
1294
1295 static inline int cvmx_helper_ports_on_interface(int interface)
1296 {
1297         return 1;
1298 }
1299
1300 static inline int cvmx_helper_get_ipd_port(int interface, int port)
1301 {
1302         return 0;
1303 }
1304
1305 static inline int cvmx_helper_ipd_and_packet_input_enable(void)
1306 {
1307         return 0;
1308 }
1309
1310 static inline void cvmx_ipd_disable(void)
1311 { }
1312
1313 static inline void cvmx_ipd_free_ptr(void)
1314 { }
1315
1316 static inline void cvmx_pko_disable(void)
1317 { }
1318
1319 static inline void cvmx_pko_shutdown(void)
1320 { }
1321
1322 static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
1323 {
1324         return port;
1325 }
1326
1327 static inline int cvmx_pko_get_base_queue(int port)
1328 {
1329         return port;
1330 }
1331
1332 static inline int cvmx_pko_get_num_queues(int port)
1333 {
1334         return port;
1335 }
1336
1337 static inline unsigned int cvmx_get_core_num(void)
1338 {
1339         return 0;
1340 }
1341
1342 static inline void cvmx_pow_work_request_async_nocheck(int scr_addr,
1343                                                        cvmx_pow_wait_t wait)
1344 { }
1345
1346 static inline void cvmx_pow_work_request_async(int scr_addr,
1347                                                        cvmx_pow_wait_t wait)
1348 { }
1349
1350 static inline struct cvmx_wqe *cvmx_pow_work_response_async(int scr_addr)
1351 {
1352         struct cvmx_wqe *wqe = (void *)(unsigned long)scr_addr;
1353
1354         return wqe;
1355 }
1356
1357 static inline struct cvmx_wqe *cvmx_pow_work_request_sync(cvmx_pow_wait_t wait)
1358 {
1359         return (void *)(unsigned long)wait;
1360 }
1361
1362 static inline int cvmx_spi_restart_interface(int interface,
1363                                         cvmx_spi_mode_t mode, int timeout)
1364 {
1365         return 0;
1366 }
1367
1368 static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr,
1369                                                   enum cvmx_fau_reg_32 reg,
1370                                                   int32_t value)
1371 { }
1372
1373 static inline union cvmx_gmxx_rxx_rx_inbnd cvmx_spi4000_check_speed(
1374         int interface,
1375         int port)
1376 {
1377         union cvmx_gmxx_rxx_rx_inbnd r;
1378
1379         r.u64 = 0;
1380         return r;
1381 }
1382
1383 static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
1384                                                 cvmx_pko_lock_t use_locking)
1385 { }
1386
1387 static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(uint64_t port,
1388                 uint64_t queue, union cvmx_pko_command_word0 pko_command,
1389                 union cvmx_buf_ptr packet, cvmx_pko_lock_t use_locking)
1390 {
1391         return 0;
1392 }
1393
1394 static inline void cvmx_wqe_set_port(struct cvmx_wqe *work, int port)
1395 { }
1396
1397 static inline void cvmx_wqe_set_qos(struct cvmx_wqe *work, int qos)
1398 { }
1399
1400 static inline int cvmx_wqe_get_qos(struct cvmx_wqe *work)
1401 {
1402         return 0;
1403 }
1404
1405 static inline void cvmx_wqe_set_grp(struct cvmx_wqe *work, int grp)
1406 { }
1407
1408 static inline void cvmx_pow_work_submit(struct cvmx_wqe *wqp, uint32_t tag,
1409                                         enum cvmx_pow_tag_type tag_type,
1410                                         uint64_t qos, uint64_t grp)
1411 { }
1412
1413 #define CVMX_ASXX_RX_CLK_SETX(a, b)     ((a)+(b))
1414 #define CVMX_ASXX_TX_CLK_SETX(a, b)     ((a)+(b))
1415 #define CVMX_CIU_TIMX(a)                (a)
1416 #define CVMX_GMXX_RXX_ADR_CAM0(a, b)    ((a)+(b))
1417 #define CVMX_GMXX_RXX_ADR_CAM1(a, b)    ((a)+(b))
1418 #define CVMX_GMXX_RXX_ADR_CAM2(a, b)    ((a)+(b))
1419 #define CVMX_GMXX_RXX_ADR_CAM3(a, b)    ((a)+(b))
1420 #define CVMX_GMXX_RXX_ADR_CAM4(a, b)    ((a)+(b))
1421 #define CVMX_GMXX_RXX_ADR_CAM5(a, b)    ((a)+(b))
1422 #define CVMX_GMXX_RXX_FRM_CTL(a, b)     ((a)+(b))
1423 #define CVMX_GMXX_RXX_INT_REG(a, b)     ((a)+(b))
1424 #define CVMX_GMXX_SMACX(a, b)           ((a)+(b))
1425 #define CVMX_PIP_PRT_TAGX(a)            (a)
1426 #define CVMX_POW_PP_GRP_MSKX(a)         (a)
1427 #define CVMX_POW_WQ_INT_THRX(a)         (a)
1428 #define CVMX_SPXX_INT_MSK(a)            (a)
1429 #define CVMX_SPXX_INT_REG(a)            (a)
1430 #define CVMX_SSO_PPX_GRP_MSK(a)         (a)
1431 #define CVMX_SSO_WQ_INT_THRX(a)         (a)
1432 #define CVMX_STXX_INT_MSK(a)            (a)
1433 #define CVMX_STXX_INT_REG(a)            (a)