2 * register description for HopeRf rf69 radio module
4 * Copyright (C) 2016 Wolf-Entwicklungen
5 * Marcus Wolf <linux@wolf-entwicklungen.de>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 /*******************************************/
19 /* RF69 register addresses */
20 /*******************************************/
22 #define REG_OPMODE 0x01
23 #define REG_DATAMODUL 0x02
24 #define REG_BITRATE_MSB 0x03
25 #define REG_BITRATE_LSB 0x04
26 #define REG_FDEV_MSB 0x05
27 #define REG_FDEV_LSB 0x06
28 #define REG_FRF_MSB 0x07
29 #define REG_FRF_MID 0x08
30 #define REG_FRF_LSB 0x09
32 #define REG_AFCCTRL 0x0B
33 #define REG_LOWBAT 0x0C
34 #define REG_LISTEN1 0x0D
35 #define REG_LISTEN2 0x0E
36 #define REG_LISTEN3 0x0F
37 #define REG_VERSION 0x10
38 #define REG_PALEVEL 0x11
39 #define REG_PARAMP 0x12
41 #define REG_AGCREF 0x14 /* not available on RF69 */
42 #define REG_AGCTHRESH1 0x15 /* not available on RF69 */
43 #define REG_AGCTHRESH2 0x16 /* not available on RF69 */
44 #define REG_AGCTHRESH3 0x17 /* not available on RF69 */
47 #define REG_AFCBW 0x1A
48 #define REG_OOKPEAK 0x1B
49 #define REG_OOKAVG 0x1C
50 #define REG_OOKFIX 0x1D
51 #define REG_AFCFEI 0x1E
52 #define REG_AFCMSB 0x1F
53 #define REG_AFCLSB 0x20
54 #define REG_FEIMSB 0x21
55 #define REG_FEILSB 0x22
56 #define REG_RSSICONFIG 0x23
57 #define REG_RSSIVALUE 0x24
58 #define REG_DIOMAPPING1 0x25
59 #define REG_DIOMAPPING2 0x26
60 #define REG_IRQFLAGS1 0x27
61 #define REG_IRQFLAGS2 0x28
62 #define REG_RSSITHRESH 0x29
63 #define REG_RXTIMEOUT1 0x2A
64 #define REG_RXTIMEOUT2 0x2B
65 #define REG_PREAMBLE_MSB 0x2C
66 #define REG_PREAMBLE_LSB 0x2D
67 #define REG_SYNC_CONFIG 0x2E
68 #define REG_SYNCVALUE1 0x2F
69 #define REG_SYNCVALUE2 0x30
70 #define REG_SYNCVALUE3 0x31
71 #define REG_SYNCVALUE4 0x32
72 #define REG_SYNCVALUE5 0x33
73 #define REG_SYNCVALUE6 0x34
74 #define REG_SYNCVALUE7 0x35
75 #define REG_SYNCVALUE8 0x36
76 #define REG_PACKETCONFIG1 0x37
77 #define REG_PAYLOAD_LENGTH 0x38
78 #define REG_NODEADRS 0x39
79 #define REG_BROADCASTADRS 0x3A
80 #define REG_AUTOMODES 0x3B
81 #define REG_FIFO_THRESH 0x3C
82 #define REG_PACKETCONFIG2 0x3D
83 #define REG_AESKEY1 0x3E
84 #define REG_AESKEY2 0x3F
85 #define REG_AESKEY3 0x40
86 #define REG_AESKEY4 0x41
87 #define REG_AESKEY5 0x42
88 #define REG_AESKEY6 0x43
89 #define REG_AESKEY7 0x44
90 #define REG_AESKEY8 0x45
91 #define REG_AESKEY9 0x46
92 #define REG_AESKEY10 0x47
93 #define REG_AESKEY11 0x48
94 #define REG_AESKEY12 0x49
95 #define REG_AESKEY13 0x4A
96 #define REG_AESKEY14 0x4B
97 #define REG_AESKEY15 0x4C
98 #define REG_AESKEY16 0x4D
99 #define REG_TEMP1 0x4E
100 #define REG_TEMP2 0x4F
101 #define REG_TESTPA1 0x5A /* only present on RFM69HW */
102 #define REG_TESTPA2 0x5C /* only present on RFM69HW */
103 #define REG_TESTDAGC 0x6F
105 /******************************************************/
106 /* RF69/SX1231 bit definition */
107 /******************************************************/
109 #define WRITE_BIT 0x80
112 #define MASK_OPMODE_SEQUENCER_OFF 0x80
113 #define MASK_OPMODE_LISTEN_ON 0x40
114 #define MASK_OPMODE_LISTEN_ABORT 0x20
115 #define MASK_OPMODE_MODE 0x1C
117 #define OPMODE_MODE_SLEEP 0x00
118 #define OPMODE_MODE_STANDBY 0x04 /* default */
119 #define OPMODE_MODE_SYNTHESIZER 0x08
120 #define OPMODE_MODE_TRANSMIT 0x0C
121 #define OPMODE_MODE_RECEIVE 0x10
124 #define MASK_DATAMODUL_MODE 0x06
125 #define MASK_DATAMODUL_MODULATION_TYPE 0x18
126 #define MASK_DATAMODUL_MODULATION_SHAPE 0x03
128 #define DATAMODUL_MODE_PACKET 0x00 /* default */
129 #define DATAMODUL_MODE_CONTINUOUS 0x40
130 #define DATAMODUL_MODE_CONTINUOUS_NOSYNC 0x60
132 #define DATAMODUL_MODULATION_TYPE_FSK 0x00 /* default */
133 #define DATAMODUL_MODULATION_TYPE_OOK 0x08
135 #define DATAMODUL_MODULATION_SHAPE_NONE 0x00 /* default */
136 #define DATAMODUL_MODULATION_SHAPE_1_0 0x01
137 #define DATAMODUL_MODULATION_SHAPE_0_5 0x02
138 #define DATAMODUL_MODULATION_SHAPE_0_3 0x03
139 #define DATAMODUL_MODULATION_SHAPE_BR 0x01
140 #define DATAMODUL_MODULATION_SHAPE_2BR 0x02
142 /* RegFDevMsb (0x05)*/
143 #define FDEVMASB_MASK 0x3f
147 * #define OSC1_RCCAL_START 0x80
148 * #define OSC1_RCCAL_DONE 0x40
151 * #define LOWBAT_MONITOR 0x10
152 * #define LOWBAT_ON 0x08
153 * #define LOWBAT_OFF 0x00 // Default
155 * #define LOWBAT_TRIM_1695 0x00
156 * #define LOWBAT_TRIM_1764 0x01
157 * #define LOWBAT_TRIM_1835 0x02 // Default
158 * #define LOWBAT_TRIM_1905 0x03
159 * #define LOWBAT_TRIM_1976 0x04
160 * #define LOWBAT_TRIM_2045 0x05
161 * #define LOWBAT_TRIM_2116 0x06
162 * #define LOWBAT_TRIM_2185 0x07
166 * #define LISTEN1_RESOL_64 0x50
167 * #define LISTEN1_RESOL_4100 0xA0 // Default
168 * #define LISTEN1_RESOL_262000 0xF0
170 * #define LISTEN1_CRITERIA_RSSI 0x00 // Default
171 * #define LISTEN1_CRITERIA_RSSIANDSYNC 0x08
173 * #define LISTEN1_END_00 0x00
174 * #define LISTEN1_END_01 0x02 // Default
175 * #define LISTEN1_END_10 0x04
179 * #define LISTEN2_COEFIDLE_VALUE 0xF5 // Default
182 * #define LISTEN3_COEFRX_VALUE 0x20 // Default
186 #define MASK_PALEVEL_PA0 0x80
187 #define MASK_PALEVEL_PA1 0x40
188 #define MASK_PALEVEL_PA2 0x20
189 #define MASK_PALEVEL_OUTPUT_POWER 0x1F
192 #define PARAMP_3400 0x00
193 #define PARAMP_2000 0x01
194 #define PARAMP_1000 0x02
195 #define PARAMP_500 0x03
196 #define PARAMP_250 0x04
197 #define PARAMP_125 0x05
198 #define PARAMP_100 0x06
199 #define PARAMP_62 0x07
200 #define PARAMP_50 0x08
201 #define PARAMP_40 0x09 /* default */
202 #define PARAMP_31 0x0A
203 #define PARAMP_25 0x0B
204 #define PARAMP_20 0x0C
205 #define PARAMP_15 0x0D
206 #define PARAMP_12 0x0E
207 #define PARAMP_10 0x0F
209 #define MASK_PARAMP 0x0F
213 * #define OCP_OFF 0x0F
214 * #define OCP_ON 0x1A // Default
216 * #define OCP_TRIM_45 0x00
217 * #define OCP_TRIM_50 0x01
218 * #define OCP_TRIM_55 0x02
219 * #define OCP_TRIM_60 0x03
220 * #define OCP_TRIM_65 0x04
221 * #define OCP_TRIM_70 0x05
222 * #define OCP_TRIM_75 0x06
223 * #define OCP_TRIM_80 0x07
224 * #define OCP_TRIM_85 0x08
225 * #define OCP_TRIM_90 0x09
226 * #define OCP_TRIM_95 0x0A
227 * #define OCP_TRIM_100 0x0B // Default
228 * #define OCP_TRIM_105 0x0C
229 * #define OCP_TRIM_110 0x0D
230 * #define OCP_TRIM_115 0x0E
231 * #define OCP_TRIM_120 0x0F
235 #define MASK_LNA_ZIN 0x80
236 #define MASK_LNA_CURRENT_GAIN 0x38
237 #define MASK_LNA_GAIN 0x07
239 #define LNA_GAIN_AUTO 0x00 /* default */
240 #define LNA_GAIN_MAX 0x01
241 #define LNA_GAIN_MAX_MINUS_6 0x02
242 #define LNA_GAIN_MAX_MINUS_12 0x03
243 #define LNA_GAIN_MAX_MINUS_24 0x04
244 #define LNA_GAIN_MAX_MINUS_36 0x05
245 #define LNA_GAIN_MAX_MINUS_48 0x06
247 /* RegRxBw (0x19) and RegAfcBw (0x1A) */
248 #define MASK_BW_DCC_FREQ 0xE0
249 #define MASK_BW_MANTISSE 0x18
250 #define MASK_BW_EXPONENT 0x07
252 #define BW_DCC_16_PERCENT 0x00
253 #define BW_DCC_8_PERCENT 0x20
254 #define BW_DCC_4_PERCENT 0x40 /* default */
255 #define BW_DCC_2_PERCENT 0x60
256 #define BW_DCC_1_PERCENT 0x80
257 #define BW_DCC_0_5_PERCENT 0xA0
258 #define BW_DCC_0_25_PERCENT 0xC0
259 #define BW_DCC_0_125_PERCENT 0xE0
261 #define BW_MANT_16 0x00
262 #define BW_MANT_20 0x08
263 #define BW_MANT_24 0x10 /* default */
265 /* RegOokPeak (0x1B) */
266 #define MASK_OOKPEAK_THRESTYPE 0xc0
267 #define MASK_OOKPEAK_THRESSTEP 0x38
268 #define MASK_OOKPEAK_THRESDEC 0x07
270 #define OOKPEAK_THRESHTYPE_FIXED 0x00
271 #define OOKPEAK_THRESHTYPE_PEAK 0x40 /* default */
272 #define OOKPEAK_THRESHTYPE_AVERAGE 0x80
274 #define OOKPEAK_THRESHSTEP_0_5_DB 0x00 /* default */
275 #define OOKPEAK_THRESHSTEP_1_0_DB 0x08
276 #define OOKPEAK_THRESHSTEP_1_5_DB 0x10
277 #define OOKPEAK_THRESHSTEP_2_0_DB 0x18
278 #define OOKPEAK_THRESHSTEP_3_0_DB 0x20
279 #define OOKPEAK_THRESHSTEP_4_0_DB 0x28
280 #define OOKPEAK_THRESHSTEP_5_0_DB 0x30
281 #define OOKPEAK_THRESHSTEP_6_0_DB 0x38
283 #define OOKPEAK_THRESHDEC_ONCE 0x00 /* default */
284 #define OOKPEAK_THRESHDEC_EVERY_2ND 0x01
285 #define OOKPEAK_THRESHDEC_EVERY_4TH 0x02
286 #define OOKPEAK_THRESHDEC_EVERY_8TH 0x03
287 #define OOKPEAK_THRESHDEC_TWICE 0x04
288 #define OOKPEAK_THRESHDEC_4_TIMES 0x05
289 #define OOKPEAK_THRESHDEC_8_TIMES 0x06
290 #define OOKPEAK_THRESHDEC_16_TIMES 0x07
294 * #define OOKAVG_AVERAGETHRESHFILT_00 0x00
295 * #define OOKAVG_AVERAGETHRESHFILT_01 0x40
296 * #define OOKAVG_AVERAGETHRESHFILT_10 0x80 // Default
297 * #define OOKAVG_AVERAGETHRESHFILT_11 0xC0
301 * #define AFCFEI_FEI_DONE 0x40
302 * #define AFCFEI_FEI_START 0x20
303 * #define AFCFEI_AFC_DONE 0x10
304 * #define AFCFEI_AFCAUTOCLEAR_ON 0x08
305 * #define AFCFEI_AFCAUTOCLEAR_OFF 0x00 // Default
307 * #define AFCFEI_AFCAUTO_ON 0x04
308 * #define AFCFEI_AFCAUTO_OFF 0x00 // Default
310 * #define AFCFEI_AFC_CLEAR 0x02
311 * #define AFCFEI_AFC_START 0x01
314 * #define RSSI_FASTRX_ON 0x08
315 * #define RSSI_FASTRX_OFF 0x00 // Default
316 * #define RSSI_DONE 0x02
317 * #define RSSI_START 0x01
321 #define MASK_DIO0 0xC0
322 #define MASK_DIO1 0x30
323 #define MASK_DIO2 0x0C
324 #define MASK_DIO3 0x03
331 #define MASK_DIO4 0xC0
332 #define MASK_DIO5 0x30
344 /* DIO Mapping values (packet mode) */
345 #define DIO_MODE_READY_DIO4 0x00
346 #define DIO_MODE_READY_DIO5 0x03
347 #define DIO_CLK_OUT 0x00
348 #define DIO_DATA 0x01
349 #define DIO_TIMEOUT_DIO1 0x03
350 #define DIO_TIMEOUT_DIO4 0x00
351 #define DIO_RSSI_DIO0 0x03
352 #define DIO_RSSI_DIO3_4 0x01
353 #define DIO_RX_READY 0x02
354 #define DIO_PLL_LOCK 0x03
355 #define DIO_TX_READY 0x01
356 #define DIO_FIFO_FULL_DIO1 0x01
357 #define DIO_FIFO_FULL_DIO3 0x00
358 #define DIO_SYNC_ADDRESS 0x02
359 #define DIO_FIFO_NOT_EMPTY_DIO1 0x02
360 #define DIO_FIFO_NOT_EMPTY_FIO2 0x00
361 #define DIO_AUTOMODE 0x04
362 #define DIO_FIFO_LEVEL 0x00
363 #define DIO_CRC_OK 0x00
364 #define DIO_PAYLOAD_READY 0x01
365 #define DIO_PACKET_SENT 0x00
366 #define DIO_DCLK 0x00
368 /* RegDioMapping2 CLK_OUT part */
369 #define MASK_DIOMAPPING2_CLK_OUT 0x07
371 #define DIOMAPPING2_CLK_OUT_NO_DIV 0x00
372 #define DIOMAPPING2_CLK_OUT_DIV_2 0x01
373 #define DIOMAPPING2_CLK_OUT_DIV_4 0x02
374 #define DIOMAPPING2_CLK_OUT_DIV_8 0x03
375 #define DIOMAPPING2_CLK_OUT_DIV_16 0x04
376 #define DIOMAPPING2_CLK_OUT_DIV_32 0x05
377 #define DIOMAPPING2_CLK_OUT_RC 0x06
378 #define DIOMAPPING2_CLK_OUT_OFF 0x07 /* default */
381 #define MASK_IRQFLAGS1_MODE_READY 0x80
382 #define MASK_IRQFLAGS1_RX_READY 0x40
383 #define MASK_IRQFLAGS1_TX_READY 0x20
384 #define MASK_IRQFLAGS1_PLL_LOCK 0x10
385 #define MASK_IRQFLAGS1_RSSI 0x08
386 #define MASK_IRQFLAGS1_TIMEOUT 0x04
387 #define MASK_IRQFLAGS1_AUTOMODE 0x02
388 #define MASK_IRQFLAGS1_SYNC_ADDRESS_MATCH 0x01
391 #define MASK_IRQFLAGS2_FIFO_FULL 0x80
392 #define MASK_IRQFLAGS2_FIFO_NOT_EMPTY 0x40
393 #define MASK_IRQFLAGS2_FIFO_LEVEL 0x20
394 #define MASK_IRQFLAGS2_FIFO_OVERRUN 0x10
395 #define MASK_IRQFLAGS2_PACKET_SENT 0x08
396 #define MASK_IRQFLAGS2_PAYLOAD_READY 0x04
397 #define MASK_IRQFLAGS2_CRC_OK 0x02
398 #define MASK_IRQFLAGS2_LOW_BAT 0x01
401 #define MASK_SYNC_CONFIG_SYNC_ON 0x80 /* default */
402 #define MASK_SYNC_CONFIG_FIFO_FILL_CONDITION 0x40
403 #define MASK_SYNC_CONFIG_SYNC_SIZE 0x38
404 #define MASK_SYNC_CONFIG_SYNC_TOLERANCE 0x07
406 /* RegPacketConfig1 */
407 #define MASK_PACKETCONFIG1_PAKET_FORMAT_VARIABLE 0x80
408 #define MASK_PACKETCONFIG1_DCFREE 0x60
409 #define MASK_PACKETCONFIG1_CRC_ON 0x10 /* default */
410 #define MASK_PACKETCONFIG1_CRCAUTOCLEAR_OFF 0x08
411 #define MASK_PACKETCONFIG1_ADDRESSFILTERING 0x06
413 #define PACKETCONFIG1_DCFREE_OFF 0x00 /* default */
414 #define PACKETCONFIG1_DCFREE_MANCHESTER 0x20
415 #define PACKETCONFIG1_DCFREE_WHITENING 0x40
416 #define PACKETCONFIG1_ADDRESSFILTERING_OFF 0x00 /* default */
417 #define PACKETCONFIG1_ADDRESSFILTERING_NODE 0x02
418 #define PACKETCONFIG1_ADDRESSFILTERING_NODEBROADCAST 0x04
422 * #define AUTOMODES_ENTER_OFF 0x00 // Default
423 * #define AUTOMODES_ENTER_FIFONOTEMPTY 0x20
424 * #define AUTOMODES_ENTER_FIFOLEVEL 0x40
425 * #define AUTOMODES_ENTER_CRCOK 0x60
426 * #define AUTOMODES_ENTER_PAYLOADREADY 0x80
427 * #define AUTOMODES_ENTER_SYNCADRSMATCH 0xA0
428 * #define AUTOMODES_ENTER_PACKETSENT 0xC0
429 * #define AUTOMODES_ENTER_FIFOEMPTY 0xE0
431 * #define AUTOMODES_EXIT_OFF 0x00 // Default
432 * #define AUTOMODES_EXIT_FIFOEMPTY 0x04
433 * #define AUTOMODES_EXIT_FIFOLEVEL 0x08
434 * #define AUTOMODES_EXIT_CRCOK 0x0C
435 * #define AUTOMODES_EXIT_PAYLOADREADY 0x10
436 * #define AUTOMODES_EXIT_SYNCADRSMATCH 0x14
437 * #define AUTOMODES_EXIT_PACKETSENT 0x18
438 * #define AUTOMODES_EXIT_RXTIMEOUT 0x1C
440 * #define AUTOMODES_INTERMEDIATE_SLEEP 0x00 // Default
441 * #define AUTOMODES_INTERMEDIATE_STANDBY 0x01
442 * #define AUTOMODES_INTERMEDIATE_RECEIVER 0x02
443 * #define AUTOMODES_INTERMEDIATE_TRANSMITTER 0x03
446 /* RegFifoThresh (0x3c) */
447 #define MASK_FIFO_THRESH_TXSTART 0x80
448 #define MASK_FIFO_THRESH_VALUE 0x7F
452 * // RegPacketConfig2
453 * #define PACKET2_RXRESTARTDELAY_1BIT 0x00 // Default
454 * #define PACKET2_RXRESTARTDELAY_2BITS 0x10
455 * #define PACKET2_RXRESTARTDELAY_4BITS 0x20
456 * #define PACKET2_RXRESTARTDELAY_8BITS 0x30
457 * #define PACKET2_RXRESTARTDELAY_16BITS 0x40
458 * #define PACKET2_RXRESTARTDELAY_32BITS 0x50
459 * #define PACKET2_RXRESTARTDELAY_64BITS 0x60
460 * #define PACKET2_RXRESTARTDELAY_128BITS 0x70
461 * #define PACKET2_RXRESTARTDELAY_256BITS 0x80
462 * #define PACKET2_RXRESTARTDELAY_512BITS 0x90
463 * #define PACKET2_RXRESTARTDELAY_1024BITS 0xA0
464 * #define PACKET2_RXRESTARTDELAY_2048BITS 0xB0
465 * #define PACKET2_RXRESTARTDELAY_NONE 0xC0
466 * #define PACKET2_RXRESTART 0x04
468 * #define PACKET2_AUTORXRESTART_ON 0x02 // Default
469 * #define PACKET2_AUTORXRESTART_OFF 0x00
471 * #define PACKET2_AES_ON 0x01
472 * #define PACKET2_AES_OFF 0x00 // Default
476 * #define TEMP1_MEAS_START 0x08
477 * #define TEMP1_MEAS_RUNNING 0x04
478 * #define TEMP1_ADCLOWPOWER_ON 0x01 // Default
479 * #define TEMP1_ADCLOWPOWER_OFF 0x00
482 // RegTestDagc (0x6F)
483 #define DAGC_NORMAL 0x00 /* Reset value */
484 #define DAGC_IMPROVED_LOWBETA1 0x20
485 #define DAGC_IMPROVED_LOWBETA0 0x30 /* Recommended val */