1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
8 * Purpose: rf function code
15 * vnt_rf_write_embedded - Embedded write RF register via MAC
18 * RF_VT3226: RobertYu:20051111, VT3226C0 and before
19 * RF_VT3226D0: RobertYu:20051228
20 * RF_VT3342A0: RobertYu:20060609
29 #define CB_AL2230_INIT_SEQ 15
30 #define AL2230_PWR_IDX_LEN 64
32 #define CB_AL7230_INIT_SEQ 16
33 #define AL7230_PWR_IDX_LEN 64
35 #define CB_VT3226_INIT_SEQ 11
36 #define VT3226_PWR_IDX_LEN 64
38 #define CB_VT3342_INIT_SEQ 13
39 #define VT3342_PWR_IDX_LEN 64
41 static u8 al2230_init_table[CB_AL2230_INIT_SEQ][3] = {
59 static u8 al2230_channel_table0[CB_MAX_CHANNEL_24G][3] = {
76 static u8 al2230_channel_table1[CB_MAX_CHANNEL_24G][3] = {
93 static u8 al7230_init_table[CB_AL7230_INIT_SEQ][3] = {
112 static u8 al7230_init_table_amode[CB_AL7230_INIT_SEQ][3] = {
131 static u8 al7230_channel_table0[CB_MAX_CHANNEL][3] = {
146 {0x0f, 0xf5, 0x20}, /* channel 15 Tf = 4915MHz */
190 static u8 al7230_channel_table1[CB_MAX_CHANNEL][3] = {
205 {0x1d, 0x55, 0x51}, /* channel = 15, Tf = 4915MHz */
249 static u8 al7230_channel_table2[CB_MAX_CHANNEL][3] = {
264 {0x7f, 0xd7, 0x84}, /* channel = 15 Tf = 4915MHz */
308 static u8 vt3226_init_table[CB_VT3226_INIT_SEQ][3] = {
322 static u8 vt3226d0_init_table[CB_VT3226_INIT_SEQ][3] = {
336 static u8 vt3226_channel_table0[CB_MAX_CHANNEL_24G][3] = {
353 static u8 vt3226_channel_table1[CB_MAX_CHANNEL_24G][3] = {
370 static const u32 vt3226d0_lo_current_table[CB_MAX_CHANNEL_24G] = {
387 static u8 vt3342a0_init_table[CB_VT3342_INIT_SEQ][3] = { /* 11b/g mode */
403 static u8 vt3342_channel_table0[CB_MAX_CHANNEL][3] = {
418 {0x01, 0x15, 0x13}, /* channel = 15 Tf = 4915MHz */
462 static u8 vt3342_channel_table1[CB_MAX_CHANNEL][3] = {
477 {0x00, 0x44, 0x44}, /* channel = 15 Tf = 4915MHz */
522 static const u32 al2230_power_table[AL2230_PWR_IDX_LEN] = {
590 * Description: Write to IF/RF, by embedded programming
592 int vnt_rf_write_embedded(struct vnt_private *priv, u32 data)
596 data |= (VNT_RF_REG_LEN << 3) | IFREGCTL_REGW;
598 reg_data[0] = (u8)data;
599 reg_data[1] = (u8)(data >> 8);
600 reg_data[2] = (u8)(data >> 16);
601 reg_data[3] = (u8)(data >> 24);
603 vnt_control_out(priv, MESSAGE_TYPE_WRITE_IFRF,
604 0, 0, ARRAY_SIZE(reg_data), reg_data);
609 /* Set Tx power by rate and channel number */
610 int vnt_rf_setpower(struct vnt_private *priv, u32 rate, u32 channel)
612 u8 power = priv->cck_pwr;
624 if (channel < sizeof(priv->cck_pwr_tbl))
625 power = priv->cck_pwr_tbl[channel];
635 if (channel > CB_MAX_CHANNEL_24G)
636 power = priv->ofdm_a_pwr_tbl[channel - 15];
638 power = priv->ofdm_pwr_tbl[channel - 1];
642 return vnt_rf_set_txpower(priv, power, rate);
645 static u8 vnt_rf_addpower(struct vnt_private *priv)
647 s32 rssi = -priv->current_rssi;
652 if (priv->rf_type == RF_VT3226D0) {
671 /* Set Tx power by power level and rate */
672 int vnt_rf_set_txpower(struct vnt_private *priv, u8 power, u32 rate)
674 u32 power_setting = 0;
677 power += vnt_rf_addpower(priv);
678 if (power > VNT_RF_MAX_POWER)
679 power = VNT_RF_MAX_POWER;
681 if (priv->power == power)
686 switch (priv->rf_type) {
688 if (power >= AL2230_PWR_IDX_LEN)
691 ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]);
693 if (rate <= RATE_11M)
694 ret &= vnt_rf_write_embedded(priv, 0x0001b400);
696 ret &= vnt_rf_write_embedded(priv, 0x0005a400);
699 if (power >= AL2230_PWR_IDX_LEN)
702 ret &= vnt_rf_write_embedded(priv, al2230_power_table[power]);
704 if (rate <= RATE_11M) {
705 ret &= vnt_rf_write_embedded(priv, 0x040c1400);
706 ret &= vnt_rf_write_embedded(priv, 0x00299b00);
708 ret &= vnt_rf_write_embedded(priv, 0x0005a400);
709 ret &= vnt_rf_write_embedded(priv, 0x00099b00);
714 if (rate <= RATE_11M)
715 ret &= vnt_rf_write_embedded(priv, 0x111bb900);
717 ret &= vnt_rf_write_embedded(priv, 0x221bb900);
719 if (power >= AL7230_PWR_IDX_LEN)
723 * 0x080F1B00 for 3 wire control TxGain(D10)
724 * and 0x31 as TX Gain value
726 power_setting = 0x080c0b00 | (power << 12);
728 ret &= vnt_rf_write_embedded(priv, power_setting);
733 if (power >= VT3226_PWR_IDX_LEN)
735 power_setting = ((0x3f - power) << 20) | (0x17 << 8);
737 ret &= vnt_rf_write_embedded(priv, power_setting);
741 if (power >= VT3226_PWR_IDX_LEN)
744 if (rate <= RATE_11M) {
745 u16 hw_value = priv->hw->conf.chandef.chan->hw_value;
747 power_setting = ((0x3f - power) << 20) | (0xe07 << 8);
749 ret &= vnt_rf_write_embedded(priv, power_setting);
750 ret &= vnt_rf_write_embedded(priv, 0x03c6a200);
752 dev_dbg(&priv->usb->dev,
753 "%s 11b channel [%d]\n", __func__, hw_value);
757 if (hw_value < ARRAY_SIZE(vt3226d0_lo_current_table))
758 ret &= vnt_rf_write_embedded(priv,
759 vt3226d0_lo_current_table[hw_value]);
761 ret &= vnt_rf_write_embedded(priv, 0x015C0800);
763 dev_dbg(&priv->usb->dev,
764 "@@@@ %s> 11G mode\n", __func__);
766 power_setting = ((0x3f - power) << 20) | (0x7 << 8);
768 ret &= vnt_rf_write_embedded(priv, power_setting);
769 ret &= vnt_rf_write_embedded(priv, 0x00C6A200);
770 ret &= vnt_rf_write_embedded(priv, 0x016BC600);
771 ret &= vnt_rf_write_embedded(priv, 0x00900800);
776 if (power >= VT3342_PWR_IDX_LEN)
779 power_setting = ((0x3f - power) << 20) | (0x27 << 8);
781 ret &= vnt_rf_write_embedded(priv, power_setting);
790 /* Convert rssi to dbm */
791 void vnt_rf_rssi_to_dbm(struct vnt_private *priv, u8 rssi, long *dbm)
793 u8 idx = ((rssi & 0xc0) >> 6) & 0x03;
794 long b = rssi & 0x3f;
796 u8 airoharf[4] = {0, 18, 0, 40};
798 switch (priv->rf_type) {
811 *dbm = -1 * (a + b * 2);
814 int vnt_rf_table_download(struct vnt_private *priv)
817 u16 length1 = 0, length2 = 0, length3 = 0;
818 u8 *addr1 = NULL, *addr2 = NULL, *addr3 = NULL;
822 switch (priv->rf_type) {
825 length1 = CB_AL2230_INIT_SEQ * 3;
826 length2 = CB_MAX_CHANNEL_24G * 3;
827 length3 = CB_MAX_CHANNEL_24G * 3;
828 addr1 = &al2230_init_table[0][0];
829 addr2 = &al2230_channel_table0[0][0];
830 addr3 = &al2230_channel_table1[0][0];
833 length1 = CB_AL7230_INIT_SEQ * 3;
834 length2 = CB_MAX_CHANNEL * 3;
835 length3 = CB_MAX_CHANNEL * 3;
836 addr1 = &al7230_init_table[0][0];
837 addr2 = &al7230_channel_table0[0][0];
838 addr3 = &al7230_channel_table1[0][0];
841 length1 = CB_VT3226_INIT_SEQ * 3;
842 length2 = CB_MAX_CHANNEL_24G * 3;
843 length3 = CB_MAX_CHANNEL_24G * 3;
844 addr1 = &vt3226_init_table[0][0];
845 addr2 = &vt3226_channel_table0[0][0];
846 addr3 = &vt3226_channel_table1[0][0];
849 length1 = CB_VT3226_INIT_SEQ * 3;
850 length2 = CB_MAX_CHANNEL_24G * 3;
851 length3 = CB_MAX_CHANNEL_24G * 3;
852 addr1 = &vt3226d0_init_table[0][0];
853 addr2 = &vt3226_channel_table0[0][0];
854 addr3 = &vt3226_channel_table1[0][0];
857 length1 = CB_VT3342_INIT_SEQ * 3;
858 length2 = CB_MAX_CHANNEL * 3;
859 length3 = CB_MAX_CHANNEL * 3;
860 addr1 = &vt3342a0_init_table[0][0];
861 addr2 = &vt3342_channel_table0[0][0];
862 addr3 = &vt3342_channel_table1[0][0];
867 memcpy(array, addr1, length1);
869 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
870 MESSAGE_REQUEST_RF_INIT, length1, array);
874 /* Channel Table 0 */
876 while (length2 > 0) {
882 memcpy(array, addr2, length);
884 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value,
885 MESSAGE_REQUEST_RF_CH0, length, array);
894 /* Channel table 1 */
896 while (length3 > 0) {
902 memcpy(array, addr3, length);
904 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value,
905 MESSAGE_REQUEST_RF_CH1, length, array);
914 if (priv->rf_type == RF_AIROHA7230) {
915 length1 = CB_AL7230_INIT_SEQ * 3;
916 length2 = CB_MAX_CHANNEL * 3;
917 addr1 = &al7230_init_table_amode[0][0];
918 addr2 = &al7230_channel_table2[0][0];
920 memcpy(array, addr1, length1);
923 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, 0,
924 MESSAGE_REQUEST_RF_INIT2, length1, array);
928 /* Channel Table 0 */
930 while (length2 > 0) {
936 memcpy(array, addr2, length);
938 ret = vnt_control_out(priv, MESSAGE_TYPE_WRITE, value,
939 MESSAGE_REQUEST_RF_CH2, length,