1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Implementation of host-to-chip MIBs of WFxxx Split Mac (WSM) API.
5 * Copyright (c) 2017-2019, Silicon Laboratories, Inc.
6 * Copyright (c) 2010, ST-Ericsson
7 * Copyright (C) 2010, ST-Ericsson SA
9 #ifndef WFX_HIF_TX_MIB_H
10 #define WFX_HIF_TX_MIB_H
12 #include <linux/etherdevice.h>
16 #include "hif_api_mib.h"
18 static inline int hif_set_output_power(struct wfx_vif *wvif, int power_level)
20 __le32 val = cpu_to_le32(power_level);
22 return hif_write_mib(wvif->wdev, wvif->id,
23 HIF_MIB_ID_CURRENT_TX_POWER_LEVEL,
27 static inline int hif_set_beacon_wakeup_period(struct wfx_vif *wvif,
28 unsigned int dtim_interval,
29 unsigned int listen_interval)
31 struct hif_mib_beacon_wake_up_period val = {
32 .wakeup_period_min = dtim_interval,
34 .wakeup_period_max = cpu_to_le16(listen_interval),
37 if (dtim_interval > 0xFF || listen_interval > 0xFFFF)
39 return hif_write_mib(wvif->wdev, wvif->id,
40 HIF_MIB_ID_BEACON_WAKEUP_PERIOD,
44 static inline int hif_set_rcpi_rssi_threshold(struct wfx_vif *wvif,
45 struct hif_mib_rcpi_rssi_threshold *arg)
47 return hif_write_mib(wvif->wdev, wvif->id,
48 HIF_MIB_ID_RCPI_RSSI_THRESHOLD, arg, sizeof(*arg));
51 static inline int hif_get_counters_table(struct wfx_dev *wdev,
52 struct hif_mib_extended_count_table *arg)
54 if (wfx_api_older_than(wdev, 1, 3)) {
55 // extended_count_table is wider than count_table
56 memset(arg, 0xFF, sizeof(*arg));
57 return hif_read_mib(wdev, 0, HIF_MIB_ID_COUNTERS_TABLE,
58 arg, sizeof(struct hif_mib_count_table));
60 return hif_read_mib(wdev, 0,
61 HIF_MIB_ID_EXTENDED_COUNTERS_TABLE, arg,
62 sizeof(struct hif_mib_extended_count_table));
66 static inline int hif_set_macaddr(struct wfx_vif *wvif, u8 *mac)
68 struct hif_mib_mac_address msg = { };
71 ether_addr_copy(msg.mac_addr, mac);
72 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_DOT11_MAC_ADDRESS,
76 static inline int hif_set_rx_filter(struct wfx_vif *wvif, bool filter_bssid,
79 struct hif_mib_rx_filter val = { };
84 val.fwd_probe_req = 1;
85 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_RX_FILTER,
89 static inline int hif_set_beacon_filter_table(struct wfx_vif *wvif,
91 struct hif_ie_table_entry *tbl)
94 struct hif_mib_bcn_filter_table *val;
95 int buf_len = struct_size(val, ie_table, tbl_len);
97 val = kzalloc(buf_len, GFP_KERNEL);
100 val->num_of_info_elmts = cpu_to_le32(tbl_len);
101 memcpy(val->ie_table, tbl, tbl_len * sizeof(*tbl));
102 ret = hif_write_mib(wvif->wdev, wvif->id,
103 HIF_MIB_ID_BEACON_FILTER_TABLE, val, buf_len);
108 static inline int hif_beacon_filter_control(struct wfx_vif *wvif,
109 int enable, int beacon_count)
111 struct hif_mib_bcn_filter_enable arg = {
112 .enable = cpu_to_le32(enable),
113 .bcn_count = cpu_to_le32(beacon_count),
115 return hif_write_mib(wvif->wdev, wvif->id,
116 HIF_MIB_ID_BEACON_FILTER_ENABLE,
120 static inline int hif_set_operational_mode(struct wfx_dev *wdev,
121 enum hif_op_power_mode mode)
123 struct hif_mib_gl_operational_power_mode val = {
125 .wup_ind_activation = 1,
128 return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_OPERATIONAL_POWER_MODE,
132 static inline int hif_set_template_frame(struct wfx_vif *wvif,
133 struct hif_mib_template_frame *arg)
135 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_TEMPLATE_FRAME,
139 static inline int hif_set_mfp(struct wfx_vif *wvif, bool capable, bool required)
141 struct hif_mib_protected_mgmt_policy val = { };
143 WARN(required && !capable, "incoherent arguments");
146 val.host_enc_auth_frames = 1;
149 val.unpmf_allowed = 1;
150 return hif_write_mib(wvif->wdev, wvif->id,
151 HIF_MIB_ID_PROTECTED_MGMT_POLICY,
155 static inline int hif_set_block_ack_policy(struct wfx_vif *wvif,
156 u8 tx_tid_policy, u8 rx_tid_policy)
158 struct hif_mib_block_ack_policy val = {
159 .block_ack_tx_tid_policy = tx_tid_policy,
160 .block_ack_rx_tid_policy = rx_tid_policy,
163 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_BLOCK_ACK_POLICY,
167 static inline int hif_set_association_mode(struct wfx_vif *wvif,
168 struct hif_mib_set_association_mode *arg)
170 return hif_write_mib(wvif->wdev, wvif->id,
171 HIF_MIB_ID_SET_ASSOCIATION_MODE, arg, sizeof(*arg));
174 static inline int hif_set_tx_rate_retry_policy(struct wfx_vif *wvif,
175 struct hif_mib_set_tx_rate_retry_policy *arg)
177 size_t size = struct_size(arg, tx_rate_retry_policy,
178 arg->num_tx_rate_policies);
180 return hif_write_mib(wvif->wdev, wvif->id,
181 HIF_MIB_ID_SET_TX_RATE_RETRY_POLICY, arg, size);
184 static inline int hif_set_mac_addr_condition(struct wfx_vif *wvif,
185 struct hif_mib_mac_addr_data_frame_condition *arg)
187 return hif_write_mib(wvif->wdev, wvif->id,
188 HIF_MIB_ID_MAC_ADDR_DATAFRAME_CONDITION,
192 static inline int hif_set_uc_mc_bc_condition(struct wfx_vif *wvif,
193 struct hif_mib_uc_mc_bc_data_frame_condition *arg)
195 return hif_write_mib(wvif->wdev, wvif->id,
196 HIF_MIB_ID_UC_MC_BC_DATAFRAME_CONDITION,
200 static inline int hif_set_config_data_filter(struct wfx_vif *wvif,
201 struct hif_mib_config_data_filter *arg)
203 return hif_write_mib(wvif->wdev, wvif->id,
204 HIF_MIB_ID_CONFIG_DATA_FILTER, arg, sizeof(*arg));
207 static inline int hif_set_data_filtering(struct wfx_vif *wvif,
208 struct hif_mib_set_data_filtering *arg)
210 return hif_write_mib(wvif->wdev, wvif->id,
211 HIF_MIB_ID_SET_DATA_FILTERING, arg, sizeof(*arg));
214 static inline int hif_keep_alive_period(struct wfx_vif *wvif, int period)
216 struct hif_mib_keep_alive_period arg = {
217 .keep_alive_period = cpu_to_le16(period),
220 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_KEEP_ALIVE_PERIOD,
224 static inline int hif_set_arp_ipv4_filter(struct wfx_vif *wvif,
225 struct hif_mib_arp_ip_addr_table *fp)
227 return hif_write_mib(wvif->wdev, wvif->id,
228 HIF_MIB_ID_ARP_IP_ADDRESSES_TABLE,
232 static inline int hif_use_multi_tx_conf(struct wfx_dev *wdev,
235 __le32 arg = enabled ? cpu_to_le32(1) : 0;
237 return hif_write_mib(wdev, -1, HIF_MIB_ID_GL_SET_MULTI_MSG,
241 static inline int hif_set_uapsd_info(struct wfx_vif *wvif,
242 struct hif_mib_set_uapsd_information *arg)
244 return hif_write_mib(wvif->wdev, wvif->id,
245 HIF_MIB_ID_SET_UAPSD_INFORMATION,
249 static inline int hif_erp_use_protection(struct wfx_vif *wvif, bool enable)
251 __le32 arg = enable ? cpu_to_le32(1) : 0;
253 return hif_write_mib(wvif->wdev, wvif->id,
254 HIF_MIB_ID_NON_ERP_PROTECTION, &arg, sizeof(arg));
257 static inline int hif_slot_time(struct wfx_vif *wvif, int val)
259 __le32 arg = cpu_to_le32(val);
261 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SLOT_TIME,
265 static inline int hif_dual_cts_protection(struct wfx_vif *wvif, bool val)
267 struct hif_mib_set_ht_protection arg = {
268 .dual_cts_prot = val,
271 return hif_write_mib(wvif->wdev, wvif->id, HIF_MIB_ID_SET_HT_PROTECTION,
275 static inline int hif_wep_default_key_id(struct wfx_vif *wvif, int val)
277 __le32 arg = cpu_to_le32(val);
279 return hif_write_mib(wvif->wdev, wvif->id,
280 HIF_MIB_ID_DOT11_WEP_DEFAULT_KEY_ID,
284 static inline int hif_rts_threshold(struct wfx_vif *wvif, int val)
286 __le32 arg = cpu_to_le32(val > 0 ? val : 0xFFFF);
288 return hif_write_mib(wvif->wdev, wvif->id,
289 HIF_MIB_ID_DOT11_RTS_THRESHOLD, &arg, sizeof(arg));