2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
4 * Sascha Hauer <s.hauer@pengutronix.de>
5 * Dawei Chien <dawei.chien@mediatek.com>
6 * Louis Yu <louis.yu@mediatek.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/nvmem-consumer.h>
25 #include <linux/of_address.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
30 #include <linux/thermal.h>
31 #include <linux/reset.h>
32 #include <linux/types.h>
34 /* AUXADC Registers */
35 #define AUXADC_CON1_SET_V 0x008
36 #define AUXADC_CON1_CLR_V 0x00c
37 #define AUXADC_CON2_V 0x010
38 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
40 #define APMIXED_SYS_TS_CON1 0x604
42 /* Thermal Controller Registers */
43 #define TEMP_MONCTL0 0x000
44 #define TEMP_MONCTL1 0x004
45 #define TEMP_MONCTL2 0x008
46 #define TEMP_MONIDET0 0x014
47 #define TEMP_MONIDET1 0x018
48 #define TEMP_MSRCTL0 0x038
49 #define TEMP_AHBPOLL 0x040
50 #define TEMP_AHBTO 0x044
51 #define TEMP_ADCPNP0 0x048
52 #define TEMP_ADCPNP1 0x04c
53 #define TEMP_ADCPNP2 0x050
54 #define TEMP_ADCPNP3 0x0b4
56 #define TEMP_ADCMUX 0x054
57 #define TEMP_ADCEN 0x060
58 #define TEMP_PNPMUXADDR 0x064
59 #define TEMP_ADCMUXADDR 0x068
60 #define TEMP_ADCENADDR 0x074
61 #define TEMP_ADCVALIDADDR 0x078
62 #define TEMP_ADCVOLTADDR 0x07c
63 #define TEMP_RDCTRL 0x080
64 #define TEMP_ADCVALIDMASK 0x084
65 #define TEMP_ADCVOLTAGESHIFT 0x088
66 #define TEMP_ADCWRITECTRL 0x08c
67 #define TEMP_MSR0 0x090
68 #define TEMP_MSR1 0x094
69 #define TEMP_MSR2 0x098
70 #define TEMP_MSR3 0x0B8
72 #define TEMP_SPARE0 0x0f0
74 #define TEMP_ADCPNP0_1 0x148
75 #define TEMP_ADCPNP1_1 0x14c
76 #define TEMP_ADCPNP2_1 0x150
77 #define TEMP_MSR0_1 0x190
78 #define TEMP_MSR1_1 0x194
79 #define TEMP_MSR2_1 0x198
80 #define TEMP_ADCPNP3_1 0x1b4
81 #define TEMP_MSR3_1 0x1B8
83 #define PTPCORESEL 0x400
85 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
87 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
88 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
90 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
92 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
93 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
95 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
96 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
98 /* MT8173 thermal sensors */
103 #define MT8173_TSABB 4
105 /* AUXADC channel 11 is used for the temperature sensors */
106 #define MT8173_TEMP_AUXADC_CHANNEL 11
108 /* The total number of temperature sensors in the MT8173 */
109 #define MT8173_NUM_SENSORS 5
111 /* The number of banks in the MT8173 */
112 #define MT8173_NUM_ZONES 4
114 /* The number of sensing points per bank */
115 #define MT8173_NUM_SENSORS_PER_ZONE 4
117 /* The number of controller in the MT8173 */
118 #define MT8173_NUM_CONTROLLER 1
120 /* The calibration coefficient of sensor */
121 #define MT8173_CALIBRATION 165
124 * Layout of the fuses providing the calibration data
125 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
126 * MT8183 has 6 sensors and needs 6 VTS calibration data.
127 * MT8173 has 5 sensors and needs 5 VTS calibration data.
128 * MT2701 has 3 sensors and needs 3 VTS calibration data.
129 * MT2712 has 4 sensors and needs 4 VTS calibration data.
131 #define CALIB_BUF0_VALID BIT(0)
132 #define CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff)
133 #define CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff)
134 #define CALIB_BUF0_VTS_TS2(x) (((x) >> 8) & 0x1ff)
135 #define CALIB_BUF1_VTS_TS3(x) (((x) >> 0) & 0x1ff)
136 #define CALIB_BUF2_VTS_TS4(x) (((x) >> 23) & 0x1ff)
137 #define CALIB_BUF2_VTS_TS5(x) (((x) >> 5) & 0x1ff)
138 #define CALIB_BUF2_VTS_TSABB(x) (((x) >> 14) & 0x1ff)
139 #define CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f)
140 #define CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f)
141 #define CALIB_BUF0_O_SLOPE_SIGN(x) (((x) >> 7) & 0x1)
142 #define CALIB_BUF1_ID(x) (((x) >> 9) & 0x1)
154 /* MT2701 thermal sensors */
157 #define MT2701_TSABB 2
159 /* AUXADC channel 11 is used for the temperature sensors */
160 #define MT2701_TEMP_AUXADC_CHANNEL 11
162 /* The total number of temperature sensors in the MT2701 */
163 #define MT2701_NUM_SENSORS 3
165 /* The number of sensing points per bank */
166 #define MT2701_NUM_SENSORS_PER_ZONE 3
168 /* The number of controller in the MT2701 */
169 #define MT2701_NUM_CONTROLLER 1
171 /* The calibration coefficient of sensor */
172 #define MT2701_CALIBRATION 165
174 /* MT2712 thermal sensors */
180 /* AUXADC channel 11 is used for the temperature sensors */
181 #define MT2712_TEMP_AUXADC_CHANNEL 11
183 /* The total number of temperature sensors in the MT2712 */
184 #define MT2712_NUM_SENSORS 4
186 /* The number of sensing points per bank */
187 #define MT2712_NUM_SENSORS_PER_ZONE 4
189 /* The number of controller in the MT2712 */
190 #define MT2712_NUM_CONTROLLER 1
192 /* The calibration coefficient of sensor */
193 #define MT2712_CALIBRATION 165
195 #define MT7622_TEMP_AUXADC_CHANNEL 11
196 #define MT7622_NUM_SENSORS 1
197 #define MT7622_NUM_ZONES 1
198 #define MT7622_NUM_SENSORS_PER_ZONE 1
200 #define MT7622_NUM_CONTROLLER 1
202 /* The maximum number of banks */
203 #define MAX_NUM_ZONES 8
205 /* The calibration coefficient of sensor */
206 #define MT7622_CALIBRATION 165
208 /* MT8183 thermal sensors */
214 #define MT8183_TSABB 5
216 /* AUXADC channel is used for the temperature sensors */
217 #define MT8183_TEMP_AUXADC_CHANNEL 11
219 /* The total number of temperature sensors in the MT8183 */
220 #define MT8183_NUM_SENSORS 6
222 /* The number of sensing points per bank */
223 #define MT8183_NUM_SENSORS_PER_ZONE 6
225 /* The number of controller in the MT8183 */
226 #define MT8183_NUM_CONTROLLER 2
228 /* The calibration coefficient of sensor */
229 #define MT8183_CALIBRATION 153
233 struct thermal_bank_cfg {
234 unsigned int num_sensors;
238 struct mtk_thermal_bank {
239 struct mtk_thermal *mt;
243 struct mtk_thermal_data {
247 const int *vts_index;
248 const int *sensor_mux_values;
252 const int num_controller;
253 const int *controller_offset;
254 bool need_switch_bank;
255 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
260 void __iomem *thermal_base;
262 struct clk *clk_peri_therm;
263 struct clk *clk_auxadc;
264 /* lock: for getting and putting banks */
267 /* Calibration values */
271 s32 vts[MAX_NUM_VTS];
273 const struct mtk_thermal_data *conf;
274 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
277 /* MT8183 thermal sensor data */
278 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
279 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
282 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
283 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
286 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
287 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
288 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
291 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
292 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
294 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
295 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
298 /* MT8173 thermal sensor data */
299 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
300 { MT8173_TS2, MT8173_TS3 },
301 { MT8173_TS2, MT8173_TS4 },
302 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
306 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
307 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
310 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
311 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
314 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
315 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
317 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
318 VTS1, VTS2, VTS3, VTS4, VTSABB
321 /* MT2701 thermal sensor data */
322 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
323 MT2701_TS1, MT2701_TS2, MT2701_TSABB
326 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
327 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
330 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
331 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
334 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
335 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
337 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
341 /* MT2712 thermal sensor data */
342 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
343 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
346 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
347 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
350 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
351 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
354 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
355 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
357 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
358 VTS1, VTS2, VTS3, VTS4
361 /* MT7622 thermal sensor data */
362 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
363 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
364 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
365 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
366 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
367 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
370 * The MT8173 thermal controller has four banks. Each bank can read up to
371 * four temperature sensors simultaneously. The MT8173 has a total of 5
372 * temperature sensors. We use each bank to measure a certain area of the
373 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
374 * areas, hence is used in different banks.
376 * The thermal core only gets the maximum temperature of all banks, so
377 * the bank concept wouldn't be necessary here. However, the SVS (Smart
378 * Voltage Scaling) unit makes its decisions based on the same bank
379 * data, and this indeed needs the temperatures of the individual banks
380 * for making better decisions.
382 static const struct mtk_thermal_data mt8173_thermal_data = {
383 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
384 .num_banks = MT8173_NUM_ZONES,
385 .num_sensors = MT8173_NUM_SENSORS,
386 .vts_index = mt8173_vts_index,
387 .cali_val = MT8173_CALIBRATION,
388 .num_controller = MT8173_NUM_CONTROLLER,
389 .controller_offset = mt8173_tc_offset,
390 .need_switch_bank = true,
394 .sensors = mt8173_bank_data[0],
397 .sensors = mt8173_bank_data[1],
400 .sensors = mt8173_bank_data[2],
403 .sensors = mt8173_bank_data[3],
407 .adcpnp = mt8173_adcpnp,
408 .sensor_mux_values = mt8173_mux_values,
412 * The MT2701 thermal controller has one bank, which can read up to
413 * three temperature sensors simultaneously. The MT2701 has a total of 3
414 * temperature sensors.
416 * The thermal core only gets the maximum temperature of this one bank,
417 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
418 * Voltage Scaling) unit makes its decisions based on the same bank
421 static const struct mtk_thermal_data mt2701_thermal_data = {
422 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
424 .num_sensors = MT2701_NUM_SENSORS,
425 .vts_index = mt2701_vts_index,
426 .cali_val = MT2701_CALIBRATION,
427 .num_controller = MT2701_NUM_CONTROLLER,
428 .controller_offset = mt2701_tc_offset,
429 .need_switch_bank = true,
433 .sensors = mt2701_bank_data,
437 .adcpnp = mt2701_adcpnp,
438 .sensor_mux_values = mt2701_mux_values,
442 * The MT2712 thermal controller has one bank, which can read up to
443 * four temperature sensors simultaneously. The MT2712 has a total of 4
444 * temperature sensors.
446 * The thermal core only gets the maximum temperature of this one bank,
447 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
448 * Voltage Scaling) unit makes its decisions based on the same bank
451 static const struct mtk_thermal_data mt2712_thermal_data = {
452 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
454 .num_sensors = MT2712_NUM_SENSORS,
455 .vts_index = mt2712_vts_index,
456 .cali_val = MT2712_CALIBRATION,
457 .num_controller = MT2712_NUM_CONTROLLER,
458 .controller_offset = mt2712_tc_offset,
459 .need_switch_bank = true,
463 .sensors = mt2712_bank_data,
467 .adcpnp = mt2712_adcpnp,
468 .sensor_mux_values = mt2712_mux_values,
472 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
475 static const struct mtk_thermal_data mt7622_thermal_data = {
476 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
477 .num_banks = MT7622_NUM_ZONES,
478 .num_sensors = MT7622_NUM_SENSORS,
479 .vts_index = mt7622_vts_index,
480 .cali_val = MT7622_CALIBRATION,
481 .num_controller = MT7622_NUM_CONTROLLER,
482 .controller_offset = mt7622_tc_offset,
483 .need_switch_bank = true,
487 .sensors = mt7622_bank_data,
491 .adcpnp = mt7622_adcpnp,
492 .sensor_mux_values = mt7622_mux_values,
496 * The MT8183 thermal controller has one bank for the current SW framework.
497 * The MT8183 has a total of 6 temperature sensors.
498 * There are two thermal controller to control the six sensor.
499 * The first one bind 2 sensor, and the other bind 4 sensors.
500 * The thermal core only gets the maximum temperature of all sensor, so
501 * the bank concept wouldn't be necessary here. However, the SVS (Smart
502 * Voltage Scaling) unit makes its decisions based on the same bank
503 * data, and this indeed needs the temperatures of the individual banks
504 * for making better decisions.
507 static const struct mtk_thermal_data mt8183_thermal_data = {
508 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
509 .num_banks = MT8183_NUM_SENSORS_PER_ZONE,
510 .num_sensors = MT8183_NUM_SENSORS,
511 .vts_index = mt8183_vts_index,
512 .cali_val = MT8183_CALIBRATION,
513 .num_controller = MT8183_NUM_CONTROLLER,
514 .controller_offset = mt8183_tc_offset,
515 .need_switch_bank = false,
519 .sensors = mt8183_bank_data,
524 .adcpnp = mt8183_adcpnp,
525 .sensor_mux_values = mt8183_mux_values,
529 * raw_to_mcelsius - convert a raw ADC value to mcelsius
530 * @mt: The thermal controller
531 * @raw: raw ADC value
533 * This converts the raw ADC value to mcelsius using the SoC specific
534 * calibration constants
536 static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
542 tmp = 203450520 << 3;
543 tmp /= mt->conf->cali_val + mt->o_slope;
544 tmp /= 10000 + mt->adc_ge;
545 tmp *= raw - mt->vts[sensno] - 3350;
548 return mt->degc_cali * 500 - tmp;
552 * mtk_thermal_get_bank - get bank
555 * The bank registers are banked, we have to select a bank in the
556 * PTPCORESEL register to access it.
558 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
560 struct mtk_thermal *mt = bank->mt;
563 if (mt->conf->need_switch_bank) {
564 mutex_lock(&mt->lock);
566 val = readl(mt->thermal_base + PTPCORESEL);
569 writel(val, mt->thermal_base + PTPCORESEL);
574 * mtk_thermal_put_bank - release bank
577 * release a bank previously taken with mtk_thermal_get_bank,
579 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
581 struct mtk_thermal *mt = bank->mt;
583 if (mt->conf->need_switch_bank)
584 mutex_unlock(&mt->lock);
588 * mtk_thermal_bank_temperature - get the temperature of a bank
591 * The temperature of a bank is considered the maximum temperature of
592 * the sensors associated to the bank.
594 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
596 struct mtk_thermal *mt = bank->mt;
597 const struct mtk_thermal_data *conf = mt->conf;
598 int i, temp = INT_MIN, max = INT_MIN;
601 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
602 raw = readl(mt->thermal_base +
603 conf->msr[conf->bank_data[bank->id].sensors[i]]);
605 temp = raw_to_mcelsius(mt,
606 conf->bank_data[bank->id].sensors[i],
610 * The first read of a sensor often contains very high bogus
611 * temperature value. Filter these out so that the system does
612 * not immediately shut down.
624 static int mtk_read_temp(void *data, int *temperature)
626 struct mtk_thermal *mt = data;
628 int tempmax = INT_MIN;
630 for (i = 0; i < mt->conf->num_banks; i++) {
631 struct mtk_thermal_bank *bank = &mt->banks[i];
633 mtk_thermal_get_bank(bank);
635 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
637 mtk_thermal_put_bank(bank);
640 *temperature = tempmax;
645 static const struct thermal_zone_of_device_ops mtk_thermal_ops = {
646 .get_temp = mtk_read_temp,
649 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
650 u32 apmixed_phys_base, u32 auxadc_phys_base,
653 struct mtk_thermal_bank *bank = &mt->banks[num];
654 const struct mtk_thermal_data *conf = mt->conf;
657 int offset = mt->conf->controller_offset[ctrl_id];
658 void __iomem *controller_base = mt->thermal_base + offset;
663 mtk_thermal_get_bank(bank);
665 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
666 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
669 * filt interval is 1 * 46.540us = 46.54us,
670 * sen interval is 429 * 46.540us = 19.96ms
672 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
673 TEMP_MONCTL2_SENSOR_INTERVAL(429),
674 controller_base + TEMP_MONCTL2);
676 /* poll is set to 10u */
677 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
678 controller_base + TEMP_AHBPOLL);
680 /* temperature sampling control, 1 sample */
681 writel(0x0, controller_base + TEMP_MSRCTL0);
683 /* exceed this polling time, IRQ would be inserted */
684 writel(0xffffffff, controller_base + TEMP_AHBTO);
686 /* number of interrupts per event, 1 is enough */
687 writel(0x0, controller_base + TEMP_MONIDET0);
688 writel(0x0, controller_base + TEMP_MONIDET1);
691 * The MT8173 thermal controller does not have its own ADC. Instead it
692 * uses AHB bus accesses to control the AUXADC. To do this the thermal
693 * controller has to be programmed with the physical addresses of the
694 * AUXADC registers and with the various bit positions in the AUXADC.
695 * Also the thermal controller controls a mux in the APMIXEDSYS register
700 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
701 * automatically by hw
703 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
705 /* AHB address for auxadc mux selection */
706 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
707 controller_base + TEMP_ADCMUXADDR);
709 /* AHB address for pnp sensor mux selection */
710 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
711 controller_base + TEMP_PNPMUXADDR);
713 /* AHB value for auxadc enable */
714 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
716 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
717 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
718 controller_base + TEMP_ADCENADDR);
720 /* AHB address for auxadc valid bit */
721 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
722 controller_base + TEMP_ADCVALIDADDR);
724 /* AHB address for auxadc voltage output */
725 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
726 controller_base + TEMP_ADCVOLTADDR);
728 /* read valid & voltage are at the same register */
729 writel(0x0, controller_base + TEMP_RDCTRL);
731 /* indicate where the valid bit is */
732 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
733 controller_base + TEMP_ADCVALIDMASK);
736 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
738 /* enable auxadc mux write transaction */
739 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
740 controller_base + TEMP_ADCWRITECTRL);
742 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
743 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
745 conf->adcpnp[conf->bank_data[num].sensors[i]]);
747 writel((1 << conf->bank_data[num].num_sensors) - 1,
748 controller_base + TEMP_MONCTL0);
750 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
751 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
752 controller_base + TEMP_ADCWRITECTRL);
754 mtk_thermal_put_bank(bank);
757 static u64 of_get_phys_base(struct device_node *np)
760 const __be32 *regaddr_p;
762 regaddr_p = of_get_address(np, 0, &size64, NULL);
766 return of_translate_address(np, regaddr_p);
769 static int mtk_thermal_get_calibration_data(struct device *dev,
770 struct mtk_thermal *mt)
772 struct nvmem_cell *cell;
777 /* Start with default values */
779 for (i = 0; i < mt->conf->num_sensors; i++)
784 cell = nvmem_cell_get(dev, "calibration-data");
786 if (PTR_ERR(cell) == -EPROBE_DEFER)
787 return PTR_ERR(cell);
791 buf = (u32 *)nvmem_cell_read(cell, &len);
793 nvmem_cell_put(cell);
798 if (len < 3 * sizeof(u32)) {
799 dev_warn(dev, "invalid calibration data\n");
804 if (buf[0] & CALIB_BUF0_VALID) {
805 mt->adc_ge = CALIB_BUF1_ADC_GE(buf[1]);
807 for (i = 0; i < mt->conf->num_sensors; i++) {
808 switch (mt->conf->vts_index[i]) {
810 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1(buf[0]);
813 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2(buf[0]);
816 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3(buf[1]);
819 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4(buf[2]);
822 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5(buf[2]);
825 mt->vts[VTSABB] = CALIB_BUF2_VTS_TSABB(buf[2]);
832 mt->degc_cali = CALIB_BUF0_DEGC_CALI(buf[0]);
833 if (CALIB_BUF1_ID(buf[1]) &
834 CALIB_BUF0_O_SLOPE_SIGN(buf[0]))
835 mt->o_slope = -CALIB_BUF0_O_SLOPE(buf[0]);
837 mt->o_slope = CALIB_BUF0_O_SLOPE(buf[0]);
839 dev_info(dev, "Device not calibrated, using default calibration values\n");
848 static const struct of_device_id mtk_thermal_of_match[] = {
850 .compatible = "mediatek,mt8173-thermal",
851 .data = (void *)&mt8173_thermal_data,
854 .compatible = "mediatek,mt2701-thermal",
855 .data = (void *)&mt2701_thermal_data,
858 .compatible = "mediatek,mt2712-thermal",
859 .data = (void *)&mt2712_thermal_data,
862 .compatible = "mediatek,mt7622-thermal",
863 .data = (void *)&mt7622_thermal_data,
866 .compatible = "mediatek,mt8183-thermal",
867 .data = (void *)&mt8183_thermal_data,
871 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
873 static int mtk_thermal_probe(struct platform_device *pdev)
876 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
877 struct mtk_thermal *mt;
878 struct resource *res;
879 u64 auxadc_phys_base, apmixed_phys_base;
880 struct thermal_zone_device *tzdev;
882 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
886 mt->conf = of_device_get_match_data(&pdev->dev);
888 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
889 if (IS_ERR(mt->clk_peri_therm))
890 return PTR_ERR(mt->clk_peri_therm);
892 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
893 if (IS_ERR(mt->clk_auxadc))
894 return PTR_ERR(mt->clk_auxadc);
896 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
897 mt->thermal_base = devm_ioremap_resource(&pdev->dev, res);
898 if (IS_ERR(mt->thermal_base))
899 return PTR_ERR(mt->thermal_base);
901 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
905 mutex_init(&mt->lock);
907 mt->dev = &pdev->dev;
909 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
911 dev_err(&pdev->dev, "missing auxadc node\n");
915 auxadc_phys_base = of_get_phys_base(auxadc);
919 if (auxadc_phys_base == OF_BAD_ADDR) {
920 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
924 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
926 dev_err(&pdev->dev, "missing apmixedsys node\n");
930 apmixed_phys_base = of_get_phys_base(apmixedsys);
932 of_node_put(apmixedsys);
934 if (apmixed_phys_base == OF_BAD_ADDR) {
935 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
939 ret = device_reset(&pdev->dev);
943 ret = clk_prepare_enable(mt->clk_auxadc);
945 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
949 ret = clk_prepare_enable(mt->clk_peri_therm);
951 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
952 goto err_disable_clk_auxadc;
955 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
956 for (i = 0; i < mt->conf->num_banks; i++)
957 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
958 auxadc_phys_base, ctrl_id);
960 platform_set_drvdata(pdev, mt);
962 tzdev = devm_thermal_zone_of_sensor_register(&pdev->dev, 0, mt,
965 ret = PTR_ERR(tzdev);
966 goto err_disable_clk_peri_therm;
971 err_disable_clk_peri_therm:
972 clk_disable_unprepare(mt->clk_peri_therm);
973 err_disable_clk_auxadc:
974 clk_disable_unprepare(mt->clk_auxadc);
979 static int mtk_thermal_remove(struct platform_device *pdev)
981 struct mtk_thermal *mt = platform_get_drvdata(pdev);
983 clk_disable_unprepare(mt->clk_peri_therm);
984 clk_disable_unprepare(mt->clk_auxadc);
989 static struct platform_driver mtk_thermal_driver = {
990 .probe = mtk_thermal_probe,
991 .remove = mtk_thermal_remove,
993 .name = "mtk-thermal",
994 .of_match_table = mtk_thermal_of_match,
998 module_platform_driver(mtk_thermal_driver);
1000 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1001 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1002 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1003 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1004 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1005 MODULE_DESCRIPTION("Mediatek thermal driver");
1006 MODULE_LICENSE("GPL v2");