2 * Copyright (c) 2011-2015, 2017, The Linux Foundation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/bitops.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/iio/consumer.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/thermal.h>
26 #include "thermal_core.h"
28 #define QPNP_TM_REG_TYPE 0x04
29 #define QPNP_TM_REG_SUBTYPE 0x05
30 #define QPNP_TM_REG_STATUS 0x08
31 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40
32 #define QPNP_TM_REG_ALARM_CTRL 0x46
34 #define QPNP_TM_TYPE 0x09
35 #define QPNP_TM_SUBTYPE_GEN1 0x08
36 #define QPNP_TM_SUBTYPE_GEN2 0x09
38 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0)
39 #define STATUS_GEN2_STATE_MASK GENMASK(6, 4)
40 #define STATUS_GEN2_STATE_SHIFT 4
42 #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6)
43 #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0)
45 #define SHUTDOWN_CTRL1_RATE_25HZ BIT(3)
47 #define ALARM_CTRL_FORCE_ENABLE BIT(7)
50 * Trip point values based on threshold control
51 * 0 = {105 C, 125 C, 145 C}
52 * 1 = {110 C, 130 C, 150 C}
53 * 2 = {115 C, 135 C, 155 C}
54 * 3 = {120 C, 140 C, 160 C}
56 #define TEMP_STAGE_STEP 20000 /* Stage step: 20.000 C */
57 #define TEMP_STAGE_HYSTERESIS 2000
59 #define TEMP_THRESH_MIN 105000 /* Threshold Min: 105 C */
60 #define TEMP_THRESH_STEP 5000 /* Threshold step: 5 C */
65 /* Stage 2 Threshold Min: 125 C */
66 #define STAGE2_THRESHOLD_MIN 125000
67 /* Stage 2 Threshold Max: 140 C */
68 #define STAGE2_THRESHOLD_MAX 140000
70 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
71 #define DEFAULT_TEMP 37000
76 struct thermal_zone_device *tz_dev;
81 unsigned int prev_stage;
83 /* protects .thresh, .stage and chip registers */
87 struct iio_channel *adc;
90 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
91 static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
93 static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
98 ret = regmap_read(chip->map, chip->base + addr, &val);
106 static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
108 return regmap_write(chip->map, chip->base + addr, data);
112 * qpnp_tm_get_temp_stage() - return over-temperature stage
113 * @chip: Pointer to the qpnp_tm chip
115 * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
117 static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
122 ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®);
126 if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
127 ret = reg & STATUS_GEN1_STAGE_MASK;
129 ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
135 * This function updates the internal temp value based on the
136 * current thermal stage and threshold as well as the previous stage
138 static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
140 unsigned int stage, stage_new, stage_old;
143 WARN_ON(!mutex_is_locked(&chip->lock));
145 ret = qpnp_tm_get_temp_stage(chip);
150 if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
152 stage_old = chip->stage;
154 stage_new = alarm_state_map[stage];
155 stage_old = alarm_state_map[chip->stage];
158 if (stage_new > stage_old) {
159 /* increasing stage, use lower bound */
160 chip->temp = (stage_new - 1) * TEMP_STAGE_STEP +
161 chip->thresh * TEMP_THRESH_STEP +
162 TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
163 } else if (stage_new < stage_old) {
164 /* decreasing stage, use upper bound */
165 chip->temp = stage_new * TEMP_STAGE_STEP +
166 chip->thresh * TEMP_THRESH_STEP -
167 TEMP_STAGE_HYSTERESIS + TEMP_THRESH_MIN;
175 static int qpnp_tm_get_temp(void *data, int *temp)
177 struct qpnp_tm_chip *chip = data;
178 int ret, mili_celsius;
183 if (!chip->initialized) {
184 *temp = DEFAULT_TEMP;
189 mutex_lock(&chip->lock);
190 ret = qpnp_tm_update_temp_no_adc(chip);
191 mutex_unlock(&chip->lock);
195 ret = iio_read_channel_processed(chip->adc, &mili_celsius);
199 chip->temp = mili_celsius;
202 *temp = chip->temp < 0 ? 0 : chip->temp;
207 static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
211 bool disable_s2_shutdown = false;
213 WARN_ON(!mutex_is_locked(&chip->lock));
216 * Default: S2 and S3 shutdown enabled, thresholds at
217 * 105C/125C/145C, monitoring at 25Hz
219 reg = SHUTDOWN_CTRL1_RATE_25HZ;
221 if (temp == THERMAL_TEMP_INVALID ||
222 temp < STAGE2_THRESHOLD_MIN) {
223 chip->thresh = THRESH_MIN;
227 if (temp <= STAGE2_THRESHOLD_MAX) {
228 chip->thresh = THRESH_MAX -
229 ((STAGE2_THRESHOLD_MAX - temp) /
231 disable_s2_shutdown = true;
233 chip->thresh = THRESH_MAX;
236 disable_s2_shutdown = true;
239 "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n");
244 if (disable_s2_shutdown)
245 reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
247 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
250 static int qpnp_tm_set_trip_temp(void *data, int trip, int temp)
252 struct qpnp_tm_chip *chip = data;
253 const struct thermal_trip *trip_points;
256 trip_points = of_thermal_get_trip_points(chip->tz_dev);
260 if (trip_points[trip].type != THERMAL_TRIP_CRITICAL)
263 mutex_lock(&chip->lock);
264 ret = qpnp_tm_update_critical_trip_temp(chip, temp);
265 mutex_unlock(&chip->lock);
270 static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = {
271 .get_temp = qpnp_tm_get_temp,
272 .set_trip_temp = qpnp_tm_set_trip_temp,
275 static irqreturn_t qpnp_tm_isr(int irq, void *data)
277 struct qpnp_tm_chip *chip = data;
279 thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
284 static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip)
287 const struct thermal_trip *trips;
290 ntrips = of_thermal_get_ntrips(chip->tz_dev);
292 return THERMAL_TEMP_INVALID;
294 trips = of_thermal_get_trip_points(chip->tz_dev);
296 return THERMAL_TEMP_INVALID;
298 for (i = 0; i < ntrips; i++) {
299 if (of_thermal_is_trip_valid(chip->tz_dev, i) &&
300 trips[i].type == THERMAL_TRIP_CRITICAL)
301 return trips[i].temperature;
304 return THERMAL_TEMP_INVALID;
308 * This function initializes the internal temp value based on only the
309 * current thermal stage and threshold. Setup threshold control and
310 * disable shutdown override.
312 static int qpnp_tm_init(struct qpnp_tm_chip *chip)
319 mutex_lock(&chip->lock);
321 ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, ®);
325 chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
326 chip->temp = DEFAULT_TEMP;
328 ret = qpnp_tm_get_temp_stage(chip);
333 stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
334 ? chip->stage : alarm_state_map[chip->stage];
337 chip->temp = chip->thresh * TEMP_THRESH_STEP +
338 (stage - 1) * TEMP_STAGE_STEP +
341 crit_temp = qpnp_tm_get_critical_trip_temp(chip);
342 ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
346 /* Enable the thermal alarm PMIC module in always-on mode. */
347 reg = ALARM_CTRL_FORCE_ENABLE;
348 ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
350 chip->initialized = true;
353 mutex_unlock(&chip->lock);
357 static int qpnp_tm_probe(struct platform_device *pdev)
359 struct qpnp_tm_chip *chip;
360 struct device_node *node;
365 node = pdev->dev.of_node;
367 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
371 dev_set_drvdata(&pdev->dev, chip);
372 chip->dev = &pdev->dev;
374 mutex_init(&chip->lock);
376 chip->map = dev_get_regmap(pdev->dev.parent, NULL);
380 ret = of_property_read_u32(node, "reg", &res);
384 irq = platform_get_irq(pdev, 0);
388 /* ADC based measurements are optional */
389 chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
390 if (IS_ERR(chip->adc)) {
391 ret = PTR_ERR(chip->adc);
393 if (ret == -EPROBE_DEFER)
399 ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
401 dev_err(&pdev->dev, "could not read type\n");
405 ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
407 dev_err(&pdev->dev, "could not read subtype\n");
411 if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
412 && subtype != QPNP_TM_SUBTYPE_GEN2)) {
413 dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
418 chip->subtype = subtype;
421 * Register the sensor before initializing the hardware to be able to
422 * read the trip points. get_temp() returns the default temperature
423 * before the hardware initialization is completed.
425 chip->tz_dev = devm_thermal_zone_of_sensor_register(
426 &pdev->dev, 0, chip, &qpnp_tm_sensor_ops);
427 if (IS_ERR(chip->tz_dev)) {
428 dev_err(&pdev->dev, "failed to register sensor\n");
429 return PTR_ERR(chip->tz_dev);
432 ret = qpnp_tm_init(chip);
434 dev_err(&pdev->dev, "init failed\n");
438 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
439 IRQF_ONESHOT, node->name, chip);
443 thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
448 static const struct of_device_id qpnp_tm_match_table[] = {
449 { .compatible = "qcom,spmi-temp-alarm" },
452 MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
454 static struct platform_driver qpnp_tm_driver = {
456 .name = "spmi-temp-alarm",
457 .of_match_table = qpnp_tm_match_table,
459 .probe = qpnp_tm_probe,
461 module_platform_driver(qpnp_tm_driver);
463 MODULE_ALIAS("platform:spmi-temp-alarm");
464 MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
465 MODULE_LICENSE("GPL v2");