2 * Thunderbolt Cactus Ridge driver - eeprom access
4 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
7 #include <linux/crc32.h>
8 #include <linux/property.h>
9 #include <linux/slab.h>
13 * tb_eeprom_ctl_write() - write control word
15 static int tb_eeprom_ctl_write(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
17 return tb_sw_write(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
21 * tb_eeprom_ctl_write() - read control word
23 static int tb_eeprom_ctl_read(struct tb_switch *sw, struct tb_eeprom_ctl *ctl)
25 return tb_sw_read(sw, ctl, TB_CFG_SWITCH, sw->cap_plug_events + 4, 1);
28 enum tb_eeprom_transfer {
34 * tb_eeprom_active - enable rom access
36 * WARNING: Always disable access after usage. Otherwise the controller will
39 static int tb_eeprom_active(struct tb_switch *sw, bool enable)
41 struct tb_eeprom_ctl ctl;
42 int res = tb_eeprom_ctl_read(sw, &ctl);
47 res = tb_eeprom_ctl_write(sw, &ctl);
51 return tb_eeprom_ctl_write(sw, &ctl);
54 res = tb_eeprom_ctl_write(sw, &ctl);
58 return tb_eeprom_ctl_write(sw, &ctl);
63 * tb_eeprom_transfer - transfer one bit
65 * If TB_EEPROM_IN is passed, then the bit can be retrieved from ctl->data_in.
66 * If TB_EEPROM_OUT is passed, then ctl->data_out will be written.
68 static int tb_eeprom_transfer(struct tb_switch *sw, struct tb_eeprom_ctl *ctl,
69 enum tb_eeprom_transfer direction)
72 if (direction == TB_EEPROM_OUT) {
73 res = tb_eeprom_ctl_write(sw, ctl);
78 res = tb_eeprom_ctl_write(sw, ctl);
81 if (direction == TB_EEPROM_IN) {
82 res = tb_eeprom_ctl_read(sw, ctl);
87 return tb_eeprom_ctl_write(sw, ctl);
91 * tb_eeprom_out - write one byte to the bus
93 static int tb_eeprom_out(struct tb_switch *sw, u8 val)
95 struct tb_eeprom_ctl ctl;
97 int res = tb_eeprom_ctl_read(sw, &ctl);
100 for (i = 0; i < 8; i++) {
101 ctl.data_out = val & 0x80;
102 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_OUT);
111 * tb_eeprom_in - read one byte from the bus
113 static int tb_eeprom_in(struct tb_switch *sw, u8 *val)
115 struct tb_eeprom_ctl ctl;
117 int res = tb_eeprom_ctl_read(sw, &ctl);
121 for (i = 0; i < 8; i++) {
123 res = tb_eeprom_transfer(sw, &ctl, TB_EEPROM_IN);
132 * tb_eeprom_read_n - read count bytes from offset into val
134 static int tb_eeprom_read_n(struct tb_switch *sw, u16 offset, u8 *val,
138 res = tb_eeprom_active(sw, true);
141 res = tb_eeprom_out(sw, 3);
144 res = tb_eeprom_out(sw, offset >> 8);
147 res = tb_eeprom_out(sw, offset);
150 for (i = 0; i < count; i++) {
151 res = tb_eeprom_in(sw, val + i);
155 return tb_eeprom_active(sw, false);
158 static u8 tb_crc8(u8 *data, int len)
162 for (i = 0; i < len; i++) {
164 for (j = 0; j < 8; j++)
165 val = (val << 1) ^ ((val & 0x80) ? 7 : 0);
170 static u32 tb_crc32(void *data, size_t len)
172 return ~__crc32c_le(~0, data, len);
175 #define TB_DROM_DATA_START 13
176 struct tb_drom_header {
178 u8 uid_crc8; /* checksum for uid */
182 u32 data_crc32; /* checksum for data_len bytes starting at byte 13 */
184 u8 device_rom_revision; /* should be <= 1 */
194 enum tb_drom_entry_type {
195 /* force unsigned to prevent "one-bit signed bitfield" warning */
196 TB_DROM_ENTRY_GENERIC = 0U,
200 struct tb_drom_entry_header {
203 bool port_disabled:1; /* only valid if type is TB_DROM_ENTRY_PORT */
204 enum tb_drom_entry_type type:1;
207 struct tb_drom_entry_generic {
208 struct tb_drom_entry_header header;
212 struct tb_drom_entry_port {
214 struct tb_drom_entry_header header;
216 u8 dual_link_port_rid:4;
219 bool has_dual_link_port:1;
222 u8 dual_link_port_nr:6;
225 /* BYTES 4 - 5 TODO decode */
230 /* BYTES 6-7, TODO: verify (find hardware that has these set) */
233 bool has_peer_port:1;
240 * tb_eeprom_get_drom_offset - get drom offset within eeprom
242 static int tb_eeprom_get_drom_offset(struct tb_switch *sw, u16 *offset)
244 struct tb_cap_plug_events cap;
246 if (!sw->cap_plug_events) {
247 tb_sw_warn(sw, "no TB_CAP_PLUG_EVENTS, cannot read eeprom\n");
250 res = tb_sw_read(sw, &cap, TB_CFG_SWITCH, sw->cap_plug_events,
255 if (!cap.eeprom_ctl.present || cap.eeprom_ctl.not_present) {
256 tb_sw_warn(sw, "no NVM\n");
260 if (cap.drom_offset > 0xffff) {
261 tb_sw_warn(sw, "drom offset is larger than 0xffff: %#x\n",
265 *offset = cap.drom_offset;
270 * tb_drom_read_uid_only - read uid directly from drom
272 * Does not use the cached copy in sw->drom. Used during resume to check switch
275 int tb_drom_read_uid_only(struct tb_switch *sw, u64 *uid)
280 int res = tb_eeprom_get_drom_offset(sw, &drom_offset);
284 if (drom_offset == 0)
288 res = tb_eeprom_read_n(sw, drom_offset, data, 9);
292 crc = tb_crc8(data + 1, 8);
293 if (crc != data[0]) {
294 tb_sw_warn(sw, "uid crc8 mismatch (expected: %#x, got: %#x)\n",
299 *uid = *(u64 *)(data+1);
303 static int tb_drom_parse_entry_generic(struct tb_switch *sw,
304 struct tb_drom_entry_header *header)
306 const struct tb_drom_entry_generic *entry =
307 (const struct tb_drom_entry_generic *)header;
309 switch (header->index) {
311 /* Length includes 2 bytes header so remove it before copy */
312 sw->vendor_name = kstrndup(entry->data,
313 header->len - sizeof(*header), GFP_KERNEL);
314 if (!sw->vendor_name)
319 sw->device_name = kstrndup(entry->data,
320 header->len - sizeof(*header), GFP_KERNEL);
321 if (!sw->device_name)
329 static int tb_drom_parse_entry_port(struct tb_switch *sw,
330 struct tb_drom_entry_header *header)
332 struct tb_port *port;
334 enum tb_port_type type;
336 port = &sw->ports[header->index];
337 port->disabled = header->port_disabled;
341 res = tb_port_read(port, &type, TB_CFG_PORT, 2, 1);
346 if (type == TB_TYPE_PORT) {
347 struct tb_drom_entry_port *entry = (void *) header;
348 if (header->len != sizeof(*entry)) {
350 "port entry has size %#x (expected %#zx)\n",
351 header->len, sizeof(struct tb_drom_entry_port));
354 port->link_nr = entry->link_nr;
355 if (entry->has_dual_link_port)
356 port->dual_link_port =
357 &port->sw->ports[entry->dual_link_port_nr];
363 * tb_drom_parse_entries - parse the linked list of drom entries
365 * Drom must have been copied to sw->drom.
367 static int tb_drom_parse_entries(struct tb_switch *sw)
369 struct tb_drom_header *header = (void *) sw->drom;
370 u16 pos = sizeof(*header);
371 u16 drom_size = header->data_len + TB_DROM_DATA_START;
374 while (pos < drom_size) {
375 struct tb_drom_entry_header *entry = (void *) (sw->drom + pos);
376 if (pos + 1 == drom_size || pos + entry->len > drom_size
378 tb_sw_warn(sw, "drom buffer overrun, aborting\n");
382 switch (entry->type) {
383 case TB_DROM_ENTRY_GENERIC:
384 res = tb_drom_parse_entry_generic(sw, entry);
386 case TB_DROM_ENTRY_PORT:
387 res = tb_drom_parse_entry_port(sw, entry);
399 * tb_drom_copy_efi - copy drom supplied by EFI to sw->drom if present
401 static int tb_drom_copy_efi(struct tb_switch *sw, u16 *size)
403 struct device *dev = &sw->tb->nhi->pdev->dev;
406 len = device_property_read_u8_array(dev, "ThunderboltDROM", NULL, 0);
407 if (len < 0 || len < sizeof(struct tb_drom_header))
410 sw->drom = kmalloc(len, GFP_KERNEL);
414 res = device_property_read_u8_array(dev, "ThunderboltDROM", sw->drom,
419 *size = ((struct tb_drom_header *)sw->drom)->data_len +
432 static int tb_drom_copy_nvm(struct tb_switch *sw, u16 *size)
440 ret = tb_sw_read(sw, &drom_offset, TB_CFG_SWITCH,
441 sw->cap_plug_events + 12, 1);
448 ret = dma_port_flash_read(sw->dma_port, drom_offset + 14, size,
453 /* Size includes CRC8 + UID + CRC32 */
455 sw->drom = kzalloc(*size, GFP_KERNEL);
459 ret = dma_port_flash_read(sw->dma_port, drom_offset, sw->drom, *size);
464 * Read UID from the minimal DROM because the one in NVM is just
467 tb_drom_read_uid_only(sw, &sw->uid);
477 * tb_drom_read - copy drom to sw->drom and parse it
479 int tb_drom_read(struct tb_switch *sw)
484 struct tb_drom_header *header;
489 if (tb_route(sw) == 0) {
491 * Apple's NHI EFI driver supplies a DROM for the root switch
492 * in a device property. Use it if available.
494 if (tb_drom_copy_efi(sw, &size) == 0)
497 /* Non-Apple hardware has the DROM as part of NVM */
498 if (tb_drom_copy_nvm(sw, &size) == 0)
502 * The root switch contains only a dummy drom (header only,
503 * no entries). Hardcode the configuration here.
505 tb_drom_read_uid_only(sw, &sw->uid);
507 sw->ports[1].link_nr = 0;
508 sw->ports[2].link_nr = 1;
509 sw->ports[1].dual_link_port = &sw->ports[2];
510 sw->ports[2].dual_link_port = &sw->ports[1];
512 sw->ports[3].link_nr = 0;
513 sw->ports[4].link_nr = 1;
514 sw->ports[3].dual_link_port = &sw->ports[4];
515 sw->ports[4].dual_link_port = &sw->ports[3];
517 /* Port 5 is inaccessible on this gen 1 controller */
518 if (sw->config.device_id == PCI_DEVICE_ID_INTEL_LIGHT_RIDGE)
519 sw->ports[5].disabled = true;
524 res = tb_eeprom_get_drom_offset(sw, &drom_offset);
528 res = tb_eeprom_read_n(sw, drom_offset + 14, (u8 *) &size, 2);
532 size += TB_DROM_DATA_START;
533 tb_sw_info(sw, "reading drom (length: %#x)\n", size);
534 if (size < sizeof(*header)) {
535 tb_sw_warn(sw, "drom too small, aborting\n");
539 sw->drom = kzalloc(size, GFP_KERNEL);
542 res = tb_eeprom_read_n(sw, drom_offset, sw->drom, size);
547 header = (void *) sw->drom;
549 if (header->data_len + TB_DROM_DATA_START != size) {
550 tb_sw_warn(sw, "drom size mismatch, aborting\n");
554 crc = tb_crc8((u8 *) &header->uid, 8);
555 if (crc != header->uid_crc8) {
557 "drom uid crc8 mismatch (expected: %#x, got: %#x), aborting\n",
558 header->uid_crc8, crc);
562 sw->uid = header->uid;
563 sw->vendor = header->vendor_id;
564 sw->device = header->model_id;
566 crc = tb_crc32(sw->drom + TB_DROM_DATA_START, header->data_len);
567 if (crc != header->data_crc32) {
569 "drom data crc32 mismatch (expected: %#x, got: %#x), continuing\n",
570 header->data_crc32, crc);
573 if (header->device_rom_revision > 2)
574 tb_sw_warn(sw, "drom device_rom_revision %#x unknown\n",
575 header->device_rom_revision);
577 return tb_drom_parse_entries(sw);