drivers/thunderbolt/tb_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Thunderbolt driver - Port/Switch config area registers
   4  *
   5  * Every thunderbolt device consists (logically) of a switch with multiple
   6  * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH,
   7  * COUNTERS) which are used to configure the device.
   8  *
   9  * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com>
  10  * Copyright (C) 2018, Intel Corporation
  11  */
  12
  13 #ifndef _TB_REGS
  14 #define _TB_REGS
  15
  16 #include <linux/types.h>
  17
  18
  19 #define TB_ROUTE_SHIFT 8  /* number of bits in a port entry of a route */
  20
  21
  22 /*
  23  * TODO: should be 63? But we do not know how to receive frames larger than 256
  24  * bytes at the frame level. (header + checksum = 16, 60*4 = 240)
  25  */
  26 #define TB_MAX_CONFIG_RW_LENGTH 60
  27
  28 enum tb_switch_cap {
  29         TB_SWITCH_CAP_VSE               = 0x05,
  30 };
  31
  32 enum tb_switch_vse_cap {
  33         TB_VSE_CAP_PLUG_EVENTS          = 0x01, /* also EEPROM */
  34         TB_VSE_CAP_TIME2                = 0x03,
  35         TB_VSE_CAP_IECS                 = 0x04,
  36         TB_VSE_CAP_LINK_CONTROLLER      = 0x06, /* also IECS */
  37 };
  38
  39 enum tb_port_cap {
  40         TB_PORT_CAP_PHY                 = 0x01,
  41         TB_PORT_CAP_TIME1               = 0x03,
  42         TB_PORT_CAP_ADAP                = 0x04,
  43         TB_PORT_CAP_VSE                 = 0x05,
  44         TB_PORT_CAP_USB4                = 0x06,
  45 };
  46
  47 enum tb_port_state {
  48         TB_PORT_DISABLED        = 0, /* tb_cap_phy.disable == 1 */
  49         TB_PORT_CONNECTING      = 1, /* retry */
  50         TB_PORT_UP              = 2,
  51         TB_PORT_UNPLUGGED       = 7,
  52 };
  53
  54 /* capability headers */
  55
  56 struct tb_cap_basic {
  57         u8 next;
  58         /* enum tb_cap cap:8; prevent "narrower than values of its type" */
  59         u8 cap; /* if cap == 0x05 then we have a extended capability */
  60 } __packed;
  61
  62 /**
  63  * struct tb_cap_extended_short - Switch extended short capability
  64  * @next: Pointer to the next capability. If @next and @length are zero
  65  *        then we have a long cap.
  66  * @cap: Base capability ID (see &enum tb_switch_cap)
  67  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  68  * @length: Length of this capability
  69  */
  70 struct tb_cap_extended_short {
  71         u8 next;
  72         u8 cap;
  73         u8 vsec_id;
  74         u8 length;
  75 } __packed;
  76
  77 /**
  78  * struct tb_cap_extended_long - Switch extended long capability
  79  * @zero1: This field should be zero
  80  * @cap: Base capability ID (see &enum tb_switch_cap)
  81  * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap)
  82  * @zero2: This field should be zero
  83  * @next: Pointer to the next capability
  84  * @length: Length of this capability
  85  */
  86 struct tb_cap_extended_long {
  87         u8 zero1;
  88         u8 cap;
  89         u8 vsec_id;
  90         u8 zero2;
  91         u16 next;
  92         u16 length;
  93 } __packed;
  94
  95 /* capabilities */
  96
  97 struct tb_cap_link_controller {
  98         struct tb_cap_extended_long cap_header;
  99         u32 count:4; /* number of link controllers */
 100         u32 unknown1:4;
 101         u32 base_offset:8; /*
 102                             * offset (into this capability) of the configuration
 103                             * area of the first link controller
 104                             */
 105         u32 length:12; /* link controller configuration area length */
 106         u32 unknown2:4; /* TODO check that length is correct */
 107 } __packed;
 108
 109 struct tb_cap_phy {
 110         struct tb_cap_basic cap_header;
 111         u32 unknown1:16;
 112         u32 unknown2:14;
 113         bool disable:1;
 114         u32 unknown3:11;
 115         enum tb_port_state state:4;
 116         u32 unknown4:2;
 117 } __packed;
 118
 119 struct tb_eeprom_ctl {
 120         bool clock:1; /* send pulse to transfer one bit */
 121         bool access_low:1; /* set to 0 before access */
 122         bool data_out:1; /* to eeprom */
 123         bool data_in:1; /* from eeprom */
 124         bool access_high:1; /* set to 1 before access */
 125         bool not_present:1; /* should be 0 */
 126         bool unknown1:1;
 127         bool present:1; /* should be 1 */
 128         u32 unknown2:24;
 129 } __packed;
 130
 131 struct tb_cap_plug_events {
 132         struct tb_cap_extended_short cap_header;
 133         u32 __unknown1:2;
 134         u32 plug_events:5;
 135         u32 __unknown2:25;
 136         u32 __unknown3;
 137         u32 __unknown4;
 138         struct tb_eeprom_ctl eeprom_ctl;
 139         u32 __unknown5[7];
 140         u32 drom_offset; /* 32 bit register, but eeprom addresses are 16 bit */
 141 } __packed;
 142
 143 /* device headers */
 144
 145 /* Present on port 0 in TB_CFG_SWITCH at address zero. */
 146 struct tb_regs_switch_header {
 147         /* DWORD 0 */
 148         u16 vendor_id;
 149         u16 device_id;
 150         /* DWORD 1 */
 151         u32 first_cap_offset:8;
 152         u32 upstream_port_number:6;
 153         u32 max_port_number:6;
 154         u32 depth:3;
 155         u32 __unknown1:1;
 156         u32 revision:8;
 157         /* DWORD 2 */
 158         u32 route_lo;
 159         /* DWORD 3 */
 160         u32 route_hi:31;
 161         bool enabled:1;
 162         /* DWORD 4 */
 163         u32 plug_events_delay:8; /*
 164                                   * RW, pause between plug events in
 165                                   * milliseconds. Writing 0x00 is interpreted
 166                                   * as 255ms.
 167                                   */
 168         u32 cmuv:8;
 169         u32 __unknown4:8;
 170         u32 thunderbolt_version:8;
 171 } __packed;
 172
 173 /* USB4 version 1.0 */
 174 #define USB4_VERSION_1_0                        0x20
 175
 176 #define ROUTER_CS_1                             0x01
 177 #define ROUTER_CS_4                             0x04
 178 #define ROUTER_CS_5                             0x05
 179 #define ROUTER_CS_5_SLP                         BIT(0)
 180 #define ROUTER_CS_5_C3S                         BIT(23)
 181 #define ROUTER_CS_5_PTO                         BIT(24)
 182 #define ROUTER_CS_5_HCO                         BIT(26)
 183 #define ROUTER_CS_5_CV                          BIT(31)
 184 #define ROUTER_CS_6                             0x06
 185 #define ROUTER_CS_6_SLPR                        BIT(0)
 186 #define ROUTER_CS_6_TNS                         BIT(1)
 187 #define ROUTER_CS_6_HCI                         BIT(18)
 188 #define ROUTER_CS_6_CR                          BIT(25)
 189 #define ROUTER_CS_7                             0x07
 190 #define ROUTER_CS_9                             0x09
 191 #define ROUTER_CS_25                            0x19
 192 #define ROUTER_CS_26                            0x1a
 193 #define ROUTER_CS_26_STATUS_MASK                GENMASK(29, 24)
 194 #define ROUTER_CS_26_STATUS_SHIFT               24
 195 #define ROUTER_CS_26_ONS                        BIT(30)
 196 #define ROUTER_CS_26_OV                         BIT(31)
 197
 198 enum tb_port_type {
 199         TB_TYPE_INACTIVE        = 0x000000,
 200         TB_TYPE_PORT            = 0x000001,
 201         TB_TYPE_NHI             = 0x000002,
 202         /* TB_TYPE_ETHERNET     = 0x020000, lower order bits are not known */
 203         /* TB_TYPE_SATA         = 0x080000, lower order bits are not known */
 204         TB_TYPE_DP_HDMI_IN      = 0x0e0101,
 205         TB_TYPE_DP_HDMI_OUT     = 0x0e0102,
 206         TB_TYPE_PCIE_DOWN       = 0x100101,
 207         TB_TYPE_PCIE_UP         = 0x100102,
 208         /* TB_TYPE_USB          = 0x200000, lower order bits are not known */
 209 };
 210
 211 /* Present on every port in TB_CF_PORT at address zero. */
 212 struct tb_regs_port_header {
 213         /* DWORD 0 */
 214         u16 vendor_id;
 215         u16 device_id;
 216         /* DWORD 1 */
 217         u32 first_cap_offset:8;
 218         u32 max_counters:11;
 219         u32 __unknown1:5;
 220         u32 revision:8;
 221         /* DWORD 2 */
 222         enum tb_port_type type:24;
 223         u32 thunderbolt_version:8;
 224         /* DWORD 3 */
 225         u32 __unknown2:20;
 226         u32 port_number:6;
 227         u32 __unknown3:6;
 228         /* DWORD 4 */
 229         u32 nfc_credits;
 230         /* DWORD 5 */
 231         u32 max_in_hop_id:11;
 232         u32 max_out_hop_id:11;
 233         u32 __unknown4:10;
 234         /* DWORD 6 */
 235         u32 __unknown5;
 236         /* DWORD 7 */
 237         u32 __unknown6;
 238
 239 } __packed;
 240
 241 /* Basic adapter configuration registers */
 242 #define ADP_CS_4                                0x04
 243 #define ADP_CS_4_NFC_BUFFERS_MASK               GENMASK(9, 0)
 244 #define ADP_CS_4_TOTAL_BUFFERS_MASK             GENMASK(29, 20)
 245 #define ADP_CS_4_TOTAL_BUFFERS_SHIFT            20
 246 #define ADP_CS_4_LCK                            BIT(31)
 247 #define ADP_CS_5                                0x05
 248 #define ADP_CS_5_LCA_MASK                       GENMASK(28, 22)
 249 #define ADP_CS_5_LCA_SHIFT                      22
 250
 251 /* Lane adapter registers */
 252 #define LANE_ADP_CS_0                           0x00
 253 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK      GENMASK(25, 20)
 254 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT     20
 255 #define LANE_ADP_CS_1                           0x01
 256 #define LANE_ADP_CS_1_TARGET_WIDTH_MASK         GENMASK(9, 4)
 257 #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT        4
 258 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE       0x1
 259 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL         0x3
 260 #define LANE_ADP_CS_1_LB                        BIT(15)
 261 #define LANE_ADP_CS_1_CURRENT_SPEED_MASK        GENMASK(19, 16)
 262 #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT       16
 263 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2        0x8
 264 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3        0x4
 265 #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK        GENMASK(25, 20)
 266 #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT       20
 267
 268 /* USB4 port registers */
 269 #define PORT_CS_18                              0x12
 270 #define PORT_CS_18_BE                           BIT(8)
 271 #define PORT_CS_19                              0x13
 272 #define PORT_CS_19_PC                           BIT(3)
 273
 274 /* Display Port adapter registers */
 275 #define ADP_DP_CS_0                             0x00
 276 #define ADP_DP_CS_0_VIDEO_HOPID_MASK            GENMASK(26, 16)
 277 #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT           16
 278 #define ADP_DP_CS_0_AE                          BIT(30)
 279 #define ADP_DP_CS_0_VE                          BIT(31)
 280 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK           GENMASK(10, 0)
 281 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK           GENMASK(21, 11)
 282 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT          11
 283 #define ADP_DP_CS_2                             0x02
 284 #define ADP_DP_CS_2_HDP                         BIT(6)
 285 #define ADP_DP_CS_3                             0x03
 286 #define ADP_DP_CS_3_HDPC                        BIT(9)
 287 #define DP_LOCAL_CAP                            0x04
 288 #define DP_REMOTE_CAP                           0x05
 289 #define DP_STATUS_CTRL                          0x06
 290 #define DP_STATUS_CTRL_CMHS                     BIT(25)
 291 #define DP_STATUS_CTRL_UF                       BIT(26)
 292 #define DP_COMMON_CAP                           0x07
 293 /*
 294  * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP
 295  * with exception of DPRX done.
 296  */
 297 #define DP_COMMON_CAP_RATE_MASK                 GENMASK(11, 8)
 298 #define DP_COMMON_CAP_RATE_SHIFT                8
 299 #define DP_COMMON_CAP_RATE_RBR                  0x0
 300 #define DP_COMMON_CAP_RATE_HBR                  0x1
 301 #define DP_COMMON_CAP_RATE_HBR2                 0x2
 302 #define DP_COMMON_CAP_RATE_HBR3                 0x3
 303 #define DP_COMMON_CAP_LANES_MASK                GENMASK(14, 12)
 304 #define DP_COMMON_CAP_LANES_SHIFT               12
 305 #define DP_COMMON_CAP_1_LANE                    0x0
 306 #define DP_COMMON_CAP_2_LANES                   0x1
 307 #define DP_COMMON_CAP_4_LANES                   0x2
 308 #define DP_COMMON_CAP_DPRX_DONE                 BIT(31)
 309
 310 /* PCIe adapter registers */
 311 #define ADP_PCIE_CS_0                           0x00
 312 #define ADP_PCIE_CS_0_PE                        BIT(31)
 313
 314 /* Hop register from TB_CFG_HOPS. 8 byte per entry. */
 315 struct tb_regs_hop {
 316         /* DWORD 0 */
 317         u32 next_hop:11; /*
 318                           * hop to take after sending the packet through
 319                           * out_port (on the incoming port of the next switch)
 320                           */
 321         u32 out_port:6; /* next port of the path (on the same switch) */
 322         u32 initial_credits:8;
 323         u32 unknown1:6; /* set to zero */
 324         bool enable:1;
 325
 326         /* DWORD 1 */
 327         u32 weight:4;
 328         u32 unknown2:4; /* set to zero */
 329         u32 priority:3;
 330         bool drop_packages:1;
 331         u32 counter:11; /* index into TB_CFG_COUNTERS on this port */
 332         bool counter_enable:1;
 333         bool ingress_fc:1;
 334         bool egress_fc:1;
 335         bool ingress_shared_buffer:1;
 336         bool egress_shared_buffer:1;
 337         bool pending:1;
 338         u32 unknown3:3; /* set to zero */
 339 } __packed;
 340
 341 /* Common link controller registers */
 342 #define TB_LC_DESC                      0x02
 343 #define TB_LC_DESC_NLC_MASK             GENMASK(3, 0)
 344 #define TB_LC_DESC_SIZE_SHIFT           8
 345 #define TB_LC_DESC_SIZE_MASK            GENMASK(15, 8)
 346 #define TB_LC_DESC_PORT_SIZE_SHIFT      16
 347 #define TB_LC_DESC_PORT_SIZE_MASK       GENMASK(27, 16)
 348 #define TB_LC_FUSE                      0x03
 349 #define TB_LC_SNK_ALLOCATION            0x10
 350 #define TB_LC_SNK_ALLOCATION_SNK0_MASK  GENMASK(3, 0)
 351 #define TB_LC_SNK_ALLOCATION_SNK0_CM    0x1
 352 #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4
 353 #define TB_LC_SNK_ALLOCATION_SNK1_MASK  GENMASK(7, 4)
 354 #define TB_LC_SNK_ALLOCATION_SNK1_CM    0x1
 355
 356 /* Link controller registers */
 357 #define TB_LC_PORT_ATTR                 0x8d
 358 #define TB_LC_PORT_ATTR_BE              BIT(12)
 359
 360 #define TB_LC_SX_CTRL                   0x96
 361 #define TB_LC_SX_CTRL_L1C               BIT(16)
 362 #define TB_LC_SX_CTRL_L2C               BIT(20)
 363 #define TB_LC_SX_CTRL_UPSTREAM          BIT(30)
 364 #define TB_LC_SX_CTRL_SLP               BIT(31)
 365
 366 #endif