drivers/tty/serial/8250/8250_of.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Serial Port driver for Open Firmware platform devices
   4  *
   5  *    Copyright (C) 2006 Arnd Bergmann <arnd@arndb.de>, IBM Corp.
   6  */
   7 #include <linux/console.h>
   8 #include <linux/module.h>
   9 #include <linux/slab.h>
  10 #include <linux/delay.h>
  11 #include <linux/serial_core.h>
  12 #include <linux/serial_reg.h>
  13 #include <linux/of_address.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/pm_runtime.h>
  17 #include <linux/clk.h>
  18 #include <linux/reset.h>
  19
  20 #include "8250.h"
  21
  22 struct of_serial_info {
  23         struct clk *clk;
  24         struct reset_control *rst;
  25         int type;
  26         int line;
  27 };
  28
  29 #ifdef CONFIG_ARCH_TEGRA
  30 static void tegra_serial_handle_break(struct uart_port *p)
  31 {
  32         unsigned int status, tmout = 10000;
  33
  34         do {
  35                 status = p->serial_in(p, UART_LSR);
  36                 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
  37                         status = p->serial_in(p, UART_RX);
  38                 else
  39                         break;
  40                 if (--tmout == 0)
  41                         break;
  42                 udelay(1);
  43         } while (1);
  44 }
  45 #else
  46 static inline void tegra_serial_handle_break(struct uart_port *port)
  47 {
  48 }
  49 #endif
  50
  51 /*
  52  * Fill a struct uart_port for a given device node
  53  */
  54 static int of_platform_serial_setup(struct platform_device *ofdev,
  55                         int type, struct uart_port *port,
  56                         struct of_serial_info *info)
  57 {
  58         struct resource resource;
  59         struct device_node *np = ofdev->dev.of_node;
  60         u32 clk, spd, prop;
  61         int ret, irq;
  62
  63         memset(port, 0, sizeof *port);
  64
  65         pm_runtime_enable(&ofdev->dev);
  66         pm_runtime_get_sync(&ofdev->dev);
  67
  68         if (of_property_read_u32(np, "clock-frequency", &clk)) {
  69
  70                 /* Get clk rate through clk driver if present */
  71                 info->clk = devm_clk_get(&ofdev->dev, NULL);
  72                 if (IS_ERR(info->clk)) {
  73                         dev_warn(&ofdev->dev,
  74                                 "clk or clock-frequency not defined\n");
  75                         ret = PTR_ERR(info->clk);
  76                         goto err_pmruntime;
  77                 }
  78
  79                 ret = clk_prepare_enable(info->clk);
  80                 if (ret < 0)
  81                         goto err_pmruntime;
  82
  83                 clk = clk_get_rate(info->clk);
  84         }
  85         /* If current-speed was set, then try not to change it. */
  86         if (of_property_read_u32(np, "current-speed", &spd) == 0)
  87                 port->custom_divisor = clk / (16 * spd);
  88
  89         ret = of_address_to_resource(np, 0, &resource);
  90         if (ret) {
  91                 dev_warn(&ofdev->dev, "invalid address\n");
  92                 goto err_unprepare;
  93         }
  94
  95         port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT |
  96                                   UPF_FIXED_TYPE;
  97         spin_lock_init(&port->lock);
  98
  99         if (resource_type(&resource) == IORESOURCE_IO) {
 100                 port->iotype = UPIO_PORT;
 101                 port->iobase = resource.start;
 102         } else {
 103                 port->mapbase = resource.start;
 104                 port->mapsize = resource_size(&resource);
 105
 106                 /* Check for shifted address mapping */
 107                 if (of_property_read_u32(np, "reg-offset", &prop) == 0)
 108                         port->mapbase += prop;
 109
 110                 port->iotype = UPIO_MEM;
 111                 if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
 112                         switch (prop) {
 113                         case 1:
 114                                 port->iotype = UPIO_MEM;
 115                                 break;
 116                         case 2:
 117                                 port->iotype = UPIO_MEM16;
 118                                 break;
 119                         case 4:
 120                                 port->iotype = of_device_is_big_endian(np) ?
 121                                                UPIO_MEM32BE : UPIO_MEM32;
 122                                 break;
 123                         default:
 124                                 dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
 125                                          prop);
 126                                 ret = -EINVAL;
 127                                 goto err_unprepare;
 128                         }
 129                 }
 130                 port->flags |= UPF_IOREMAP;
 131         }
 132
 133         /* Check for registers offset within the devices address range */
 134         if (of_property_read_u32(np, "reg-shift", &prop) == 0)
 135                 port->regshift = prop;
 136
 137         /* Check for fifo size */
 138         if (of_property_read_u32(np, "fifo-size", &prop) == 0)
 139                 port->fifosize = prop;
 140
 141         /* Check for a fixed line number */
 142         ret = of_alias_get_id(np, "serial");
 143         if (ret >= 0)
 144                 port->line = ret;
 145
 146         irq = of_irq_get(np, 0);
 147         if (irq < 0) {
 148                 if (irq == -EPROBE_DEFER) {
 149                         ret = -EPROBE_DEFER;
 150                         goto err_unprepare;
 151                 }
 152                 /* IRQ support not mandatory */
 153                 irq = 0;
 154         }
 155
 156         port->irq = irq;
 157
 158         info->rst = devm_reset_control_get_optional_shared(&ofdev->dev, NULL);
 159         if (IS_ERR(info->rst)) {
 160                 ret = PTR_ERR(info->rst);
 161                 goto err_unprepare;
 162         }
 163
 164         ret = reset_control_deassert(info->rst);
 165         if (ret)
 166                 goto err_unprepare;
 167
 168         port->type = type;
 169         port->uartclk = clk;
 170         port->irqflags |= IRQF_SHARED;
 171
 172         if (of_property_read_bool(np, "no-loopback-test"))
 173                 port->flags |= UPF_SKIP_TEST;
 174
 175         port->dev = &ofdev->dev;
 176
 177         switch (type) {
 178         case PORT_TEGRA:
 179                 port->handle_break = tegra_serial_handle_break;
 180                 break;
 181
 182         case PORT_RT2880:
 183                 port->iotype = UPIO_AU;
 184                 break;
 185         }
 186
 187         if (IS_ENABLED(CONFIG_SERIAL_8250_FSL) &&
 188             (of_device_is_compatible(np, "fsl,ns16550") ||
 189              of_device_is_compatible(np, "fsl,16550-FIFO64")))
 190                 port->handle_irq = fsl8250_handle_irq;
 191
 192         return 0;
 193 err_unprepare:
 194         clk_disable_unprepare(info->clk);
 195 err_pmruntime:
 196         pm_runtime_put_sync(&ofdev->dev);
 197         pm_runtime_disable(&ofdev->dev);
 198         return ret;
 199 }
 200
 201 /*
 202  * Try to register a serial port
 203  */
 204 static const struct of_device_id of_platform_serial_table[];
 205 static int of_platform_serial_probe(struct platform_device *ofdev)
 206 {
 207         const struct of_device_id *match;
 208         struct of_serial_info *info;
 209         struct uart_8250_port port8250;
 210         u32 tx_threshold;
 211         int port_type;
 212         int ret;
 213
 214         match = of_match_device(of_platform_serial_table, &ofdev->dev);
 215         if (!match)
 216                 return -EINVAL;
 217
 218         if (of_property_read_bool(ofdev->dev.of_node, "used-by-rtas"))
 219                 return -EBUSY;
 220
 221         info = kzalloc(sizeof(*info), GFP_KERNEL);
 222         if (info == NULL)
 223                 return -ENOMEM;
 224
 225         port_type = (unsigned long)match->data;
 226         memset(&port8250, 0, sizeof(port8250));
 227         ret = of_platform_serial_setup(ofdev, port_type, &port8250.port, info);
 228         if (ret)
 229                 goto err_free;
 230
 231         if (port8250.port.fifosize)
 232                 port8250.capabilities = UART_CAP_FIFO;
 233
 234         /* Check for TX FIFO threshold & set tx_loadsz */
 235         if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
 236                                   &tx_threshold) == 0) &&
 237             (tx_threshold < port8250.port.fifosize))
 238                 port8250.tx_loadsz = port8250.port.fifosize - tx_threshold;
 239
 240         if (of_property_read_bool(ofdev->dev.of_node, "auto-flow-control"))
 241                 port8250.capabilities |= UART_CAP_AFE;
 242
 243         ret = serial8250_register_8250_port(&port8250);
 244         if (ret < 0)
 245                 goto err_dispose;
 246
 247         info->type = port_type;
 248         info->line = ret;
 249         platform_set_drvdata(ofdev, info);
 250         return 0;
 251 err_dispose:
 252         irq_dispose_mapping(port8250.port.irq);
 253         pm_runtime_put_sync(&ofdev->dev);
 254         pm_runtime_disable(&ofdev->dev);
 255         clk_disable_unprepare(info->clk);
 256 err_free:
 257         kfree(info);
 258         return ret;
 259 }
 260
 261 /*
 262  * Release a line
 263  */
 264 static int of_platform_serial_remove(struct platform_device *ofdev)
 265 {
 266         struct of_serial_info *info = platform_get_drvdata(ofdev);
 267
 268         serial8250_unregister_port(info->line);
 269
 270         reset_control_assert(info->rst);
 271         pm_runtime_put_sync(&ofdev->dev);
 272         pm_runtime_disable(&ofdev->dev);
 273         clk_disable_unprepare(info->clk);
 274         kfree(info);
 275         return 0;
 276 }
 277
 278 #ifdef CONFIG_PM_SLEEP
 279 static int of_serial_suspend(struct device *dev)
 280 {
 281         struct of_serial_info *info = dev_get_drvdata(dev);
 282         struct uart_8250_port *port8250 = serial8250_get_port(info->line);
 283         struct uart_port *port = &port8250->port;
 284
 285         serial8250_suspend_port(info->line);
 286
 287         if (!uart_console(port) || console_suspend_enabled) {
 288                 pm_runtime_put_sync(dev);
 289                 clk_disable_unprepare(info->clk);
 290         }
 291         return 0;
 292 }
 293
 294 static int of_serial_resume(struct device *dev)
 295 {
 296         struct of_serial_info *info = dev_get_drvdata(dev);
 297         struct uart_8250_port *port8250 = serial8250_get_port(info->line);
 298         struct uart_port *port = &port8250->port;
 299
 300         if (!uart_console(port) || console_suspend_enabled) {
 301                 pm_runtime_get_sync(dev);
 302                 clk_prepare_enable(info->clk);
 303         }
 304
 305         serial8250_resume_port(info->line);
 306
 307         return 0;
 308 }
 309 #endif
 310 static SIMPLE_DEV_PM_OPS(of_serial_pm_ops, of_serial_suspend, of_serial_resume);
 311
 312 /*
 313  * A few common types, add more as needed.
 314  */
 315 static const struct of_device_id of_platform_serial_table[] = {
 316         { .compatible = "ns8250",   .data = (void *)PORT_8250, },
 317         { .compatible = "ns16450",  .data = (void *)PORT_16450, },
 318         { .compatible = "ns16550a", .data = (void *)PORT_16550A, },
 319         { .compatible = "ns16550",  .data = (void *)PORT_16550, },
 320         { .compatible = "ns16750",  .data = (void *)PORT_16750, },
 321         { .compatible = "ns16850",  .data = (void *)PORT_16850, },
 322         { .compatible = "nvidia,tegra20-uart", .data = (void *)PORT_TEGRA, },
 323         { .compatible = "nxp,lpc3220-uart", .data = (void *)PORT_LPC3220, },
 324         { .compatible = "ralink,rt2880-uart", .data = (void *)PORT_RT2880, },
 325         { .compatible = "altr,16550-FIFO32",
 326                 .data = (void *)PORT_ALTR_16550_F32, },
 327         { .compatible = "altr,16550-FIFO64",
 328                 .data = (void *)PORT_ALTR_16550_F64, },
 329         { .compatible = "altr,16550-FIFO128",
 330                 .data = (void *)PORT_ALTR_16550_F128, },
 331         { .compatible = "mediatek,mtk-btif",
 332                 .data = (void *)PORT_MTK_BTIF, },
 333         { .compatible = "mrvl,mmp-uart",
 334                 .data = (void *)PORT_XSCALE, },
 335         { .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },
 336         { .compatible = "nuvoton,npcm750-uart", .data = (void *)PORT_NPCM, },
 337         { /* end of list */ },
 338 };
 339 MODULE_DEVICE_TABLE(of, of_platform_serial_table);
 340
 341 static struct platform_driver of_platform_serial_driver = {
 342         .driver = {
 343                 .name = "of_serial",
 344                 .of_match_table = of_platform_serial_table,
 345                 .pm = &of_serial_pm_ops,
 346         },
 347         .probe = of_platform_serial_probe,
 348         .remove = of_platform_serial_remove,
 349 };
 350
 351 module_platform_driver(of_platform_serial_driver);
 352
 353 MODULE_AUTHOR("Arnd Bergmann <arnd@arndb.de>");
 354 MODULE_LICENSE("GPL");
 355 MODULE_DESCRIPTION("Serial Port driver for Open Firmware platform devices");