1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale lpuart serial port driver
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
9 #include <linux/console.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dmapool.h>
14 #include <linux/irq.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/of_dma.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty_flip.h>
23 /* All registers are 8-bit width */
33 #define UARTMODEM 0x0d
34 #define UARTPFIFO 0x10
35 #define UARTCFIFO 0x11
36 #define UARTSFIFO 0x12
37 #define UARTTWFIFO 0x13
38 #define UARTTCFIFO 0x14
39 #define UARTRWFIFO 0x15
41 #define UARTBDH_LBKDIE 0x80
42 #define UARTBDH_RXEDGIE 0x40
43 #define UARTBDH_SBR_MASK 0x1f
45 #define UARTCR1_LOOPS 0x80
46 #define UARTCR1_RSRC 0x20
47 #define UARTCR1_M 0x10
48 #define UARTCR1_WAKE 0x08
49 #define UARTCR1_ILT 0x04
50 #define UARTCR1_PE 0x02
51 #define UARTCR1_PT 0x01
53 #define UARTCR2_TIE 0x80
54 #define UARTCR2_TCIE 0x40
55 #define UARTCR2_RIE 0x20
56 #define UARTCR2_ILIE 0x10
57 #define UARTCR2_TE 0x08
58 #define UARTCR2_RE 0x04
59 #define UARTCR2_RWU 0x02
60 #define UARTCR2_SBK 0x01
62 #define UARTSR1_TDRE 0x80
63 #define UARTSR1_TC 0x40
64 #define UARTSR1_RDRF 0x20
65 #define UARTSR1_IDLE 0x10
66 #define UARTSR1_OR 0x08
67 #define UARTSR1_NF 0x04
68 #define UARTSR1_FE 0x02
69 #define UARTSR1_PE 0x01
71 #define UARTCR3_R8 0x80
72 #define UARTCR3_T8 0x40
73 #define UARTCR3_TXDIR 0x20
74 #define UARTCR3_TXINV 0x10
75 #define UARTCR3_ORIE 0x08
76 #define UARTCR3_NEIE 0x04
77 #define UARTCR3_FEIE 0x02
78 #define UARTCR3_PEIE 0x01
80 #define UARTCR4_MAEN1 0x80
81 #define UARTCR4_MAEN2 0x40
82 #define UARTCR4_M10 0x20
83 #define UARTCR4_BRFA_MASK 0x1f
84 #define UARTCR4_BRFA_OFF 0
86 #define UARTCR5_TDMAS 0x80
87 #define UARTCR5_RDMAS 0x20
89 #define UARTMODEM_RXRTSE 0x08
90 #define UARTMODEM_TXRTSPOL 0x04
91 #define UARTMODEM_TXRTSE 0x02
92 #define UARTMODEM_TXCTSE 0x01
94 #define UARTPFIFO_TXFE 0x80
95 #define UARTPFIFO_FIFOSIZE_MASK 0x7
96 #define UARTPFIFO_TXSIZE_OFF 4
97 #define UARTPFIFO_RXFE 0x08
98 #define UARTPFIFO_RXSIZE_OFF 0
100 #define UARTCFIFO_TXFLUSH 0x80
101 #define UARTCFIFO_RXFLUSH 0x40
102 #define UARTCFIFO_RXOFE 0x04
103 #define UARTCFIFO_TXOFE 0x02
104 #define UARTCFIFO_RXUFE 0x01
106 #define UARTSFIFO_TXEMPT 0x80
107 #define UARTSFIFO_RXEMPT 0x40
108 #define UARTSFIFO_RXOF 0x04
109 #define UARTSFIFO_TXOF 0x02
110 #define UARTSFIFO_RXUF 0x01
112 /* 32-bit register definition */
113 #define UARTBAUD 0x00
114 #define UARTSTAT 0x04
115 #define UARTCTRL 0x08
116 #define UARTDATA 0x0C
117 #define UARTMATCH 0x10
118 #define UARTMODIR 0x14
119 #define UARTFIFO 0x18
120 #define UARTWATER 0x1c
122 #define UARTBAUD_MAEN1 0x80000000
123 #define UARTBAUD_MAEN2 0x40000000
124 #define UARTBAUD_M10 0x20000000
125 #define UARTBAUD_TDMAE 0x00800000
126 #define UARTBAUD_RDMAE 0x00200000
127 #define UARTBAUD_MATCFG 0x00400000
128 #define UARTBAUD_BOTHEDGE 0x00020000
129 #define UARTBAUD_RESYNCDIS 0x00010000
130 #define UARTBAUD_LBKDIE 0x00008000
131 #define UARTBAUD_RXEDGIE 0x00004000
132 #define UARTBAUD_SBNS 0x00002000
133 #define UARTBAUD_SBR 0x00000000
134 #define UARTBAUD_SBR_MASK 0x1fff
135 #define UARTBAUD_OSR_MASK 0x1f
136 #define UARTBAUD_OSR_SHIFT 24
138 #define UARTSTAT_LBKDIF 0x80000000
139 #define UARTSTAT_RXEDGIF 0x40000000
140 #define UARTSTAT_MSBF 0x20000000
141 #define UARTSTAT_RXINV 0x10000000
142 #define UARTSTAT_RWUID 0x08000000
143 #define UARTSTAT_BRK13 0x04000000
144 #define UARTSTAT_LBKDE 0x02000000
145 #define UARTSTAT_RAF 0x01000000
146 #define UARTSTAT_TDRE 0x00800000
147 #define UARTSTAT_TC 0x00400000
148 #define UARTSTAT_RDRF 0x00200000
149 #define UARTSTAT_IDLE 0x00100000
150 #define UARTSTAT_OR 0x00080000
151 #define UARTSTAT_NF 0x00040000
152 #define UARTSTAT_FE 0x00020000
153 #define UARTSTAT_PE 0x00010000
154 #define UARTSTAT_MA1F 0x00008000
155 #define UARTSTAT_M21F 0x00004000
157 #define UARTCTRL_R8T9 0x80000000
158 #define UARTCTRL_R9T8 0x40000000
159 #define UARTCTRL_TXDIR 0x20000000
160 #define UARTCTRL_TXINV 0x10000000
161 #define UARTCTRL_ORIE 0x08000000
162 #define UARTCTRL_NEIE 0x04000000
163 #define UARTCTRL_FEIE 0x02000000
164 #define UARTCTRL_PEIE 0x01000000
165 #define UARTCTRL_TIE 0x00800000
166 #define UARTCTRL_TCIE 0x00400000
167 #define UARTCTRL_RIE 0x00200000
168 #define UARTCTRL_ILIE 0x00100000
169 #define UARTCTRL_TE 0x00080000
170 #define UARTCTRL_RE 0x00040000
171 #define UARTCTRL_RWU 0x00020000
172 #define UARTCTRL_SBK 0x00010000
173 #define UARTCTRL_MA1IE 0x00008000
174 #define UARTCTRL_MA2IE 0x00004000
175 #define UARTCTRL_IDLECFG 0x00000100
176 #define UARTCTRL_LOOPS 0x00000080
177 #define UARTCTRL_DOZEEN 0x00000040
178 #define UARTCTRL_RSRC 0x00000020
179 #define UARTCTRL_M 0x00000010
180 #define UARTCTRL_WAKE 0x00000008
181 #define UARTCTRL_ILT 0x00000004
182 #define UARTCTRL_PE 0x00000002
183 #define UARTCTRL_PT 0x00000001
185 #define UARTDATA_NOISY 0x00008000
186 #define UARTDATA_PARITYE 0x00004000
187 #define UARTDATA_FRETSC 0x00002000
188 #define UARTDATA_RXEMPT 0x00001000
189 #define UARTDATA_IDLINE 0x00000800
190 #define UARTDATA_MASK 0x3ff
192 #define UARTMODIR_IREN 0x00020000
193 #define UARTMODIR_TXCTSSRC 0x00000020
194 #define UARTMODIR_TXCTSC 0x00000010
195 #define UARTMODIR_RXRTSE 0x00000008
196 #define UARTMODIR_TXRTSPOL 0x00000004
197 #define UARTMODIR_TXRTSE 0x00000002
198 #define UARTMODIR_TXCTSE 0x00000001
200 #define UARTFIFO_TXEMPT 0x00800000
201 #define UARTFIFO_RXEMPT 0x00400000
202 #define UARTFIFO_TXOF 0x00020000
203 #define UARTFIFO_RXUF 0x00010000
204 #define UARTFIFO_TXFLUSH 0x00008000
205 #define UARTFIFO_RXFLUSH 0x00004000
206 #define UARTFIFO_TXOFE 0x00000200
207 #define UARTFIFO_RXUFE 0x00000100
208 #define UARTFIFO_TXFE 0x00000080
209 #define UARTFIFO_FIFOSIZE_MASK 0x7
210 #define UARTFIFO_TXSIZE_OFF 4
211 #define UARTFIFO_RXFE 0x00000008
212 #define UARTFIFO_RXSIZE_OFF 0
213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0))
215 #define UARTWATER_COUNT_MASK 0xff
216 #define UARTWATER_TXCNT_OFF 8
217 #define UARTWATER_RXCNT_OFF 24
218 #define UARTWATER_WATER_MASK 0xff
219 #define UARTWATER_TXWATER_OFF 0
220 #define UARTWATER_RXWATER_OFF 16
222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
223 #define DMA_RX_TIMEOUT (10)
225 #define DRIVER_NAME "fsl-lpuart"
226 #define DEV_NAME "ttyLP"
229 /* IMX lpuart has four extra unused regs located at the beginning */
230 #define IMX_REG_OFF 0x10
232 static DEFINE_IDA(fsl_lpuart_ida);
242 struct uart_port port;
243 enum lpuart_type devtype;
245 struct clk *baud_clk;
246 unsigned int txfifo_size;
247 unsigned int rxfifo_size;
249 bool lpuart_dma_tx_use;
250 bool lpuart_dma_rx_use;
251 struct dma_chan *dma_tx_chan;
252 struct dma_chan *dma_rx_chan;
253 struct dma_async_tx_descriptor *dma_tx_desc;
254 struct dma_async_tx_descriptor *dma_rx_desc;
255 dma_cookie_t dma_tx_cookie;
256 dma_cookie_t dma_rx_cookie;
257 unsigned int dma_tx_bytes;
258 unsigned int dma_rx_bytes;
259 bool dma_tx_in_progress;
260 unsigned int dma_rx_timeout;
261 struct timer_list lpuart_timer;
262 struct scatterlist rx_sgl, tx_sgl[2];
263 struct circ_buf rx_ring;
264 int rx_dma_rng_buf_len;
265 unsigned int dma_tx_nents;
266 wait_queue_head_t dma_wait;
270 struct lpuart_soc_data {
271 enum lpuart_type devtype;
276 static const struct lpuart_soc_data vf_data = {
277 .devtype = VF610_LPUART,
281 static const struct lpuart_soc_data ls_data = {
282 .devtype = LS1021A_LPUART,
283 .iotype = UPIO_MEM32BE,
286 static struct lpuart_soc_data imx7ulp_data = {
287 .devtype = IMX7ULP_LPUART,
288 .iotype = UPIO_MEM32,
289 .reg_off = IMX_REG_OFF,
292 static struct lpuart_soc_data imx8qxp_data = {
293 .devtype = IMX8QXP_LPUART,
294 .iotype = UPIO_MEM32,
295 .reg_off = IMX_REG_OFF,
298 static const struct of_device_id lpuart_dt_ids[] = {
299 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
300 { .compatible = "fsl,ls1021a-lpuart", .data = &ls_data, },
301 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, },
302 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, },
305 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
307 /* Forward declare this for the dma callbacks*/
308 static void lpuart_dma_tx_complete(void *arg);
310 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
312 return sport->devtype == IMX8QXP_LPUART;
315 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
317 switch (port->iotype) {
319 return readl(port->membase + off);
321 return ioread32be(port->membase + off);
327 static inline void lpuart32_write(struct uart_port *port, u32 val,
330 switch (port->iotype) {
332 writel(val, port->membase + off);
335 iowrite32be(val, port->membase + off);
340 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
345 ret = clk_prepare_enable(sport->ipg_clk);
349 ret = clk_prepare_enable(sport->baud_clk);
351 clk_disable_unprepare(sport->ipg_clk);
355 clk_disable_unprepare(sport->baud_clk);
356 clk_disable_unprepare(sport->ipg_clk);
362 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
364 if (is_imx8qxp_lpuart(sport))
365 return clk_get_rate(sport->baud_clk);
367 return clk_get_rate(sport->ipg_clk);
370 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true)
371 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false)
373 static void lpuart_stop_tx(struct uart_port *port)
377 temp = readb(port->membase + UARTCR2);
378 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
379 writeb(temp, port->membase + UARTCR2);
382 static void lpuart32_stop_tx(struct uart_port *port)
386 temp = lpuart32_read(port, UARTCTRL);
387 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
388 lpuart32_write(port, temp, UARTCTRL);
391 static void lpuart_stop_rx(struct uart_port *port)
395 temp = readb(port->membase + UARTCR2);
396 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
399 static void lpuart32_stop_rx(struct uart_port *port)
403 temp = lpuart32_read(port, UARTCTRL);
404 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
407 static void lpuart_dma_tx(struct lpuart_port *sport)
409 struct circ_buf *xmit = &sport->port.state->xmit;
410 struct scatterlist *sgl = sport->tx_sgl;
411 struct device *dev = sport->port.dev;
414 if (sport->dma_tx_in_progress)
417 sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
419 if (xmit->tail < xmit->head || xmit->head == 0) {
420 sport->dma_tx_nents = 1;
421 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
423 sport->dma_tx_nents = 2;
424 sg_init_table(sgl, 2);
425 sg_set_buf(sgl, xmit->buf + xmit->tail,
426 UART_XMIT_SIZE - xmit->tail);
427 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
430 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
432 dev_err(dev, "DMA mapping error for TX.\n");
436 sport->dma_tx_desc = dmaengine_prep_slave_sg(sport->dma_tx_chan, sgl,
439 if (!sport->dma_tx_desc) {
440 dma_unmap_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
441 dev_err(dev, "Cannot prepare TX slave DMA!\n");
445 sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
446 sport->dma_tx_desc->callback_param = sport;
447 sport->dma_tx_in_progress = true;
448 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
449 dma_async_issue_pending(sport->dma_tx_chan);
452 static bool lpuart_stopped_or_empty(struct uart_port *port)
454 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
457 static void lpuart_dma_tx_complete(void *arg)
459 struct lpuart_port *sport = arg;
460 struct scatterlist *sgl = &sport->tx_sgl[0];
461 struct circ_buf *xmit = &sport->port.state->xmit;
464 spin_lock_irqsave(&sport->port.lock, flags);
466 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
468 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1);
470 sport->port.icount.tx += sport->dma_tx_bytes;
471 sport->dma_tx_in_progress = false;
472 spin_unlock_irqrestore(&sport->port.lock, flags);
474 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
475 uart_write_wakeup(&sport->port);
477 if (waitqueue_active(&sport->dma_wait)) {
478 wake_up(&sport->dma_wait);
482 spin_lock_irqsave(&sport->port.lock, flags);
484 if (!lpuart_stopped_or_empty(&sport->port))
485 lpuart_dma_tx(sport);
487 spin_unlock_irqrestore(&sport->port.lock, flags);
490 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
492 switch (sport->port.iotype) {
494 return sport->port.mapbase + UARTDATA;
496 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
498 return sport->port.mapbase + UARTDR;
501 static int lpuart_dma_tx_request(struct uart_port *port)
503 struct lpuart_port *sport = container_of(port,
504 struct lpuart_port, port);
505 struct dma_slave_config dma_tx_sconfig = {};
508 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
509 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
510 dma_tx_sconfig.dst_maxburst = 1;
511 dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
512 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
515 dev_err(sport->port.dev,
516 "DMA slave config failed, err = %d\n", ret);
523 static bool lpuart_is_32(struct lpuart_port *sport)
525 return sport->port.iotype == UPIO_MEM32 ||
526 sport->port.iotype == UPIO_MEM32BE;
529 static void lpuart_flush_buffer(struct uart_port *port)
531 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
534 if (sport->lpuart_dma_tx_use) {
535 if (sport->dma_tx_in_progress) {
536 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
537 sport->dma_tx_nents, DMA_TO_DEVICE);
538 sport->dma_tx_in_progress = false;
540 dmaengine_terminate_all(sport->dma_tx_chan);
543 if (lpuart_is_32(sport)) {
544 val = lpuart32_read(&sport->port, UARTFIFO);
545 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
546 lpuart32_write(&sport->port, val, UARTFIFO);
548 val = readb(sport->port.membase + UARTCFIFO);
549 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
550 writeb(val, sport->port.membase + UARTCFIFO);
554 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
557 while (!(readb(port->membase + offset) & bit))
561 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
564 while (!(lpuart32_read(port, offset) & bit))
568 #if defined(CONFIG_CONSOLE_POLL)
570 static int lpuart_poll_init(struct uart_port *port)
572 struct lpuart_port *sport = container_of(port,
573 struct lpuart_port, port);
577 sport->port.fifosize = 0;
579 spin_lock_irqsave(&sport->port.lock, flags);
580 /* Disable Rx & Tx */
581 writeb(0, sport->port.membase + UARTCR2);
583 temp = readb(sport->port.membase + UARTPFIFO);
584 /* Enable Rx and Tx FIFO */
585 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
586 sport->port.membase + UARTPFIFO);
588 /* flush Tx and Rx FIFO */
589 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
590 sport->port.membase + UARTCFIFO);
592 /* explicitly clear RDRF */
593 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
594 readb(sport->port.membase + UARTDR);
595 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
598 writeb(0, sport->port.membase + UARTTWFIFO);
599 writeb(1, sport->port.membase + UARTRWFIFO);
601 /* Enable Rx and Tx */
602 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
603 spin_unlock_irqrestore(&sport->port.lock, flags);
608 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
611 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
612 writeb(c, port->membase + UARTDR);
615 static int lpuart_poll_get_char(struct uart_port *port)
617 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
620 return readb(port->membase + UARTDR);
623 static int lpuart32_poll_init(struct uart_port *port)
626 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
629 sport->port.fifosize = 0;
631 spin_lock_irqsave(&sport->port.lock, flags);
633 /* Disable Rx & Tx */
634 lpuart32_write(&sport->port, UARTCTRL, 0);
636 temp = lpuart32_read(&sport->port, UARTFIFO);
638 /* Enable Rx and Tx FIFO */
639 lpuart32_write(&sport->port, UARTFIFO,
640 temp | UARTFIFO_RXFE | UARTFIFO_TXFE);
642 /* flush Tx and Rx FIFO */
643 lpuart32_write(&sport->port, UARTFIFO,
644 UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH);
646 /* explicitly clear RDRF */
647 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
648 lpuart32_read(&sport->port, UARTDATA);
649 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF);
652 /* Enable Rx and Tx */
653 lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE);
654 spin_unlock_irqrestore(&sport->port.lock, flags);
659 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
661 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
662 lpuart32_write(port, UARTDATA, c);
665 static int lpuart32_poll_get_char(struct uart_port *port)
667 if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF))
670 return lpuart32_read(port, UARTDATA);
674 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
676 struct circ_buf *xmit = &sport->port.state->xmit;
678 if (sport->port.x_char) {
679 writeb(sport->port.x_char, sport->port.membase + UARTDR);
680 sport->port.icount.tx++;
681 sport->port.x_char = 0;
685 if (lpuart_stopped_or_empty(&sport->port)) {
686 lpuart_stop_tx(&sport->port);
690 while (!uart_circ_empty(xmit) &&
691 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) {
692 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR);
693 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
694 sport->port.icount.tx++;
697 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
698 uart_write_wakeup(&sport->port);
700 if (uart_circ_empty(xmit))
701 lpuart_stop_tx(&sport->port);
704 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
706 struct circ_buf *xmit = &sport->port.state->xmit;
709 if (sport->port.x_char) {
710 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
711 sport->port.icount.tx++;
712 sport->port.x_char = 0;
716 if (lpuart_stopped_or_empty(&sport->port)) {
717 lpuart32_stop_tx(&sport->port);
721 txcnt = lpuart32_read(&sport->port, UARTWATER);
722 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
723 txcnt &= UARTWATER_COUNT_MASK;
724 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
725 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
726 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
727 sport->port.icount.tx++;
728 txcnt = lpuart32_read(&sport->port, UARTWATER);
729 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
730 txcnt &= UARTWATER_COUNT_MASK;
733 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
734 uart_write_wakeup(&sport->port);
736 if (uart_circ_empty(xmit))
737 lpuart32_stop_tx(&sport->port);
740 static void lpuart_start_tx(struct uart_port *port)
742 struct lpuart_port *sport = container_of(port,
743 struct lpuart_port, port);
746 temp = readb(port->membase + UARTCR2);
747 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
749 if (sport->lpuart_dma_tx_use) {
750 if (!lpuart_stopped_or_empty(port))
751 lpuart_dma_tx(sport);
753 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
754 lpuart_transmit_buffer(sport);
758 static void lpuart32_start_tx(struct uart_port *port)
760 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
763 if (sport->lpuart_dma_tx_use) {
764 if (!lpuart_stopped_or_empty(port))
765 lpuart_dma_tx(sport);
767 temp = lpuart32_read(port, UARTCTRL);
768 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
770 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
771 lpuart32_transmit_buffer(sport);
775 /* return TIOCSER_TEMT when transmitter is not busy */
776 static unsigned int lpuart_tx_empty(struct uart_port *port)
778 struct lpuart_port *sport = container_of(port,
779 struct lpuart_port, port);
780 unsigned char sr1 = readb(port->membase + UARTSR1);
781 unsigned char sfifo = readb(port->membase + UARTSFIFO);
783 if (sport->dma_tx_in_progress)
786 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
792 static unsigned int lpuart32_tx_empty(struct uart_port *port)
794 struct lpuart_port *sport = container_of(port,
795 struct lpuart_port, port);
796 unsigned long stat = lpuart32_read(port, UARTSTAT);
797 unsigned long sfifo = lpuart32_read(port, UARTFIFO);
799 if (sport->dma_tx_in_progress)
802 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT)
808 static void lpuart_txint(struct lpuart_port *sport)
812 spin_lock_irqsave(&sport->port.lock, flags);
813 lpuart_transmit_buffer(sport);
814 spin_unlock_irqrestore(&sport->port.lock, flags);
817 static void lpuart_rxint(struct lpuart_port *sport)
819 unsigned int flg, ignored = 0, overrun = 0;
820 struct tty_port *port = &sport->port.state->port;
822 unsigned char rx, sr;
824 spin_lock_irqsave(&sport->port.lock, flags);
826 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
828 sport->port.icount.rx++;
830 * to clear the FE, OR, NF, FE, PE flags,
831 * read SR1 then read DR
833 sr = readb(sport->port.membase + UARTSR1);
834 rx = readb(sport->port.membase + UARTDR);
836 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
839 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
841 sport->port.icount.parity++;
842 else if (sr & UARTSR1_FE)
843 sport->port.icount.frame++;
848 if (sr & sport->port.ignore_status_mask) {
854 sr &= sport->port.read_status_mask;
858 else if (sr & UARTSR1_FE)
864 sport->port.sysrq = 0;
867 tty_insert_flip_char(port, rx, flg);
872 sport->port.icount.overrun += overrun;
875 * Overruns cause FIFO pointers to become missaligned.
876 * Flushing the receive FIFO reinitializes the pointers.
878 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
879 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
882 spin_unlock_irqrestore(&sport->port.lock, flags);
884 tty_flip_buffer_push(port);
887 static void lpuart32_txint(struct lpuart_port *sport)
891 spin_lock_irqsave(&sport->port.lock, flags);
892 lpuart32_transmit_buffer(sport);
893 spin_unlock_irqrestore(&sport->port.lock, flags);
896 static void lpuart32_rxint(struct lpuart_port *sport)
898 unsigned int flg, ignored = 0;
899 struct tty_port *port = &sport->port.state->port;
901 unsigned long rx, sr;
903 spin_lock_irqsave(&sport->port.lock, flags);
905 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
907 sport->port.icount.rx++;
909 * to clear the FE, OR, NF, FE, PE flags,
910 * read STAT then read DATA reg
912 sr = lpuart32_read(&sport->port, UARTSTAT);
913 rx = lpuart32_read(&sport->port, UARTDATA);
916 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
919 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
920 if (sr & UARTSTAT_PE)
921 sport->port.icount.parity++;
922 else if (sr & UARTSTAT_FE)
923 sport->port.icount.frame++;
925 if (sr & UARTSTAT_OR)
926 sport->port.icount.overrun++;
928 if (sr & sport->port.ignore_status_mask) {
934 sr &= sport->port.read_status_mask;
936 if (sr & UARTSTAT_PE)
938 else if (sr & UARTSTAT_FE)
941 if (sr & UARTSTAT_OR)
944 sport->port.sysrq = 0;
947 tty_insert_flip_char(port, rx, flg);
951 spin_unlock_irqrestore(&sport->port.lock, flags);
953 tty_flip_buffer_push(port);
956 static irqreturn_t lpuart_int(int irq, void *dev_id)
958 struct lpuart_port *sport = dev_id;
961 sts = readb(sport->port.membase + UARTSR1);
963 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
966 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
972 static irqreturn_t lpuart32_int(int irq, void *dev_id)
974 struct lpuart_port *sport = dev_id;
975 unsigned long sts, rxcount;
977 sts = lpuart32_read(&sport->port, UARTSTAT);
978 rxcount = lpuart32_read(&sport->port, UARTWATER);
979 rxcount = rxcount >> UARTWATER_RXCNT_OFF;
981 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
982 lpuart32_rxint(sport);
984 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
985 lpuart32_txint(sport);
987 lpuart32_write(&sport->port, sts, UARTSTAT);
991 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
993 struct tty_port *port = &sport->port.state->port;
994 struct dma_tx_state state;
995 enum dma_status dmastat;
996 struct circ_buf *ring = &sport->rx_ring;
1000 if (lpuart_is_32(sport)) {
1001 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1003 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1004 /* Read DR to clear the error flags */
1005 lpuart32_read(&sport->port, UARTDATA);
1007 if (sr & UARTSTAT_PE)
1008 sport->port.icount.parity++;
1009 else if (sr & UARTSTAT_FE)
1010 sport->port.icount.frame++;
1013 unsigned char sr = readb(sport->port.membase + UARTSR1);
1015 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1018 /* Disable receiver during this operation... */
1019 cr2 = readb(sport->port.membase + UARTCR2);
1021 writeb(cr2, sport->port.membase + UARTCR2);
1023 /* Read DR to clear the error flags */
1024 readb(sport->port.membase + UARTDR);
1026 if (sr & UARTSR1_PE)
1027 sport->port.icount.parity++;
1028 else if (sr & UARTSR1_FE)
1029 sport->port.icount.frame++;
1031 * At this point parity/framing error is
1032 * cleared However, since the DMA already read
1033 * the data register and we had to read it
1034 * again after reading the status register to
1035 * properly clear the flags, the FIFO actually
1036 * underflowed... This requires a clearing of
1039 if (readb(sport->port.membase + UARTSFIFO) &
1041 writeb(UARTSFIFO_RXUF,
1042 sport->port.membase + UARTSFIFO);
1043 writeb(UARTCFIFO_RXFLUSH,
1044 sport->port.membase + UARTCFIFO);
1048 writeb(cr2, sport->port.membase + UARTCR2);
1052 async_tx_ack(sport->dma_rx_desc);
1054 spin_lock_irqsave(&sport->port.lock, flags);
1056 dmastat = dmaengine_tx_status(sport->dma_rx_chan,
1057 sport->dma_rx_cookie,
1060 if (dmastat == DMA_ERROR) {
1061 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1062 spin_unlock_irqrestore(&sport->port.lock, flags);
1066 /* CPU claims ownership of RX DMA buffer */
1067 dma_sync_sg_for_cpu(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1070 * ring->head points to the end of data already written by the DMA.
1071 * ring->tail points to the beginning of data to be read by the
1073 * The current transfer size should not be larger than the dma buffer
1076 ring->head = sport->rx_sgl.length - state.residue;
1077 BUG_ON(ring->head > sport->rx_sgl.length);
1079 * At this point ring->head may point to the first byte right after the
1080 * last byte of the dma buffer:
1081 * 0 <= ring->head <= sport->rx_sgl.length
1083 * However ring->tail must always points inside the dma buffer:
1084 * 0 <= ring->tail <= sport->rx_sgl.length - 1
1086 * Since we use a ring buffer, we have to handle the case
1087 * where head is lower than tail. In such a case, we first read from
1088 * tail to the end of the buffer then reset tail.
1090 if (ring->head < ring->tail) {
1091 count = sport->rx_sgl.length - ring->tail;
1093 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1095 sport->port.icount.rx += count;
1098 /* Finally we read data from tail to head */
1099 if (ring->tail < ring->head) {
1100 count = ring->head - ring->tail;
1101 tty_insert_flip_string(port, ring->buf + ring->tail, count);
1102 /* Wrap ring->head if needed */
1103 if (ring->head >= sport->rx_sgl.length)
1105 ring->tail = ring->head;
1106 sport->port.icount.rx += count;
1109 dma_sync_sg_for_device(sport->port.dev, &sport->rx_sgl, 1,
1112 spin_unlock_irqrestore(&sport->port.lock, flags);
1114 tty_flip_buffer_push(port);
1115 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1118 static void lpuart_dma_rx_complete(void *arg)
1120 struct lpuart_port *sport = arg;
1122 lpuart_copy_rx_to_tty(sport);
1125 static void lpuart_timer_func(struct timer_list *t)
1127 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1129 lpuart_copy_rx_to_tty(sport);
1132 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1134 struct dma_slave_config dma_rx_sconfig = {};
1135 struct circ_buf *ring = &sport->rx_ring;
1138 struct tty_port *port = &sport->port.state->port;
1139 struct tty_struct *tty = port->tty;
1140 struct ktermios *termios = &tty->termios;
1142 baud = tty_get_baud_rate(tty);
1144 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10;
1145 if (termios->c_cflag & PARENB)
1149 * Calculate length of one DMA buffer size to keep latency below
1150 * 10ms at any baud rate.
1152 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2;
1153 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1));
1154 if (sport->rx_dma_rng_buf_len < 16)
1155 sport->rx_dma_rng_buf_len = 16;
1157 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1161 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1162 nent = dma_map_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1165 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1169 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1170 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1171 dma_rx_sconfig.src_maxburst = 1;
1172 dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1173 ret = dmaengine_slave_config(sport->dma_rx_chan, &dma_rx_sconfig);
1176 dev_err(sport->port.dev,
1177 "DMA Rx slave config failed, err = %d\n", ret);
1181 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(sport->dma_rx_chan,
1182 sg_dma_address(&sport->rx_sgl),
1183 sport->rx_sgl.length,
1184 sport->rx_sgl.length / 2,
1186 DMA_PREP_INTERRUPT);
1187 if (!sport->dma_rx_desc) {
1188 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1192 sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1193 sport->dma_rx_desc->callback_param = sport;
1194 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1195 dma_async_issue_pending(sport->dma_rx_chan);
1197 if (lpuart_is_32(sport)) {
1198 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1200 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1202 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1203 sport->port.membase + UARTCR5);
1209 static void lpuart_dma_rx_free(struct uart_port *port)
1211 struct lpuart_port *sport = container_of(port,
1212 struct lpuart_port, port);
1214 if (sport->dma_rx_chan)
1215 dmaengine_terminate_all(sport->dma_rx_chan);
1217 dma_unmap_sg(sport->port.dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1218 kfree(sport->rx_ring.buf);
1219 sport->rx_ring.tail = 0;
1220 sport->rx_ring.head = 0;
1221 sport->dma_rx_desc = NULL;
1222 sport->dma_rx_cookie = -EINVAL;
1225 static int lpuart_config_rs485(struct uart_port *port,
1226 struct serial_rs485 *rs485)
1228 struct lpuart_port *sport = container_of(port,
1229 struct lpuart_port, port);
1231 u8 modem = readb(sport->port.membase + UARTMODEM) &
1232 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1233 writeb(modem, sport->port.membase + UARTMODEM);
1235 /* clear unsupported configurations */
1236 rs485->delay_rts_before_send = 0;
1237 rs485->delay_rts_after_send = 0;
1238 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1240 if (rs485->flags & SER_RS485_ENABLED) {
1241 /* Enable auto RS-485 RTS mode */
1242 modem |= UARTMODEM_TXRTSE;
1245 * RTS needs to be logic HIGH either during transer _or_ after
1246 * transfer, other variants are not supported by the hardware.
1249 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1250 SER_RS485_RTS_AFTER_SEND)))
1251 rs485->flags |= SER_RS485_RTS_ON_SEND;
1253 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1254 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1255 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1258 * The hardware defaults to RTS logic HIGH while transfer.
1259 * Switch polarity in case RTS shall be logic HIGH
1261 * Note: UART is assumed to be active high.
1263 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1264 modem &= ~UARTMODEM_TXRTSPOL;
1265 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1266 modem |= UARTMODEM_TXRTSPOL;
1269 /* Store the new configuration */
1270 sport->port.rs485 = *rs485;
1272 writeb(modem, sport->port.membase + UARTMODEM);
1276 static int lpuart32_config_rs485(struct uart_port *port,
1277 struct serial_rs485 *rs485)
1279 struct lpuart_port *sport = container_of(port,
1280 struct lpuart_port, port);
1282 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1283 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1284 lpuart32_write(&sport->port, modem, UARTMODIR);
1286 /* clear unsupported configurations */
1287 rs485->delay_rts_before_send = 0;
1288 rs485->delay_rts_after_send = 0;
1289 rs485->flags &= ~SER_RS485_RX_DURING_TX;
1291 if (rs485->flags & SER_RS485_ENABLED) {
1292 /* Enable auto RS-485 RTS mode */
1293 modem |= UARTMODEM_TXRTSE;
1296 * RTS needs to be logic HIGH either during transer _or_ after
1297 * transfer, other variants are not supported by the hardware.
1300 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND |
1301 SER_RS485_RTS_AFTER_SEND)))
1302 rs485->flags |= SER_RS485_RTS_ON_SEND;
1304 if (rs485->flags & SER_RS485_RTS_ON_SEND &&
1305 rs485->flags & SER_RS485_RTS_AFTER_SEND)
1306 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
1309 * The hardware defaults to RTS logic HIGH while transfer.
1310 * Switch polarity in case RTS shall be logic HIGH
1312 * Note: UART is assumed to be active high.
1314 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1315 modem &= ~UARTMODEM_TXRTSPOL;
1316 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1317 modem |= UARTMODEM_TXRTSPOL;
1320 /* Store the new configuration */
1321 sport->port.rs485 = *rs485;
1323 lpuart32_write(&sport->port, modem, UARTMODIR);
1327 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1329 unsigned int temp = 0;
1332 reg = readb(port->membase + UARTMODEM);
1333 if (reg & UARTMODEM_TXCTSE)
1336 if (reg & UARTMODEM_RXRTSE)
1342 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1344 unsigned int temp = 0;
1347 reg = lpuart32_read(port, UARTMODIR);
1348 if (reg & UARTMODIR_TXCTSE)
1351 if (reg & UARTMODIR_RXRTSE)
1357 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1360 struct lpuart_port *sport = container_of(port,
1361 struct lpuart_port, port);
1363 /* Make sure RXRTSE bit is not set when RS485 is enabled */
1364 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) {
1365 temp = readb(sport->port.membase + UARTMODEM) &
1366 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1368 if (mctrl & TIOCM_RTS)
1369 temp |= UARTMODEM_RXRTSE;
1371 if (mctrl & TIOCM_CTS)
1372 temp |= UARTMODEM_TXCTSE;
1374 writeb(temp, port->membase + UARTMODEM);
1378 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1383 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1387 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1389 if (break_state != 0)
1390 temp |= UARTCR2_SBK;
1392 writeb(temp, port->membase + UARTCR2);
1395 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1399 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK;
1401 if (break_state != 0)
1402 temp |= UARTCTRL_SBK;
1404 lpuart32_write(port, temp, UARTCTRL);
1407 static void lpuart_setup_watermark(struct lpuart_port *sport)
1409 unsigned char val, cr2;
1410 unsigned char cr2_saved;
1412 cr2 = readb(sport->port.membase + UARTCR2);
1414 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1415 UARTCR2_RIE | UARTCR2_RE);
1416 writeb(cr2, sport->port.membase + UARTCR2);
1418 val = readb(sport->port.membase + UARTPFIFO);
1419 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1420 sport->port.membase + UARTPFIFO);
1422 /* flush Tx and Rx FIFO */
1423 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1424 sport->port.membase + UARTCFIFO);
1426 /* explicitly clear RDRF */
1427 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1428 readb(sport->port.membase + UARTDR);
1429 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1432 writeb(0, sport->port.membase + UARTTWFIFO);
1433 writeb(1, sport->port.membase + UARTRWFIFO);
1436 writeb(cr2_saved, sport->port.membase + UARTCR2);
1439 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1443 lpuart_setup_watermark(sport);
1445 cr2 = readb(sport->port.membase + UARTCR2);
1446 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1447 writeb(cr2, sport->port.membase + UARTCR2);
1450 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1452 unsigned long val, ctrl;
1453 unsigned long ctrl_saved;
1455 ctrl = lpuart32_read(&sport->port, UARTCTRL);
1457 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1458 UARTCTRL_RIE | UARTCTRL_RE);
1459 lpuart32_write(&sport->port, ctrl, UARTCTRL);
1461 /* enable FIFO mode */
1462 val = lpuart32_read(&sport->port, UARTFIFO);
1463 val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1464 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1465 lpuart32_write(&sport->port, val, UARTFIFO);
1467 /* set the watermark */
1468 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF);
1469 lpuart32_write(&sport->port, val, UARTWATER);
1472 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1475 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1479 lpuart32_setup_watermark(sport);
1481 temp = lpuart32_read(&sport->port, UARTCTRL);
1482 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE;
1483 lpuart32_write(&sport->port, temp, UARTCTRL);
1486 static void rx_dma_timer_init(struct lpuart_port *sport)
1488 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1489 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1490 add_timer(&sport->lpuart_timer);
1493 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1497 if (sport->dma_tx_chan && !lpuart_dma_tx_request(&sport->port)) {
1498 init_waitqueue_head(&sport->dma_wait);
1499 sport->lpuart_dma_tx_use = true;
1500 if (lpuart_is_32(sport)) {
1501 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1502 lpuart32_write(&sport->port,
1503 uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1505 writeb(readb(sport->port.membase + UARTCR5) |
1506 UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1509 sport->lpuart_dma_tx_use = false;
1513 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1515 if (sport->dma_rx_chan && !lpuart_start_rx_dma(sport)) {
1516 /* set Rx DMA timeout */
1517 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1518 if (!sport->dma_rx_timeout)
1519 sport->dma_rx_timeout = 1;
1521 sport->lpuart_dma_rx_use = true;
1522 rx_dma_timer_init(sport);
1524 sport->lpuart_dma_rx_use = false;
1528 static int lpuart_startup(struct uart_port *port)
1530 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1531 unsigned long flags;
1534 /* determine FIFO size and enable FIFO mode */
1535 temp = readb(sport->port.membase + UARTPFIFO);
1537 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1538 UARTPFIFO_FIFOSIZE_MASK);
1539 sport->port.fifosize = sport->txfifo_size;
1541 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1542 UARTPFIFO_FIFOSIZE_MASK);
1544 spin_lock_irqsave(&sport->port.lock, flags);
1546 lpuart_setup_watermark_enable(sport);
1548 lpuart_rx_dma_startup(sport);
1549 lpuart_tx_dma_startup(sport);
1551 spin_unlock_irqrestore(&sport->port.lock, flags);
1556 static void lpuart32_configure(struct lpuart_port *sport)
1560 if (sport->lpuart_dma_rx_use) {
1561 /* RXWATER must be 0 */
1562 temp = lpuart32_read(&sport->port, UARTWATER);
1563 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF);
1564 lpuart32_write(&sport->port, temp, UARTWATER);
1566 temp = lpuart32_read(&sport->port, UARTCTRL);
1567 if (!sport->lpuart_dma_rx_use)
1568 temp |= UARTCTRL_RIE;
1569 if (!sport->lpuart_dma_tx_use)
1570 temp |= UARTCTRL_TIE;
1571 lpuart32_write(&sport->port, temp, UARTCTRL);
1574 static int lpuart32_startup(struct uart_port *port)
1576 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1577 unsigned long flags;
1580 /* determine FIFO size */
1581 temp = lpuart32_read(&sport->port, UARTFIFO);
1583 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1584 UARTFIFO_FIFOSIZE_MASK);
1585 sport->port.fifosize = sport->txfifo_size;
1587 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1588 UARTFIFO_FIFOSIZE_MASK);
1590 spin_lock_irqsave(&sport->port.lock, flags);
1592 lpuart32_setup_watermark_enable(sport);
1595 lpuart_rx_dma_startup(sport);
1596 lpuart_tx_dma_startup(sport);
1598 lpuart32_configure(sport);
1600 spin_unlock_irqrestore(&sport->port.lock, flags);
1604 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1606 if (sport->lpuart_dma_rx_use) {
1607 del_timer_sync(&sport->lpuart_timer);
1608 lpuart_dma_rx_free(&sport->port);
1611 if (sport->lpuart_dma_tx_use) {
1612 if (wait_event_interruptible(sport->dma_wait,
1613 !sport->dma_tx_in_progress) != false) {
1614 sport->dma_tx_in_progress = false;
1615 dmaengine_terminate_all(sport->dma_tx_chan);
1620 static void lpuart_shutdown(struct uart_port *port)
1622 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1624 unsigned long flags;
1626 spin_lock_irqsave(&port->lock, flags);
1628 /* disable Rx/Tx and interrupts */
1629 temp = readb(port->membase + UARTCR2);
1630 temp &= ~(UARTCR2_TE | UARTCR2_RE |
1631 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1632 writeb(temp, port->membase + UARTCR2);
1634 spin_unlock_irqrestore(&port->lock, flags);
1636 lpuart_dma_shutdown(sport);
1639 static void lpuart32_shutdown(struct uart_port *port)
1641 struct lpuart_port *sport =
1642 container_of(port, struct lpuart_port, port);
1644 unsigned long flags;
1646 spin_lock_irqsave(&port->lock, flags);
1648 /* disable Rx/Tx and interrupts */
1649 temp = lpuart32_read(port, UARTCTRL);
1650 temp &= ~(UARTCTRL_TE | UARTCTRL_RE |
1651 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
1652 lpuart32_write(port, temp, UARTCTRL);
1654 spin_unlock_irqrestore(&port->lock, flags);
1656 lpuart_dma_shutdown(sport);
1660 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1661 struct ktermios *old)
1663 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1664 unsigned long flags;
1665 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1667 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1668 unsigned int sbr, brfa;
1670 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1671 old_cr2 = readb(sport->port.membase + UARTCR2);
1672 cr3 = readb(sport->port.membase + UARTCR3);
1673 cr4 = readb(sport->port.membase + UARTCR4);
1674 bdh = readb(sport->port.membase + UARTBDH);
1675 modem = readb(sport->port.membase + UARTMODEM);
1677 * only support CS8 and CS7, and for CS7 must enable PE.
1684 while ((termios->c_cflag & CSIZE) != CS8 &&
1685 (termios->c_cflag & CSIZE) != CS7) {
1686 termios->c_cflag &= ~CSIZE;
1687 termios->c_cflag |= old_csize;
1691 if ((termios->c_cflag & CSIZE) == CS8 ||
1692 (termios->c_cflag & CSIZE) == CS7)
1693 cr1 = old_cr1 & ~UARTCR1_M;
1695 if (termios->c_cflag & CMSPAR) {
1696 if ((termios->c_cflag & CSIZE) != CS8) {
1697 termios->c_cflag &= ~CSIZE;
1698 termios->c_cflag |= CS8;
1704 * When auto RS-485 RTS mode is enabled,
1705 * hardware flow control need to be disabled.
1707 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1708 termios->c_cflag &= ~CRTSCTS;
1710 if (termios->c_cflag & CRTSCTS)
1711 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1713 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1715 termios->c_cflag &= ~CSTOPB;
1717 /* parity must be enabled when CS7 to match 8-bits format */
1718 if ((termios->c_cflag & CSIZE) == CS7)
1719 termios->c_cflag |= PARENB;
1721 if (termios->c_cflag & PARENB) {
1722 if (termios->c_cflag & CMSPAR) {
1724 if (termios->c_cflag & PARODD)
1730 if ((termios->c_cflag & CSIZE) == CS8)
1732 if (termios->c_cflag & PARODD)
1741 /* ask the core to calculate the divisor */
1742 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1745 * Need to update the Ring buffer length according to the selected
1746 * baud rate and restart Rx DMA path.
1748 * Since timer function acqures sport->port.lock, need to stop before
1749 * acquring same lock because otherwise del_timer_sync() can deadlock.
1751 if (old && sport->lpuart_dma_rx_use) {
1752 del_timer_sync(&sport->lpuart_timer);
1753 lpuart_dma_rx_free(&sport->port);
1756 spin_lock_irqsave(&sport->port.lock, flags);
1758 sport->port.read_status_mask = 0;
1759 if (termios->c_iflag & INPCK)
1760 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1761 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1762 sport->port.read_status_mask |= UARTSR1_FE;
1764 /* characters to ignore */
1765 sport->port.ignore_status_mask = 0;
1766 if (termios->c_iflag & IGNPAR)
1767 sport->port.ignore_status_mask |= UARTSR1_PE;
1768 if (termios->c_iflag & IGNBRK) {
1769 sport->port.ignore_status_mask |= UARTSR1_FE;
1771 * if we're ignoring parity and break indicators,
1772 * ignore overruns too (for real raw support).
1774 if (termios->c_iflag & IGNPAR)
1775 sport->port.ignore_status_mask |= UARTSR1_OR;
1778 /* update the per-port timeout */
1779 uart_update_timeout(port, termios->c_cflag, baud);
1781 /* wait transmit engin complete */
1782 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
1784 /* disable transmit and receive */
1785 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
1786 sport->port.membase + UARTCR2);
1788 sbr = sport->port.uartclk / (16 * baud);
1789 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
1790 bdh &= ~UARTBDH_SBR_MASK;
1791 bdh |= (sbr >> 8) & 0x1F;
1792 cr4 &= ~UARTCR4_BRFA_MASK;
1793 brfa &= UARTCR4_BRFA_MASK;
1794 writeb(cr4 | brfa, sport->port.membase + UARTCR4);
1795 writeb(bdh, sport->port.membase + UARTBDH);
1796 writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
1797 writeb(cr3, sport->port.membase + UARTCR3);
1798 writeb(cr1, sport->port.membase + UARTCR1);
1799 writeb(modem, sport->port.membase + UARTMODEM);
1801 /* restore control register */
1802 writeb(old_cr2, sport->port.membase + UARTCR2);
1804 if (old && sport->lpuart_dma_rx_use) {
1805 if (!lpuart_start_rx_dma(sport))
1806 rx_dma_timer_init(sport);
1808 sport->lpuart_dma_rx_use = false;
1811 spin_unlock_irqrestore(&sport->port.lock, flags);
1815 lpuart32_serial_setbrg(struct lpuart_port *sport, unsigned int baudrate)
1817 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
1818 u32 clk = sport->port.uartclk;
1821 * The idea is to use the best OSR (over-sampling rate) possible.
1822 * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
1823 * Loop to find the best OSR value possible, one that generates minimum
1824 * baud_diff iterate through the rest of the supported values of OSR.
1826 * Calculation Formula:
1827 * Baud Rate = baud clock / ((OSR+1) × SBR)
1829 baud_diff = baudrate;
1833 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
1834 /* calculate the temporary sbr value */
1835 tmp_sbr = (clk / (baudrate * tmp_osr));
1840 * calculate the baud rate difference based on the temporary
1841 * osr and sbr values
1843 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
1845 /* select best values between sbr and sbr+1 */
1846 tmp = clk / (tmp_osr * (tmp_sbr + 1));
1847 if (tmp_diff > (baudrate - tmp)) {
1848 tmp_diff = baudrate - tmp;
1852 if (tmp_diff <= baud_diff) {
1853 baud_diff = tmp_diff;
1862 /* handle buadrate outside acceptable rate */
1863 if (baud_diff > ((baudrate / 100) * 3))
1864 dev_warn(sport->port.dev,
1865 "unacceptable baud rate difference of more than 3%%\n");
1867 tmp = lpuart32_read(&sport->port, UARTBAUD);
1869 if ((osr > 3) && (osr < 8))
1870 tmp |= UARTBAUD_BOTHEDGE;
1872 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
1873 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
1875 tmp &= ~UARTBAUD_SBR_MASK;
1876 tmp |= sbr & UARTBAUD_SBR_MASK;
1878 if (!sport->lpuart_dma_rx_use)
1879 tmp &= ~UARTBAUD_RDMAE;
1880 if (!sport->lpuart_dma_tx_use)
1881 tmp &= ~UARTBAUD_TDMAE;
1883 lpuart32_write(&sport->port, tmp, UARTBAUD);
1887 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
1888 struct ktermios *old)
1890 struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1891 unsigned long flags;
1892 unsigned long ctrl, old_ctrl, modem;
1894 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1896 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
1897 modem = lpuart32_read(&sport->port, UARTMODIR);
1899 * only support CS8 and CS7, and for CS7 must enable PE.
1906 while ((termios->c_cflag & CSIZE) != CS8 &&
1907 (termios->c_cflag & CSIZE) != CS7) {
1908 termios->c_cflag &= ~CSIZE;
1909 termios->c_cflag |= old_csize;
1913 if ((termios->c_cflag & CSIZE) == CS8 ||
1914 (termios->c_cflag & CSIZE) == CS7)
1915 ctrl = old_ctrl & ~UARTCTRL_M;
1917 if (termios->c_cflag & CMSPAR) {
1918 if ((termios->c_cflag & CSIZE) != CS8) {
1919 termios->c_cflag &= ~CSIZE;
1920 termios->c_cflag |= CS8;
1926 * When auto RS-485 RTS mode is enabled,
1927 * hardware flow control need to be disabled.
1929 if (sport->port.rs485.flags & SER_RS485_ENABLED)
1930 termios->c_cflag &= ~CRTSCTS;
1932 if (termios->c_cflag & CRTSCTS) {
1933 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1935 termios->c_cflag &= ~CRTSCTS;
1936 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
1939 if (termios->c_cflag & CSTOPB)
1940 termios->c_cflag &= ~CSTOPB;
1942 /* parity must be enabled when CS7 to match 8-bits format */
1943 if ((termios->c_cflag & CSIZE) == CS7)
1944 termios->c_cflag |= PARENB;
1946 if ((termios->c_cflag & PARENB)) {
1947 if (termios->c_cflag & CMSPAR) {
1948 ctrl &= ~UARTCTRL_PE;
1951 ctrl |= UARTCTRL_PE;
1952 if ((termios->c_cflag & CSIZE) == CS8)
1954 if (termios->c_cflag & PARODD)
1955 ctrl |= UARTCTRL_PT;
1957 ctrl &= ~UARTCTRL_PT;
1960 ctrl &= ~UARTCTRL_PE;
1963 /* ask the core to calculate the divisor */
1964 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
1967 * Need to update the Ring buffer length according to the selected
1968 * baud rate and restart Rx DMA path.
1970 * Since timer function acqures sport->port.lock, need to stop before
1971 * acquring same lock because otherwise del_timer_sync() can deadlock.
1973 if (old && sport->lpuart_dma_rx_use) {
1974 del_timer_sync(&sport->lpuart_timer);
1975 lpuart_dma_rx_free(&sport->port);
1978 spin_lock_irqsave(&sport->port.lock, flags);
1980 sport->port.read_status_mask = 0;
1981 if (termios->c_iflag & INPCK)
1982 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
1983 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1984 sport->port.read_status_mask |= UARTSTAT_FE;
1986 /* characters to ignore */
1987 sport->port.ignore_status_mask = 0;
1988 if (termios->c_iflag & IGNPAR)
1989 sport->port.ignore_status_mask |= UARTSTAT_PE;
1990 if (termios->c_iflag & IGNBRK) {
1991 sport->port.ignore_status_mask |= UARTSTAT_FE;
1993 * if we're ignoring parity and break indicators,
1994 * ignore overruns too (for real raw support).
1996 if (termios->c_iflag & IGNPAR)
1997 sport->port.ignore_status_mask |= UARTSTAT_OR;
2000 /* update the per-port timeout */
2001 uart_update_timeout(port, termios->c_cflag, baud);
2003 /* wait transmit engin complete */
2004 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2006 /* disable transmit and receive */
2007 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2010 lpuart32_serial_setbrg(sport, baud);
2011 lpuart32_write(&sport->port, modem, UARTMODIR);
2012 lpuart32_write(&sport->port, ctrl, UARTCTRL);
2013 /* restore control register */
2015 if (old && sport->lpuart_dma_rx_use) {
2016 if (!lpuart_start_rx_dma(sport))
2017 rx_dma_timer_init(sport);
2019 sport->lpuart_dma_rx_use = false;
2022 spin_unlock_irqrestore(&sport->port.lock, flags);
2025 static const char *lpuart_type(struct uart_port *port)
2027 return "FSL_LPUART";
2030 static void lpuart_release_port(struct uart_port *port)
2035 static int lpuart_request_port(struct uart_port *port)
2040 /* configure/autoconfigure the port */
2041 static void lpuart_config_port(struct uart_port *port, int flags)
2043 if (flags & UART_CONFIG_TYPE)
2044 port->type = PORT_LPUART;
2047 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2051 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2053 if (port->irq != ser->irq)
2055 if (ser->io_type != UPIO_MEM)
2057 if (port->uartclk / 16 != ser->baud_base)
2059 if (port->iobase != ser->port)
2066 static const struct uart_ops lpuart_pops = {
2067 .tx_empty = lpuart_tx_empty,
2068 .set_mctrl = lpuart_set_mctrl,
2069 .get_mctrl = lpuart_get_mctrl,
2070 .stop_tx = lpuart_stop_tx,
2071 .start_tx = lpuart_start_tx,
2072 .stop_rx = lpuart_stop_rx,
2073 .break_ctl = lpuart_break_ctl,
2074 .startup = lpuart_startup,
2075 .shutdown = lpuart_shutdown,
2076 .set_termios = lpuart_set_termios,
2077 .type = lpuart_type,
2078 .request_port = lpuart_request_port,
2079 .release_port = lpuart_release_port,
2080 .config_port = lpuart_config_port,
2081 .verify_port = lpuart_verify_port,
2082 .flush_buffer = lpuart_flush_buffer,
2083 #if defined(CONFIG_CONSOLE_POLL)
2084 .poll_init = lpuart_poll_init,
2085 .poll_get_char = lpuart_poll_get_char,
2086 .poll_put_char = lpuart_poll_put_char,
2090 static const struct uart_ops lpuart32_pops = {
2091 .tx_empty = lpuart32_tx_empty,
2092 .set_mctrl = lpuart32_set_mctrl,
2093 .get_mctrl = lpuart32_get_mctrl,
2094 .stop_tx = lpuart32_stop_tx,
2095 .start_tx = lpuart32_start_tx,
2096 .stop_rx = lpuart32_stop_rx,
2097 .break_ctl = lpuart32_break_ctl,
2098 .startup = lpuart32_startup,
2099 .shutdown = lpuart32_shutdown,
2100 .set_termios = lpuart32_set_termios,
2101 .type = lpuart_type,
2102 .request_port = lpuart_request_port,
2103 .release_port = lpuart_release_port,
2104 .config_port = lpuart_config_port,
2105 .verify_port = lpuart_verify_port,
2106 .flush_buffer = lpuart_flush_buffer,
2107 #if defined(CONFIG_CONSOLE_POLL)
2108 .poll_init = lpuart32_poll_init,
2109 .poll_get_char = lpuart32_poll_get_char,
2110 .poll_put_char = lpuart32_poll_put_char,
2114 static struct lpuart_port *lpuart_ports[UART_NR];
2116 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2117 static void lpuart_console_putchar(struct uart_port *port, int ch)
2119 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2120 writeb(ch, port->membase + UARTDR);
2123 static void lpuart32_console_putchar(struct uart_port *port, int ch)
2125 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2126 lpuart32_write(port, ch, UARTDATA);
2130 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2132 struct lpuart_port *sport = lpuart_ports[co->index];
2133 unsigned char old_cr2, cr2;
2134 unsigned long flags;
2137 if (sport->port.sysrq || oops_in_progress)
2138 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2140 spin_lock_irqsave(&sport->port.lock, flags);
2142 /* first save CR2 and then disable interrupts */
2143 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2144 cr2 |= UARTCR2_TE | UARTCR2_RE;
2145 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2146 writeb(cr2, sport->port.membase + UARTCR2);
2148 uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2150 /* wait for transmitter finish complete and restore CR2 */
2151 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2153 writeb(old_cr2, sport->port.membase + UARTCR2);
2156 spin_unlock_irqrestore(&sport->port.lock, flags);
2160 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2162 struct lpuart_port *sport = lpuart_ports[co->index];
2163 unsigned long old_cr, cr;
2164 unsigned long flags;
2167 if (sport->port.sysrq || oops_in_progress)
2168 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2170 spin_lock_irqsave(&sport->port.lock, flags);
2172 /* first save CR2 and then disable interrupts */
2173 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2174 cr |= UARTCTRL_TE | UARTCTRL_RE;
2175 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2176 lpuart32_write(&sport->port, cr, UARTCTRL);
2178 uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2180 /* wait for transmitter finish complete and restore CR2 */
2181 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2183 lpuart32_write(&sport->port, old_cr, UARTCTRL);
2186 spin_unlock_irqrestore(&sport->port.lock, flags);
2190 * if the port was already initialised (eg, by a boot loader),
2191 * try to determine the current setup.
2194 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2195 int *parity, int *bits)
2197 unsigned char cr, bdh, bdl, brfa;
2198 unsigned int sbr, uartclk, baud_raw;
2200 cr = readb(sport->port.membase + UARTCR2);
2201 cr &= UARTCR2_TE | UARTCR2_RE;
2205 /* ok, the port was enabled */
2207 cr = readb(sport->port.membase + UARTCR1);
2210 if (cr & UARTCR1_PE) {
2211 if (cr & UARTCR1_PT)
2222 bdh = readb(sport->port.membase + UARTBDH);
2223 bdh &= UARTBDH_SBR_MASK;
2224 bdl = readb(sport->port.membase + UARTBDL);
2228 brfa = readb(sport->port.membase + UARTCR4);
2229 brfa &= UARTCR4_BRFA_MASK;
2231 uartclk = lpuart_get_baud_clk_rate(sport);
2233 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2235 baud_raw = uartclk / (16 * (sbr + brfa / 32));
2237 if (*baud != baud_raw)
2238 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2239 "from %d to %d\n", baud_raw, *baud);
2243 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2244 int *parity, int *bits)
2246 unsigned long cr, bd;
2247 unsigned int sbr, uartclk, baud_raw;
2249 cr = lpuart32_read(&sport->port, UARTCTRL);
2250 cr &= UARTCTRL_TE | UARTCTRL_RE;
2254 /* ok, the port was enabled */
2256 cr = lpuart32_read(&sport->port, UARTCTRL);
2259 if (cr & UARTCTRL_PE) {
2260 if (cr & UARTCTRL_PT)
2266 if (cr & UARTCTRL_M)
2271 bd = lpuart32_read(&sport->port, UARTBAUD);
2272 bd &= UARTBAUD_SBR_MASK;
2274 uartclk = lpuart_get_baud_clk_rate(sport);
2276 * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2278 baud_raw = uartclk / (16 * sbr);
2280 if (*baud != baud_raw)
2281 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2282 "from %d to %d\n", baud_raw, *baud);
2285 static int __init lpuart_console_setup(struct console *co, char *options)
2287 struct lpuart_port *sport;
2294 * check whether an invalid uart number has been specified, and
2295 * if so, search for the first available port that does have
2298 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2301 sport = lpuart_ports[co->index];
2306 uart_parse_options(options, &baud, &parity, &bits, &flow);
2308 if (lpuart_is_32(sport))
2309 lpuart32_console_get_options(sport, &baud, &parity, &bits);
2311 lpuart_console_get_options(sport, &baud, &parity, &bits);
2313 if (lpuart_is_32(sport))
2314 lpuart32_setup_watermark(sport);
2316 lpuart_setup_watermark(sport);
2318 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2321 static struct uart_driver lpuart_reg;
2322 static struct console lpuart_console = {
2324 .write = lpuart_console_write,
2325 .device = uart_console_device,
2326 .setup = lpuart_console_setup,
2327 .flags = CON_PRINTBUFFER,
2329 .data = &lpuart_reg,
2332 static struct console lpuart32_console = {
2334 .write = lpuart32_console_write,
2335 .device = uart_console_device,
2336 .setup = lpuart_console_setup,
2337 .flags = CON_PRINTBUFFER,
2339 .data = &lpuart_reg,
2342 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2344 struct earlycon_device *dev = con->data;
2346 uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2349 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2351 struct earlycon_device *dev = con->data;
2353 uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2356 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2359 if (!device->port.membase)
2362 device->con->write = lpuart_early_write;
2366 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2369 if (!device->port.membase)
2372 if (device->port.iotype != UPIO_MEM32)
2373 device->port.iotype = UPIO_MEM32BE;
2375 device->con->write = lpuart32_early_write;
2379 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2382 if (!device->port.membase)
2385 device->port.iotype = UPIO_MEM32;
2386 device->port.membase += IMX_REG_OFF;
2387 device->con->write = lpuart32_early_write;
2391 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2392 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2393 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2394 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2395 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2397 #define LPUART_CONSOLE (&lpuart_console)
2398 #define LPUART32_CONSOLE (&lpuart32_console)
2400 #define LPUART_CONSOLE NULL
2401 #define LPUART32_CONSOLE NULL
2404 static struct uart_driver lpuart_reg = {
2405 .owner = THIS_MODULE,
2406 .driver_name = DRIVER_NAME,
2407 .dev_name = DEV_NAME,
2408 .nr = ARRAY_SIZE(lpuart_ports),
2409 .cons = LPUART_CONSOLE,
2412 static int lpuart_probe(struct platform_device *pdev)
2414 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids,
2416 const struct lpuart_soc_data *sdata = of_id->data;
2417 struct device_node *np = pdev->dev.of_node;
2418 struct lpuart_port *sport;
2419 struct resource *res;
2422 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2426 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2427 sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2428 if (IS_ERR(sport->port.membase))
2429 return PTR_ERR(sport->port.membase);
2431 sport->port.membase += sdata->reg_off;
2432 sport->port.mapbase = res->start;
2433 sport->port.dev = &pdev->dev;
2434 sport->port.type = PORT_LPUART;
2435 sport->devtype = sdata->devtype;
2436 ret = platform_get_irq(pdev, 0);
2439 sport->port.irq = ret;
2440 sport->port.iotype = sdata->iotype;
2441 if (lpuart_is_32(sport))
2442 sport->port.ops = &lpuart32_pops;
2444 sport->port.ops = &lpuart_pops;
2445 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2446 sport->port.flags = UPF_BOOT_AUTOCONF;
2448 if (lpuart_is_32(sport))
2449 sport->port.rs485_config = lpuart32_config_rs485;
2451 sport->port.rs485_config = lpuart_config_rs485;
2453 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2454 if (IS_ERR(sport->ipg_clk)) {
2455 ret = PTR_ERR(sport->ipg_clk);
2456 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2460 sport->baud_clk = NULL;
2461 if (is_imx8qxp_lpuart(sport)) {
2462 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2463 if (IS_ERR(sport->baud_clk)) {
2464 ret = PTR_ERR(sport->baud_clk);
2465 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2470 ret = of_alias_get_id(np, "serial");
2472 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL);
2474 dev_err(&pdev->dev, "port line is full, add device failed\n");
2477 sport->id_allocated = true;
2479 if (ret >= ARRAY_SIZE(lpuart_ports)) {
2480 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2482 goto failed_out_of_range;
2484 sport->port.line = ret;
2486 ret = lpuart_enable_clks(sport);
2488 goto failed_clock_enable;
2489 sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2491 lpuart_ports[sport->port.line] = sport;
2493 platform_set_drvdata(pdev, &sport->port);
2495 if (lpuart_is_32(sport)) {
2496 lpuart_reg.cons = LPUART32_CONSOLE;
2497 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0,
2498 DRIVER_NAME, sport);
2500 lpuart_reg.cons = LPUART_CONSOLE;
2501 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0,
2502 DRIVER_NAME, sport);
2506 goto failed_irq_request;
2508 ret = uart_add_one_port(&lpuart_reg, &sport->port);
2510 goto failed_attach_port;
2512 uart_get_rs485_mode(&pdev->dev, &sport->port.rs485);
2514 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX)
2515 dev_err(&pdev->dev, "driver doesn't support RX during TX\n");
2517 if (sport->port.rs485.delay_rts_before_send ||
2518 sport->port.rs485.delay_rts_after_send)
2519 dev_err(&pdev->dev, "driver doesn't support RTS delays\n");
2521 sport->port.rs485_config(&sport->port, &sport->port.rs485);
2523 sport->dma_tx_chan = dma_request_slave_channel(sport->port.dev, "tx");
2524 if (!sport->dma_tx_chan)
2525 dev_info(sport->port.dev, "DMA tx channel request failed, "
2526 "operating without tx DMA\n");
2528 sport->dma_rx_chan = dma_request_slave_channel(sport->port.dev, "rx");
2529 if (!sport->dma_rx_chan)
2530 dev_info(sport->port.dev, "DMA rx channel request failed, "
2531 "operating without rx DMA\n");
2537 lpuart_disable_clks(sport);
2538 failed_clock_enable:
2539 failed_out_of_range:
2540 if (sport->id_allocated)
2541 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2545 static int lpuart_remove(struct platform_device *pdev)
2547 struct lpuart_port *sport = platform_get_drvdata(pdev);
2549 uart_remove_one_port(&lpuart_reg, &sport->port);
2551 if (sport->id_allocated)
2552 ida_simple_remove(&fsl_lpuart_ida, sport->port.line);
2554 lpuart_disable_clks(sport);
2556 if (sport->dma_tx_chan)
2557 dma_release_channel(sport->dma_tx_chan);
2559 if (sport->dma_rx_chan)
2560 dma_release_channel(sport->dma_rx_chan);
2565 #ifdef CONFIG_PM_SLEEP
2566 static int lpuart_suspend(struct device *dev)
2568 struct lpuart_port *sport = dev_get_drvdata(dev);
2572 if (lpuart_is_32(sport)) {
2573 /* disable Rx/Tx and interrupts */
2574 temp = lpuart32_read(&sport->port, UARTCTRL);
2575 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
2576 lpuart32_write(&sport->port, temp, UARTCTRL);
2578 /* disable Rx/Tx and interrupts */
2579 temp = readb(sport->port.membase + UARTCR2);
2580 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
2581 writeb(temp, sport->port.membase + UARTCR2);
2584 uart_suspend_port(&lpuart_reg, &sport->port);
2586 /* uart_suspend_port() might set wakeup flag */
2587 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2589 if (sport->lpuart_dma_rx_use) {
2591 * EDMA driver during suspend will forcefully release any
2592 * non-idle DMA channels. If port wakeup is enabled or if port
2593 * is console port or 'no_console_suspend' is set the Rx DMA
2594 * cannot resume as as expected, hence gracefully release the
2595 * Rx DMA path before suspend and start Rx DMA path on resume.
2598 del_timer_sync(&sport->lpuart_timer);
2599 lpuart_dma_rx_free(&sport->port);
2602 /* Disable Rx DMA to use UART port as wakeup source */
2603 if (lpuart_is_32(sport)) {
2604 temp = lpuart32_read(&sport->port, UARTBAUD);
2605 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
2608 writeb(readb(sport->port.membase + UARTCR5) &
2609 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
2613 if (sport->lpuart_dma_tx_use) {
2614 sport->dma_tx_in_progress = false;
2615 dmaengine_terminate_all(sport->dma_tx_chan);
2618 if (sport->port.suspended && !irq_wake)
2619 lpuart_disable_clks(sport);
2624 static int lpuart_resume(struct device *dev)
2626 struct lpuart_port *sport = dev_get_drvdata(dev);
2627 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2629 if (sport->port.suspended && !irq_wake)
2630 lpuart_enable_clks(sport);
2632 if (lpuart_is_32(sport))
2633 lpuart32_setup_watermark_enable(sport);
2635 lpuart_setup_watermark_enable(sport);
2637 if (sport->lpuart_dma_rx_use) {
2639 if (!lpuart_start_rx_dma(sport))
2640 rx_dma_timer_init(sport);
2642 sport->lpuart_dma_rx_use = false;
2646 lpuart_tx_dma_startup(sport);
2648 if (lpuart_is_32(sport))
2649 lpuart32_configure(sport);
2651 uart_resume_port(&lpuart_reg, &sport->port);
2657 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume);
2659 static struct platform_driver lpuart_driver = {
2660 .probe = lpuart_probe,
2661 .remove = lpuart_remove,
2663 .name = "fsl-lpuart",
2664 .of_match_table = lpuart_dt_ids,
2665 .pm = &lpuart_pm_ops,
2669 static int __init lpuart_serial_init(void)
2671 int ret = uart_register_driver(&lpuart_reg);
2676 ret = platform_driver_register(&lpuart_driver);
2678 uart_unregister_driver(&lpuart_reg);
2683 static void __exit lpuart_serial_exit(void)
2685 ida_destroy(&fsl_lpuart_ida);
2686 platform_driver_unregister(&lpuart_driver);
2687 uart_unregister_driver(&lpuart_reg);
2690 module_init(lpuart_serial_init);
2691 module_exit(lpuart_serial_exit);
2693 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
2694 MODULE_LICENSE("GPL v2");