2 * Driver for Motorola/Freescale IMX serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/platform_device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/clk.h>
35 #include <linux/delay.h>
36 #include <linux/rational.h>
37 #include <linux/slab.h>
39 #include <linux/of_device.h>
41 #include <linux/dma-mapping.h>
44 #include <linux/platform_data/serial-imx.h>
45 #include <linux/platform_data/dma-imx.h>
47 #include "serial_mctrl_gpio.h"
49 /* Register definitions */
50 #define URXD0 0x0 /* Receiver Register */
51 #define URTX0 0x40 /* Transmitter Register */
52 #define UCR1 0x80 /* Control Register 1 */
53 #define UCR2 0x84 /* Control Register 2 */
54 #define UCR3 0x88 /* Control Register 3 */
55 #define UCR4 0x8c /* Control Register 4 */
56 #define UFCR 0x90 /* FIFO Control Register */
57 #define USR1 0x94 /* Status Register 1 */
58 #define USR2 0x98 /* Status Register 2 */
59 #define UESC 0x9c /* Escape Character Register */
60 #define UTIM 0xa0 /* Escape Timer Register */
61 #define UBIR 0xa4 /* BRM Incremental Register */
62 #define UBMR 0xa8 /* BRM Modulator Register */
63 #define UBRC 0xac /* Baud Rate Count Register */
64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
68 /* UART Control Register Bit Fields.*/
69 #define URXD_DUMMY_READ (1<<16)
70 #define URXD_CHARRDY (1<<15)
71 #define URXD_ERR (1<<14)
72 #define URXD_OVRRUN (1<<13)
73 #define URXD_FRMERR (1<<12)
74 #define URXD_BRK (1<<11)
75 #define URXD_PRERR (1<<10)
76 #define URXD_RX_DATA (0xFF<<0)
77 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
78 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
79 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
80 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
82 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
83 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
84 #define UCR1_IREN (1<<7) /* Infrared interface enable */
85 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
86 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
87 #define UCR1_SNDBRK (1<<4) /* Send break */
88 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
90 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
91 #define UCR1_DOZE (1<<1) /* Doze */
92 #define UCR1_UARTEN (1<<0) /* UART enabled */
93 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
94 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
95 #define UCR2_CTSC (1<<13) /* CTS pin control */
96 #define UCR2_CTS (1<<12) /* Clear to send */
97 #define UCR2_ESCEN (1<<11) /* Escape enable */
98 #define UCR2_PREN (1<<8) /* Parity enable */
99 #define UCR2_PROE (1<<7) /* Parity odd/even */
100 #define UCR2_STPB (1<<6) /* Stop */
101 #define UCR2_WS (1<<5) /* Word size */
102 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
103 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
104 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
105 #define UCR2_RXEN (1<<1) /* Receiver enabled */
106 #define UCR2_SRST (1<<0) /* SW reset */
107 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
108 #define UCR3_PARERREN (1<<12) /* Parity enable */
109 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
110 #define UCR3_DSR (1<<10) /* Data set ready */
111 #define UCR3_DCD (1<<9) /* Data carrier detect */
112 #define UCR3_RI (1<<8) /* Ring indicator */
113 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
114 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
115 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
116 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
117 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
118 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
119 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
120 #define UCR3_BPEN (1<<0) /* Preset registers enable */
121 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
122 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
123 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
124 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
125 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
126 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
127 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
128 #define UCR4_IRSC (1<<5) /* IR special case */
129 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
130 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
131 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
132 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
133 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
134 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
135 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
136 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
137 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
138 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
139 #define USR1_RTSS (1<<14) /* RTS pin status */
140 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
141 #define USR1_RTSD (1<<12) /* RTS delta */
142 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
143 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
144 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
145 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
146 #define USR1_DTRD (1<<7) /* DTR Delta */
147 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
148 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
149 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
150 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
151 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
152 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
153 #define USR2_IDLE (1<<12) /* Idle condition */
154 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
155 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
156 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
157 #define USR2_WAKE (1<<7) /* Wake */
158 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
159 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
160 #define USR2_TXDC (1<<3) /* Transmitter complete */
161 #define USR2_BRCD (1<<2) /* Break condition */
162 #define USR2_ORE (1<<1) /* Overrun error */
163 #define USR2_RDR (1<<0) /* Recv data ready */
164 #define UTS_FRCPERR (1<<13) /* Force parity error */
165 #define UTS_LOOP (1<<12) /* Loop tx and rx */
166 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
167 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
168 #define UTS_TXFULL (1<<4) /* TxFIFO full */
169 #define UTS_RXFULL (1<<3) /* RxFIFO full */
170 #define UTS_SOFTRST (1<<0) /* Software reset */
172 /* We've been assigned a range on the "Low-density serial ports" major */
173 #define SERIAL_IMX_MAJOR 207
174 #define MINOR_START 16
175 #define DEV_NAME "ttymxc"
178 * This determines how often we check the modem status signals
179 * for any change. They generally aren't connected to an IRQ
180 * so we have to poll them. We also check immediately before
181 * filling the TX fifo incase CTS has been dropped.
183 #define MCTRL_TIMEOUT (250*HZ/1000)
185 #define DRIVER_NAME "IMX-uart"
189 /* RX DMA buffer periods */
190 #define RX_DMA_PERIODS 4
191 #define RX_BUF_SIZE (PAGE_SIZE)
194 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
202 /* device type dependent stuff */
203 struct imx_uart_data {
205 enum imx_uart_type devtype;
209 struct uart_port port;
210 struct timer_list timer;
211 unsigned int old_status;
212 unsigned int have_rtscts:1;
213 unsigned int have_rtsgpio:1;
214 unsigned int dte_mode:1;
217 const struct imx_uart_data *devdata;
219 struct mctrl_gpios *gpios;
222 unsigned int dma_is_inited:1;
223 unsigned int dma_is_enabled:1;
224 unsigned int dma_is_rxing:1;
225 unsigned int dma_is_txing:1;
226 struct dma_chan *dma_chan_rx, *dma_chan_tx;
227 struct scatterlist rx_sgl, tx_sgl[2];
229 unsigned int rx_buf_size;
230 struct circ_buf rx_ring;
231 unsigned int rx_periods;
232 dma_cookie_t rx_cookie;
233 unsigned int tx_bytes;
234 unsigned int dma_tx_nents;
235 wait_queue_head_t dma_wait;
236 unsigned int saved_reg[10];
240 struct imx_port_ucrs {
246 static struct imx_uart_data imx_uart_devdata[] = {
249 .devtype = IMX1_UART,
252 .uts_reg = IMX21_UTS,
253 .devtype = IMX21_UART,
256 .uts_reg = IMX21_UTS,
257 .devtype = IMX53_UART,
260 .uts_reg = IMX21_UTS,
261 .devtype = IMX6Q_UART,
265 static const struct platform_device_id imx_uart_devtype[] = {
268 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
270 .name = "imx21-uart",
271 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
273 .name = "imx53-uart",
274 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
276 .name = "imx6q-uart",
277 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
282 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
284 static const struct of_device_id imx_uart_dt_ids[] = {
285 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
286 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
287 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
288 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
291 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
293 static inline unsigned uts_reg(struct imx_port *sport)
295 return sport->devdata->uts_reg;
298 static inline int is_imx1_uart(struct imx_port *sport)
300 return sport->devdata->devtype == IMX1_UART;
303 static inline int is_imx21_uart(struct imx_port *sport)
305 return sport->devdata->devtype == IMX21_UART;
308 static inline int is_imx53_uart(struct imx_port *sport)
310 return sport->devdata->devtype == IMX53_UART;
313 static inline int is_imx6q_uart(struct imx_port *sport)
315 return sport->devdata->devtype == IMX6Q_UART;
318 * Save and restore functions for UCR1, UCR2 and UCR3 registers
320 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
321 static void imx_port_ucrs_save(struct uart_port *port,
322 struct imx_port_ucrs *ucr)
324 /* save control registers */
325 ucr->ucr1 = readl(port->membase + UCR1);
326 ucr->ucr2 = readl(port->membase + UCR2);
327 ucr->ucr3 = readl(port->membase + UCR3);
330 static void imx_port_ucrs_restore(struct uart_port *port,
331 struct imx_port_ucrs *ucr)
333 /* restore control registers */
334 writel(ucr->ucr1, port->membase + UCR1);
335 writel(ucr->ucr2, port->membase + UCR2);
336 writel(ucr->ucr3, port->membase + UCR3);
340 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
342 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
344 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
347 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
352 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
355 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
361 * interrupts disabled on entry
363 static void imx_stop_tx(struct uart_port *port)
365 struct imx_port *sport = (struct imx_port *)port;
369 * We are maybe in the SMP context, so if the DMA TX thread is running
370 * on other cpu, we have to wait for it to finish.
372 if (sport->dma_is_enabled && sport->dma_is_txing)
375 temp = readl(port->membase + UCR1);
376 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
378 /* in rs485 mode disable transmitter if shifter is empty */
379 if (port->rs485.flags & SER_RS485_ENABLED &&
380 readl(port->membase + USR2) & USR2_TXDC) {
381 temp = readl(port->membase + UCR2);
382 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
383 imx_port_rts_active(sport, &temp);
385 imx_port_rts_inactive(sport, &temp);
387 writel(temp, port->membase + UCR2);
389 temp = readl(port->membase + UCR4);
391 writel(temp, port->membase + UCR4);
396 * interrupts disabled on entry
398 static void imx_stop_rx(struct uart_port *port)
400 struct imx_port *sport = (struct imx_port *)port;
403 if (sport->dma_is_enabled && sport->dma_is_rxing) {
404 if (sport->port.suspended) {
405 dmaengine_terminate_all(sport->dma_chan_rx);
406 sport->dma_is_rxing = 0;
412 temp = readl(sport->port.membase + UCR2);
413 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
415 /* disable the `Receiver Ready Interrrupt` */
416 temp = readl(sport->port.membase + UCR1);
417 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
421 * Set the modem control timer to fire immediately.
423 static void imx_enable_ms(struct uart_port *port)
425 struct imx_port *sport = (struct imx_port *)port;
427 mod_timer(&sport->timer, jiffies);
429 mctrl_gpio_enable_ms(sport->gpios);
432 static void imx_dma_tx(struct imx_port *sport);
433 static inline void imx_transmit_buffer(struct imx_port *sport)
435 struct circ_buf *xmit = &sport->port.state->xmit;
438 if (sport->port.x_char) {
440 writel(sport->port.x_char, sport->port.membase + URTX0);
441 sport->port.icount.tx++;
442 sport->port.x_char = 0;
446 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
447 imx_stop_tx(&sport->port);
451 if (sport->dma_is_enabled) {
453 * We've just sent a X-char Ensure the TX DMA is enabled
454 * and the TX IRQ is disabled.
456 temp = readl(sport->port.membase + UCR1);
457 temp &= ~UCR1_TXMPTYEN;
458 if (sport->dma_is_txing) {
460 writel(temp, sport->port.membase + UCR1);
462 writel(temp, sport->port.membase + UCR1);
467 while (!uart_circ_empty(xmit) &&
468 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
469 /* send xmit->buf[xmit->tail]
470 * out the port here */
471 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
472 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
473 sport->port.icount.tx++;
476 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
477 uart_write_wakeup(&sport->port);
479 if (uart_circ_empty(xmit))
480 imx_stop_tx(&sport->port);
483 static void dma_tx_callback(void *data)
485 struct imx_port *sport = data;
486 struct scatterlist *sgl = &sport->tx_sgl[0];
487 struct circ_buf *xmit = &sport->port.state->xmit;
491 spin_lock_irqsave(&sport->port.lock, flags);
493 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
495 temp = readl(sport->port.membase + UCR1);
496 temp &= ~UCR1_TDMAEN;
497 writel(temp, sport->port.membase + UCR1);
499 /* update the stat */
500 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
501 sport->port.icount.tx += sport->tx_bytes;
503 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
505 sport->dma_is_txing = 0;
507 spin_unlock_irqrestore(&sport->port.lock, flags);
509 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
510 uart_write_wakeup(&sport->port);
512 if (waitqueue_active(&sport->dma_wait)) {
513 wake_up(&sport->dma_wait);
514 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
518 spin_lock_irqsave(&sport->port.lock, flags);
519 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
521 spin_unlock_irqrestore(&sport->port.lock, flags);
524 static void imx_dma_tx(struct imx_port *sport)
526 struct circ_buf *xmit = &sport->port.state->xmit;
527 struct scatterlist *sgl = sport->tx_sgl;
528 struct dma_async_tx_descriptor *desc;
529 struct dma_chan *chan = sport->dma_chan_tx;
530 struct device *dev = sport->port.dev;
534 if (sport->dma_is_txing)
537 sport->tx_bytes = uart_circ_chars_pending(xmit);
539 if (xmit->tail < xmit->head) {
540 sport->dma_tx_nents = 1;
541 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
543 sport->dma_tx_nents = 2;
544 sg_init_table(sgl, 2);
545 sg_set_buf(sgl, xmit->buf + xmit->tail,
546 UART_XMIT_SIZE - xmit->tail);
547 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
550 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
552 dev_err(dev, "DMA mapping error for TX.\n");
555 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
556 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
558 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
560 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
563 desc->callback = dma_tx_callback;
564 desc->callback_param = sport;
566 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
567 uart_circ_chars_pending(xmit));
569 temp = readl(sport->port.membase + UCR1);
571 writel(temp, sport->port.membase + UCR1);
574 sport->dma_is_txing = 1;
575 dmaengine_submit(desc);
576 dma_async_issue_pending(chan);
581 * interrupts disabled on entry
583 static void imx_start_tx(struct uart_port *port)
585 struct imx_port *sport = (struct imx_port *)port;
588 if (port->rs485.flags & SER_RS485_ENABLED) {
589 temp = readl(port->membase + UCR2);
590 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
591 imx_port_rts_active(sport, &temp);
593 imx_port_rts_inactive(sport, &temp);
594 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
596 writel(temp, port->membase + UCR2);
598 /* enable transmitter and shifter empty irq */
599 temp = readl(port->membase + UCR4);
601 writel(temp, port->membase + UCR4);
604 if (!sport->dma_is_enabled) {
605 temp = readl(sport->port.membase + UCR1);
606 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
609 if (sport->dma_is_enabled) {
610 if (sport->port.x_char) {
611 /* We have X-char to send, so enable TX IRQ and
612 * disable TX DMA to let TX interrupt to send X-char */
613 temp = readl(sport->port.membase + UCR1);
614 temp &= ~UCR1_TDMAEN;
615 temp |= UCR1_TXMPTYEN;
616 writel(temp, sport->port.membase + UCR1);
620 if (!uart_circ_empty(&port->state->xmit) &&
621 !uart_tx_stopped(port))
627 static irqreturn_t imx_rtsint(int irq, void *dev_id)
629 struct imx_port *sport = dev_id;
633 spin_lock_irqsave(&sport->port.lock, flags);
635 writel(USR1_RTSD, sport->port.membase + USR1);
636 val = readl(sport->port.membase + USR1) & USR1_RTSS;
637 uart_handle_cts_change(&sport->port, !!val);
638 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
640 spin_unlock_irqrestore(&sport->port.lock, flags);
644 static irqreturn_t imx_txint(int irq, void *dev_id)
646 struct imx_port *sport = dev_id;
649 spin_lock_irqsave(&sport->port.lock, flags);
650 imx_transmit_buffer(sport);
651 spin_unlock_irqrestore(&sport->port.lock, flags);
655 static irqreturn_t imx_rxint(int irq, void *dev_id)
657 struct imx_port *sport = dev_id;
658 unsigned int rx, flg, ignored = 0;
659 struct tty_port *port = &sport->port.state->port;
660 unsigned long flags, temp;
662 spin_lock_irqsave(&sport->port.lock, flags);
664 while (readl(sport->port.membase + USR2) & USR2_RDR) {
666 sport->port.icount.rx++;
668 rx = readl(sport->port.membase + URXD0);
670 temp = readl(sport->port.membase + USR2);
671 if (temp & USR2_BRCD) {
672 writel(USR2_BRCD, sport->port.membase + USR2);
673 if (uart_handle_break(&sport->port))
677 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
680 if (unlikely(rx & URXD_ERR)) {
682 sport->port.icount.brk++;
683 else if (rx & URXD_PRERR)
684 sport->port.icount.parity++;
685 else if (rx & URXD_FRMERR)
686 sport->port.icount.frame++;
687 if (rx & URXD_OVRRUN)
688 sport->port.icount.overrun++;
690 if (rx & sport->port.ignore_status_mask) {
696 rx &= (sport->port.read_status_mask | 0xFF);
700 else if (rx & URXD_PRERR)
702 else if (rx & URXD_FRMERR)
704 if (rx & URXD_OVRRUN)
708 sport->port.sysrq = 0;
712 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
715 if (tty_insert_flip_char(port, rx, flg) == 0)
716 sport->port.icount.buf_overrun++;
720 spin_unlock_irqrestore(&sport->port.lock, flags);
721 tty_flip_buffer_push(port);
725 static void imx_disable_rx_int(struct imx_port *sport)
729 sport->dma_is_rxing = 1;
731 /* disable the receiver ready and aging timer interrupts */
732 temp = readl(sport->port.membase + UCR1);
733 temp &= ~(UCR1_RRDYEN);
734 writel(temp, sport->port.membase + UCR1);
736 temp = readl(sport->port.membase + UCR2);
737 temp &= ~(UCR2_ATEN);
738 writel(temp, sport->port.membase + UCR2);
740 /* disable the rx errors interrupts */
741 temp = readl(sport->port.membase + UCR4);
743 writel(temp, sport->port.membase + UCR4);
746 static void clear_rx_errors(struct imx_port *sport);
747 static int start_rx_dma(struct imx_port *sport);
749 * If the RXFIFO is filled with some data, and then we
750 * arise a DMA operation to receive them.
752 static void imx_dma_rxint(struct imx_port *sport)
757 spin_lock_irqsave(&sport->port.lock, flags);
759 temp = readl(sport->port.membase + USR2);
760 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
762 imx_disable_rx_int(sport);
764 /* tell the DMA to receive the data. */
768 spin_unlock_irqrestore(&sport->port.lock, flags);
772 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
774 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
776 unsigned int tmp = TIOCM_DSR;
777 unsigned usr1 = readl(sport->port.membase + USR1);
778 unsigned usr2 = readl(sport->port.membase + USR2);
780 if (usr1 & USR1_RTSS)
783 /* in DCE mode DCDIN is always 0 */
784 if (!(usr2 & USR2_DCDIN))
788 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
795 * Handle any change of modem status signal since we were last called.
797 static void imx_mctrl_check(struct imx_port *sport)
799 unsigned int status, changed;
801 status = imx_get_hwmctrl(sport);
802 changed = status ^ sport->old_status;
807 sport->old_status = status;
809 if (changed & TIOCM_RI && status & TIOCM_RI)
810 sport->port.icount.rng++;
811 if (changed & TIOCM_DSR)
812 sport->port.icount.dsr++;
813 if (changed & TIOCM_CAR)
814 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
815 if (changed & TIOCM_CTS)
816 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
818 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
821 static irqreturn_t imx_int(int irq, void *dev_id)
823 struct imx_port *sport = dev_id;
826 irqreturn_t ret = IRQ_NONE;
828 sts = readl(sport->port.membase + USR1);
829 sts2 = readl(sport->port.membase + USR2);
831 if (sts & (USR1_RRDY | USR1_AGTIM)) {
832 if (sport->dma_is_enabled)
833 imx_dma_rxint(sport);
835 imx_rxint(irq, dev_id);
839 if ((sts & USR1_TRDY &&
840 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
842 readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
843 imx_txint(irq, dev_id);
847 if (sts & USR1_DTRD) {
851 writel(USR1_DTRD, sport->port.membase + USR1);
853 spin_lock_irqsave(&sport->port.lock, flags);
854 imx_mctrl_check(sport);
855 spin_unlock_irqrestore(&sport->port.lock, flags);
860 if (sts & USR1_RTSD) {
861 imx_rtsint(irq, dev_id);
865 if (sts & USR1_AWAKE) {
866 writel(USR1_AWAKE, sport->port.membase + USR1);
870 if (sts2 & USR2_ORE) {
871 sport->port.icount.overrun++;
872 writel(USR2_ORE, sport->port.membase + USR2);
880 * Return TIOCSER_TEMT when transmitter is not busy.
882 static unsigned int imx_tx_empty(struct uart_port *port)
884 struct imx_port *sport = (struct imx_port *)port;
887 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
889 /* If the TX DMA is working, return 0. */
890 if (sport->dma_is_enabled && sport->dma_is_txing)
896 static unsigned int imx_get_mctrl(struct uart_port *port)
898 struct imx_port *sport = (struct imx_port *)port;
899 unsigned int ret = imx_get_hwmctrl(sport);
901 mctrl_gpio_get(sport->gpios, &ret);
906 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
908 struct imx_port *sport = (struct imx_port *)port;
911 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
912 temp = readl(sport->port.membase + UCR2);
913 temp &= ~(UCR2_CTS | UCR2_CTSC);
914 if (mctrl & TIOCM_RTS)
915 temp |= UCR2_CTS | UCR2_CTSC;
916 writel(temp, sport->port.membase + UCR2);
919 temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
920 if (!(mctrl & TIOCM_DTR))
922 writel(temp, sport->port.membase + UCR3);
924 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
925 if (mctrl & TIOCM_LOOP)
927 writel(temp, sport->port.membase + uts_reg(sport));
929 mctrl_gpio_set(sport->gpios, mctrl);
933 * Interrupts always disabled.
935 static void imx_break_ctl(struct uart_port *port, int break_state)
937 struct imx_port *sport = (struct imx_port *)port;
938 unsigned long flags, temp;
940 spin_lock_irqsave(&sport->port.lock, flags);
942 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
944 if (break_state != 0)
947 writel(temp, sport->port.membase + UCR1);
949 spin_unlock_irqrestore(&sport->port.lock, flags);
953 * This is our per-port timeout handler, for checking the
954 * modem status signals.
956 static void imx_timeout(unsigned long data)
958 struct imx_port *sport = (struct imx_port *)data;
961 if (sport->port.state) {
962 spin_lock_irqsave(&sport->port.lock, flags);
963 imx_mctrl_check(sport);
964 spin_unlock_irqrestore(&sport->port.lock, flags);
966 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
971 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
972 * [1] the RX DMA buffer is full.
973 * [2] the aging timer expires
975 * Condition [2] is triggered when a character has been sitting in the FIFO
976 * for at least 8 byte durations.
978 static void dma_rx_callback(void *data)
980 struct imx_port *sport = data;
981 struct dma_chan *chan = sport->dma_chan_rx;
982 struct scatterlist *sgl = &sport->rx_sgl;
983 struct tty_port *port = &sport->port.state->port;
984 struct dma_tx_state state;
985 struct circ_buf *rx_ring = &sport->rx_ring;
986 enum dma_status status;
987 unsigned int w_bytes = 0;
988 unsigned int r_bytes;
989 unsigned int bd_size;
991 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
993 if (status == DMA_ERROR) {
994 dev_err(sport->port.dev, "DMA transaction error.\n");
995 clear_rx_errors(sport);
999 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1002 * The state-residue variable represents the empty space
1003 * relative to the entire buffer. Taking this in consideration
1004 * the head is always calculated base on the buffer total
1005 * length - DMA transaction residue. The UART script from the
1006 * SDMA firmware will jump to the next buffer descriptor,
1007 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1008 * Taking this in consideration the tail is always at the
1009 * beginning of the buffer descriptor that contains the head.
1012 /* Calculate the head */
1013 rx_ring->head = sg_dma_len(sgl) - state.residue;
1015 /* Calculate the tail. */
1016 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1017 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1019 if (rx_ring->head <= sg_dma_len(sgl) &&
1020 rx_ring->head > rx_ring->tail) {
1022 /* Move data from tail to head */
1023 r_bytes = rx_ring->head - rx_ring->tail;
1025 /* CPU claims ownership of RX DMA buffer */
1026 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1029 w_bytes = tty_insert_flip_string(port,
1030 sport->rx_buf + rx_ring->tail, r_bytes);
1032 /* UART retrieves ownership of RX DMA buffer */
1033 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1036 if (w_bytes != r_bytes)
1037 sport->port.icount.buf_overrun++;
1039 sport->port.icount.rx += w_bytes;
1041 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1042 WARN_ON(rx_ring->head <= rx_ring->tail);
1047 tty_flip_buffer_push(port);
1048 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1052 static int start_rx_dma(struct imx_port *sport)
1054 struct scatterlist *sgl = &sport->rx_sgl;
1055 struct dma_chan *chan = sport->dma_chan_rx;
1056 struct device *dev = sport->port.dev;
1057 struct dma_async_tx_descriptor *desc;
1060 sport->rx_ring.head = 0;
1061 sport->rx_ring.tail = 0;
1063 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1064 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1066 dev_err(dev, "DMA mapping error for RX.\n");
1070 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1071 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1072 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1075 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1076 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1079 desc->callback = dma_rx_callback;
1080 desc->callback_param = sport;
1082 dev_dbg(dev, "RX: prepare for the DMA.\n");
1083 sport->rx_cookie = dmaengine_submit(desc);
1084 dma_async_issue_pending(chan);
1088 static void clear_rx_errors(struct imx_port *sport)
1090 unsigned int status_usr1, status_usr2;
1092 status_usr1 = readl(sport->port.membase + USR1);
1093 status_usr2 = readl(sport->port.membase + USR2);
1095 if (status_usr2 & USR2_BRCD) {
1096 sport->port.icount.brk++;
1097 writel(USR2_BRCD, sport->port.membase + USR2);
1098 } else if (status_usr1 & USR1_FRAMERR) {
1099 sport->port.icount.frame++;
1100 writel(USR1_FRAMERR, sport->port.membase + USR1);
1101 } else if (status_usr1 & USR1_PARITYERR) {
1102 sport->port.icount.parity++;
1103 writel(USR1_PARITYERR, sport->port.membase + USR1);
1106 if (status_usr2 & USR2_ORE) {
1107 sport->port.icount.overrun++;
1108 writel(USR2_ORE, sport->port.membase + USR2);
1113 #define TXTL_DEFAULT 2 /* reset default */
1114 #define RXTL_DEFAULT 1 /* reset default */
1115 #define TXTL_DMA 8 /* DMA burst setting */
1116 #define RXTL_DMA 9 /* DMA burst setting */
1118 static void imx_setup_ufcr(struct imx_port *sport,
1119 unsigned char txwl, unsigned char rxwl)
1123 /* set receiver / transmitter trigger level */
1124 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1125 val |= txwl << UFCR_TXTL_SHF | rxwl;
1126 writel(val, sport->port.membase + UFCR);
1129 static void imx_uart_dma_exit(struct imx_port *sport)
1131 if (sport->dma_chan_rx) {
1132 dmaengine_terminate_sync(sport->dma_chan_rx);
1133 dma_release_channel(sport->dma_chan_rx);
1134 sport->dma_chan_rx = NULL;
1135 sport->rx_cookie = -EINVAL;
1136 kfree(sport->rx_buf);
1137 sport->rx_buf = NULL;
1140 if (sport->dma_chan_tx) {
1141 dmaengine_terminate_sync(sport->dma_chan_tx);
1142 dma_release_channel(sport->dma_chan_tx);
1143 sport->dma_chan_tx = NULL;
1146 sport->dma_is_inited = 0;
1149 static int imx_uart_dma_init(struct imx_port *sport)
1151 struct dma_slave_config slave_config = {};
1152 struct device *dev = sport->port.dev;
1155 /* Prepare for RX : */
1156 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1157 if (!sport->dma_chan_rx) {
1158 dev_dbg(dev, "cannot get the DMA channel.\n");
1163 slave_config.direction = DMA_DEV_TO_MEM;
1164 slave_config.src_addr = sport->port.mapbase + URXD0;
1165 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1166 /* one byte less than the watermark level to enable the aging timer */
1167 slave_config.src_maxburst = RXTL_DMA - 1;
1168 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1170 dev_err(dev, "error in RX dma configuration.\n");
1174 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1175 if (!sport->rx_buf) {
1179 sport->rx_ring.buf = sport->rx_buf;
1181 /* Prepare for TX : */
1182 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1183 if (!sport->dma_chan_tx) {
1184 dev_err(dev, "cannot get the TX DMA channel!\n");
1189 slave_config.direction = DMA_MEM_TO_DEV;
1190 slave_config.dst_addr = sport->port.mapbase + URTX0;
1191 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1192 slave_config.dst_maxburst = TXTL_DMA;
1193 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1195 dev_err(dev, "error in TX dma configuration.");
1199 sport->dma_is_inited = 1;
1203 imx_uart_dma_exit(sport);
1207 static void imx_enable_dma(struct imx_port *sport)
1211 init_waitqueue_head(&sport->dma_wait);
1214 temp = readl(sport->port.membase + UCR1);
1215 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1216 writel(temp, sport->port.membase + UCR1);
1218 temp = readl(sport->port.membase + UCR2);
1220 writel(temp, sport->port.membase + UCR2);
1222 imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1224 sport->dma_is_enabled = 1;
1227 static void imx_disable_dma(struct imx_port *sport)
1232 temp = readl(sport->port.membase + UCR1);
1233 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1234 writel(temp, sport->port.membase + UCR1);
1237 temp = readl(sport->port.membase + UCR2);
1238 temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1239 writel(temp, sport->port.membase + UCR2);
1241 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1243 sport->dma_is_enabled = 0;
1246 /* half the RX buffer size */
1249 static int imx_startup(struct uart_port *port)
1251 struct imx_port *sport = (struct imx_port *)port;
1253 unsigned long flags, temp;
1255 retval = clk_prepare_enable(sport->clk_per);
1258 retval = clk_prepare_enable(sport->clk_ipg);
1260 clk_disable_unprepare(sport->clk_per);
1264 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1266 /* disable the DREN bit (Data Ready interrupt enable) before
1269 temp = readl(sport->port.membase + UCR4);
1271 /* set the trigger level for CTS */
1272 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1273 temp |= CTSTL << UCR4_CTSTL_SHF;
1275 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1277 /* Can we enable the DMA support? */
1278 if (!uart_console(port) && !sport->dma_is_inited)
1279 imx_uart_dma_init(sport);
1281 spin_lock_irqsave(&sport->port.lock, flags);
1282 /* Reset fifo's and state machines */
1285 temp = readl(sport->port.membase + UCR2);
1287 writel(temp, sport->port.membase + UCR2);
1289 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1293 * Finally, clear and enable interrupts
1295 writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1296 writel(USR2_ORE, sport->port.membase + USR2);
1298 if (sport->dma_is_inited && !sport->dma_is_enabled)
1299 imx_enable_dma(sport);
1301 temp = readl(sport->port.membase + UCR1);
1302 temp |= UCR1_RRDYEN | UCR1_UARTEN;
1303 if (sport->have_rtscts)
1304 temp |= UCR1_RTSDEN;
1306 writel(temp, sport->port.membase + UCR1);
1308 temp = readl(sport->port.membase + UCR4);
1310 writel(temp, sport->port.membase + UCR4);
1312 temp = readl(sport->port.membase + UCR2);
1313 temp |= (UCR2_RXEN | UCR2_TXEN);
1314 if (!sport->have_rtscts)
1317 * make sure the edge sensitive RTS-irq is disabled,
1318 * we're using RTSD instead.
1320 if (!is_imx1_uart(sport))
1321 temp &= ~UCR2_RTSEN;
1322 writel(temp, sport->port.membase + UCR2);
1324 if (!is_imx1_uart(sport)) {
1325 temp = readl(sport->port.membase + UCR3);
1327 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1329 if (sport->dte_mode)
1330 /* disable broken interrupts */
1331 temp &= ~(UCR3_RI | UCR3_DCD);
1333 writel(temp, sport->port.membase + UCR3);
1337 * Enable modem status interrupts
1339 imx_enable_ms(&sport->port);
1342 * Start RX DMA immediately instead of waiting for RX FIFO interrupts.
1343 * In our iMX53 the average delay for the first reception dropped from
1344 * approximately 35000 microseconds to 1000 microseconds.
1346 if (sport->dma_is_enabled) {
1347 imx_disable_rx_int(sport);
1348 start_rx_dma(sport);
1351 spin_unlock_irqrestore(&sport->port.lock, flags);
1356 static void imx_shutdown(struct uart_port *port)
1358 struct imx_port *sport = (struct imx_port *)port;
1360 unsigned long flags;
1362 if (sport->dma_is_enabled) {
1363 sport->dma_is_rxing = 0;
1364 sport->dma_is_txing = 0;
1365 dmaengine_terminate_sync(sport->dma_chan_tx);
1366 dmaengine_terminate_sync(sport->dma_chan_rx);
1368 spin_lock_irqsave(&sport->port.lock, flags);
1371 imx_disable_dma(sport);
1372 spin_unlock_irqrestore(&sport->port.lock, flags);
1373 imx_uart_dma_exit(sport);
1376 mctrl_gpio_disable_ms(sport->gpios);
1378 spin_lock_irqsave(&sport->port.lock, flags);
1379 temp = readl(sport->port.membase + UCR2);
1380 temp &= ~(UCR2_TXEN);
1381 writel(temp, sport->port.membase + UCR2);
1382 spin_unlock_irqrestore(&sport->port.lock, flags);
1387 del_timer_sync(&sport->timer);
1390 * Disable all interrupts, port and break condition.
1393 spin_lock_irqsave(&sport->port.lock, flags);
1394 temp = readl(sport->port.membase + UCR1);
1395 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1397 writel(temp, sport->port.membase + UCR1);
1398 spin_unlock_irqrestore(&sport->port.lock, flags);
1400 clk_disable_unprepare(sport->clk_per);
1401 clk_disable_unprepare(sport->clk_ipg);
1404 static void imx_flush_buffer(struct uart_port *port)
1406 struct imx_port *sport = (struct imx_port *)port;
1407 struct scatterlist *sgl = &sport->tx_sgl[0];
1409 int i = 100, ubir, ubmr, uts;
1411 if (!sport->dma_chan_tx)
1414 sport->tx_bytes = 0;
1415 dmaengine_terminate_all(sport->dma_chan_tx);
1416 if (sport->dma_is_txing) {
1417 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1419 temp = readl(sport->port.membase + UCR1);
1420 temp &= ~UCR1_TDMAEN;
1421 writel(temp, sport->port.membase + UCR1);
1422 sport->dma_is_txing = false;
1426 * According to the Reference Manual description of the UART SRST bit:
1427 * "Reset the transmit and receive state machines,
1428 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1429 * and UTS[6-3]". As we don't need to restore the old values from
1430 * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1432 ubir = readl(sport->port.membase + UBIR);
1433 ubmr = readl(sport->port.membase + UBMR);
1434 uts = readl(sport->port.membase + IMX21_UTS);
1436 temp = readl(sport->port.membase + UCR2);
1438 writel(temp, sport->port.membase + UCR2);
1440 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1443 /* Restore the registers */
1444 writel(ubir, sport->port.membase + UBIR);
1445 writel(ubmr, sport->port.membase + UBMR);
1446 writel(uts, sport->port.membase + IMX21_UTS);
1450 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1451 struct ktermios *old)
1453 struct imx_port *sport = (struct imx_port *)port;
1454 unsigned long flags;
1455 unsigned long ucr2, old_ucr1, old_ucr2;
1456 unsigned int baud, quot;
1457 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1458 unsigned long div, ufcr;
1459 unsigned long num, denom;
1463 * We only support CS7 and CS8.
1465 while ((termios->c_cflag & CSIZE) != CS7 &&
1466 (termios->c_cflag & CSIZE) != CS8) {
1467 termios->c_cflag &= ~CSIZE;
1468 termios->c_cflag |= old_csize;
1472 if ((termios->c_cflag & CSIZE) == CS8)
1473 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1475 ucr2 = UCR2_SRST | UCR2_IRTS;
1477 if (termios->c_cflag & CRTSCTS) {
1478 if (sport->have_rtscts) {
1481 if (port->rs485.flags & SER_RS485_ENABLED) {
1483 * RTS is mandatory for rs485 operation, so keep
1484 * it under manual control and keep transmitter
1487 if (port->rs485.flags &
1488 SER_RS485_RTS_AFTER_SEND)
1489 imx_port_rts_active(sport, &ucr2);
1491 imx_port_rts_inactive(sport, &ucr2);
1493 imx_port_rts_auto(sport, &ucr2);
1496 termios->c_cflag &= ~CRTSCTS;
1498 } else if (port->rs485.flags & SER_RS485_ENABLED) {
1499 /* disable transmitter */
1500 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1501 imx_port_rts_active(sport, &ucr2);
1503 imx_port_rts_inactive(sport, &ucr2);
1507 if (termios->c_cflag & CSTOPB)
1509 if (termios->c_cflag & PARENB) {
1511 if (termios->c_cflag & PARODD)
1515 del_timer_sync(&sport->timer);
1518 * Ask the core to calculate the divisor for us.
1520 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1521 quot = uart_get_divisor(port, baud);
1523 spin_lock_irqsave(&sport->port.lock, flags);
1525 sport->port.read_status_mask = 0;
1526 if (termios->c_iflag & INPCK)
1527 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1528 if (termios->c_iflag & (BRKINT | PARMRK))
1529 sport->port.read_status_mask |= URXD_BRK;
1532 * Characters to ignore
1534 sport->port.ignore_status_mask = 0;
1535 if (termios->c_iflag & IGNPAR)
1536 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1537 if (termios->c_iflag & IGNBRK) {
1538 sport->port.ignore_status_mask |= URXD_BRK;
1540 * If we're ignoring parity and break indicators,
1541 * ignore overruns too (for real raw support).
1543 if (termios->c_iflag & IGNPAR)
1544 sport->port.ignore_status_mask |= URXD_OVRRUN;
1547 if ((termios->c_cflag & CREAD) == 0)
1548 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1551 * Update the per-port timeout.
1553 uart_update_timeout(port, termios->c_cflag, baud);
1556 * disable interrupts and drain transmitter
1558 old_ucr1 = readl(sport->port.membase + UCR1);
1559 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1560 sport->port.membase + UCR1);
1562 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1565 /* then, disable everything */
1566 old_ucr2 = readl(sport->port.membase + UCR2);
1567 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1568 sport->port.membase + UCR2);
1569 old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1571 /* custom-baudrate handling */
1572 div = sport->port.uartclk / (baud * 16);
1573 if (baud == 38400 && quot != div)
1574 baud = sport->port.uartclk / (quot * 16);
1576 div = sport->port.uartclk / (baud * 16);
1582 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1583 1 << 16, 1 << 16, &num, &denom);
1585 tdiv64 = sport->port.uartclk;
1587 do_div(tdiv64, denom * 16 * div);
1588 tty_termios_encode_baud_rate(termios,
1589 (speed_t)tdiv64, (speed_t)tdiv64);
1594 ufcr = readl(sport->port.membase + UFCR);
1595 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1596 writel(ufcr, sport->port.membase + UFCR);
1598 writel(num, sport->port.membase + UBIR);
1599 writel(denom, sport->port.membase + UBMR);
1601 if (!is_imx1_uart(sport))
1602 writel(sport->port.uartclk / div / 1000,
1603 sport->port.membase + IMX21_ONEMS);
1605 writel(old_ucr1, sport->port.membase + UCR1);
1607 /* set the parity, stop bits and data size */
1608 writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1610 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1611 imx_enable_ms(&sport->port);
1613 spin_unlock_irqrestore(&sport->port.lock, flags);
1616 static const char *imx_type(struct uart_port *port)
1618 struct imx_port *sport = (struct imx_port *)port;
1620 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1624 * Configure/autoconfigure the port.
1626 static void imx_config_port(struct uart_port *port, int flags)
1628 struct imx_port *sport = (struct imx_port *)port;
1630 if (flags & UART_CONFIG_TYPE)
1631 sport->port.type = PORT_IMX;
1635 * Verify the new serial_struct (for TIOCSSERIAL).
1636 * The only change we allow are to the flags and type, and
1637 * even then only between PORT_IMX and PORT_UNKNOWN
1640 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1642 struct imx_port *sport = (struct imx_port *)port;
1645 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1647 if (sport->port.irq != ser->irq)
1649 if (ser->io_type != UPIO_MEM)
1651 if (sport->port.uartclk / 16 != ser->baud_base)
1653 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1655 if (sport->port.iobase != ser->port)
1662 #if defined(CONFIG_CONSOLE_POLL)
1664 static int imx_poll_init(struct uart_port *port)
1666 struct imx_port *sport = (struct imx_port *)port;
1667 unsigned long flags;
1671 retval = clk_prepare_enable(sport->clk_ipg);
1674 retval = clk_prepare_enable(sport->clk_per);
1676 clk_disable_unprepare(sport->clk_ipg);
1678 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1680 spin_lock_irqsave(&sport->port.lock, flags);
1682 temp = readl(sport->port.membase + UCR1);
1683 if (is_imx1_uart(sport))
1684 temp |= IMX1_UCR1_UARTCLKEN;
1685 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1686 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1687 writel(temp, sport->port.membase + UCR1);
1689 temp = readl(sport->port.membase + UCR2);
1691 writel(temp, sport->port.membase + UCR2);
1693 spin_unlock_irqrestore(&sport->port.lock, flags);
1698 static int imx_poll_get_char(struct uart_port *port)
1700 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1701 return NO_POLL_CHAR;
1703 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1706 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1708 unsigned int status;
1712 status = readl_relaxed(port->membase + USR1);
1713 } while (~status & USR1_TRDY);
1716 writel_relaxed(c, port->membase + URTX0);
1720 status = readl_relaxed(port->membase + USR2);
1721 } while (~status & USR2_TXDC);
1725 static int imx_rs485_config(struct uart_port *port,
1726 struct serial_rs485 *rs485conf)
1728 struct imx_port *sport = (struct imx_port *)port;
1732 rs485conf->delay_rts_before_send = 0;
1733 rs485conf->delay_rts_after_send = 0;
1735 /* RTS is required to control the transmitter */
1736 if (!sport->have_rtscts && !sport->have_rtsgpio)
1737 rs485conf->flags &= ~SER_RS485_ENABLED;
1739 if (rs485conf->flags & SER_RS485_ENABLED) {
1740 /* disable transmitter */
1741 temp = readl(sport->port.membase + UCR2);
1742 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1743 imx_port_rts_active(sport, &temp);
1745 imx_port_rts_inactive(sport, &temp);
1746 writel(temp, sport->port.membase + UCR2);
1749 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1750 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1751 rs485conf->flags & SER_RS485_RX_DURING_TX) {
1752 temp = readl(sport->port.membase + UCR2);
1754 writel(temp, sport->port.membase + UCR2);
1757 port->rs485 = *rs485conf;
1762 static const struct uart_ops imx_pops = {
1763 .tx_empty = imx_tx_empty,
1764 .set_mctrl = imx_set_mctrl,
1765 .get_mctrl = imx_get_mctrl,
1766 .stop_tx = imx_stop_tx,
1767 .start_tx = imx_start_tx,
1768 .stop_rx = imx_stop_rx,
1769 .enable_ms = imx_enable_ms,
1770 .break_ctl = imx_break_ctl,
1771 .startup = imx_startup,
1772 .shutdown = imx_shutdown,
1773 .flush_buffer = imx_flush_buffer,
1774 .set_termios = imx_set_termios,
1776 .config_port = imx_config_port,
1777 .verify_port = imx_verify_port,
1778 #if defined(CONFIG_CONSOLE_POLL)
1779 .poll_init = imx_poll_init,
1780 .poll_get_char = imx_poll_get_char,
1781 .poll_put_char = imx_poll_put_char,
1785 static struct imx_port *imx_ports[UART_NR];
1787 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1788 static void imx_console_putchar(struct uart_port *port, int ch)
1790 struct imx_port *sport = (struct imx_port *)port;
1792 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1795 writel(ch, sport->port.membase + URTX0);
1799 * Interrupts are disabled on entering
1802 imx_console_write(struct console *co, const char *s, unsigned int count)
1804 struct imx_port *sport = imx_ports[co->index];
1805 struct imx_port_ucrs old_ucr;
1807 unsigned long flags = 0;
1811 retval = clk_enable(sport->clk_per);
1814 retval = clk_enable(sport->clk_ipg);
1816 clk_disable(sport->clk_per);
1820 if (sport->port.sysrq)
1822 else if (oops_in_progress)
1823 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1825 spin_lock_irqsave(&sport->port.lock, flags);
1828 * First, save UCR1/2/3 and then disable interrupts
1830 imx_port_ucrs_save(&sport->port, &old_ucr);
1831 ucr1 = old_ucr.ucr1;
1833 if (is_imx1_uart(sport))
1834 ucr1 |= IMX1_UCR1_UARTCLKEN;
1835 ucr1 |= UCR1_UARTEN;
1836 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1838 writel(ucr1, sport->port.membase + UCR1);
1840 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1842 uart_console_write(&sport->port, s, count, imx_console_putchar);
1845 * Finally, wait for transmitter to become empty
1846 * and restore UCR1/2/3
1848 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1850 imx_port_ucrs_restore(&sport->port, &old_ucr);
1853 spin_unlock_irqrestore(&sport->port.lock, flags);
1855 clk_disable(sport->clk_ipg);
1856 clk_disable(sport->clk_per);
1860 * If the port was already initialised (eg, by a boot loader),
1861 * try to determine the current setup.
1864 imx_console_get_options(struct imx_port *sport, int *baud,
1865 int *parity, int *bits)
1868 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1869 /* ok, the port was enabled */
1870 unsigned int ucr2, ubir, ubmr, uartclk;
1871 unsigned int baud_raw;
1872 unsigned int ucfr_rfdiv;
1874 ucr2 = readl(sport->port.membase + UCR2);
1877 if (ucr2 & UCR2_PREN) {
1878 if (ucr2 & UCR2_PROE)
1889 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1890 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1892 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1893 if (ucfr_rfdiv == 6)
1896 ucfr_rfdiv = 6 - ucfr_rfdiv;
1898 uartclk = clk_get_rate(sport->clk_per);
1899 uartclk /= ucfr_rfdiv;
1902 * The next code provides exact computation of
1903 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1904 * without need of float support or long long division,
1905 * which would be required to prevent 32bit arithmetic overflow
1907 unsigned int mul = ubir + 1;
1908 unsigned int div = 16 * (ubmr + 1);
1909 unsigned int rem = uartclk % div;
1911 baud_raw = (uartclk / div) * mul;
1912 baud_raw += (rem * mul + div / 2) / div;
1913 *baud = (baud_raw + 50) / 100 * 100;
1916 if (*baud != baud_raw)
1917 pr_info("Console IMX rounded baud rate from %d to %d\n",
1923 imx_console_setup(struct console *co, char *options)
1925 struct imx_port *sport;
1933 * Check whether an invalid uart number has been specified, and
1934 * if so, search for the first available port that does have
1937 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1939 sport = imx_ports[co->index];
1943 /* For setting the registers, we only need to enable the ipg clock. */
1944 retval = clk_prepare_enable(sport->clk_ipg);
1949 uart_parse_options(options, &baud, &parity, &bits, &flow);
1951 imx_console_get_options(sport, &baud, &parity, &bits);
1953 imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1955 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1957 clk_disable(sport->clk_ipg);
1959 clk_unprepare(sport->clk_ipg);
1963 retval = clk_prepare(sport->clk_per);
1965 clk_disable_unprepare(sport->clk_ipg);
1971 static struct uart_driver imx_reg;
1972 static struct console imx_console = {
1974 .write = imx_console_write,
1975 .device = uart_console_device,
1976 .setup = imx_console_setup,
1977 .flags = CON_PRINTBUFFER,
1982 #define IMX_CONSOLE &imx_console
1985 static void imx_console_early_putchar(struct uart_port *port, int ch)
1987 while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1990 writel_relaxed(ch, port->membase + URTX0);
1993 static void imx_console_early_write(struct console *con, const char *s,
1996 struct earlycon_device *dev = con->data;
1998 uart_console_write(&dev->port, s, count, imx_console_early_putchar);
2002 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2004 if (!dev->port.membase)
2007 dev->con->write = imx_console_early_write;
2011 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2012 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2016 #define IMX_CONSOLE NULL
2019 static struct uart_driver imx_reg = {
2020 .owner = THIS_MODULE,
2021 .driver_name = DRIVER_NAME,
2022 .dev_name = DEV_NAME,
2023 .major = SERIAL_IMX_MAJOR,
2024 .minor = MINOR_START,
2025 .nr = ARRAY_SIZE(imx_ports),
2026 .cons = IMX_CONSOLE,
2031 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2032 * could successfully get all information from dt or a negative errno.
2034 static int serial_imx_probe_dt(struct imx_port *sport,
2035 struct platform_device *pdev)
2037 struct device_node *np = pdev->dev.of_node;
2039 u32 dma_buf_size[2];
2041 sport->devdata = of_device_get_match_data(&pdev->dev);
2042 if (!sport->devdata)
2043 /* no device tree device */
2046 ret = of_alias_get_id(np, "serial");
2048 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2051 sport->port.line = ret;
2053 if (of_get_property(np, "uart-has-rtscts", NULL) ||
2054 of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2055 sport->have_rtscts = 1;
2057 if (of_get_property(np, "fsl,dte-mode", NULL))
2058 sport->dte_mode = 1;
2060 if (of_get_property(np, "rts-gpios", NULL))
2061 sport->have_rtsgpio = 1;
2063 if (!of_property_read_u32_array(np, "fsl,dma-size", dma_buf_size, 2)) {
2064 sport->rx_buf_size = dma_buf_size[0] * dma_buf_size[1];
2065 sport->rx_periods = dma_buf_size[1];
2067 sport->rx_buf_size = RX_BUF_SIZE;
2068 sport->rx_periods = RX_DMA_PERIODS;
2074 static inline int serial_imx_probe_dt(struct imx_port *sport,
2075 struct platform_device *pdev)
2081 static void serial_imx_probe_pdata(struct imx_port *sport,
2082 struct platform_device *pdev)
2084 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2086 sport->port.line = pdev->id;
2087 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
2092 if (pdata->flags & IMXUART_HAVE_RTSCTS)
2093 sport->have_rtscts = 1;
2096 static int serial_imx_probe(struct platform_device *pdev)
2098 struct imx_port *sport;
2101 struct resource *res;
2102 int txirq, rxirq, rtsirq;
2104 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2108 ret = serial_imx_probe_dt(sport, pdev);
2110 serial_imx_probe_pdata(sport, pdev);
2114 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2115 base = devm_ioremap_resource(&pdev->dev, res);
2117 return PTR_ERR(base);
2119 rxirq = platform_get_irq(pdev, 0);
2120 txirq = platform_get_irq(pdev, 1);
2121 rtsirq = platform_get_irq(pdev, 2);
2123 sport->port.dev = &pdev->dev;
2124 sport->port.mapbase = res->start;
2125 sport->port.membase = base;
2126 sport->port.type = PORT_IMX,
2127 sport->port.iotype = UPIO_MEM;
2128 sport->port.irq = rxirq;
2129 sport->port.fifosize = 32;
2130 sport->port.ops = &imx_pops;
2131 sport->port.rs485_config = imx_rs485_config;
2132 sport->port.rs485.flags =
2133 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2134 sport->port.flags = UPF_BOOT_AUTOCONF;
2135 init_timer(&sport->timer);
2136 sport->timer.function = imx_timeout;
2137 sport->timer.data = (unsigned long)sport;
2139 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2140 if (IS_ERR(sport->gpios))
2141 return PTR_ERR(sport->gpios);
2143 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2144 if (IS_ERR(sport->clk_ipg)) {
2145 ret = PTR_ERR(sport->clk_ipg);
2146 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2150 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2151 if (IS_ERR(sport->clk_per)) {
2152 ret = PTR_ERR(sport->clk_per);
2153 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2157 sport->port.uartclk = clk_get_rate(sport->clk_per);
2159 /* For register access, we only need to enable the ipg clock. */
2160 ret = clk_prepare_enable(sport->clk_ipg);
2162 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2166 /* Disable interrupts before requesting them */
2167 reg = readl_relaxed(sport->port.membase + UCR1);
2168 reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2169 UCR1_TXMPTYEN | UCR1_RTSDEN);
2170 writel_relaxed(reg, sport->port.membase + UCR1);
2172 if (!is_imx1_uart(sport) && sport->dte_mode) {
2174 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2175 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2176 * and DCD (when they are outputs) or enables the respective
2177 * irqs. So set this bit early, i.e. before requesting irqs.
2179 reg = readl(sport->port.membase + UFCR);
2180 if (!(reg & UFCR_DCEDTE))
2181 writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR);
2184 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2185 * enabled later because they cannot be cleared
2186 * (confirmed on i.MX25) which makes them unusable.
2188 writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2189 sport->port.membase + UCR3);
2192 unsigned long ucr3 = UCR3_DSR;
2194 reg = readl(sport->port.membase + UFCR);
2195 if (reg & UFCR_DCEDTE)
2196 writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR);
2198 if (!is_imx1_uart(sport))
2199 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2200 writel(ucr3, sport->port.membase + UCR3);
2203 clk_disable_unprepare(sport->clk_ipg);
2206 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2207 * chips only have one interrupt.
2210 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2211 dev_name(&pdev->dev), sport);
2213 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2218 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2219 dev_name(&pdev->dev), sport);
2221 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2226 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2227 dev_name(&pdev->dev), sport);
2229 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2234 imx_ports[sport->port.line] = sport;
2236 platform_set_drvdata(pdev, sport);
2238 return uart_add_one_port(&imx_reg, &sport->port);
2241 static int serial_imx_remove(struct platform_device *pdev)
2243 struct imx_port *sport = platform_get_drvdata(pdev);
2245 return uart_remove_one_port(&imx_reg, &sport->port);
2248 static void serial_imx_restore_context(struct imx_port *sport)
2250 if (!sport->context_saved)
2253 writel(sport->saved_reg[4], sport->port.membase + UFCR);
2254 writel(sport->saved_reg[5], sport->port.membase + UESC);
2255 writel(sport->saved_reg[6], sport->port.membase + UTIM);
2256 writel(sport->saved_reg[7], sport->port.membase + UBIR);
2257 writel(sport->saved_reg[8], sport->port.membase + UBMR);
2258 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2259 writel(sport->saved_reg[0], sport->port.membase + UCR1);
2260 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2261 writel(sport->saved_reg[2], sport->port.membase + UCR3);
2262 writel(sport->saved_reg[3], sport->port.membase + UCR4);
2263 sport->context_saved = false;
2266 static void serial_imx_save_context(struct imx_port *sport)
2268 /* Save necessary regs */
2269 sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2270 sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2271 sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2272 sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2273 sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2274 sport->saved_reg[5] = readl(sport->port.membase + UESC);
2275 sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2276 sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2277 sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2278 sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2279 sport->context_saved = true;
2282 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2286 val = readl(sport->port.membase + UCR3);
2290 val &= ~UCR3_AWAKEN;
2291 writel(val, sport->port.membase + UCR3);
2293 val = readl(sport->port.membase + UCR1);
2297 val &= ~UCR1_RTSDEN;
2298 writel(val, sport->port.membase + UCR1);
2301 static int imx_serial_port_suspend_noirq(struct device *dev)
2303 struct platform_device *pdev = to_platform_device(dev);
2304 struct imx_port *sport = platform_get_drvdata(pdev);
2307 ret = clk_enable(sport->clk_ipg);
2311 serial_imx_save_context(sport);
2313 clk_disable(sport->clk_ipg);
2318 static int imx_serial_port_resume_noirq(struct device *dev)
2320 struct platform_device *pdev = to_platform_device(dev);
2321 struct imx_port *sport = platform_get_drvdata(pdev);
2324 ret = clk_enable(sport->clk_ipg);
2328 serial_imx_restore_context(sport);
2330 clk_disable(sport->clk_ipg);
2335 static int imx_serial_port_suspend(struct device *dev)
2337 struct platform_device *pdev = to_platform_device(dev);
2338 struct imx_port *sport = platform_get_drvdata(pdev);
2340 /* enable wakeup from i.MX UART */
2341 serial_imx_enable_wakeup(sport, true);
2343 uart_suspend_port(&imx_reg, &sport->port);
2345 /* Needed to enable clock in suspend_noirq */
2346 return clk_prepare(sport->clk_ipg);
2349 static int imx_serial_port_resume(struct device *dev)
2351 struct platform_device *pdev = to_platform_device(dev);
2352 struct imx_port *sport = platform_get_drvdata(pdev);
2354 /* disable wakeup from i.MX UART */
2355 serial_imx_enable_wakeup(sport, false);
2357 uart_resume_port(&imx_reg, &sport->port);
2359 clk_unprepare(sport->clk_ipg);
2364 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2365 .suspend_noirq = imx_serial_port_suspend_noirq,
2366 .resume_noirq = imx_serial_port_resume_noirq,
2367 .suspend = imx_serial_port_suspend,
2368 .resume = imx_serial_port_resume,
2371 static struct platform_driver serial_imx_driver = {
2372 .probe = serial_imx_probe,
2373 .remove = serial_imx_remove,
2375 .id_table = imx_uart_devtype,
2378 .of_match_table = imx_uart_dt_ids,
2379 .pm = &imx_serial_port_pm_ops,
2383 static int __init imx_serial_init(void)
2385 int ret = uart_register_driver(&imx_reg);
2390 ret = platform_driver_register(&serial_imx_driver);
2392 uart_unregister_driver(&imx_reg);
2397 static void __exit imx_serial_exit(void)
2399 platform_driver_unregister(&serial_imx_driver);
2400 uart_unregister_driver(&imx_reg);
2403 module_init(imx_serial_init);
2404 module_exit(imx_serial_exit);
2406 MODULE_AUTHOR("Sascha Hauer");
2407 MODULE_DESCRIPTION("IMX generic serial port driver");
2408 MODULE_LICENSE("GPL");
2409 MODULE_ALIAS("platform:imx-uart");