drivers/tty/serial/msm_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for msm7k serial device and console
   4  *
   5  * Copyright (C) 2007 Google, Inc.
   6  * Author: Robert Love <rlove@google.com>
   7  * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/atomic.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/dmaengine.h>
  14 #include <linux/module.h>
  15 #include <linux/io.h>
  16 #include <linux/ioport.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/init.h>
  19 #include <linux/console.h>
  20 #include <linux/tty.h>
  21 #include <linux/tty_flip.h>
  22 #include <linux/serial_core.h>
  23 #include <linux/slab.h>
  24 #include <linux/clk.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/delay.h>
  27 #include <linux/of.h>
  28 #include <linux/of_device.h>
  29 #include <linux/wait.h>
  30
  31 #define UART_MR1                        0x0000
  32
  33 #define UART_MR1_AUTO_RFR_LEVEL0        0x3F
  34 #define UART_MR1_AUTO_RFR_LEVEL1        0x3FF00
  35 #define UART_DM_MR1_AUTO_RFR_LEVEL1     0xFFFFFF00
  36 #define UART_MR1_RX_RDY_CTL             BIT(7)
  37 #define UART_MR1_CTS_CTL                BIT(6)
  38
  39 #define UART_MR2                        0x0004
  40 #define UART_MR2_ERROR_MODE             BIT(6)
  41 #define UART_MR2_BITS_PER_CHAR          0x30
  42 #define UART_MR2_BITS_PER_CHAR_5        (0x0 << 4)
  43 #define UART_MR2_BITS_PER_CHAR_6        (0x1 << 4)
  44 #define UART_MR2_BITS_PER_CHAR_7        (0x2 << 4)
  45 #define UART_MR2_BITS_PER_CHAR_8        (0x3 << 4)
  46 #define UART_MR2_STOP_BIT_LEN_ONE       (0x1 << 2)
  47 #define UART_MR2_STOP_BIT_LEN_TWO       (0x3 << 2)
  48 #define UART_MR2_PARITY_MODE_NONE       0x0
  49 #define UART_MR2_PARITY_MODE_ODD        0x1
  50 #define UART_MR2_PARITY_MODE_EVEN       0x2
  51 #define UART_MR2_PARITY_MODE_SPACE      0x3
  52 #define UART_MR2_PARITY_MODE            0x3
  53
  54 #define UART_CSR                        0x0008
  55
  56 #define UART_TF                         0x000C
  57 #define UARTDM_TF                       0x0070
  58
  59 #define UART_CR                         0x0010
  60 #define UART_CR_CMD_NULL                (0 << 4)
  61 #define UART_CR_CMD_RESET_RX            (1 << 4)
  62 #define UART_CR_CMD_RESET_TX            (2 << 4)
  63 #define UART_CR_CMD_RESET_ERR           (3 << 4)
  64 #define UART_CR_CMD_RESET_BREAK_INT     (4 << 4)
  65 #define UART_CR_CMD_START_BREAK         (5 << 4)
  66 #define UART_CR_CMD_STOP_BREAK          (6 << 4)
  67 #define UART_CR_CMD_RESET_CTS           (7 << 4)
  68 #define UART_CR_CMD_RESET_STALE_INT     (8 << 4)
  69 #define UART_CR_CMD_PACKET_MODE         (9 << 4)
  70 #define UART_CR_CMD_MODE_RESET          (12 << 4)
  71 #define UART_CR_CMD_SET_RFR             (13 << 4)
  72 #define UART_CR_CMD_RESET_RFR           (14 << 4)
  73 #define UART_CR_CMD_PROTECTION_EN       (16 << 4)
  74 #define UART_CR_CMD_STALE_EVENT_DISABLE (6 << 8)
  75 #define UART_CR_CMD_STALE_EVENT_ENABLE  (80 << 4)
  76 #define UART_CR_CMD_FORCE_STALE         (4 << 8)
  77 #define UART_CR_CMD_RESET_TX_READY      (3 << 8)
  78 #define UART_CR_TX_DISABLE              BIT(3)
  79 #define UART_CR_TX_ENABLE               BIT(2)
  80 #define UART_CR_RX_DISABLE              BIT(1)
  81 #define UART_CR_RX_ENABLE               BIT(0)
  82 #define UART_CR_CMD_RESET_RXBREAK_START ((1 << 11) | (2 << 4))
  83
  84 #define UART_IMR                        0x0014
  85 #define UART_IMR_TXLEV                  BIT(0)
  86 #define UART_IMR_RXSTALE                BIT(3)
  87 #define UART_IMR_RXLEV                  BIT(4)
  88 #define UART_IMR_DELTA_CTS              BIT(5)
  89 #define UART_IMR_CURRENT_CTS            BIT(6)
  90 #define UART_IMR_RXBREAK_START          BIT(10)
  91
  92 #define UART_IPR_RXSTALE_LAST           0x20
  93 #define UART_IPR_STALE_LSB              0x1F
  94 #define UART_IPR_STALE_TIMEOUT_MSB      0x3FF80
  95 #define UART_DM_IPR_STALE_TIMEOUT_MSB   0xFFFFFF80
  96
  97 #define UART_IPR                        0x0018
  98 #define UART_TFWR                       0x001C
  99 #define UART_RFWR                       0x0020
 100 #define UART_HCR                        0x0024
 101
 102 #define UART_MREG                       0x0028
 103 #define UART_NREG                       0x002C
 104 #define UART_DREG                       0x0030
 105 #define UART_MNDREG                     0x0034
 106 #define UART_IRDA                       0x0038
 107 #define UART_MISR_MODE                  0x0040
 108 #define UART_MISR_RESET                 0x0044
 109 #define UART_MISR_EXPORT                0x0048
 110 #define UART_MISR_VAL                   0x004C
 111 #define UART_TEST_CTRL                  0x0050
 112
 113 #define UART_SR                         0x0008
 114 #define UART_SR_HUNT_CHAR               BIT(7)
 115 #define UART_SR_RX_BREAK                BIT(6)
 116 #define UART_SR_PAR_FRAME_ERR           BIT(5)
 117 #define UART_SR_OVERRUN                 BIT(4)
 118 #define UART_SR_TX_EMPTY                BIT(3)
 119 #define UART_SR_TX_READY                BIT(2)
 120 #define UART_SR_RX_FULL                 BIT(1)
 121 #define UART_SR_RX_READY                BIT(0)
 122
 123 #define UART_RF                         0x000C
 124 #define UARTDM_RF                       0x0070
 125 #define UART_MISR                       0x0010
 126 #define UART_ISR                        0x0014
 127 #define UART_ISR_TX_READY               BIT(7)
 128
 129 #define UARTDM_RXFS                     0x50
 130 #define UARTDM_RXFS_BUF_SHIFT           0x7
 131 #define UARTDM_RXFS_BUF_MASK            0x7
 132
 133 #define UARTDM_DMEN                     0x3C
 134 #define UARTDM_DMEN_RX_SC_ENABLE        BIT(5)
 135 #define UARTDM_DMEN_TX_SC_ENABLE        BIT(4)
 136
 137 #define UARTDM_DMEN_TX_BAM_ENABLE       BIT(2)  /* UARTDM_1P4 */
 138 #define UARTDM_DMEN_TX_DM_ENABLE        BIT(0)  /* < UARTDM_1P4 */
 139
 140 #define UARTDM_DMEN_RX_BAM_ENABLE       BIT(3)  /* UARTDM_1P4 */
 141 #define UARTDM_DMEN_RX_DM_ENABLE        BIT(1)  /* < UARTDM_1P4 */
 142
 143 #define UARTDM_DMRX                     0x34
 144 #define UARTDM_NCF_TX                   0x40
 145 #define UARTDM_RX_TOTAL_SNAP            0x38
 146
 147 #define UARTDM_BURST_SIZE               16   /* in bytes */
 148 #define UARTDM_TX_AIGN(x)               ((x) & ~0x3) /* valid for > 1p3 */
 149 #define UARTDM_TX_MAX                   256   /* in bytes, valid for <= 1p3 */
 150 #define UARTDM_RX_SIZE                  (UART_XMIT_SIZE / 4)
 151
 152 enum {
 153         UARTDM_1P1 = 1,
 154         UARTDM_1P2,
 155         UARTDM_1P3,
 156         UARTDM_1P4,
 157 };
 158
 159 struct msm_dma {
 160         struct dma_chan         *chan;
 161         enum dma_data_direction dir;
 162         dma_addr_t              phys;
 163         unsigned char           *virt;
 164         dma_cookie_t            cookie;
 165         u32                     enable_bit;
 166         unsigned int            count;
 167         struct dma_async_tx_descriptor  *desc;
 168 };
 169
 170 struct msm_port {
 171         struct uart_port        uart;
 172         char                    name[16];
 173         struct clk              *clk;
 174         struct clk              *pclk;
 175         unsigned int            imr;
 176         int                     is_uartdm;
 177         unsigned int            old_snap_state;
 178         bool                    break_detected;
 179         struct msm_dma          tx_dma;
 180         struct msm_dma          rx_dma;
 181 };
 182
 183 #define UART_TO_MSM(uart_port)  container_of(uart_port, struct msm_port, uart)
 184
 185 static
 186 void msm_write(struct uart_port *port, unsigned int val, unsigned int off)
 187 {
 188         writel_relaxed(val, port->membase + off);
 189 }
 190
 191 static
 192 unsigned int msm_read(struct uart_port *port, unsigned int off)
 193 {
 194         return readl_relaxed(port->membase + off);
 195 }
 196
 197 /*
 198  * Setup the MND registers to use the TCXO clock.
 199  */
 200 static void msm_serial_set_mnd_regs_tcxo(struct uart_port *port)
 201 {
 202         msm_write(port, 0x06, UART_MREG);
 203         msm_write(port, 0xF1, UART_NREG);
 204         msm_write(port, 0x0F, UART_DREG);
 205         msm_write(port, 0x1A, UART_MNDREG);
 206         port->uartclk = 1843200;
 207 }
 208
 209 /*
 210  * Setup the MND registers to use the TCXO clock divided by 4.
 211  */
 212 static void msm_serial_set_mnd_regs_tcxoby4(struct uart_port *port)
 213 {
 214         msm_write(port, 0x18, UART_MREG);
 215         msm_write(port, 0xF6, UART_NREG);
 216         msm_write(port, 0x0F, UART_DREG);
 217         msm_write(port, 0x0A, UART_MNDREG);
 218         port->uartclk = 1843200;
 219 }
 220
 221 static void msm_serial_set_mnd_regs(struct uart_port *port)
 222 {
 223         struct msm_port *msm_port = UART_TO_MSM(port);
 224
 225         /*
 226          * These registers don't exist so we change the clk input rate
 227          * on uartdm hardware instead
 228          */
 229         if (msm_port->is_uartdm)
 230                 return;
 231
 232         if (port->uartclk == 19200000)
 233                 msm_serial_set_mnd_regs_tcxo(port);
 234         else if (port->uartclk == 4800000)
 235                 msm_serial_set_mnd_regs_tcxoby4(port);
 236 }
 237
 238 static void msm_handle_tx(struct uart_port *port);
 239 static void msm_start_rx_dma(struct msm_port *msm_port);
 240
 241 static void msm_stop_dma(struct uart_port *port, struct msm_dma *dma)
 242 {
 243         struct device *dev = port->dev;
 244         unsigned int mapped;
 245         u32 val;
 246
 247         mapped = dma->count;
 248         dma->count = 0;
 249
 250         dmaengine_terminate_all(dma->chan);
 251
 252         /*
 253          * DMA Stall happens if enqueue and flush command happens concurrently.
 254          * For example before changing the baud rate/protocol configuration and
 255          * sending flush command to ADM, disable the channel of UARTDM.
 256          * Note: should not reset the receiver here immediately as it is not
 257          * suggested to do disable/reset or reset/disable at the same time.
 258          */
 259         val = msm_read(port, UARTDM_DMEN);
 260         val &= ~dma->enable_bit;
 261         msm_write(port, val, UARTDM_DMEN);
 262
 263         if (mapped)
 264                 dma_unmap_single(dev, dma->phys, mapped, dma->dir);
 265 }
 266
 267 static void msm_release_dma(struct msm_port *msm_port)
 268 {
 269         struct msm_dma *dma;
 270
 271         dma = &msm_port->tx_dma;
 272         if (dma->chan) {
 273                 msm_stop_dma(&msm_port->uart, dma);
 274                 dma_release_channel(dma->chan);
 275         }
 276
 277         memset(dma, 0, sizeof(*dma));
 278
 279         dma = &msm_port->rx_dma;
 280         if (dma->chan) {
 281                 msm_stop_dma(&msm_port->uart, dma);
 282                 dma_release_channel(dma->chan);
 283                 kfree(dma->virt);
 284         }
 285
 286         memset(dma, 0, sizeof(*dma));
 287 }
 288
 289 static void msm_request_tx_dma(struct msm_port *msm_port, resource_size_t base)
 290 {
 291         struct device *dev = msm_port->uart.dev;
 292         struct dma_slave_config conf;
 293         struct msm_dma *dma;
 294         u32 crci = 0;
 295         int ret;
 296
 297         dma = &msm_port->tx_dma;
 298
 299         /* allocate DMA resources, if available */
 300         dma->chan = dma_request_chan(dev, "tx");
 301         if (IS_ERR(dma->chan))
 302                 goto no_tx;
 303
 304         of_property_read_u32(dev->of_node, "qcom,tx-crci", &crci);
 305
 306         memset(&conf, 0, sizeof(conf));
 307         conf.direction = DMA_MEM_TO_DEV;
 308         conf.device_fc = true;
 309         conf.dst_addr = base + UARTDM_TF;
 310         conf.dst_maxburst = UARTDM_BURST_SIZE;
 311         conf.slave_id = crci;
 312
 313         ret = dmaengine_slave_config(dma->chan, &conf);
 314         if (ret)
 315                 goto rel_tx;
 316
 317         dma->dir = DMA_TO_DEVICE;
 318
 319         if (msm_port->is_uartdm < UARTDM_1P4)
 320                 dma->enable_bit = UARTDM_DMEN_TX_DM_ENABLE;
 321         else
 322                 dma->enable_bit = UARTDM_DMEN_TX_BAM_ENABLE;
 323
 324         return;
 325
 326 rel_tx:
 327         dma_release_channel(dma->chan);
 328 no_tx:
 329         memset(dma, 0, sizeof(*dma));
 330 }
 331
 332 static void msm_request_rx_dma(struct msm_port *msm_port, resource_size_t base)
 333 {
 334         struct device *dev = msm_port->uart.dev;
 335         struct dma_slave_config conf;
 336         struct msm_dma *dma;
 337         u32 crci = 0;
 338         int ret;
 339
 340         dma = &msm_port->rx_dma;
 341
 342         /* allocate DMA resources, if available */
 343         dma->chan = dma_request_chan(dev, "rx");
 344         if (IS_ERR(dma->chan))
 345                 goto no_rx;
 346
 347         of_property_read_u32(dev->of_node, "qcom,rx-crci", &crci);
 348
 349         dma->virt = kzalloc(UARTDM_RX_SIZE, GFP_KERNEL);
 350         if (!dma->virt)
 351                 goto rel_rx;
 352
 353         memset(&conf, 0, sizeof(conf));
 354         conf.direction = DMA_DEV_TO_MEM;
 355         conf.device_fc = true;
 356         conf.src_addr = base + UARTDM_RF;
 357         conf.src_maxburst = UARTDM_BURST_SIZE;
 358         conf.slave_id = crci;
 359
 360         ret = dmaengine_slave_config(dma->chan, &conf);
 361         if (ret)
 362                 goto err;
 363
 364         dma->dir = DMA_FROM_DEVICE;
 365
 366         if (msm_port->is_uartdm < UARTDM_1P4)
 367                 dma->enable_bit = UARTDM_DMEN_RX_DM_ENABLE;
 368         else
 369                 dma->enable_bit = UARTDM_DMEN_RX_BAM_ENABLE;
 370
 371         return;
 372 err:
 373         kfree(dma->virt);
 374 rel_rx:
 375         dma_release_channel(dma->chan);
 376 no_rx:
 377         memset(dma, 0, sizeof(*dma));
 378 }
 379
 380 static inline void msm_wait_for_xmitr(struct uart_port *port)
 381 {
 382         unsigned int timeout = 500000;
 383
 384         while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
 385                 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
 386                         break;
 387                 udelay(1);
 388                 if (!timeout--)
 389                         break;
 390         }
 391         msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
 392 }
 393
 394 static void msm_stop_tx(struct uart_port *port)
 395 {
 396         struct msm_port *msm_port = UART_TO_MSM(port);
 397
 398         msm_port->imr &= ~UART_IMR_TXLEV;
 399         msm_write(port, msm_port->imr, UART_IMR);
 400 }
 401
 402 static void msm_start_tx(struct uart_port *port)
 403 {
 404         struct msm_port *msm_port = UART_TO_MSM(port);
 405         struct msm_dma *dma = &msm_port->tx_dma;
 406
 407         /* Already started in DMA mode */
 408         if (dma->count)
 409                 return;
 410
 411         msm_port->imr |= UART_IMR_TXLEV;
 412         msm_write(port, msm_port->imr, UART_IMR);
 413 }
 414
 415 static void msm_reset_dm_count(struct uart_port *port, int count)
 416 {
 417         msm_wait_for_xmitr(port);
 418         msm_write(port, count, UARTDM_NCF_TX);
 419         msm_read(port, UARTDM_NCF_TX);
 420 }
 421
 422 static void msm_complete_tx_dma(void *args)
 423 {
 424         struct msm_port *msm_port = args;
 425         struct uart_port *port = &msm_port->uart;
 426         struct circ_buf *xmit = &port->state->xmit;
 427         struct msm_dma *dma = &msm_port->tx_dma;
 428         struct dma_tx_state state;
 429         enum dma_status status;
 430         unsigned long flags;
 431         unsigned int count;
 432         u32 val;
 433
 434         spin_lock_irqsave(&port->lock, flags);
 435
 436         /* Already stopped */
 437         if (!dma->count)
 438                 goto done;
 439
 440         status = dmaengine_tx_status(dma->chan, dma->cookie, &state);
 441
 442         dma_unmap_single(port->dev, dma->phys, dma->count, dma->dir);
 443
 444         val = msm_read(port, UARTDM_DMEN);
 445         val &= ~dma->enable_bit;
 446         msm_write(port, val, UARTDM_DMEN);
 447
 448         if (msm_port->is_uartdm > UARTDM_1P3) {
 449                 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
 450                 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
 451         }
 452
 453         count = dma->count - state.residue;
 454         port->icount.tx += count;
 455         dma->count = 0;
 456
 457         xmit->tail += count;
 458         xmit->tail &= UART_XMIT_SIZE - 1;
 459
 460         /* Restore "Tx FIFO below watermark" interrupt */
 461         msm_port->imr |= UART_IMR_TXLEV;
 462         msm_write(port, msm_port->imr, UART_IMR);
 463
 464         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 465                 uart_write_wakeup(port);
 466
 467         msm_handle_tx(port);
 468 done:
 469         spin_unlock_irqrestore(&port->lock, flags);
 470 }
 471
 472 static int msm_handle_tx_dma(struct msm_port *msm_port, unsigned int count)
 473 {
 474         struct circ_buf *xmit = &msm_port->uart.state->xmit;
 475         struct uart_port *port = &msm_port->uart;
 476         struct msm_dma *dma = &msm_port->tx_dma;
 477         void *cpu_addr;
 478         int ret;
 479         u32 val;
 480
 481         cpu_addr = &xmit->buf[xmit->tail];
 482
 483         dma->phys = dma_map_single(port->dev, cpu_addr, count, dma->dir);
 484         ret = dma_mapping_error(port->dev, dma->phys);
 485         if (ret)
 486                 return ret;
 487
 488         dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
 489                                                 count, DMA_MEM_TO_DEV,
 490                                                 DMA_PREP_INTERRUPT |
 491                                                 DMA_PREP_FENCE);
 492         if (!dma->desc) {
 493                 ret = -EIO;
 494                 goto unmap;
 495         }
 496
 497         dma->desc->callback = msm_complete_tx_dma;
 498         dma->desc->callback_param = msm_port;
 499
 500         dma->cookie = dmaengine_submit(dma->desc);
 501         ret = dma_submit_error(dma->cookie);
 502         if (ret)
 503                 goto unmap;
 504
 505         /*
 506          * Using DMA complete for Tx FIFO reload, no need for
 507          * "Tx FIFO below watermark" one, disable it
 508          */
 509         msm_port->imr &= ~UART_IMR_TXLEV;
 510         msm_write(port, msm_port->imr, UART_IMR);
 511
 512         dma->count = count;
 513
 514         val = msm_read(port, UARTDM_DMEN);
 515         val |= dma->enable_bit;
 516
 517         if (msm_port->is_uartdm < UARTDM_1P4)
 518                 msm_write(port, val, UARTDM_DMEN);
 519
 520         msm_reset_dm_count(port, count);
 521
 522         if (msm_port->is_uartdm > UARTDM_1P3)
 523                 msm_write(port, val, UARTDM_DMEN);
 524
 525         dma_async_issue_pending(dma->chan);
 526         return 0;
 527 unmap:
 528         dma_unmap_single(port->dev, dma->phys, count, dma->dir);
 529         return ret;
 530 }
 531
 532 static void msm_complete_rx_dma(void *args)
 533 {
 534         struct msm_port *msm_port = args;
 535         struct uart_port *port = &msm_port->uart;
 536         struct tty_port *tport = &port->state->port;
 537         struct msm_dma *dma = &msm_port->rx_dma;
 538         int count = 0, i, sysrq;
 539         unsigned long flags;
 540         u32 val;
 541
 542         spin_lock_irqsave(&port->lock, flags);
 543
 544         /* Already stopped */
 545         if (!dma->count)
 546                 goto done;
 547
 548         val = msm_read(port, UARTDM_DMEN);
 549         val &= ~dma->enable_bit;
 550         msm_write(port, val, UARTDM_DMEN);
 551
 552         if (msm_read(port, UART_SR) & UART_SR_OVERRUN) {
 553                 port->icount.overrun++;
 554                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 555                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 556         }
 557
 558         count = msm_read(port, UARTDM_RX_TOTAL_SNAP);
 559
 560         port->icount.rx += count;
 561
 562         dma->count = 0;
 563
 564         dma_unmap_single(port->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
 565
 566         for (i = 0; i < count; i++) {
 567                 char flag = TTY_NORMAL;
 568
 569                 if (msm_port->break_detected && dma->virt[i] == 0) {
 570                         port->icount.brk++;
 571                         flag = TTY_BREAK;
 572                         msm_port->break_detected = false;
 573                         if (uart_handle_break(port))
 574                                 continue;
 575                 }
 576
 577                 if (!(port->read_status_mask & UART_SR_RX_BREAK))
 578                         flag = TTY_NORMAL;
 579
 580                 spin_unlock_irqrestore(&port->lock, flags);
 581                 sysrq = uart_handle_sysrq_char(port, dma->virt[i]);
 582                 spin_lock_irqsave(&port->lock, flags);
 583                 if (!sysrq)
 584                         tty_insert_flip_char(tport, dma->virt[i], flag);
 585         }
 586
 587         msm_start_rx_dma(msm_port);
 588 done:
 589         spin_unlock_irqrestore(&port->lock, flags);
 590
 591         if (count)
 592                 tty_flip_buffer_push(tport);
 593 }
 594
 595 static void msm_start_rx_dma(struct msm_port *msm_port)
 596 {
 597         struct msm_dma *dma = &msm_port->rx_dma;
 598         struct uart_port *uart = &msm_port->uart;
 599         u32 val;
 600         int ret;
 601
 602         if (!dma->chan)
 603                 return;
 604
 605         dma->phys = dma_map_single(uart->dev, dma->virt,
 606                                    UARTDM_RX_SIZE, dma->dir);
 607         ret = dma_mapping_error(uart->dev, dma->phys);
 608         if (ret)
 609                 goto sw_mode;
 610
 611         dma->desc = dmaengine_prep_slave_single(dma->chan, dma->phys,
 612                                                 UARTDM_RX_SIZE, DMA_DEV_TO_MEM,
 613                                                 DMA_PREP_INTERRUPT);
 614         if (!dma->desc)
 615                 goto unmap;
 616
 617         dma->desc->callback = msm_complete_rx_dma;
 618         dma->desc->callback_param = msm_port;
 619
 620         dma->cookie = dmaengine_submit(dma->desc);
 621         ret = dma_submit_error(dma->cookie);
 622         if (ret)
 623                 goto unmap;
 624         /*
 625          * Using DMA for FIFO off-load, no need for "Rx FIFO over
 626          * watermark" or "stale" interrupts, disable them
 627          */
 628         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 629
 630         /*
 631          * Well, when DMA is ADM3 engine(implied by <= UARTDM v1.3),
 632          * we need RXSTALE to flush input DMA fifo to memory
 633          */
 634         if (msm_port->is_uartdm < UARTDM_1P4)
 635                 msm_port->imr |= UART_IMR_RXSTALE;
 636
 637         msm_write(uart, msm_port->imr, UART_IMR);
 638
 639         dma->count = UARTDM_RX_SIZE;
 640
 641         dma_async_issue_pending(dma->chan);
 642
 643         msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 644         msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 645
 646         val = msm_read(uart, UARTDM_DMEN);
 647         val |= dma->enable_bit;
 648
 649         if (msm_port->is_uartdm < UARTDM_1P4)
 650                 msm_write(uart, val, UARTDM_DMEN);
 651
 652         msm_write(uart, UARTDM_RX_SIZE, UARTDM_DMRX);
 653
 654         if (msm_port->is_uartdm > UARTDM_1P3)
 655                 msm_write(uart, val, UARTDM_DMEN);
 656
 657         return;
 658 unmap:
 659         dma_unmap_single(uart->dev, dma->phys, UARTDM_RX_SIZE, dma->dir);
 660
 661 sw_mode:
 662         /*
 663          * Switch from DMA to SW/FIFO mode. After clearing Rx BAM (UARTDM_DMEN),
 664          * receiver must be reset.
 665          */
 666         msm_write(uart, UART_CR_CMD_RESET_RX, UART_CR);
 667         msm_write(uart, UART_CR_RX_ENABLE, UART_CR);
 668
 669         msm_write(uart, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 670         msm_write(uart, 0xFFFFFF, UARTDM_DMRX);
 671         msm_write(uart, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 672
 673         /* Re-enable RX interrupts */
 674         msm_port->imr |= (UART_IMR_RXLEV | UART_IMR_RXSTALE);
 675         msm_write(uart, msm_port->imr, UART_IMR);
 676 }
 677
 678 static void msm_stop_rx(struct uart_port *port)
 679 {
 680         struct msm_port *msm_port = UART_TO_MSM(port);
 681         struct msm_dma *dma = &msm_port->rx_dma;
 682
 683         msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
 684         msm_write(port, msm_port->imr, UART_IMR);
 685
 686         if (dma->chan)
 687                 msm_stop_dma(port, dma);
 688 }
 689
 690 static void msm_enable_ms(struct uart_port *port)
 691 {
 692         struct msm_port *msm_port = UART_TO_MSM(port);
 693
 694         msm_port->imr |= UART_IMR_DELTA_CTS;
 695         msm_write(port, msm_port->imr, UART_IMR);
 696 }
 697
 698 static void msm_handle_rx_dm(struct uart_port *port, unsigned int misr)
 699 {
 700         struct tty_port *tport = &port->state->port;
 701         unsigned int sr;
 702         int count = 0;
 703         struct msm_port *msm_port = UART_TO_MSM(port);
 704
 705         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 706                 port->icount.overrun++;
 707                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 708                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 709         }
 710
 711         if (misr & UART_IMR_RXSTALE) {
 712                 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
 713                         msm_port->old_snap_state;
 714                 msm_port->old_snap_state = 0;
 715         } else {
 716                 count = 4 * (msm_read(port, UART_RFWR));
 717                 msm_port->old_snap_state += count;
 718         }
 719
 720         /* TODO: Precise error reporting */
 721
 722         port->icount.rx += count;
 723
 724         while (count > 0) {
 725                 unsigned char buf[4];
 726                 int sysrq, r_count, i;
 727
 728                 sr = msm_read(port, UART_SR);
 729                 if ((sr & UART_SR_RX_READY) == 0) {
 730                         msm_port->old_snap_state -= count;
 731                         break;
 732                 }
 733
 734                 ioread32_rep(port->membase + UARTDM_RF, buf, 1);
 735                 r_count = min_t(int, count, sizeof(buf));
 736
 737                 for (i = 0; i < r_count; i++) {
 738                         char flag = TTY_NORMAL;
 739
 740                         if (msm_port->break_detected && buf[i] == 0) {
 741                                 port->icount.brk++;
 742                                 flag = TTY_BREAK;
 743                                 msm_port->break_detected = false;
 744                                 if (uart_handle_break(port))
 745                                         continue;
 746                         }
 747
 748                         if (!(port->read_status_mask & UART_SR_RX_BREAK))
 749                                 flag = TTY_NORMAL;
 750
 751                         spin_unlock(&port->lock);
 752                         sysrq = uart_handle_sysrq_char(port, buf[i]);
 753                         spin_lock(&port->lock);
 754                         if (!sysrq)
 755                                 tty_insert_flip_char(tport, buf[i], flag);
 756                 }
 757                 count -= r_count;
 758         }
 759
 760         spin_unlock(&port->lock);
 761         tty_flip_buffer_push(tport);
 762         spin_lock(&port->lock);
 763
 764         if (misr & (UART_IMR_RXSTALE))
 765                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
 766         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
 767         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
 768
 769         /* Try to use DMA */
 770         msm_start_rx_dma(msm_port);
 771 }
 772
 773 static void msm_handle_rx(struct uart_port *port)
 774 {
 775         struct tty_port *tport = &port->state->port;
 776         unsigned int sr;
 777
 778         /*
 779          * Handle overrun. My understanding of the hardware is that overrun
 780          * is not tied to the RX buffer, so we handle the case out of band.
 781          */
 782         if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
 783                 port->icount.overrun++;
 784                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 785                 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
 786         }
 787
 788         /* and now the main RX loop */
 789         while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
 790                 unsigned int c;
 791                 char flag = TTY_NORMAL;
 792                 int sysrq;
 793
 794                 c = msm_read(port, UART_RF);
 795
 796                 if (sr & UART_SR_RX_BREAK) {
 797                         port->icount.brk++;
 798                         if (uart_handle_break(port))
 799                                 continue;
 800                 } else if (sr & UART_SR_PAR_FRAME_ERR) {
 801                         port->icount.frame++;
 802                 } else {
 803                         port->icount.rx++;
 804                 }
 805
 806                 /* Mask conditions we're ignorning. */
 807                 sr &= port->read_status_mask;
 808
 809                 if (sr & UART_SR_RX_BREAK)
 810                         flag = TTY_BREAK;
 811                 else if (sr & UART_SR_PAR_FRAME_ERR)
 812                         flag = TTY_FRAME;
 813
 814                 spin_unlock(&port->lock);
 815                 sysrq = uart_handle_sysrq_char(port, c);
 816                 spin_lock(&port->lock);
 817                 if (!sysrq)
 818                         tty_insert_flip_char(tport, c, flag);
 819         }
 820
 821         spin_unlock(&port->lock);
 822         tty_flip_buffer_push(tport);
 823         spin_lock(&port->lock);
 824 }
 825
 826 static void msm_handle_tx_pio(struct uart_port *port, unsigned int tx_count)
 827 {
 828         struct circ_buf *xmit = &port->state->xmit;
 829         struct msm_port *msm_port = UART_TO_MSM(port);
 830         unsigned int num_chars;
 831         unsigned int tf_pointer = 0;
 832         void __iomem *tf;
 833
 834         if (msm_port->is_uartdm)
 835                 tf = port->membase + UARTDM_TF;
 836         else
 837                 tf = port->membase + UART_TF;
 838
 839         if (tx_count && msm_port->is_uartdm)
 840                 msm_reset_dm_count(port, tx_count);
 841
 842         while (tf_pointer < tx_count) {
 843                 int i;
 844                 char buf[4] = { 0 };
 845
 846                 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
 847                         break;
 848
 849                 if (msm_port->is_uartdm)
 850                         num_chars = min(tx_count - tf_pointer,
 851                                         (unsigned int)sizeof(buf));
 852                 else
 853                         num_chars = 1;
 854
 855                 for (i = 0; i < num_chars; i++) {
 856                         buf[i] = xmit->buf[xmit->tail + i];
 857                         port->icount.tx++;
 858                 }
 859
 860                 iowrite32_rep(tf, buf, 1);
 861                 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
 862                 tf_pointer += num_chars;
 863         }
 864
 865         /* disable tx interrupts if nothing more to send */
 866         if (uart_circ_empty(xmit))
 867                 msm_stop_tx(port);
 868
 869         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 870                 uart_write_wakeup(port);
 871 }
 872
 873 static void msm_handle_tx(struct uart_port *port)
 874 {
 875         struct msm_port *msm_port = UART_TO_MSM(port);
 876         struct circ_buf *xmit = &msm_port->uart.state->xmit;
 877         struct msm_dma *dma = &msm_port->tx_dma;
 878         unsigned int pio_count, dma_count, dma_min;
 879         char buf[4] = { 0 };
 880         void __iomem *tf;
 881         int err = 0;
 882
 883         if (port->x_char) {
 884                 if (msm_port->is_uartdm)
 885                         tf = port->membase + UARTDM_TF;
 886                 else
 887                         tf = port->membase + UART_TF;
 888
 889                 buf[0] = port->x_char;
 890
 891                 if (msm_port->is_uartdm)
 892                         msm_reset_dm_count(port, 1);
 893
 894                 iowrite32_rep(tf, buf, 1);
 895                 port->icount.tx++;
 896                 port->x_char = 0;
 897                 return;
 898         }
 899
 900         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 901                 msm_stop_tx(port);
 902                 return;
 903         }
 904
 905         pio_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 906         dma_count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 907
 908         dma_min = 1;    /* Always DMA */
 909         if (msm_port->is_uartdm > UARTDM_1P3) {
 910                 dma_count = UARTDM_TX_AIGN(dma_count);
 911                 dma_min = UARTDM_BURST_SIZE;
 912         } else {
 913                 if (dma_count > UARTDM_TX_MAX)
 914                         dma_count = UARTDM_TX_MAX;
 915         }
 916
 917         if (pio_count > port->fifosize)
 918                 pio_count = port->fifosize;
 919
 920         if (!dma->chan || dma_count < dma_min)
 921                 msm_handle_tx_pio(port, pio_count);
 922         else
 923                 err = msm_handle_tx_dma(msm_port, dma_count);
 924
 925         if (err)        /* fall back to PIO mode */
 926                 msm_handle_tx_pio(port, pio_count);
 927 }
 928
 929 static void msm_handle_delta_cts(struct uart_port *port)
 930 {
 931         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
 932         port->icount.cts++;
 933         wake_up_interruptible(&port->state->port.delta_msr_wait);
 934 }
 935
 936 static irqreturn_t msm_uart_irq(int irq, void *dev_id)
 937 {
 938         struct uart_port *port = dev_id;
 939         struct msm_port *msm_port = UART_TO_MSM(port);
 940         struct msm_dma *dma = &msm_port->rx_dma;
 941         unsigned long flags;
 942         unsigned int misr;
 943         u32 val;
 944
 945         spin_lock_irqsave(&port->lock, flags);
 946         misr = msm_read(port, UART_MISR);
 947         msm_write(port, 0, UART_IMR); /* disable interrupt */
 948
 949         if (misr & UART_IMR_RXBREAK_START) {
 950                 msm_port->break_detected = true;
 951                 msm_write(port, UART_CR_CMD_RESET_RXBREAK_START, UART_CR);
 952         }
 953
 954         if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
 955                 if (dma->count) {
 956                         val = UART_CR_CMD_STALE_EVENT_DISABLE;
 957                         msm_write(port, val, UART_CR);
 958                         val = UART_CR_CMD_RESET_STALE_INT;
 959                         msm_write(port, val, UART_CR);
 960                         /*
 961                          * Flush DMA input fifo to memory, this will also
 962                          * trigger DMA RX completion
 963                          */
 964                         dmaengine_terminate_all(dma->chan);
 965                 } else if (msm_port->is_uartdm) {
 966                         msm_handle_rx_dm(port, misr);
 967                 } else {
 968                         msm_handle_rx(port);
 969                 }
 970         }
 971         if (misr & UART_IMR_TXLEV)
 972                 msm_handle_tx(port);
 973         if (misr & UART_IMR_DELTA_CTS)
 974                 msm_handle_delta_cts(port);
 975
 976         msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
 977         spin_unlock_irqrestore(&port->lock, flags);
 978
 979         return IRQ_HANDLED;
 980 }
 981
 982 static unsigned int msm_tx_empty(struct uart_port *port)
 983 {
 984         return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
 985 }
 986
 987 static unsigned int msm_get_mctrl(struct uart_port *port)
 988 {
 989         return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
 990 }
 991
 992 static void msm_reset(struct uart_port *port)
 993 {
 994         struct msm_port *msm_port = UART_TO_MSM(port);
 995         unsigned int mr;
 996
 997         /* reset everything */
 998         msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
 999         msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
1000         msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
1001         msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
1002         msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
1003         msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1004         mr = msm_read(port, UART_MR1);
1005         mr &= ~UART_MR1_RX_RDY_CTL;
1006         msm_write(port, mr, UART_MR1);
1007
1008         /* Disable DM modes */
1009         if (msm_port->is_uartdm)
1010                 msm_write(port, 0, UARTDM_DMEN);
1011 }
1012
1013 static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
1014 {
1015         unsigned int mr;
1016
1017         mr = msm_read(port, UART_MR1);
1018
1019         if (!(mctrl & TIOCM_RTS)) {
1020                 mr &= ~UART_MR1_RX_RDY_CTL;
1021                 msm_write(port, mr, UART_MR1);
1022                 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
1023         } else {
1024                 mr |= UART_MR1_RX_RDY_CTL;
1025                 msm_write(port, mr, UART_MR1);
1026         }
1027 }
1028
1029 static void msm_break_ctl(struct uart_port *port, int break_ctl)
1030 {
1031         if (break_ctl)
1032                 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
1033         else
1034                 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
1035 }
1036
1037 struct msm_baud_map {
1038         u16     divisor;
1039         u8      code;
1040         u8      rxstale;
1041 };
1042
1043 static const struct msm_baud_map *
1044 msm_find_best_baud(struct uart_port *port, unsigned int baud,
1045                    unsigned long *rate)
1046 {
1047         struct msm_port *msm_port = UART_TO_MSM(port);
1048         unsigned int divisor, result;
1049         unsigned long target, old, best_rate = 0, diff, best_diff = ULONG_MAX;
1050         const struct msm_baud_map *entry, *end, *best;
1051         static const struct msm_baud_map table[] = {
1052                 {    1, 0xff, 31 },
1053                 {    2, 0xee, 16 },
1054                 {    3, 0xdd,  8 },
1055                 {    4, 0xcc,  6 },
1056                 {    6, 0xbb,  6 },
1057                 {    8, 0xaa,  6 },
1058                 {   12, 0x99,  6 },
1059                 {   16, 0x88,  1 },
1060                 {   24, 0x77,  1 },
1061                 {   32, 0x66,  1 },
1062                 {   48, 0x55,  1 },
1063                 {   96, 0x44,  1 },
1064                 {  192, 0x33,  1 },
1065                 {  384, 0x22,  1 },
1066                 {  768, 0x11,  1 },
1067                 { 1536, 0x00,  1 },
1068         };
1069
1070         best = table; /* Default to smallest divider */
1071         target = clk_round_rate(msm_port->clk, 16 * baud);
1072         divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1073
1074         end = table + ARRAY_SIZE(table);
1075         entry = table;
1076         while (entry < end) {
1077                 if (entry->divisor <= divisor) {
1078                         result = target / entry->divisor / 16;
1079                         diff = abs(result - baud);
1080
1081                         /* Keep track of best entry */
1082                         if (diff < best_diff) {
1083                                 best_diff = diff;
1084                                 best = entry;
1085                                 best_rate = target;
1086                         }
1087
1088                         if (result == baud)
1089                                 break;
1090                 } else if (entry->divisor > divisor) {
1091                         old = target;
1092                         target = clk_round_rate(msm_port->clk, old + 1);
1093                         /*
1094                          * The rate didn't get any faster so we can't do
1095                          * better at dividing it down
1096                          */
1097                         if (target == old)
1098                                 break;
1099
1100                         /* Start the divisor search over at this new rate */
1101                         entry = table;
1102                         divisor = DIV_ROUND_CLOSEST(target, 16 * baud);
1103                         continue;
1104                 }
1105                 entry++;
1106         }
1107
1108         *rate = best_rate;
1109         return best;
1110 }
1111
1112 static int msm_set_baud_rate(struct uart_port *port, unsigned int baud,
1113                              unsigned long *saved_flags)
1114 {
1115         unsigned int rxstale, watermark, mask;
1116         struct msm_port *msm_port = UART_TO_MSM(port);
1117         const struct msm_baud_map *entry;
1118         unsigned long flags, rate;
1119
1120         flags = *saved_flags;
1121         spin_unlock_irqrestore(&port->lock, flags);
1122
1123         entry = msm_find_best_baud(port, baud, &rate);
1124         clk_set_rate(msm_port->clk, rate);
1125         baud = rate / 16 / entry->divisor;
1126
1127         spin_lock_irqsave(&port->lock, flags);
1128         *saved_flags = flags;
1129         port->uartclk = rate;
1130
1131         msm_write(port, entry->code, UART_CSR);
1132
1133         /* RX stale watermark */
1134         rxstale = entry->rxstale;
1135         watermark = UART_IPR_STALE_LSB & rxstale;
1136         if (msm_port->is_uartdm) {
1137                 mask = UART_DM_IPR_STALE_TIMEOUT_MSB;
1138         } else {
1139                 watermark |= UART_IPR_RXSTALE_LAST;
1140                 mask = UART_IPR_STALE_TIMEOUT_MSB;
1141         }
1142
1143         watermark |= mask & (rxstale << 2);
1144
1145         msm_write(port, watermark, UART_IPR);
1146
1147         /* set RX watermark */
1148         watermark = (port->fifosize * 3) / 4;
1149         msm_write(port, watermark, UART_RFWR);
1150
1151         /* set TX watermark */
1152         msm_write(port, 10, UART_TFWR);
1153
1154         msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
1155         msm_reset(port);
1156
1157         /* Enable RX and TX */
1158         msm_write(port, UART_CR_TX_ENABLE | UART_CR_RX_ENABLE, UART_CR);
1159
1160         /* turn on RX and CTS interrupts */
1161         msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
1162                         UART_IMR_CURRENT_CTS | UART_IMR_RXBREAK_START;
1163
1164         msm_write(port, msm_port->imr, UART_IMR);
1165
1166         if (msm_port->is_uartdm) {
1167                 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1168                 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1169                 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
1170         }
1171
1172         return baud;
1173 }
1174
1175 static void msm_init_clock(struct uart_port *port)
1176 {
1177         struct msm_port *msm_port = UART_TO_MSM(port);
1178
1179         clk_prepare_enable(msm_port->clk);
1180         clk_prepare_enable(msm_port->pclk);
1181         msm_serial_set_mnd_regs(port);
1182 }
1183
1184 static int msm_startup(struct uart_port *port)
1185 {
1186         struct msm_port *msm_port = UART_TO_MSM(port);
1187         unsigned int data, rfr_level, mask;
1188         int ret;
1189
1190         snprintf(msm_port->name, sizeof(msm_port->name),
1191                  "msm_serial%d", port->line);
1192
1193         msm_init_clock(port);
1194
1195         if (likely(port->fifosize > 12))
1196                 rfr_level = port->fifosize - 12;
1197         else
1198                 rfr_level = port->fifosize;
1199
1200         /* set automatic RFR level */
1201         data = msm_read(port, UART_MR1);
1202
1203         if (msm_port->is_uartdm)
1204                 mask = UART_DM_MR1_AUTO_RFR_LEVEL1;
1205         else
1206                 mask = UART_MR1_AUTO_RFR_LEVEL1;
1207
1208         data &= ~mask;
1209         data &= ~UART_MR1_AUTO_RFR_LEVEL0;
1210         data |= mask & (rfr_level << 2);
1211         data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
1212         msm_write(port, data, UART_MR1);
1213
1214         if (msm_port->is_uartdm) {
1215                 msm_request_tx_dma(msm_port, msm_port->uart.mapbase);
1216                 msm_request_rx_dma(msm_port, msm_port->uart.mapbase);
1217         }
1218
1219         ret = request_irq(port->irq, msm_uart_irq, IRQF_TRIGGER_HIGH,
1220                           msm_port->name, port);
1221         if (unlikely(ret))
1222                 goto err_irq;
1223
1224         return 0;
1225
1226 err_irq:
1227         if (msm_port->is_uartdm)
1228                 msm_release_dma(msm_port);
1229
1230         clk_disable_unprepare(msm_port->pclk);
1231         clk_disable_unprepare(msm_port->clk);
1232
1233         return ret;
1234 }
1235
1236 static void msm_shutdown(struct uart_port *port)
1237 {
1238         struct msm_port *msm_port = UART_TO_MSM(port);
1239
1240         msm_port->imr = 0;
1241         msm_write(port, 0, UART_IMR); /* disable interrupts */
1242
1243         if (msm_port->is_uartdm)
1244                 msm_release_dma(msm_port);
1245
1246         clk_disable_unprepare(msm_port->clk);
1247
1248         free_irq(port->irq, port);
1249 }
1250
1251 static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
1252                             struct ktermios *old)
1253 {
1254         struct msm_port *msm_port = UART_TO_MSM(port);
1255         struct msm_dma *dma = &msm_port->rx_dma;
1256         unsigned long flags;
1257         unsigned int baud, mr;
1258
1259         spin_lock_irqsave(&port->lock, flags);
1260
1261         if (dma->chan) /* Terminate if any */
1262                 msm_stop_dma(port, dma);
1263
1264         /* calculate and set baud rate */
1265         baud = uart_get_baud_rate(port, termios, old, 300, 4000000);
1266         baud = msm_set_baud_rate(port, baud, &flags);
1267         if (tty_termios_baud_rate(termios))
1268                 tty_termios_encode_baud_rate(termios, baud, baud);
1269
1270         /* calculate parity */
1271         mr = msm_read(port, UART_MR2);
1272         mr &= ~UART_MR2_PARITY_MODE;
1273         if (termios->c_cflag & PARENB) {
1274                 if (termios->c_cflag & PARODD)
1275                         mr |= UART_MR2_PARITY_MODE_ODD;
1276                 else if (termios->c_cflag & CMSPAR)
1277                         mr |= UART_MR2_PARITY_MODE_SPACE;
1278                 else
1279                         mr |= UART_MR2_PARITY_MODE_EVEN;
1280         }
1281
1282         /* calculate bits per char */
1283         mr &= ~UART_MR2_BITS_PER_CHAR;
1284         switch (termios->c_cflag & CSIZE) {
1285         case CS5:
1286                 mr |= UART_MR2_BITS_PER_CHAR_5;
1287                 break;
1288         case CS6:
1289                 mr |= UART_MR2_BITS_PER_CHAR_6;
1290                 break;
1291         case CS7:
1292                 mr |= UART_MR2_BITS_PER_CHAR_7;
1293                 break;
1294         case CS8:
1295         default:
1296                 mr |= UART_MR2_BITS_PER_CHAR_8;
1297                 break;
1298         }
1299
1300         /* calculate stop bits */
1301         mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
1302         if (termios->c_cflag & CSTOPB)
1303                 mr |= UART_MR2_STOP_BIT_LEN_TWO;
1304         else
1305                 mr |= UART_MR2_STOP_BIT_LEN_ONE;
1306
1307         /* set parity, bits per char, and stop bit */
1308         msm_write(port, mr, UART_MR2);
1309
1310         /* calculate and set hardware flow control */
1311         mr = msm_read(port, UART_MR1);
1312         mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
1313         if (termios->c_cflag & CRTSCTS) {
1314                 mr |= UART_MR1_CTS_CTL;
1315                 mr |= UART_MR1_RX_RDY_CTL;
1316         }
1317         msm_write(port, mr, UART_MR1);
1318
1319         /* Configure status bits to ignore based on termio flags. */
1320         port->read_status_mask = 0;
1321         if (termios->c_iflag & INPCK)
1322                 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
1323         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1324                 port->read_status_mask |= UART_SR_RX_BREAK;
1325
1326         uart_update_timeout(port, termios->c_cflag, baud);
1327
1328         /* Try to use DMA */
1329         msm_start_rx_dma(msm_port);
1330
1331         spin_unlock_irqrestore(&port->lock, flags);
1332 }
1333
1334 static const char *msm_type(struct uart_port *port)
1335 {
1336         return "MSM";
1337 }
1338
1339 static void msm_release_port(struct uart_port *port)
1340 {
1341         struct platform_device *pdev = to_platform_device(port->dev);
1342         struct resource *uart_resource;
1343         resource_size_t size;
1344
1345         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1346         if (unlikely(!uart_resource))
1347                 return;
1348         size = resource_size(uart_resource);
1349
1350         release_mem_region(port->mapbase, size);
1351         iounmap(port->membase);
1352         port->membase = NULL;
1353 }
1354
1355 static int msm_request_port(struct uart_port *port)
1356 {
1357         struct platform_device *pdev = to_platform_device(port->dev);
1358         struct resource *uart_resource;
1359         resource_size_t size;
1360         int ret;
1361
1362         uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1363         if (unlikely(!uart_resource))
1364                 return -ENXIO;
1365
1366         size = resource_size(uart_resource);
1367
1368         if (!request_mem_region(port->mapbase, size, "msm_serial"))
1369                 return -EBUSY;
1370
1371         port->membase = ioremap(port->mapbase, size);
1372         if (!port->membase) {
1373                 ret = -EBUSY;
1374                 goto fail_release_port;
1375         }
1376
1377         return 0;
1378
1379 fail_release_port:
1380         release_mem_region(port->mapbase, size);
1381         return ret;
1382 }
1383
1384 static void msm_config_port(struct uart_port *port, int flags)
1385 {
1386         int ret;
1387
1388         if (flags & UART_CONFIG_TYPE) {
1389                 port->type = PORT_MSM;
1390                 ret = msm_request_port(port);
1391                 if (ret)
1392                         return;
1393         }
1394 }
1395
1396 static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
1397 {
1398         if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
1399                 return -EINVAL;
1400         if (unlikely(port->irq != ser->irq))
1401                 return -EINVAL;
1402         return 0;
1403 }
1404
1405 static void msm_power(struct uart_port *port, unsigned int state,
1406                       unsigned int oldstate)
1407 {
1408         struct msm_port *msm_port = UART_TO_MSM(port);
1409
1410         switch (state) {
1411         case 0:
1412                 clk_prepare_enable(msm_port->clk);
1413                 clk_prepare_enable(msm_port->pclk);
1414                 break;
1415         case 3:
1416                 clk_disable_unprepare(msm_port->clk);
1417                 clk_disable_unprepare(msm_port->pclk);
1418                 break;
1419         default:
1420                 pr_err("msm_serial: Unknown PM state %d\n", state);
1421         }
1422 }
1423
1424 #ifdef CONFIG_CONSOLE_POLL
1425 static int msm_poll_get_char_single(struct uart_port *port)
1426 {
1427         struct msm_port *msm_port = UART_TO_MSM(port);
1428         unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
1429
1430         if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
1431                 return NO_POLL_CHAR;
1432
1433         return msm_read(port, rf_reg) & 0xff;
1434 }
1435
1436 static int msm_poll_get_char_dm(struct uart_port *port)
1437 {
1438         int c;
1439         static u32 slop;
1440         static int count;
1441         unsigned char *sp = (unsigned char *)&slop;
1442
1443         /* Check if a previous read had more than one char */
1444         if (count) {
1445                 c = sp[sizeof(slop) - count];
1446                 count--;
1447         /* Or if FIFO is empty */
1448         } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
1449                 /*
1450                  * If RX packing buffer has less than a word, force stale to
1451                  * push contents into RX FIFO
1452                  */
1453                 count = msm_read(port, UARTDM_RXFS);
1454                 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
1455                 if (count) {
1456                         msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
1457                         slop = msm_read(port, UARTDM_RF);
1458                         c = sp[0];
1459                         count--;
1460                         msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
1461                         msm_write(port, 0xFFFFFF, UARTDM_DMRX);
1462                         msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE,
1463                                   UART_CR);
1464                 } else {
1465                         c = NO_POLL_CHAR;
1466                 }
1467         /* FIFO has a word */
1468         } else {
1469                 slop = msm_read(port, UARTDM_RF);
1470                 c = sp[0];
1471                 count = sizeof(slop) - 1;
1472         }
1473
1474         return c;
1475 }
1476
1477 static int msm_poll_get_char(struct uart_port *port)
1478 {
1479         u32 imr;
1480         int c;
1481         struct msm_port *msm_port = UART_TO_MSM(port);
1482
1483         /* Disable all interrupts */
1484         imr = msm_read(port, UART_IMR);
1485         msm_write(port, 0, UART_IMR);
1486
1487         if (msm_port->is_uartdm)
1488                 c = msm_poll_get_char_dm(port);
1489         else
1490                 c = msm_poll_get_char_single(port);
1491
1492         /* Enable interrupts */
1493         msm_write(port, imr, UART_IMR);
1494
1495         return c;
1496 }
1497
1498 static void msm_poll_put_char(struct uart_port *port, unsigned char c)
1499 {
1500         u32 imr;
1501         struct msm_port *msm_port = UART_TO_MSM(port);
1502
1503         /* Disable all interrupts */
1504         imr = msm_read(port, UART_IMR);
1505         msm_write(port, 0, UART_IMR);
1506
1507         if (msm_port->is_uartdm)
1508                 msm_reset_dm_count(port, 1);
1509
1510         /* Wait until FIFO is empty */
1511         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1512                 cpu_relax();
1513
1514         /* Write a character */
1515         msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
1516
1517         /* Wait until FIFO is empty */
1518         while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1519                 cpu_relax();
1520
1521         /* Enable interrupts */
1522         msm_write(port, imr, UART_IMR);
1523 }
1524 #endif
1525
1526 static struct uart_ops msm_uart_pops = {
1527         .tx_empty = msm_tx_empty,
1528         .set_mctrl = msm_set_mctrl,
1529         .get_mctrl = msm_get_mctrl,
1530         .stop_tx = msm_stop_tx,
1531         .start_tx = msm_start_tx,
1532         .stop_rx = msm_stop_rx,
1533         .enable_ms = msm_enable_ms,
1534         .break_ctl = msm_break_ctl,
1535         .startup = msm_startup,
1536         .shutdown = msm_shutdown,
1537         .set_termios = msm_set_termios,
1538         .type = msm_type,
1539         .release_port = msm_release_port,
1540         .request_port = msm_request_port,
1541         .config_port = msm_config_port,
1542         .verify_port = msm_verify_port,
1543         .pm = msm_power,
1544 #ifdef CONFIG_CONSOLE_POLL
1545         .poll_get_char  = msm_poll_get_char,
1546         .poll_put_char  = msm_poll_put_char,
1547 #endif
1548 };
1549
1550 static struct msm_port msm_uart_ports[] = {
1551         {
1552                 .uart = {
1553                         .iotype = UPIO_MEM,
1554                         .ops = &msm_uart_pops,
1555                         .flags = UPF_BOOT_AUTOCONF,
1556                         .fifosize = 64,
1557                         .line = 0,
1558                 },
1559         },
1560         {
1561                 .uart = {
1562                         .iotype = UPIO_MEM,
1563                         .ops = &msm_uart_pops,
1564                         .flags = UPF_BOOT_AUTOCONF,
1565                         .fifosize = 64,
1566                         .line = 1,
1567                 },
1568         },
1569         {
1570                 .uart = {
1571                         .iotype = UPIO_MEM,
1572                         .ops = &msm_uart_pops,
1573                         .flags = UPF_BOOT_AUTOCONF,
1574                         .fifosize = 64,
1575                         .line = 2,
1576                 },
1577         },
1578 };
1579
1580 #define UART_NR ARRAY_SIZE(msm_uart_ports)
1581
1582 static inline struct uart_port *msm_get_port_from_line(unsigned int line)
1583 {
1584         return &msm_uart_ports[line].uart;
1585 }
1586
1587 #ifdef CONFIG_SERIAL_MSM_CONSOLE
1588 static void __msm_console_write(struct uart_port *port, const char *s,
1589                                 unsigned int count, bool is_uartdm)
1590 {
1591         int i;
1592         int num_newlines = 0;
1593         bool replaced = false;
1594         void __iomem *tf;
1595         int locked = 1;
1596
1597         if (is_uartdm)
1598                 tf = port->membase + UARTDM_TF;
1599         else
1600                 tf = port->membase + UART_TF;
1601
1602         /* Account for newlines that will get a carriage return added */
1603         for (i = 0; i < count; i++)
1604                 if (s[i] == '\n')
1605                         num_newlines++;
1606         count += num_newlines;
1607
1608         if (port->sysrq)
1609                 locked = 0;
1610         else if (oops_in_progress)
1611                 locked = spin_trylock(&port->lock);
1612         else
1613                 spin_lock(&port->lock);
1614
1615         if (is_uartdm)
1616                 msm_reset_dm_count(port, count);
1617
1618         i = 0;
1619         while (i < count) {
1620                 int j;
1621                 unsigned int num_chars;
1622                 char buf[4] = { 0 };
1623
1624                 if (is_uartdm)
1625                         num_chars = min(count - i, (unsigned int)sizeof(buf));
1626                 else
1627                         num_chars = 1;
1628
1629                 for (j = 0; j < num_chars; j++) {
1630                         char c = *s;
1631
1632                         if (c == '\n' && !replaced) {
1633                                 buf[j] = '\r';
1634                                 j++;
1635                                 replaced = true;
1636                         }
1637                         if (j < num_chars) {
1638                                 buf[j] = c;
1639                                 s++;
1640                                 replaced = false;
1641                         }
1642                 }
1643
1644                 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
1645                         cpu_relax();
1646
1647                 iowrite32_rep(tf, buf, 1);
1648                 i += num_chars;
1649         }
1650
1651         if (locked)
1652                 spin_unlock(&port->lock);
1653 }
1654
1655 static void msm_console_write(struct console *co, const char *s,
1656                               unsigned int count)
1657 {
1658         struct uart_port *port;
1659         struct msm_port *msm_port;
1660
1661         BUG_ON(co->index < 0 || co->index >= UART_NR);
1662
1663         port = msm_get_port_from_line(co->index);
1664         msm_port = UART_TO_MSM(port);
1665
1666         __msm_console_write(port, s, count, msm_port->is_uartdm);
1667 }
1668
1669 static int msm_console_setup(struct console *co, char *options)
1670 {
1671         struct uart_port *port;
1672         int baud = 115200;
1673         int bits = 8;
1674         int parity = 'n';
1675         int flow = 'n';
1676
1677         if (unlikely(co->index >= UART_NR || co->index < 0))
1678                 return -ENXIO;
1679
1680         port = msm_get_port_from_line(co->index);
1681
1682         if (unlikely(!port->membase))
1683                 return -ENXIO;
1684
1685         msm_init_clock(port);
1686
1687         if (options)
1688                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1689
1690         pr_info("msm_serial: console setup on port #%d\n", port->line);
1691
1692         return uart_set_options(port, co, baud, parity, bits, flow);
1693 }
1694
1695 static void
1696 msm_serial_early_write(struct console *con, const char *s, unsigned n)
1697 {
1698         struct earlycon_device *dev = con->data;
1699
1700         __msm_console_write(&dev->port, s, n, false);
1701 }
1702
1703 static int __init
1704 msm_serial_early_console_setup(struct earlycon_device *device, const char *opt)
1705 {
1706         if (!device->port.membase)
1707                 return -ENODEV;
1708
1709         device->con->write = msm_serial_early_write;
1710         return 0;
1711 }
1712 OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
1713                     msm_serial_early_console_setup);
1714
1715 static void
1716 msm_serial_early_write_dm(struct console *con, const char *s, unsigned n)
1717 {
1718         struct earlycon_device *dev = con->data;
1719
1720         __msm_console_write(&dev->port, s, n, true);
1721 }
1722
1723 static int __init
1724 msm_serial_early_console_setup_dm(struct earlycon_device *device,
1725                                   const char *opt)
1726 {
1727         if (!device->port.membase)
1728                 return -ENODEV;
1729
1730         device->con->write = msm_serial_early_write_dm;
1731         return 0;
1732 }
1733 OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
1734                     msm_serial_early_console_setup_dm);
1735
1736 static struct uart_driver msm_uart_driver;
1737
1738 static struct console msm_console = {
1739         .name = "ttyMSM",
1740         .write = msm_console_write,
1741         .device = uart_console_device,
1742         .setup = msm_console_setup,
1743         .flags = CON_PRINTBUFFER,
1744         .index = -1,
1745         .data = &msm_uart_driver,
1746 };
1747
1748 #define MSM_CONSOLE     (&msm_console)
1749
1750 #else
1751 #define MSM_CONSOLE     NULL
1752 #endif
1753
1754 static struct uart_driver msm_uart_driver = {
1755         .owner = THIS_MODULE,
1756         .driver_name = "msm_serial",
1757         .dev_name = "ttyMSM",
1758         .nr = UART_NR,
1759         .cons = MSM_CONSOLE,
1760 };
1761
1762 static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1763
1764 static const struct of_device_id msm_uartdm_table[] = {
1765         { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1766         { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1767         { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1768         { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1769         { }
1770 };
1771
1772 static int msm_serial_probe(struct platform_device *pdev)
1773 {
1774         struct msm_port *msm_port;
1775         struct resource *resource;
1776         struct uart_port *port;
1777         const struct of_device_id *id;
1778         int irq, line;
1779
1780         if (pdev->dev.of_node)
1781                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1782         else
1783                 line = pdev->id;
1784
1785         if (line < 0)
1786                 line = atomic_inc_return(&msm_uart_next_id) - 1;
1787
1788         if (unlikely(line < 0 || line >= UART_NR))
1789                 return -ENXIO;
1790
1791         dev_info(&pdev->dev, "msm_serial: detected port #%d\n", line);
1792
1793         port = msm_get_port_from_line(line);
1794         port->dev = &pdev->dev;
1795         msm_port = UART_TO_MSM(port);
1796
1797         id = of_match_device(msm_uartdm_table, &pdev->dev);
1798         if (id)
1799                 msm_port->is_uartdm = (unsigned long)id->data;
1800         else
1801                 msm_port->is_uartdm = 0;
1802
1803         msm_port->clk = devm_clk_get(&pdev->dev, "core");
1804         if (IS_ERR(msm_port->clk))
1805                 return PTR_ERR(msm_port->clk);
1806
1807         if (msm_port->is_uartdm) {
1808                 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1809                 if (IS_ERR(msm_port->pclk))
1810                         return PTR_ERR(msm_port->pclk);
1811         }
1812
1813         port->uartclk = clk_get_rate(msm_port->clk);
1814         dev_info(&pdev->dev, "uartclk = %d\n", port->uartclk);
1815
1816         resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1817         if (unlikely(!resource))
1818                 return -ENXIO;
1819         port->mapbase = resource->start;
1820
1821         irq = platform_get_irq(pdev, 0);
1822         if (unlikely(irq < 0))
1823                 return -ENXIO;
1824         port->irq = irq;
1825         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_MSM_CONSOLE);
1826
1827         platform_set_drvdata(pdev, port);
1828
1829         return uart_add_one_port(&msm_uart_driver, port);
1830 }
1831
1832 static int msm_serial_remove(struct platform_device *pdev)
1833 {
1834         struct uart_port *port = platform_get_drvdata(pdev);
1835
1836         uart_remove_one_port(&msm_uart_driver, port);
1837
1838         return 0;
1839 }
1840
1841 static const struct of_device_id msm_match_table[] = {
1842         { .compatible = "qcom,msm-uart" },
1843         { .compatible = "qcom,msm-uartdm" },
1844         {}
1845 };
1846 MODULE_DEVICE_TABLE(of, msm_match_table);
1847
1848 static int __maybe_unused msm_serial_suspend(struct device *dev)
1849 {
1850         struct msm_port *port = dev_get_drvdata(dev);
1851
1852         uart_suspend_port(&msm_uart_driver, &port->uart);
1853
1854         return 0;
1855 }
1856
1857 static int __maybe_unused msm_serial_resume(struct device *dev)
1858 {
1859         struct msm_port *port = dev_get_drvdata(dev);
1860
1861         uart_resume_port(&msm_uart_driver, &port->uart);
1862
1863         return 0;
1864 }
1865
1866 static const struct dev_pm_ops msm_serial_dev_pm_ops = {
1867         SET_SYSTEM_SLEEP_PM_OPS(msm_serial_suspend, msm_serial_resume)
1868 };
1869
1870 static struct platform_driver msm_platform_driver = {
1871         .remove = msm_serial_remove,
1872         .probe = msm_serial_probe,
1873         .driver = {
1874                 .name = "msm_serial",
1875                 .pm = &msm_serial_dev_pm_ops,
1876                 .of_match_table = msm_match_table,
1877         },
1878 };
1879
1880 static int __init msm_serial_init(void)
1881 {
1882         int ret;
1883
1884         ret = uart_register_driver(&msm_uart_driver);
1885         if (unlikely(ret))
1886                 return ret;
1887
1888         ret = platform_driver_register(&msm_platform_driver);
1889         if (unlikely(ret))
1890                 uart_unregister_driver(&msm_uart_driver);
1891
1892         pr_info("msm_serial: driver initialized\n");
1893
1894         return ret;
1895 }
1896
1897 static void __exit msm_serial_exit(void)
1898 {
1899         platform_driver_unregister(&msm_platform_driver);
1900         uart_unregister_driver(&msm_uart_driver);
1901 }
1902
1903 module_init(msm_serial_init);
1904 module_exit(msm_serial_exit);
1905
1906 MODULE_AUTHOR("Robert Love <rlove@google.com>");
1907 MODULE_DESCRIPTION("Driver for msm7x serial device");
1908 MODULE_LICENSE("GPL");