1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
5 #include <linux/console.h>
7 #include <linux/iopoll.h>
9 #include <linux/module.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/pm_wakeirq.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/serial.h>
17 #include <linux/serial_core.h>
18 #include <linux/slab.h>
19 #include <linux/tty.h>
20 #include <linux/tty_flip.h>
22 /* UART specific GENI registers */
23 #define SE_UART_LOOPBACK_CFG 0x22c
24 #define SE_UART_TX_TRANS_CFG 0x25c
25 #define SE_UART_TX_WORD_LEN 0x268
26 #define SE_UART_TX_STOP_BIT_LEN 0x26c
27 #define SE_UART_TX_TRANS_LEN 0x270
28 #define SE_UART_RX_TRANS_CFG 0x280
29 #define SE_UART_RX_WORD_LEN 0x28c
30 #define SE_UART_RX_STALE_CNT 0x294
31 #define SE_UART_TX_PARITY_CFG 0x2a4
32 #define SE_UART_RX_PARITY_CFG 0x2a8
33 #define SE_UART_MANUAL_RFR 0x2ac
35 /* SE_UART_TRANS_CFG */
36 #define UART_TX_PAR_EN BIT(0)
37 #define UART_CTS_MASK BIT(1)
39 /* SE_UART_TX_WORD_LEN */
40 #define TX_WORD_LEN_MSK GENMASK(9, 0)
42 /* SE_UART_TX_STOP_BIT_LEN */
43 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
44 #define TX_STOP_BIT_LEN_1 0
45 #define TX_STOP_BIT_LEN_1_5 1
46 #define TX_STOP_BIT_LEN_2 2
48 /* SE_UART_TX_TRANS_LEN */
49 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
51 /* SE_UART_RX_TRANS_CFG */
52 #define UART_RX_INS_STATUS_BIT BIT(2)
53 #define UART_RX_PAR_EN BIT(3)
55 /* SE_UART_RX_WORD_LEN */
56 #define RX_WORD_LEN_MASK GENMASK(9, 0)
58 /* SE_UART_RX_STALE_CNT */
59 #define RX_STALE_CNT GENMASK(23, 0)
61 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
62 #define PAR_CALC_EN BIT(0)
63 #define PAR_MODE_MSK GENMASK(2, 1)
64 #define PAR_MODE_SHFT 1
67 #define PAR_SPACE 0x10
70 /* SE_UART_MANUAL_RFR register fields */
71 #define UART_MANUAL_RFR_EN BIT(31)
72 #define UART_RFR_NOT_READY BIT(1)
73 #define UART_RFR_READY BIT(0)
75 /* UART M_CMD OP codes */
76 #define UART_START_TX 0x1
77 #define UART_START_BREAK 0x4
78 #define UART_STOP_BREAK 0x5
79 /* UART S_CMD OP codes */
80 #define UART_START_READ 0x1
81 #define UART_PARAM 0x1
83 #define UART_OVERSAMPLING 32
84 #define STALE_TIMEOUT 16
85 #define DEFAULT_BITS_PER_CHAR 10
86 #define GENI_UART_CONS_PORTS 1
87 #define GENI_UART_PORTS 3
88 #define DEF_FIFO_DEPTH_WORDS 16
90 #define DEF_FIFO_WIDTH_BITS 32
93 /* SE_UART_LOOPBACK_CFG */
94 #define RX_TX_SORTED BIT(0)
95 #define CTS_RTS_SORTED BIT(1)
96 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
98 #ifdef CONFIG_CONSOLE_POLL
99 #define CONSOLE_RX_BYTES_PW 1
101 #define CONSOLE_RX_BYTES_PW 4
104 struct qcom_geni_serial_port {
105 struct uart_port uport;
112 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
114 unsigned int tx_bytes_pw;
115 unsigned int rx_bytes_pw;
120 unsigned int tx_remaining;
124 static const struct uart_ops qcom_geni_console_pops;
125 static const struct uart_ops qcom_geni_uart_pops;
126 static struct uart_driver qcom_geni_console_driver;
127 static struct uart_driver qcom_geni_uart_driver;
128 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
129 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
130 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
131 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
132 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
134 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
135 32000000, 48000000, 64000000, 80000000,
136 96000000, 100000000, 102400000,
137 112000000, 120000000, 128000000};
139 #define to_dev_port(ptr, member) \
140 container_of(ptr, struct qcom_geni_serial_port, member)
142 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
146 .ops = &qcom_geni_uart_pops,
147 .flags = UPF_BOOT_AUTOCONF,
154 .ops = &qcom_geni_uart_pops,
155 .flags = UPF_BOOT_AUTOCONF,
162 .ops = &qcom_geni_uart_pops,
163 .flags = UPF_BOOT_AUTOCONF,
169 static struct qcom_geni_serial_port qcom_geni_console_port = {
172 .ops = &qcom_geni_console_pops,
173 .flags = UPF_BOOT_AUTOCONF,
178 static int qcom_geni_serial_request_port(struct uart_port *uport)
180 struct platform_device *pdev = to_platform_device(uport->dev);
181 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
183 uport->membase = devm_platform_ioremap_resource(pdev, 0);
184 if (IS_ERR(uport->membase))
185 return PTR_ERR(uport->membase);
186 port->se.base = uport->membase;
190 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
192 if (cfg_flags & UART_CONFIG_TYPE) {
193 uport->type = PORT_MSM;
194 qcom_geni_serial_request_port(uport);
198 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
200 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
203 if (uart_console(uport)) {
206 geni_ios = readl(uport->membase + SE_GENI_IOS);
207 if (!(geni_ios & IO2_DATA_IN))
214 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
217 u32 uart_manual_rfr = 0;
218 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
220 if (uart_console(uport))
223 if (mctrl & TIOCM_LOOP)
224 port->loopback = RX_TX_CTS_RTS_SORTED;
226 if (!(mctrl & TIOCM_RTS))
227 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
228 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
231 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
236 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
238 struct qcom_geni_serial_port *port;
239 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
241 if (line < 0 || line >= nr_ports)
242 return ERR_PTR(-ENXIO);
244 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
248 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
249 int offset, int field, bool set)
252 struct qcom_geni_serial_port *port;
254 unsigned int fifo_bits;
255 unsigned long timeout_us = 20000;
257 if (uport->private_data) {
258 port = to_dev_port(uport, uport);
262 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
264 * Total polling iterations based on FIFO worth of bytes to be
265 * sent at current baud. Add a little fluff to the wait.
267 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
271 * Use custom implementation instead of readl_poll_atomic since ktimer
272 * is not ready at the time of early console.
274 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
276 reg = readl(uport->membase + offset);
277 if ((bool)(reg & field) == set)
285 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
289 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
290 m_cmd = UART_START_TX << M_OPCODE_SHFT;
291 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
294 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
297 u32 irq_clear = M_CMD_DONE_EN;
299 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
300 M_CMD_DONE_EN, true);
302 writel(M_GENI_CMD_ABORT, uport->membase +
303 SE_GENI_M_CMD_CTRL_REG);
304 irq_clear |= M_CMD_ABORT_EN;
305 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
306 M_CMD_ABORT_EN, true);
308 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
311 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
313 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
315 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
316 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
317 S_GENI_CMD_ABORT, false);
318 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
319 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
322 #ifdef CONFIG_CONSOLE_POLL
323 static int qcom_geni_serial_get_char(struct uart_port *uport)
328 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
329 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
331 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
332 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
334 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
335 if (!(status & RX_FIFO_WC_MSK))
338 rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
339 return rx_fifo & 0xff;
342 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
345 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
346 qcom_geni_serial_setup_tx(uport, 1);
347 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
348 M_TX_FIFO_WATERMARK_EN, true));
349 writel(c, uport->membase + SE_GENI_TX_FIFOn);
350 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
351 qcom_geni_serial_poll_tx_done(uport);
355 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
356 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
358 writel(ch, uport->membase + SE_GENI_TX_FIFOn);
362 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
366 u32 bytes_to_send = count;
368 for (i = 0; i < count; i++) {
370 * uart_console_write() adds a carriage return for each newline.
371 * Account for additional bytes to be written.
377 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
378 qcom_geni_serial_setup_tx(uport, bytes_to_send);
379 for (i = 0; i < count; ) {
380 size_t chars_to_write = 0;
381 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
384 * If the WM bit never set, then the Tx state machine is not
385 * in a valid state, so break, cancel/abort any existing
386 * command. Unfortunately the current data being written is
389 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
390 M_TX_FIFO_WATERMARK_EN, true))
392 chars_to_write = min_t(size_t, count - i, avail / 2);
393 uart_console_write(uport, s + i, chars_to_write,
394 qcom_geni_serial_wr_char);
395 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
396 SE_GENI_M_IRQ_CLEAR);
399 qcom_geni_serial_poll_tx_done(uport);
402 static void qcom_geni_serial_console_write(struct console *co, const char *s,
405 struct uart_port *uport;
406 struct qcom_geni_serial_port *port;
412 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
414 port = get_port_from_line(co->index, true);
418 uport = &port->uport;
419 if (oops_in_progress)
420 locked = spin_trylock_irqsave(&uport->lock, flags);
422 spin_lock_irqsave(&uport->lock, flags);
424 geni_status = readl(uport->membase + SE_GENI_STATUS);
426 /* Cancel the current write to log the fault */
428 geni_se_cancel_m_cmd(&port->se);
429 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
430 M_CMD_CANCEL_EN, true)) {
431 geni_se_abort_m_cmd(&port->se);
432 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
433 M_CMD_ABORT_EN, true);
434 writel(M_CMD_ABORT_EN, uport->membase +
435 SE_GENI_M_IRQ_CLEAR);
437 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
438 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
440 * It seems we can't interrupt existing transfers if all data
441 * has been sent, in which case we need to look for done first.
443 qcom_geni_serial_poll_tx_done(uport);
445 if (uart_circ_chars_pending(&uport->state->xmit)) {
446 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
447 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
448 uport->membase + SE_GENI_M_IRQ_EN);
452 __qcom_geni_serial_console_write(uport, s, count);
454 if (port->tx_remaining)
455 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
458 spin_unlock_irqrestore(&uport->lock, flags);
461 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
464 unsigned char buf[sizeof(u32)];
465 struct tty_port *tport;
466 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
468 tport = &uport->state->port;
469 for (i = 0; i < bytes; ) {
471 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
473 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
478 for (c = 0; c < chunk; c++) {
482 if (port->brk && buf[c] == 0) {
484 if (uart_handle_break(uport))
488 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
491 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
495 tty_flip_buffer_push(tport);
499 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
504 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
506 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
509 struct tty_port *tport;
510 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
511 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
512 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
515 tport = &uport->state->port;
516 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
520 buf = (unsigned char *)port->rx_fifo;
521 ret = tty_insert_flip_string(tport, buf, bytes);
523 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
524 __func__, ret, bytes);
527 uport->icount.rx += ret;
528 tty_flip_buffer_push(tport);
532 static void qcom_geni_serial_start_tx(struct uart_port *uport)
537 status = readl(uport->membase + SE_GENI_STATUS);
538 if (status & M_GENI_CMD_ACTIVE)
541 if (!qcom_geni_serial_tx_empty(uport))
544 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
545 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
547 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
548 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
551 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
555 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
557 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
558 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
559 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
560 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
561 status = readl(uport->membase + SE_GENI_STATUS);
562 /* Possible stop tx is called multiple times. */
563 if (!(status & M_GENI_CMD_ACTIVE))
566 geni_se_cancel_m_cmd(&port->se);
567 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
568 M_CMD_CANCEL_EN, true)) {
569 geni_se_abort_m_cmd(&port->se);
570 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
571 M_CMD_ABORT_EN, true);
572 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
574 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
577 static void qcom_geni_serial_start_rx(struct uart_port *uport)
581 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
583 status = readl(uport->membase + SE_GENI_STATUS);
584 if (status & S_GENI_CMD_ACTIVE)
585 qcom_geni_serial_stop_rx(uport);
587 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
589 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
590 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
591 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
593 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
594 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
595 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
598 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
602 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
605 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
606 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
607 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
609 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
610 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
611 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
613 status = readl(uport->membase + SE_GENI_STATUS);
614 /* Possible stop rx is called multiple times. */
615 if (!(status & S_GENI_CMD_ACTIVE))
618 geni_se_cancel_s_cmd(&port->se);
619 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
620 S_CMD_CANCEL_EN, true);
622 * If timeout occurs secondary engine remains active
623 * and Abort sequence is executed.
625 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
626 /* Flush the Rx buffer */
627 if (s_irq_status & S_RX_FIFO_LAST_EN)
628 qcom_geni_serial_handle_rx(uport, true);
629 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
631 status = readl(uport->membase + SE_GENI_STATUS);
632 if (status & S_GENI_CMD_ACTIVE)
633 qcom_geni_serial_abort_rx(uport);
636 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
640 u32 last_word_byte_cnt;
641 u32 last_word_partial;
643 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
645 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
646 word_cnt = status & RX_FIFO_WC_MSK;
647 last_word_partial = status & RX_LAST;
648 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
649 RX_LAST_BYTE_VALID_SHFT;
653 total_bytes = port->rx_bytes_pw * (word_cnt - 1);
654 if (last_word_partial && last_word_byte_cnt)
655 total_bytes += last_word_byte_cnt;
657 total_bytes += port->rx_bytes_pw;
658 port->handle_rx(uport, total_bytes, drop);
661 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
664 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
665 struct circ_buf *xmit = &uport->state->xmit;
675 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
677 /* Complete the current tx command before taking newly added data */
679 pending = port->tx_remaining;
681 pending = uart_circ_chars_pending(xmit);
683 /* All data has been transmitted and acknowledged as received */
684 if (!pending && !status && done) {
685 qcom_geni_serial_stop_tx(uport);
686 goto out_write_wakeup;
689 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
690 avail *= port->tx_bytes_pw;
693 chunk = min(avail, pending);
695 goto out_write_wakeup;
697 if (!port->tx_remaining) {
698 qcom_geni_serial_setup_tx(uport, pending);
699 port->tx_remaining = pending;
701 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
702 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
703 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
704 uport->membase + SE_GENI_M_IRQ_EN);
708 for (i = 0; i < chunk; ) {
709 unsigned int tx_bytes;
713 memset(buf, 0, ARRAY_SIZE(buf));
714 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
716 for (c = 0; c < tx_bytes ; c++) {
717 buf[c] = xmit->buf[tail++];
718 tail &= UART_XMIT_SIZE - 1;
721 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
724 uport->icount.tx += tx_bytes;
725 remaining -= tx_bytes;
726 port->tx_remaining -= tx_bytes;
732 * The tx fifo watermark is level triggered and latched. Though we had
733 * cleared it in qcom_geni_serial_isr it will have already reasserted
734 * so we must clear it again here after our writes.
736 writel(M_TX_FIFO_WATERMARK_EN,
737 uport->membase + SE_GENI_M_IRQ_CLEAR);
740 if (!port->tx_remaining) {
741 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
742 if (irq_en & M_TX_FIFO_WATERMARK_EN)
743 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
744 uport->membase + SE_GENI_M_IRQ_EN);
747 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
748 uart_write_wakeup(uport);
751 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
757 struct uart_port *uport = dev;
759 bool drop_rx = false;
760 struct tty_port *tport = &uport->state->port;
761 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
763 if (uport->suspended)
766 spin_lock_irqsave(&uport->lock, flags);
767 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
768 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
769 geni_status = readl(uport->membase + SE_GENI_STATUS);
770 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
771 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
772 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
774 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
777 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
778 uport->icount.overrun++;
779 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
782 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
783 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
784 geni_status & M_GENI_CMD_ACTIVE);
786 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
787 if (s_irq_status & S_GP_IRQ_0_EN)
788 uport->icount.parity++;
790 } else if (s_irq_status & S_GP_IRQ_2_EN ||
791 s_irq_status & S_GP_IRQ_3_EN) {
796 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
797 s_irq_status & S_RX_FIFO_LAST_EN)
798 qcom_geni_serial_handle_rx(uport, drop_rx);
801 uart_unlock_and_check_sysrq(uport, flags);
806 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
808 struct uart_port *uport;
810 uport = &port->uport;
811 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
812 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
813 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
815 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
819 static void qcom_geni_serial_shutdown(struct uart_port *uport)
823 /* Stop the console before stopping the current tx */
824 if (uart_console(uport))
825 console_stop(uport->cons);
827 disable_irq(uport->irq);
828 spin_lock_irqsave(&uport->lock, flags);
829 qcom_geni_serial_stop_tx(uport);
830 qcom_geni_serial_stop_rx(uport);
831 spin_unlock_irqrestore(&uport->lock, flags);
834 static int qcom_geni_serial_port_setup(struct uart_port *uport)
836 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
837 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
840 if (uart_console(uport)) {
841 port->tx_bytes_pw = 1;
842 port->rx_bytes_pw = CONSOLE_RX_BYTES_PW;
844 port->tx_bytes_pw = 4;
845 port->rx_bytes_pw = 4;
848 proto = geni_se_read_proto(&port->se);
849 if (proto != GENI_SE_UART) {
850 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
854 qcom_geni_serial_stop_rx(uport);
856 get_tx_fifo_size(port);
858 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
860 * Make an unconditional cancel on the main sequencer to reset
861 * it else we could end up in data loss scenarios.
863 if (uart_console(uport))
864 qcom_geni_serial_poll_tx_done(uport);
865 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
867 geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
869 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
870 geni_se_select_mode(&port->se, GENI_SE_FIFO);
871 if (!uart_console(uport)) {
872 port->rx_fifo = devm_kcalloc(uport->dev,
873 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
882 static int qcom_geni_serial_startup(struct uart_port *uport)
885 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
888 ret = qcom_geni_serial_port_setup(uport);
892 enable_irq(uport->irq);
897 static unsigned long get_clk_cfg(unsigned long clk_freq)
901 for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
902 if (!(root_freq[i] % clk_freq))
908 static unsigned long get_clk_div_rate(unsigned int baud,
909 unsigned int sampling_rate, unsigned int *clk_div)
911 unsigned long ser_clk;
912 unsigned long desired_clk;
914 desired_clk = baud * sampling_rate;
915 ser_clk = get_clk_cfg(desired_clk);
917 pr_err("%s: Can't find matching DFS entry for baud %d\n",
922 *clk_div = ser_clk / desired_clk;
926 static void qcom_geni_serial_set_termios(struct uart_port *uport,
927 struct ktermios *termios, struct ktermios *old)
936 unsigned int clk_div;
938 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
939 unsigned long clk_rate;
940 u32 ver, sampling_rate;
942 qcom_geni_serial_stop_rx(uport);
944 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
947 sampling_rate = UART_OVERSAMPLING;
948 /* Sampling rate is halved for IP versions >= 2.5 */
949 ver = geni_se_get_qup_hw_version(&port->se);
950 if (GENI_SE_VERSION_MAJOR(ver) >= 2 && GENI_SE_VERSION_MINOR(ver) >= 5)
953 clk_rate = get_clk_div_rate(baud, sampling_rate, &clk_div);
957 uport->uartclk = clk_rate;
958 clk_set_rate(port->se.clk, clk_rate);
959 ser_clk_cfg = SER_CLK_EN;
960 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
963 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
964 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
965 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
966 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
967 if (termios->c_cflag & PARENB) {
968 tx_trans_cfg |= UART_TX_PAR_EN;
969 rx_trans_cfg |= UART_RX_PAR_EN;
970 tx_parity_cfg |= PAR_CALC_EN;
971 rx_parity_cfg |= PAR_CALC_EN;
972 if (termios->c_cflag & PARODD) {
973 tx_parity_cfg |= PAR_ODD;
974 rx_parity_cfg |= PAR_ODD;
975 } else if (termios->c_cflag & CMSPAR) {
976 tx_parity_cfg |= PAR_SPACE;
977 rx_parity_cfg |= PAR_SPACE;
979 tx_parity_cfg |= PAR_EVEN;
980 rx_parity_cfg |= PAR_EVEN;
983 tx_trans_cfg &= ~UART_TX_PAR_EN;
984 rx_trans_cfg &= ~UART_RX_PAR_EN;
985 tx_parity_cfg &= ~PAR_CALC_EN;
986 rx_parity_cfg &= ~PAR_CALC_EN;
990 switch (termios->c_cflag & CSIZE) {
1007 if (termios->c_cflag & CSTOPB)
1008 stop_bit_len = TX_STOP_BIT_LEN_2;
1010 stop_bit_len = TX_STOP_BIT_LEN_1;
1012 /* flow control, clear the CTS_MASK bit if using flow control. */
1013 if (termios->c_cflag & CRTSCTS)
1014 tx_trans_cfg &= ~UART_CTS_MASK;
1016 tx_trans_cfg |= UART_CTS_MASK;
1019 uart_update_timeout(uport, termios->c_cflag, baud);
1021 if (!uart_console(uport))
1022 writel(port->loopback,
1023 uport->membase + SE_UART_LOOPBACK_CFG);
1024 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1025 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1026 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1027 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1028 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1029 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1030 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1031 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1032 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1034 qcom_geni_serial_start_rx(uport);
1037 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1039 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1042 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1043 static int __init qcom_geni_console_setup(struct console *co, char *options)
1045 struct uart_port *uport;
1046 struct qcom_geni_serial_port *port;
1053 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1056 port = get_port_from_line(co->index, true);
1058 pr_err("Invalid line %d\n", co->index);
1059 return PTR_ERR(port);
1062 uport = &port->uport;
1064 if (unlikely(!uport->membase))
1068 ret = qcom_geni_serial_port_setup(uport);
1074 uart_parse_options(options, &baud, &parity, &bits, &flow);
1076 return uart_set_options(uport, co, baud, parity, bits, flow);
1079 static void qcom_geni_serial_earlycon_write(struct console *con,
1080 const char *s, unsigned int n)
1082 struct earlycon_device *dev = con->data;
1084 __qcom_geni_serial_console_write(&dev->port, s, n);
1087 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1090 struct uart_port *uport = &dev->port;
1092 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1093 u32 rx_trans_cfg = 0;
1094 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1095 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1099 if (!uport->membase)
1102 memset(&se, 0, sizeof(se));
1103 se.base = uport->membase;
1104 if (geni_se_read_proto(&se) != GENI_SE_UART)
1107 * Ignore Flow control.
1110 tx_trans_cfg = UART_CTS_MASK;
1111 bits_per_char = BITS_PER_BYTE;
1114 * Make an unconditional cancel on the main sequencer to reset
1115 * it else we could end up in data loss scenarios.
1117 qcom_geni_serial_poll_tx_done(uport);
1118 qcom_geni_serial_abort_rx(uport);
1119 geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1120 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1121 geni_se_select_mode(&se, GENI_SE_FIFO);
1123 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1124 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1125 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1126 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1127 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1128 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1129 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1131 dev->con->write = qcom_geni_serial_earlycon_write;
1132 dev->con->setup = NULL;
1135 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1136 qcom_geni_serial_earlycon_setup);
1138 static int __init console_register(struct uart_driver *drv)
1140 return uart_register_driver(drv);
1143 static void console_unregister(struct uart_driver *drv)
1145 uart_unregister_driver(drv);
1148 static struct console cons_ops = {
1150 .write = qcom_geni_serial_console_write,
1151 .device = uart_console_device,
1152 .setup = qcom_geni_console_setup,
1153 .flags = CON_PRINTBUFFER,
1155 .data = &qcom_geni_console_driver,
1158 static struct uart_driver qcom_geni_console_driver = {
1159 .owner = THIS_MODULE,
1160 .driver_name = "qcom_geni_console",
1161 .dev_name = "ttyMSM",
1162 .nr = GENI_UART_CONS_PORTS,
1166 static int console_register(struct uart_driver *drv)
1171 static void console_unregister(struct uart_driver *drv)
1174 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1176 static struct uart_driver qcom_geni_uart_driver = {
1177 .owner = THIS_MODULE,
1178 .driver_name = "qcom_geni_uart",
1179 .dev_name = "ttyHS",
1180 .nr = GENI_UART_PORTS,
1183 static void qcom_geni_serial_pm(struct uart_port *uport,
1184 unsigned int new_state, unsigned int old_state)
1186 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1188 /* If we've never been called, treat it as off */
1189 if (old_state == UART_PM_STATE_UNDEFINED)
1190 old_state = UART_PM_STATE_OFF;
1192 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1193 geni_se_resources_on(&port->se);
1194 else if (new_state == UART_PM_STATE_OFF &&
1195 old_state == UART_PM_STATE_ON)
1196 geni_se_resources_off(&port->se);
1199 static const struct uart_ops qcom_geni_console_pops = {
1200 .tx_empty = qcom_geni_serial_tx_empty,
1201 .stop_tx = qcom_geni_serial_stop_tx,
1202 .start_tx = qcom_geni_serial_start_tx,
1203 .stop_rx = qcom_geni_serial_stop_rx,
1204 .set_termios = qcom_geni_serial_set_termios,
1205 .startup = qcom_geni_serial_startup,
1206 .request_port = qcom_geni_serial_request_port,
1207 .config_port = qcom_geni_serial_config_port,
1208 .shutdown = qcom_geni_serial_shutdown,
1209 .type = qcom_geni_serial_get_type,
1210 .set_mctrl = qcom_geni_serial_set_mctrl,
1211 .get_mctrl = qcom_geni_serial_get_mctrl,
1212 #ifdef CONFIG_CONSOLE_POLL
1213 .poll_get_char = qcom_geni_serial_get_char,
1214 .poll_put_char = qcom_geni_serial_poll_put_char,
1216 .pm = qcom_geni_serial_pm,
1219 static const struct uart_ops qcom_geni_uart_pops = {
1220 .tx_empty = qcom_geni_serial_tx_empty,
1221 .stop_tx = qcom_geni_serial_stop_tx,
1222 .start_tx = qcom_geni_serial_start_tx,
1223 .stop_rx = qcom_geni_serial_stop_rx,
1224 .set_termios = qcom_geni_serial_set_termios,
1225 .startup = qcom_geni_serial_startup,
1226 .request_port = qcom_geni_serial_request_port,
1227 .config_port = qcom_geni_serial_config_port,
1228 .shutdown = qcom_geni_serial_shutdown,
1229 .type = qcom_geni_serial_get_type,
1230 .set_mctrl = qcom_geni_serial_set_mctrl,
1231 .get_mctrl = qcom_geni_serial_get_mctrl,
1232 .pm = qcom_geni_serial_pm,
1235 static int qcom_geni_serial_probe(struct platform_device *pdev)
1239 struct qcom_geni_serial_port *port;
1240 struct uart_port *uport;
1241 struct resource *res;
1243 bool console = false;
1244 struct uart_driver *drv;
1246 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1250 drv = &qcom_geni_console_driver;
1251 line = of_alias_get_id(pdev->dev.of_node, "serial");
1253 drv = &qcom_geni_uart_driver;
1254 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1257 port = get_port_from_line(line, console);
1259 dev_err(&pdev->dev, "Invalid line %d\n", line);
1260 return PTR_ERR(port);
1263 uport = &port->uport;
1264 /* Don't allow 2 drivers to access the same port */
1265 if (uport->private_data)
1268 uport->dev = &pdev->dev;
1269 port->se.dev = &pdev->dev;
1270 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1271 port->se.clk = devm_clk_get(&pdev->dev, "se");
1272 if (IS_ERR(port->se.clk)) {
1273 ret = PTR_ERR(port->se.clk);
1274 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1278 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1281 uport->mapbase = res->start;
1283 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1284 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1285 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1287 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1288 "qcom_geni_serial_%s%d",
1289 uart_console(uport) ? "console" : "uart", uport->line);
1293 irq = platform_get_irq(pdev, 0);
1297 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1300 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1302 uport->private_data = drv;
1303 platform_set_drvdata(pdev, port);
1304 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1306 ret = uart_add_one_port(drv, uport);
1310 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1311 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1312 IRQF_TRIGGER_HIGH, port->name, uport);
1314 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1315 uart_remove_one_port(drv, uport);
1320 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1321 * enabled/disabled from dev_pm_arm_wake_irq during system
1322 * suspend/resume respectively.
1324 pm_runtime_set_active(&pdev->dev);
1326 if (port->wakeup_irq > 0) {
1327 device_init_wakeup(&pdev->dev, true);
1328 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1331 device_init_wakeup(&pdev->dev, false);
1332 uart_remove_one_port(drv, uport);
1340 static int qcom_geni_serial_remove(struct platform_device *pdev)
1342 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1343 struct uart_driver *drv = port->uport.private_data;
1345 dev_pm_clear_wake_irq(&pdev->dev);
1346 device_init_wakeup(&pdev->dev, false);
1347 uart_remove_one_port(drv, &port->uport);
1352 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1354 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1355 struct uart_port *uport = &port->uport;
1357 return uart_suspend_port(uport->private_data, uport);
1360 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1362 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1363 struct uart_port *uport = &port->uport;
1365 return uart_resume_port(uport->private_data, uport);
1368 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1369 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1370 qcom_geni_serial_sys_resume)
1373 static const struct of_device_id qcom_geni_serial_match_table[] = {
1374 { .compatible = "qcom,geni-debug-uart", },
1375 { .compatible = "qcom,geni-uart", },
1378 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1380 static struct platform_driver qcom_geni_serial_platform_driver = {
1381 .remove = qcom_geni_serial_remove,
1382 .probe = qcom_geni_serial_probe,
1384 .name = "qcom_geni_serial",
1385 .of_match_table = qcom_geni_serial_match_table,
1386 .pm = &qcom_geni_serial_pm_ops,
1390 static int __init qcom_geni_serial_init(void)
1394 ret = console_register(&qcom_geni_console_driver);
1398 ret = uart_register_driver(&qcom_geni_uart_driver);
1400 console_unregister(&qcom_geni_console_driver);
1404 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1406 console_unregister(&qcom_geni_console_driver);
1407 uart_unregister_driver(&qcom_geni_uart_driver);
1411 module_init(qcom_geni_serial_init);
1413 static void __exit qcom_geni_serial_exit(void)
1415 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1416 console_unregister(&qcom_geni_console_driver);
1417 uart_unregister_driver(&qcom_geni_uart_driver);
1419 module_exit(qcom_geni_serial_exit);
1421 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1422 MODULE_LICENSE("GPL v2");