drivers/tty/serial/samsung_tty.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7  */
   8
   9 /* Hote on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22  */
  23
  24 #include <linux/dmaengine.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include <linux/ioport.h>
  29 #include <linux/io.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/init.h>
  32 #include <linux/sysrq.h>
  33 #include <linux/console.h>
  34 #include <linux/tty.h>
  35 #include <linux/tty_flip.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/serial.h>
  38 #include <linux/serial_s3c.h>
  39 #include <linux/delay.h>
  40 #include <linux/clk.h>
  41 #include <linux/cpufreq.h>
  42 #include <linux/of.h>
  43 #include <asm/irq.h>
  44
  45 /* UART name and device definitions */
  46
  47 #define S3C24XX_SERIAL_NAME     "ttySAC"
  48 #define S3C24XX_SERIAL_MAJOR    204
  49 #define S3C24XX_SERIAL_MINOR    64
  50
  51 #define S3C24XX_TX_PIO                  1
  52 #define S3C24XX_TX_DMA                  2
  53 #define S3C24XX_RX_PIO                  1
  54 #define S3C24XX_RX_DMA                  2
  55
  56 /* flag to ignore all characters coming in */
  57 #define RXSTAT_DUMMY_READ (0x10000000)
  58
  59 struct s3c24xx_uart_info {
  60         char                    *name;
  61         unsigned int            type;
  62         unsigned int            fifosize;
  63         unsigned long           rx_fifomask;
  64         unsigned long           rx_fifoshift;
  65         unsigned long           rx_fifofull;
  66         unsigned long           tx_fifomask;
  67         unsigned long           tx_fifoshift;
  68         unsigned long           tx_fifofull;
  69         unsigned int            def_clk_sel;
  70         unsigned long           num_clks;
  71         unsigned long           clksel_mask;
  72         unsigned long           clksel_shift;
  73
  74         /* uart port features */
  75
  76         unsigned int            has_divslot:1;
  77 };
  78
  79 struct s3c24xx_serial_drv_data {
  80         struct s3c24xx_uart_info        *info;
  81         struct s3c2410_uartcfg          *def_cfg;
  82         unsigned int                    fifosize[CONFIG_SERIAL_SAMSUNG_UARTS];
  83 };
  84
  85 struct s3c24xx_uart_dma {
  86         unsigned int                    rx_chan_id;
  87         unsigned int                    tx_chan_id;
  88
  89         struct dma_slave_config         rx_conf;
  90         struct dma_slave_config         tx_conf;
  91
  92         struct dma_chan                 *rx_chan;
  93         struct dma_chan                 *tx_chan;
  94
  95         dma_addr_t                      rx_addr;
  96         dma_addr_t                      tx_addr;
  97
  98         dma_cookie_t                    rx_cookie;
  99         dma_cookie_t                    tx_cookie;
 100
 101         char                            *rx_buf;
 102
 103         dma_addr_t                      tx_transfer_addr;
 104
 105         size_t                          rx_size;
 106         size_t                          tx_size;
 107
 108         struct dma_async_tx_descriptor  *tx_desc;
 109         struct dma_async_tx_descriptor  *rx_desc;
 110
 111         int                             tx_bytes_requested;
 112         int                             rx_bytes_requested;
 113 };
 114
 115 struct s3c24xx_uart_port {
 116         unsigned char                   rx_claimed;
 117         unsigned char                   tx_claimed;
 118         unsigned char                   rx_enabled;
 119         unsigned char                   tx_enabled;
 120         unsigned int                    pm_level;
 121         unsigned long                   baudclk_rate;
 122         unsigned int                    min_dma_size;
 123
 124         unsigned int                    rx_irq;
 125         unsigned int                    tx_irq;
 126
 127         unsigned int                    tx_in_progress;
 128         unsigned int                    tx_mode;
 129         unsigned int                    rx_mode;
 130
 131         struct s3c24xx_uart_info        *info;
 132         struct clk                      *clk;
 133         struct clk                      *baudclk;
 134         struct uart_port                port;
 135         struct s3c24xx_serial_drv_data  *drv_data;
 136
 137         /* reference to platform data */
 138         struct s3c2410_uartcfg          *cfg;
 139
 140         struct s3c24xx_uart_dma         *dma;
 141
 142 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
 143         struct notifier_block           freq_transition;
 144 #endif
 145 };
 146
 147 /* conversion functions */
 148
 149 #define s3c24xx_dev_to_port(__dev) dev_get_drvdata(__dev)
 150
 151 /* register access controls */
 152
 153 #define portaddr(port, reg) ((port)->membase + (reg))
 154 #define portaddrl(port, reg) \
 155         ((unsigned long *)(unsigned long)((port)->membase + (reg)))
 156
 157 #define rd_regb(port, reg) (readb_relaxed(portaddr(port, reg)))
 158 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg)))
 159
 160 #define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
 161 #define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
 162
 163 /* Byte-order aware bit setting/clearing functions. */
 164
 165 static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
 166                                    unsigned int reg)
 167 {
 168         unsigned long flags;
 169         u32 val;
 170
 171         local_irq_save(flags);
 172         val = rd_regl(port, reg);
 173         val |= (1 << idx);
 174         wr_regl(port, reg, val);
 175         local_irq_restore(flags);
 176 }
 177
 178 static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
 179                                      unsigned int reg)
 180 {
 181         unsigned long flags;
 182         u32 val;
 183
 184         local_irq_save(flags);
 185         val = rd_regl(port, reg);
 186         val &= ~(1 << idx);
 187         wr_regl(port, reg, val);
 188         local_irq_restore(flags);
 189 }
 190
 191 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
 192 {
 193         return container_of(port, struct s3c24xx_uart_port, port);
 194 }
 195
 196 /* translate a port to the device name */
 197
 198 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 199 {
 200         return to_platform_device(port->dev)->name;
 201 }
 202
 203 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 204 {
 205         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 206 }
 207
 208 /*
 209  * s3c64xx and later SoC's include the interrupt mask and status registers in
 210  * the controller itself, unlike the s3c24xx SoC's which have these registers
 211  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 212  */
 213 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 214 {
 215         return to_ourport(port)->info->type == PORT_S3C6400;
 216 }
 217
 218 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 219 {
 220         struct s3c24xx_uart_port *ourport = to_ourport(port);
 221         unsigned long flags;
 222         unsigned int ucon, ufcon;
 223         int count = 10000;
 224
 225         spin_lock_irqsave(&port->lock, flags);
 226
 227         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 228                 udelay(100);
 229
 230         ufcon = rd_regl(port, S3C2410_UFCON);
 231         ufcon |= S3C2410_UFCON_RESETRX;
 232         wr_regl(port, S3C2410_UFCON, ufcon);
 233
 234         ucon = rd_regl(port, S3C2410_UCON);
 235         ucon |= S3C2410_UCON_RXIRQMODE;
 236         wr_regl(port, S3C2410_UCON, ucon);
 237
 238         ourport->rx_enabled = 1;
 239         spin_unlock_irqrestore(&port->lock, flags);
 240 }
 241
 242 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 243 {
 244         struct s3c24xx_uart_port *ourport = to_ourport(port);
 245         unsigned long flags;
 246         unsigned int ucon;
 247
 248         spin_lock_irqsave(&port->lock, flags);
 249
 250         ucon = rd_regl(port, S3C2410_UCON);
 251         ucon &= ~S3C2410_UCON_RXIRQMODE;
 252         wr_regl(port, S3C2410_UCON, ucon);
 253
 254         ourport->rx_enabled = 0;
 255         spin_unlock_irqrestore(&port->lock, flags);
 256 }
 257
 258 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 259 {
 260         struct s3c24xx_uart_port *ourport = to_ourport(port);
 261         struct s3c24xx_uart_dma *dma = ourport->dma;
 262         struct circ_buf *xmit = &port->state->xmit;
 263         struct dma_tx_state state;
 264         int count;
 265
 266         if (!ourport->tx_enabled)
 267                 return;
 268
 269         if (s3c24xx_serial_has_interrupt_mask(port))
 270                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 271         else
 272                 disable_irq_nosync(ourport->tx_irq);
 273
 274         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 275                 dmaengine_pause(dma->tx_chan);
 276                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 277                 dmaengine_terminate_all(dma->tx_chan);
 278                 dma_sync_single_for_cpu(ourport->port.dev,
 279                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 280                 async_tx_ack(dma->tx_desc);
 281                 count = dma->tx_bytes_requested - state.residue;
 282                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 283                 port->icount.tx += count;
 284         }
 285
 286         ourport->tx_enabled = 0;
 287         ourport->tx_in_progress = 0;
 288
 289         if (port->flags & UPF_CONS_FLOW)
 290                 s3c24xx_serial_rx_enable(port);
 291
 292         ourport->tx_mode = 0;
 293 }
 294
 295 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 296
 297 static void s3c24xx_serial_tx_dma_complete(void *args)
 298 {
 299         struct s3c24xx_uart_port *ourport = args;
 300         struct uart_port *port = &ourport->port;
 301         struct circ_buf *xmit = &port->state->xmit;
 302         struct s3c24xx_uart_dma *dma = ourport->dma;
 303         struct dma_tx_state state;
 304         unsigned long flags;
 305         int count;
 306
 307
 308         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 309         count = dma->tx_bytes_requested - state.residue;
 310         async_tx_ack(dma->tx_desc);
 311
 312         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 313                                 dma->tx_size, DMA_TO_DEVICE);
 314
 315         spin_lock_irqsave(&port->lock, flags);
 316
 317         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 318         port->icount.tx += count;
 319         ourport->tx_in_progress = 0;
 320
 321         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 322                 uart_write_wakeup(port);
 323
 324         s3c24xx_serial_start_next_tx(ourport);
 325         spin_unlock_irqrestore(&port->lock, flags);
 326 }
 327
 328 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 329 {
 330         struct uart_port *port = &ourport->port;
 331         u32 ucon;
 332
 333         /* Mask Tx interrupt */
 334         if (s3c24xx_serial_has_interrupt_mask(port))
 335                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 336         else
 337                 disable_irq_nosync(ourport->tx_irq);
 338
 339         /* Enable tx dma mode */
 340         ucon = rd_regl(port, S3C2410_UCON);
 341         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 342         ucon |= (dma_get_cache_alignment() >= 16) ?
 343                 S3C64XX_UCON_TXBURST_16 : S3C64XX_UCON_TXBURST_1;
 344         ucon |= S3C64XX_UCON_TXMODE_DMA;
 345         wr_regl(port,  S3C2410_UCON, ucon);
 346
 347         ourport->tx_mode = S3C24XX_TX_DMA;
 348 }
 349
 350 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 351 {
 352         struct uart_port *port = &ourport->port;
 353         u32 ucon, ufcon;
 354
 355         /* Set ufcon txtrig */
 356         ourport->tx_in_progress = S3C24XX_TX_PIO;
 357         ufcon = rd_regl(port, S3C2410_UFCON);
 358         wr_regl(port,  S3C2410_UFCON, ufcon);
 359
 360         /* Enable tx pio mode */
 361         ucon = rd_regl(port, S3C2410_UCON);
 362         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 363         ucon |= S3C64XX_UCON_TXMODE_CPU;
 364         wr_regl(port,  S3C2410_UCON, ucon);
 365
 366         /* Unmask Tx interrupt */
 367         if (s3c24xx_serial_has_interrupt_mask(port))
 368                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 369                                   S3C64XX_UINTM);
 370         else
 371                 enable_irq(ourport->tx_irq);
 372
 373         ourport->tx_mode = S3C24XX_TX_PIO;
 374 }
 375
 376 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 377 {
 378         if (ourport->tx_mode != S3C24XX_TX_PIO)
 379                 enable_tx_pio(ourport);
 380 }
 381
 382 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 383                                       unsigned int count)
 384 {
 385         struct uart_port *port = &ourport->port;
 386         struct circ_buf *xmit = &port->state->xmit;
 387         struct s3c24xx_uart_dma *dma = ourport->dma;
 388
 389
 390         if (ourport->tx_mode != S3C24XX_TX_DMA)
 391                 enable_tx_dma(ourport);
 392
 393         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 394         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 395
 396         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 397                                 dma->tx_size, DMA_TO_DEVICE);
 398
 399         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 400                                 dma->tx_transfer_addr, dma->tx_size,
 401                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 402         if (!dma->tx_desc) {
 403                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 404                 return -EIO;
 405         }
 406
 407         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 408         dma->tx_desc->callback_param = ourport;
 409         dma->tx_bytes_requested = dma->tx_size;
 410
 411         ourport->tx_in_progress = S3C24XX_TX_DMA;
 412         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 413         dma_async_issue_pending(dma->tx_chan);
 414         return 0;
 415 }
 416
 417 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 418 {
 419         struct uart_port *port = &ourport->port;
 420         struct circ_buf *xmit = &port->state->xmit;
 421         unsigned long count;
 422
 423         /* Get data size up to the end of buffer */
 424         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 425
 426         if (!count) {
 427                 s3c24xx_serial_stop_tx(port);
 428                 return;
 429         }
 430
 431         if (!ourport->dma || !ourport->dma->tx_chan ||
 432             count < ourport->min_dma_size ||
 433             xmit->tail & (dma_get_cache_alignment() - 1))
 434                 s3c24xx_serial_start_tx_pio(ourport);
 435         else
 436                 s3c24xx_serial_start_tx_dma(ourport, count);
 437 }
 438
 439 static void s3c24xx_serial_start_tx(struct uart_port *port)
 440 {
 441         struct s3c24xx_uart_port *ourport = to_ourport(port);
 442         struct circ_buf *xmit = &port->state->xmit;
 443
 444         if (!ourport->tx_enabled) {
 445                 if (port->flags & UPF_CONS_FLOW)
 446                         s3c24xx_serial_rx_disable(port);
 447
 448                 ourport->tx_enabled = 1;
 449                 if (!ourport->dma || !ourport->dma->tx_chan)
 450                         s3c24xx_serial_start_tx_pio(ourport);
 451         }
 452
 453         if (ourport->dma && ourport->dma->tx_chan) {
 454                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 455                         s3c24xx_serial_start_next_tx(ourport);
 456         }
 457 }
 458
 459 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 460                 struct tty_port *tty, int count)
 461 {
 462         struct s3c24xx_uart_dma *dma = ourport->dma;
 463         int copied;
 464
 465         if (!count)
 466                 return;
 467
 468         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 469                                 dma->rx_size, DMA_FROM_DEVICE);
 470
 471         ourport->port.icount.rx += count;
 472         if (!tty) {
 473                 dev_err(ourport->port.dev, "No tty port\n");
 474                 return;
 475         }
 476         copied = tty_insert_flip_string(tty,
 477                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 478         if (copied != count) {
 479                 WARN_ON(1);
 480                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 481         }
 482 }
 483
 484 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 485 {
 486         struct s3c24xx_uart_port *ourport = to_ourport(port);
 487         struct s3c24xx_uart_dma *dma = ourport->dma;
 488         struct tty_port *t = &port->state->port;
 489         struct dma_tx_state state;
 490         enum dma_status dma_status;
 491         unsigned int received;
 492
 493         if (ourport->rx_enabled) {
 494                 dev_dbg(port->dev, "stopping rx\n");
 495                 if (s3c24xx_serial_has_interrupt_mask(port))
 496                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 497                                         S3C64XX_UINTM);
 498                 else
 499                         disable_irq_nosync(ourport->rx_irq);
 500                 ourport->rx_enabled = 0;
 501         }
 502         if (dma && dma->rx_chan) {
 503                 dmaengine_pause(dma->tx_chan);
 504                 dma_status = dmaengine_tx_status(dma->rx_chan,
 505                                 dma->rx_cookie, &state);
 506                 if (dma_status == DMA_IN_PROGRESS ||
 507                         dma_status == DMA_PAUSED) {
 508                         received = dma->rx_bytes_requested - state.residue;
 509                         dmaengine_terminate_all(dma->rx_chan);
 510                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 511                 }
 512         }
 513 }
 514
 515 static inline struct s3c24xx_uart_info
 516         *s3c24xx_port_to_info(struct uart_port *port)
 517 {
 518         return to_ourport(port)->info;
 519 }
 520
 521 static inline struct s3c2410_uartcfg
 522         *s3c24xx_port_to_cfg(struct uart_port *port)
 523 {
 524         struct s3c24xx_uart_port *ourport;
 525
 526         if (port->dev == NULL)
 527                 return NULL;
 528
 529         ourport = container_of(port, struct s3c24xx_uart_port, port);
 530         return ourport->cfg;
 531 }
 532
 533 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 534                                      unsigned long ufstat)
 535 {
 536         struct s3c24xx_uart_info *info = ourport->info;
 537
 538         if (ufstat & info->rx_fifofull)
 539                 return ourport->port.fifosize;
 540
 541         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 542 }
 543
 544 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 545 static void s3c24xx_serial_rx_dma_complete(void *args)
 546 {
 547         struct s3c24xx_uart_port *ourport = args;
 548         struct uart_port *port = &ourport->port;
 549
 550         struct s3c24xx_uart_dma *dma = ourport->dma;
 551         struct tty_port *t = &port->state->port;
 552         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 553
 554         struct dma_tx_state state;
 555         unsigned long flags;
 556         int received;
 557
 558         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 559         received  = dma->rx_bytes_requested - state.residue;
 560         async_tx_ack(dma->rx_desc);
 561
 562         spin_lock_irqsave(&port->lock, flags);
 563
 564         if (received)
 565                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 566
 567         if (tty) {
 568                 tty_flip_buffer_push(t);
 569                 tty_kref_put(tty);
 570         }
 571
 572         s3c64xx_start_rx_dma(ourport);
 573
 574         spin_unlock_irqrestore(&port->lock, flags);
 575 }
 576
 577 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 578 {
 579         struct s3c24xx_uart_dma *dma = ourport->dma;
 580
 581         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 582                                 dma->rx_size, DMA_FROM_DEVICE);
 583
 584         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 585                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 586                                 DMA_PREP_INTERRUPT);
 587         if (!dma->rx_desc) {
 588                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 589                 return;
 590         }
 591
 592         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 593         dma->rx_desc->callback_param = ourport;
 594         dma->rx_bytes_requested = dma->rx_size;
 595
 596         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 597         dma_async_issue_pending(dma->rx_chan);
 598 }
 599
 600 /* ? - where has parity gone?? */
 601 #define S3C2410_UERSTAT_PARITY (0x1000)
 602
 603 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 604 {
 605         struct uart_port *port = &ourport->port;
 606         unsigned int ucon;
 607
 608         /* set Rx mode to DMA mode */
 609         ucon = rd_regl(port, S3C2410_UCON);
 610         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 611                         S3C64XX_UCON_TIMEOUT_MASK |
 612                         S3C64XX_UCON_EMPTYINT_EN |
 613                         S3C64XX_UCON_DMASUS_EN |
 614                         S3C64XX_UCON_TIMEOUT_EN |
 615                         S3C64XX_UCON_RXMODE_MASK);
 616         ucon |= S3C64XX_UCON_RXBURST_16 |
 617                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 618                         S3C64XX_UCON_EMPTYINT_EN |
 619                         S3C64XX_UCON_TIMEOUT_EN |
 620                         S3C64XX_UCON_RXMODE_DMA;
 621         wr_regl(port, S3C2410_UCON, ucon);
 622
 623         ourport->rx_mode = S3C24XX_RX_DMA;
 624 }
 625
 626 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 627 {
 628         struct uart_port *port = &ourport->port;
 629         unsigned int ucon;
 630
 631         /* set Rx mode to DMA mode */
 632         ucon = rd_regl(port, S3C2410_UCON);
 633         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 634                         S3C64XX_UCON_EMPTYINT_EN |
 635                         S3C64XX_UCON_DMASUS_EN |
 636                         S3C64XX_UCON_TIMEOUT_EN |
 637                         S3C64XX_UCON_RXMODE_MASK);
 638         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 639                         S3C64XX_UCON_TIMEOUT_EN |
 640                         S3C64XX_UCON_RXMODE_CPU;
 641         wr_regl(port, S3C2410_UCON, ucon);
 642
 643         ourport->rx_mode = S3C24XX_RX_PIO;
 644 }
 645
 646 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 647
 648 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 649 {
 650         unsigned int utrstat, received;
 651         struct s3c24xx_uart_port *ourport = dev_id;
 652         struct uart_port *port = &ourport->port;
 653         struct s3c24xx_uart_dma *dma = ourport->dma;
 654         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 655         struct tty_port *t = &port->state->port;
 656         unsigned long flags;
 657         struct dma_tx_state state;
 658
 659         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 660         rd_regl(port, S3C2410_UFSTAT);
 661
 662         spin_lock_irqsave(&port->lock, flags);
 663
 664         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 665                 s3c64xx_start_rx_dma(ourport);
 666                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 667                         enable_rx_dma(ourport);
 668                 goto finish;
 669         }
 670
 671         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 672                 dmaengine_pause(dma->rx_chan);
 673                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 674                 dmaengine_terminate_all(dma->rx_chan);
 675                 received = dma->rx_bytes_requested - state.residue;
 676                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 677
 678                 enable_rx_pio(ourport);
 679         }
 680
 681         s3c24xx_serial_rx_drain_fifo(ourport);
 682
 683         if (tty) {
 684                 tty_flip_buffer_push(t);
 685                 tty_kref_put(tty);
 686         }
 687
 688         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 689
 690 finish:
 691         spin_unlock_irqrestore(&port->lock, flags);
 692
 693         return IRQ_HANDLED;
 694 }
 695
 696 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 697 {
 698         struct uart_port *port = &ourport->port;
 699         unsigned int ufcon, ch, flag, ufstat, uerstat;
 700         unsigned int fifocnt = 0;
 701         int max_count = port->fifosize;
 702
 703         while (max_count-- > 0) {
 704                 /*
 705                  * Receive all characters known to be in FIFO
 706                  * before reading FIFO level again
 707                  */
 708                 if (fifocnt == 0) {
 709                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 710                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 711                         if (fifocnt == 0)
 712                                 break;
 713                 }
 714                 fifocnt--;
 715
 716                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 717                 ch = rd_regb(port, S3C2410_URXH);
 718
 719                 if (port->flags & UPF_CONS_FLOW) {
 720                         int txe = s3c24xx_serial_txempty_nofifo(port);
 721
 722                         if (ourport->rx_enabled) {
 723                                 if (!txe) {
 724                                         ourport->rx_enabled = 0;
 725                                         continue;
 726                                 }
 727                         } else {
 728                                 if (txe) {
 729                                         ufcon = rd_regl(port, S3C2410_UFCON);
 730                                         ufcon |= S3C2410_UFCON_RESETRX;
 731                                         wr_regl(port, S3C2410_UFCON, ufcon);
 732                                         ourport->rx_enabled = 1;
 733                                         return;
 734                                 }
 735                                 continue;
 736                         }
 737                 }
 738
 739                 /* insert the character into the buffer */
 740
 741                 flag = TTY_NORMAL;
 742                 port->icount.rx++;
 743
 744                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 745                         dev_dbg(port->dev,
 746                                 "rxerr: port ch=0x%02x, rxs=0x%08x\n",
 747                                 ch, uerstat);
 748
 749                         /* check for break */
 750                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 751                                 dev_dbg(port->dev, "break!\n");
 752                                 port->icount.brk++;
 753                                 if (uart_handle_break(port))
 754                                         continue; /* Ignore character */
 755                         }
 756
 757                         if (uerstat & S3C2410_UERSTAT_FRAME)
 758                                 port->icount.frame++;
 759                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 760                                 port->icount.overrun++;
 761
 762                         uerstat &= port->read_status_mask;
 763
 764                         if (uerstat & S3C2410_UERSTAT_BREAK)
 765                                 flag = TTY_BREAK;
 766                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 767                                 flag = TTY_PARITY;
 768                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 769                                             S3C2410_UERSTAT_OVERRUN))
 770                                 flag = TTY_FRAME;
 771                 }
 772
 773                 if (uart_handle_sysrq_char(port, ch))
 774                         continue; /* Ignore character */
 775
 776                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 777                                  ch, flag);
 778         }
 779
 780         tty_flip_buffer_push(&port->state->port);
 781 }
 782
 783 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 784 {
 785         struct s3c24xx_uart_port *ourport = dev_id;
 786         struct uart_port *port = &ourport->port;
 787         unsigned long flags;
 788
 789         spin_lock_irqsave(&port->lock, flags);
 790         s3c24xx_serial_rx_drain_fifo(ourport);
 791         spin_unlock_irqrestore(&port->lock, flags);
 792
 793         return IRQ_HANDLED;
 794 }
 795
 796
 797 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 798 {
 799         struct s3c24xx_uart_port *ourport = dev_id;
 800
 801         if (ourport->dma && ourport->dma->rx_chan)
 802                 return s3c24xx_serial_rx_chars_dma(dev_id);
 803         return s3c24xx_serial_rx_chars_pio(dev_id);
 804 }
 805
 806 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 807 {
 808         struct s3c24xx_uart_port *ourport = id;
 809         struct uart_port *port = &ourport->port;
 810         struct circ_buf *xmit = &port->state->xmit;
 811         unsigned long flags;
 812         int count, dma_count = 0;
 813
 814         spin_lock_irqsave(&port->lock, flags);
 815
 816         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 817
 818         if (ourport->dma && ourport->dma->tx_chan &&
 819             count >= ourport->min_dma_size) {
 820                 int align = dma_get_cache_alignment() -
 821                         (xmit->tail & (dma_get_cache_alignment() - 1));
 822                 if (count-align >= ourport->min_dma_size) {
 823                         dma_count = count-align;
 824                         count = align;
 825                 }
 826         }
 827
 828         if (port->x_char) {
 829                 wr_regb(port, S3C2410_UTXH, port->x_char);
 830                 port->icount.tx++;
 831                 port->x_char = 0;
 832                 goto out;
 833         }
 834
 835         /* if there isn't anything more to transmit, or the uart is now
 836          * stopped, disable the uart and exit
 837          */
 838
 839         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 840                 s3c24xx_serial_stop_tx(port);
 841                 goto out;
 842         }
 843
 844         /* try and drain the buffer... */
 845
 846         if (count > port->fifosize) {
 847                 count = port->fifosize;
 848                 dma_count = 0;
 849         }
 850
 851         while (!uart_circ_empty(xmit) && count > 0) {
 852                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 853                         break;
 854
 855                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 856                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 857                 port->icount.tx++;
 858                 count--;
 859         }
 860
 861         if (!count && dma_count) {
 862                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 863                 goto out;
 864         }
 865
 866         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 867                 spin_unlock(&port->lock);
 868                 uart_write_wakeup(port);
 869                 spin_lock(&port->lock);
 870         }
 871
 872         if (uart_circ_empty(xmit))
 873                 s3c24xx_serial_stop_tx(port);
 874
 875 out:
 876         spin_unlock_irqrestore(&port->lock, flags);
 877         return IRQ_HANDLED;
 878 }
 879
 880 /* interrupt handler for s3c64xx and later SoC's.*/
 881 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 882 {
 883         struct s3c24xx_uart_port *ourport = id;
 884         struct uart_port *port = &ourport->port;
 885         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 886         irqreturn_t ret = IRQ_HANDLED;
 887
 888         if (pend & S3C64XX_UINTM_RXD_MSK) {
 889                 ret = s3c24xx_serial_rx_chars(irq, id);
 890                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 891         }
 892         if (pend & S3C64XX_UINTM_TXD_MSK) {
 893                 ret = s3c24xx_serial_tx_chars(irq, id);
 894                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 895         }
 896         return ret;
 897 }
 898
 899 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 900 {
 901         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 902         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 903         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 904
 905         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 906                 if ((ufstat & info->tx_fifomask) != 0 ||
 907                     (ufstat & info->tx_fifofull))
 908                         return 0;
 909
 910                 return 1;
 911         }
 912
 913         return s3c24xx_serial_txempty_nofifo(port);
 914 }
 915
 916 /* no modem control lines */
 917 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 918 {
 919         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 920
 921         if (umstat & S3C2410_UMSTAT_CTS)
 922                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 923         else
 924                 return TIOCM_CAR | TIOCM_DSR;
 925 }
 926
 927 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 928 {
 929         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 930
 931         if (mctrl & TIOCM_RTS)
 932                 umcon |= S3C2410_UMCOM_RTS_LOW;
 933         else
 934                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 935
 936         wr_regl(port, S3C2410_UMCON, umcon);
 937 }
 938
 939 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 940 {
 941         unsigned long flags;
 942         unsigned int ucon;
 943
 944         spin_lock_irqsave(&port->lock, flags);
 945
 946         ucon = rd_regl(port, S3C2410_UCON);
 947
 948         if (break_state)
 949                 ucon |= S3C2410_UCON_SBREAK;
 950         else
 951                 ucon &= ~S3C2410_UCON_SBREAK;
 952
 953         wr_regl(port, S3C2410_UCON, ucon);
 954
 955         spin_unlock_irqrestore(&port->lock, flags);
 956 }
 957
 958 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 959 {
 960         struct s3c24xx_uart_dma *dma = p->dma;
 961         struct dma_slave_caps dma_caps;
 962         const char *reason = NULL;
 963         int ret;
 964
 965         /* Default slave configuration parameters */
 966         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 967         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 968         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 969         dma->rx_conf.src_maxburst       = 1;
 970
 971         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 972         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 973         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 974         dma->tx_conf.dst_maxburst       = 1;
 975
 976         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 977
 978         if (IS_ERR(dma->rx_chan)) {
 979                 reason = "DMA RX channel request failed";
 980                 ret = PTR_ERR(dma->rx_chan);
 981                 goto err_warn;
 982         }
 983
 984         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
 985         if (ret < 0 ||
 986             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
 987                 reason = "insufficient DMA RX engine capabilities";
 988                 ret = -EOPNOTSUPP;
 989                 goto err_release_rx;
 990         }
 991
 992         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 993
 994         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 995         if (IS_ERR(dma->tx_chan)) {
 996                 reason = "DMA TX channel request failed";
 997                 ret = PTR_ERR(dma->tx_chan);
 998                 goto err_release_rx;
 999         }
1000
1001         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
1002         if (ret < 0 ||
1003             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
1004                 reason = "insufficient DMA TX engine capabilities";
1005                 ret = -EOPNOTSUPP;
1006                 goto err_release_tx;
1007         }
1008
1009         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
1010
1011         /* RX buffer */
1012         dma->rx_size = PAGE_SIZE;
1013
1014         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
1015         if (!dma->rx_buf) {
1016                 ret = -ENOMEM;
1017                 goto err_release_tx;
1018         }
1019
1020         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
1021                                 dma->rx_size, DMA_FROM_DEVICE);
1022         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
1023                 reason = "DMA mapping error for RX buffer";
1024                 ret = -EIO;
1025                 goto err_free_rx;
1026         }
1027
1028         /* TX buffer */
1029         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
1030                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1031         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
1032                 reason = "DMA mapping error for TX buffer";
1033                 ret = -EIO;
1034                 goto err_unmap_rx;
1035         }
1036
1037         return 0;
1038
1039 err_unmap_rx:
1040         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
1041                          DMA_FROM_DEVICE);
1042 err_free_rx:
1043         kfree(dma->rx_buf);
1044 err_release_tx:
1045         dma_release_channel(dma->tx_chan);
1046 err_release_rx:
1047         dma_release_channel(dma->rx_chan);
1048 err_warn:
1049         if (reason)
1050                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
1051         return ret;
1052 }
1053
1054 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
1055 {
1056         struct s3c24xx_uart_dma *dma = p->dma;
1057
1058         if (dma->rx_chan) {
1059                 dmaengine_terminate_all(dma->rx_chan);
1060                 dma_unmap_single(p->port.dev, dma->rx_addr,
1061                                 dma->rx_size, DMA_FROM_DEVICE);
1062                 kfree(dma->rx_buf);
1063                 dma_release_channel(dma->rx_chan);
1064                 dma->rx_chan = NULL;
1065         }
1066
1067         if (dma->tx_chan) {
1068                 dmaengine_terminate_all(dma->tx_chan);
1069                 dma_unmap_single(p->port.dev, dma->tx_addr,
1070                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1071                 dma_release_channel(dma->tx_chan);
1072                 dma->tx_chan = NULL;
1073         }
1074 }
1075
1076 static void s3c24xx_serial_shutdown(struct uart_port *port)
1077 {
1078         struct s3c24xx_uart_port *ourport = to_ourport(port);
1079
1080         if (ourport->tx_claimed) {
1081                 if (!s3c24xx_serial_has_interrupt_mask(port))
1082                         free_irq(ourport->tx_irq, ourport);
1083                 ourport->tx_enabled = 0;
1084                 ourport->tx_claimed = 0;
1085                 ourport->tx_mode = 0;
1086         }
1087
1088         if (ourport->rx_claimed) {
1089                 if (!s3c24xx_serial_has_interrupt_mask(port))
1090                         free_irq(ourport->rx_irq, ourport);
1091                 ourport->rx_claimed = 0;
1092                 ourport->rx_enabled = 0;
1093         }
1094
1095         /* Clear pending interrupts and mask all interrupts */
1096         if (s3c24xx_serial_has_interrupt_mask(port)) {
1097                 free_irq(port->irq, ourport);
1098
1099                 wr_regl(port, S3C64XX_UINTP, 0xf);
1100                 wr_regl(port, S3C64XX_UINTM, 0xf);
1101         }
1102
1103         if (ourport->dma)
1104                 s3c24xx_serial_release_dma(ourport);
1105
1106         ourport->tx_in_progress = 0;
1107 }
1108
1109 static int s3c24xx_serial_startup(struct uart_port *port)
1110 {
1111         struct s3c24xx_uart_port *ourport = to_ourport(port);
1112         int ret;
1113
1114         ourport->rx_enabled = 1;
1115
1116         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1117                           s3c24xx_serial_portname(port), ourport);
1118
1119         if (ret != 0) {
1120                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1121                 return ret;
1122         }
1123
1124         ourport->rx_claimed = 1;
1125
1126         dev_dbg(port->dev, "requesting tx irq...\n");
1127
1128         ourport->tx_enabled = 1;
1129
1130         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1131                           s3c24xx_serial_portname(port), ourport);
1132
1133         if (ret) {
1134                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1135                 goto err;
1136         }
1137
1138         ourport->tx_claimed = 1;
1139
1140         /* the port reset code should have done the correct
1141          * register setup for the port controls
1142          */
1143
1144         return ret;
1145
1146 err:
1147         s3c24xx_serial_shutdown(port);
1148         return ret;
1149 }
1150
1151 static int s3c64xx_serial_startup(struct uart_port *port)
1152 {
1153         struct s3c24xx_uart_port *ourport = to_ourport(port);
1154         unsigned long flags;
1155         unsigned int ufcon;
1156         int ret;
1157
1158         wr_regl(port, S3C64XX_UINTM, 0xf);
1159         if (ourport->dma) {
1160                 ret = s3c24xx_serial_request_dma(ourport);
1161                 if (ret < 0) {
1162                         devm_kfree(port->dev, ourport->dma);
1163                         ourport->dma = NULL;
1164                 }
1165         }
1166
1167         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1168                           s3c24xx_serial_portname(port), ourport);
1169         if (ret) {
1170                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1171                 return ret;
1172         }
1173
1174         /* For compatibility with s3c24xx Soc's */
1175         ourport->rx_enabled = 1;
1176         ourport->rx_claimed = 1;
1177         ourport->tx_enabled = 0;
1178         ourport->tx_claimed = 1;
1179
1180         spin_lock_irqsave(&port->lock, flags);
1181
1182         ufcon = rd_regl(port, S3C2410_UFCON);
1183         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1184         if (!uart_console(port))
1185                 ufcon |= S3C2410_UFCON_RESETTX;
1186         wr_regl(port, S3C2410_UFCON, ufcon);
1187
1188         enable_rx_pio(ourport);
1189
1190         spin_unlock_irqrestore(&port->lock, flags);
1191
1192         /* Enable Rx Interrupt */
1193         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1194
1195         return ret;
1196 }
1197
1198 /* power power management control */
1199
1200 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1201                               unsigned int old)
1202 {
1203         struct s3c24xx_uart_port *ourport = to_ourport(port);
1204         int timeout = 10000;
1205
1206         ourport->pm_level = level;
1207
1208         switch (level) {
1209         case 3:
1210                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1211                         udelay(100);
1212
1213                 if (!IS_ERR(ourport->baudclk))
1214                         clk_disable_unprepare(ourport->baudclk);
1215
1216                 clk_disable_unprepare(ourport->clk);
1217                 break;
1218
1219         case 0:
1220                 clk_prepare_enable(ourport->clk);
1221
1222                 if (!IS_ERR(ourport->baudclk))
1223                         clk_prepare_enable(ourport->baudclk);
1224
1225                 break;
1226         default:
1227                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1228         }
1229 }
1230
1231 /* baud rate calculation
1232  *
1233  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1234  * of different sources, including the peripheral clock ("pclk") and an
1235  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1236  * with a programmable extra divisor.
1237  *
1238  * The following code goes through the clock sources, and calculates the
1239  * baud clocks (and the resultant actual baud rates) and then tries to
1240  * pick the closest one and select that.
1241  *
1242  */
1243
1244 #define MAX_CLK_NAME_LENGTH 15
1245
1246 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1247 {
1248         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1249         unsigned int ucon;
1250
1251         if (info->num_clks == 1)
1252                 return 0;
1253
1254         ucon = rd_regl(port, S3C2410_UCON);
1255         ucon &= info->clksel_mask;
1256         return ucon >> info->clksel_shift;
1257 }
1258
1259 static void s3c24xx_serial_setsource(struct uart_port *port,
1260                         unsigned int clk_sel)
1261 {
1262         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1263         unsigned int ucon;
1264
1265         if (info->num_clks == 1)
1266                 return;
1267
1268         ucon = rd_regl(port, S3C2410_UCON);
1269         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1270                 return;
1271
1272         ucon &= ~info->clksel_mask;
1273         ucon |= clk_sel << info->clksel_shift;
1274         wr_regl(port, S3C2410_UCON, ucon);
1275 }
1276
1277 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1278                         unsigned int req_baud, struct clk **best_clk,
1279                         unsigned int *clk_num)
1280 {
1281         struct s3c24xx_uart_info *info = ourport->info;
1282         struct clk *clk;
1283         unsigned long rate;
1284         unsigned int cnt, baud, quot, clk_sel, best_quot = 0;
1285         char clkname[MAX_CLK_NAME_LENGTH];
1286         int calc_deviation, deviation = (1 << 30) - 1;
1287
1288         clk_sel = (ourport->cfg->clk_sel) ? ourport->cfg->clk_sel :
1289                         ourport->info->def_clk_sel;
1290         for (cnt = 0; cnt < info->num_clks; cnt++) {
1291                 if (!(clk_sel & (1 << cnt)))
1292                         continue;
1293
1294                 sprintf(clkname, "clk_uart_baud%d", cnt);
1295                 clk = clk_get(ourport->port.dev, clkname);
1296                 if (IS_ERR(clk))
1297                         continue;
1298
1299                 rate = clk_get_rate(clk);
1300                 if (!rate)
1301                         continue;
1302
1303                 if (ourport->info->has_divslot) {
1304                         unsigned long div = rate / req_baud;
1305
1306                         /* The UDIVSLOT register on the newer UARTs allows us to
1307                          * get a divisor adjustment of 1/16th on the baud clock.
1308                          *
1309                          * We don't keep the UDIVSLOT value (the 16ths we
1310                          * calculated by not multiplying the baud by 16) as it
1311                          * is easy enough to recalculate.
1312                          */
1313
1314                         quot = div / 16;
1315                         baud = rate / div;
1316                 } else {
1317                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1318                         baud = rate / (quot * 16);
1319                 }
1320                 quot--;
1321
1322                 calc_deviation = req_baud - baud;
1323                 if (calc_deviation < 0)
1324                         calc_deviation = -calc_deviation;
1325
1326                 if (calc_deviation < deviation) {
1327                         *best_clk = clk;
1328                         best_quot = quot;
1329                         *clk_num = cnt;
1330                         deviation = calc_deviation;
1331                 }
1332         }
1333
1334         return best_quot;
1335 }
1336
1337 /* udivslot_table[]
1338  *
1339  * This table takes the fractional value of the baud divisor and gives
1340  * the recommended setting for the UDIVSLOT register.
1341  */
1342 static u16 udivslot_table[16] = {
1343         [0] = 0x0000,
1344         [1] = 0x0080,
1345         [2] = 0x0808,
1346         [3] = 0x0888,
1347         [4] = 0x2222,
1348         [5] = 0x4924,
1349         [6] = 0x4A52,
1350         [7] = 0x54AA,
1351         [8] = 0x5555,
1352         [9] = 0xD555,
1353         [10] = 0xD5D5,
1354         [11] = 0xDDD5,
1355         [12] = 0xDDDD,
1356         [13] = 0xDFDD,
1357         [14] = 0xDFDF,
1358         [15] = 0xFFDF,
1359 };
1360
1361 static void s3c24xx_serial_set_termios(struct uart_port *port,
1362                                        struct ktermios *termios,
1363                                        struct ktermios *old)
1364 {
1365         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1366         struct s3c24xx_uart_port *ourport = to_ourport(port);
1367         struct clk *clk = ERR_PTR(-EINVAL);
1368         unsigned long flags;
1369         unsigned int baud, quot, clk_sel = 0;
1370         unsigned int ulcon;
1371         unsigned int umcon;
1372         unsigned int udivslot = 0;
1373
1374         /*
1375          * We don't support modem control lines.
1376          */
1377         termios->c_cflag &= ~(HUPCL | CMSPAR);
1378         termios->c_cflag |= CLOCAL;
1379
1380         /*
1381          * Ask the core to calculate the divisor for us.
1382          */
1383
1384         baud = uart_get_baud_rate(port, termios, old, 0, 3000000);
1385         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1386         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1387                 quot = port->custom_divisor;
1388         if (IS_ERR(clk))
1389                 return;
1390
1391         /* check to see if we need  to change clock source */
1392
1393         if (ourport->baudclk != clk) {
1394                 clk_prepare_enable(clk);
1395
1396                 s3c24xx_serial_setsource(port, clk_sel);
1397
1398                 if (!IS_ERR(ourport->baudclk)) {
1399                         clk_disable_unprepare(ourport->baudclk);
1400                         ourport->baudclk = ERR_PTR(-EINVAL);
1401                 }
1402
1403                 ourport->baudclk = clk;
1404                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1405         }
1406
1407         if (ourport->info->has_divslot) {
1408                 unsigned int div = ourport->baudclk_rate / baud;
1409
1410                 if (cfg->has_fracval) {
1411                         udivslot = (div & 15);
1412                         dev_dbg(port->dev, "fracval = %04x\n", udivslot);
1413                 } else {
1414                         udivslot = udivslot_table[div & 15];
1415                         dev_dbg(port->dev, "udivslot = %04x (div %d)\n",
1416                                 udivslot, div & 15);
1417                 }
1418         }
1419
1420         switch (termios->c_cflag & CSIZE) {
1421         case CS5:
1422                 dev_dbg(port->dev, "config: 5bits/char\n");
1423                 ulcon = S3C2410_LCON_CS5;
1424                 break;
1425         case CS6:
1426                 dev_dbg(port->dev, "config: 6bits/char\n");
1427                 ulcon = S3C2410_LCON_CS6;
1428                 break;
1429         case CS7:
1430                 dev_dbg(port->dev, "config: 7bits/char\n");
1431                 ulcon = S3C2410_LCON_CS7;
1432                 break;
1433         case CS8:
1434         default:
1435                 dev_dbg(port->dev, "config: 8bits/char\n");
1436                 ulcon = S3C2410_LCON_CS8;
1437                 break;
1438         }
1439
1440         /* preserve original lcon IR settings */
1441         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1442
1443         if (termios->c_cflag & CSTOPB)
1444                 ulcon |= S3C2410_LCON_STOPB;
1445
1446         if (termios->c_cflag & PARENB) {
1447                 if (termios->c_cflag & PARODD)
1448                         ulcon |= S3C2410_LCON_PODD;
1449                 else
1450                         ulcon |= S3C2410_LCON_PEVEN;
1451         } else {
1452                 ulcon |= S3C2410_LCON_PNONE;
1453         }
1454
1455         spin_lock_irqsave(&port->lock, flags);
1456
1457         dev_dbg(port->dev,
1458                 "setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1459                 ulcon, quot, udivslot);
1460
1461         wr_regl(port, S3C2410_ULCON, ulcon);
1462         wr_regl(port, S3C2410_UBRDIV, quot);
1463
1464         port->status &= ~UPSTAT_AUTOCTS;
1465
1466         umcon = rd_regl(port, S3C2410_UMCON);
1467         if (termios->c_cflag & CRTSCTS) {
1468                 umcon |= S3C2410_UMCOM_AFC;
1469                 /* Disable RTS when RX FIFO contains 63 bytes */
1470                 umcon &= ~S3C2412_UMCON_AFC_8;
1471                 port->status = UPSTAT_AUTOCTS;
1472         } else {
1473                 umcon &= ~S3C2410_UMCOM_AFC;
1474         }
1475         wr_regl(port, S3C2410_UMCON, umcon);
1476
1477         if (ourport->info->has_divslot)
1478                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1479
1480         dev_dbg(port->dev,
1481                 "uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1482                 rd_regl(port, S3C2410_ULCON),
1483                 rd_regl(port, S3C2410_UCON),
1484                 rd_regl(port, S3C2410_UFCON));
1485
1486         /*
1487          * Update the per-port timeout.
1488          */
1489         uart_update_timeout(port, termios->c_cflag, baud);
1490
1491         /*
1492          * Which character status flags are we interested in?
1493          */
1494         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1495         if (termios->c_iflag & INPCK)
1496                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1497                         S3C2410_UERSTAT_PARITY;
1498         /*
1499          * Which character status flags should we ignore?
1500          */
1501         port->ignore_status_mask = 0;
1502         if (termios->c_iflag & IGNPAR)
1503                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1504         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1505                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1506
1507         /*
1508          * Ignore all characters if CREAD is not set.
1509          */
1510         if ((termios->c_cflag & CREAD) == 0)
1511                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1512
1513         spin_unlock_irqrestore(&port->lock, flags);
1514 }
1515
1516 static const char *s3c24xx_serial_type(struct uart_port *port)
1517 {
1518         switch (port->type) {
1519         case PORT_S3C2410:
1520                 return "S3C2410";
1521         case PORT_S3C2440:
1522                 return "S3C2440";
1523         case PORT_S3C2412:
1524                 return "S3C2412";
1525         case PORT_S3C6400:
1526                 return "S3C6400/10";
1527         default:
1528                 return NULL;
1529         }
1530 }
1531
1532 #define MAP_SIZE (0x100)
1533
1534 static void s3c24xx_serial_release_port(struct uart_port *port)
1535 {
1536         release_mem_region(port->mapbase, MAP_SIZE);
1537 }
1538
1539 static int s3c24xx_serial_request_port(struct uart_port *port)
1540 {
1541         const char *name = s3c24xx_serial_portname(port);
1542
1543         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1544 }
1545
1546 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1547 {
1548         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1549
1550         if (flags & UART_CONFIG_TYPE &&
1551             s3c24xx_serial_request_port(port) == 0)
1552                 port->type = info->type;
1553 }
1554
1555 /*
1556  * verify the new serial_struct (for TIOCSSERIAL).
1557  */
1558 static int
1559 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1560 {
1561         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1562
1563         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1564                 return -EINVAL;
1565
1566         return 0;
1567 }
1568
1569
1570 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1571
1572 static struct console s3c24xx_serial_console;
1573
1574 static int __init s3c24xx_serial_console_init(void)
1575 {
1576         register_console(&s3c24xx_serial_console);
1577         return 0;
1578 }
1579 console_initcall(s3c24xx_serial_console_init);
1580
1581 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1582 #else
1583 #define S3C24XX_SERIAL_CONSOLE NULL
1584 #endif
1585
1586 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1587 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1588 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1589                          unsigned char c);
1590 #endif
1591
1592 static struct uart_ops s3c24xx_serial_ops = {
1593         .pm             = s3c24xx_serial_pm,
1594         .tx_empty       = s3c24xx_serial_tx_empty,
1595         .get_mctrl      = s3c24xx_serial_get_mctrl,
1596         .set_mctrl      = s3c24xx_serial_set_mctrl,
1597         .stop_tx        = s3c24xx_serial_stop_tx,
1598         .start_tx       = s3c24xx_serial_start_tx,
1599         .stop_rx        = s3c24xx_serial_stop_rx,
1600         .break_ctl      = s3c24xx_serial_break_ctl,
1601         .startup        = s3c24xx_serial_startup,
1602         .shutdown       = s3c24xx_serial_shutdown,
1603         .set_termios    = s3c24xx_serial_set_termios,
1604         .type           = s3c24xx_serial_type,
1605         .release_port   = s3c24xx_serial_release_port,
1606         .request_port   = s3c24xx_serial_request_port,
1607         .config_port    = s3c24xx_serial_config_port,
1608         .verify_port    = s3c24xx_serial_verify_port,
1609 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1610         .poll_get_char = s3c24xx_serial_get_poll_char,
1611         .poll_put_char = s3c24xx_serial_put_poll_char,
1612 #endif
1613 };
1614
1615 static struct uart_driver s3c24xx_uart_drv = {
1616         .owner          = THIS_MODULE,
1617         .driver_name    = "s3c2410_serial",
1618         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1619         .cons           = S3C24XX_SERIAL_CONSOLE,
1620         .dev_name       = S3C24XX_SERIAL_NAME,
1621         .major          = S3C24XX_SERIAL_MAJOR,
1622         .minor          = S3C24XX_SERIAL_MINOR,
1623 };
1624
1625 #define __PORT_LOCK_UNLOCKED(i) \
1626         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1627 static struct s3c24xx_uart_port
1628 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1629         [0] = {
1630                 .port = {
1631                         .lock           = __PORT_LOCK_UNLOCKED(0),
1632                         .iotype         = UPIO_MEM,
1633                         .uartclk        = 0,
1634                         .fifosize       = 16,
1635                         .ops            = &s3c24xx_serial_ops,
1636                         .flags          = UPF_BOOT_AUTOCONF,
1637                         .line           = 0,
1638                 }
1639         },
1640         [1] = {
1641                 .port = {
1642                         .lock           = __PORT_LOCK_UNLOCKED(1),
1643                         .iotype         = UPIO_MEM,
1644                         .uartclk        = 0,
1645                         .fifosize       = 16,
1646                         .ops            = &s3c24xx_serial_ops,
1647                         .flags          = UPF_BOOT_AUTOCONF,
1648                         .line           = 1,
1649                 }
1650         },
1651 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1652
1653         [2] = {
1654                 .port = {
1655                         .lock           = __PORT_LOCK_UNLOCKED(2),
1656                         .iotype         = UPIO_MEM,
1657                         .uartclk        = 0,
1658                         .fifosize       = 16,
1659                         .ops            = &s3c24xx_serial_ops,
1660                         .flags          = UPF_BOOT_AUTOCONF,
1661                         .line           = 2,
1662                 }
1663         },
1664 #endif
1665 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1666         [3] = {
1667                 .port = {
1668                         .lock           = __PORT_LOCK_UNLOCKED(3),
1669                         .iotype         = UPIO_MEM,
1670                         .uartclk        = 0,
1671                         .fifosize       = 16,
1672                         .ops            = &s3c24xx_serial_ops,
1673                         .flags          = UPF_BOOT_AUTOCONF,
1674                         .line           = 3,
1675                 }
1676         }
1677 #endif
1678 };
1679 #undef __PORT_LOCK_UNLOCKED
1680
1681 /* s3c24xx_serial_resetport
1682  *
1683  * reset the fifos and other the settings.
1684  */
1685
1686 static void s3c24xx_serial_resetport(struct uart_port *port,
1687                                    struct s3c2410_uartcfg *cfg)
1688 {
1689         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1690         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1691         unsigned int ucon_mask;
1692
1693         ucon_mask = info->clksel_mask;
1694         if (info->type == PORT_S3C2440)
1695                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1696
1697         ucon &= ucon_mask;
1698         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1699
1700         /* reset both fifos */
1701         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1702         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1703
1704         /* some delay is required after fifo reset */
1705         udelay(1);
1706 }
1707
1708
1709 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1710
1711 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1712                                              unsigned long val, void *data)
1713 {
1714         struct s3c24xx_uart_port *port;
1715         struct uart_port *uport;
1716
1717         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1718         uport = &port->port;
1719
1720         /* check to see if port is enabled */
1721
1722         if (port->pm_level != 0)
1723                 return 0;
1724
1725         /* try and work out if the baudrate is changing, we can detect
1726          * a change in rate, but we do not have support for detecting
1727          * a disturbance in the clock-rate over the change.
1728          */
1729
1730         if (IS_ERR(port->baudclk))
1731                 goto exit;
1732
1733         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1734                 goto exit;
1735
1736         if (val == CPUFREQ_PRECHANGE) {
1737                 /* we should really shut the port down whilst the
1738                  * frequency change is in progress.
1739                  */
1740
1741         } else if (val == CPUFREQ_POSTCHANGE) {
1742                 struct ktermios *termios;
1743                 struct tty_struct *tty;
1744
1745                 if (uport->state == NULL)
1746                         goto exit;
1747
1748                 tty = uport->state->port.tty;
1749
1750                 if (tty == NULL)
1751                         goto exit;
1752
1753                 termios = &tty->termios;
1754
1755                 if (termios == NULL) {
1756                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1757                         goto exit;
1758                 }
1759
1760                 s3c24xx_serial_set_termios(uport, termios, NULL);
1761         }
1762
1763 exit:
1764         return 0;
1765 }
1766
1767 static inline int
1768 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1769 {
1770         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1771
1772         return cpufreq_register_notifier(&port->freq_transition,
1773                                          CPUFREQ_TRANSITION_NOTIFIER);
1774 }
1775
1776 static inline void
1777 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1778 {
1779         cpufreq_unregister_notifier(&port->freq_transition,
1780                                     CPUFREQ_TRANSITION_NOTIFIER);
1781 }
1782
1783 #else
1784 static inline int
1785 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1786 {
1787         return 0;
1788 }
1789
1790 static inline void
1791 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1792 {
1793 }
1794 #endif
1795
1796 static int s3c24xx_serial_enable_baudclk(struct s3c24xx_uart_port *ourport)
1797 {
1798         struct device *dev = ourport->port.dev;
1799         struct s3c24xx_uart_info *info = ourport->info;
1800         char clk_name[MAX_CLK_NAME_LENGTH];
1801         unsigned int clk_sel;
1802         struct clk *clk;
1803         int clk_num;
1804         int ret;
1805
1806         clk_sel = ourport->cfg->clk_sel ? : info->def_clk_sel;
1807         for (clk_num = 0; clk_num < info->num_clks; clk_num++) {
1808                 if (!(clk_sel & (1 << clk_num)))
1809                         continue;
1810
1811                 sprintf(clk_name, "clk_uart_baud%d", clk_num);
1812                 clk = clk_get(dev, clk_name);
1813                 if (IS_ERR(clk))
1814                         continue;
1815
1816                 ret = clk_prepare_enable(clk);
1817                 if (ret) {
1818                         clk_put(clk);
1819                         continue;
1820                 }
1821
1822                 ourport->baudclk = clk;
1823                 ourport->baudclk_rate = clk_get_rate(clk);
1824                 s3c24xx_serial_setsource(&ourport->port, clk_num);
1825
1826                 return 0;
1827         }
1828
1829         return -EINVAL;
1830 }
1831
1832 /* s3c24xx_serial_init_port
1833  *
1834  * initialise a single serial port from the platform device given
1835  */
1836
1837 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1838                                     struct platform_device *platdev)
1839 {
1840         struct uart_port *port = &ourport->port;
1841         struct s3c2410_uartcfg *cfg = ourport->cfg;
1842         struct resource *res;
1843         int ret;
1844
1845         if (platdev == NULL)
1846                 return -ENODEV;
1847
1848         if (port->mapbase != 0)
1849                 return -EINVAL;
1850
1851         /* setup info for port */
1852         port->dev       = &platdev->dev;
1853
1854         /* Startup sequence is different for s3c64xx and higher SoC's */
1855         if (s3c24xx_serial_has_interrupt_mask(port))
1856                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1857
1858         port->uartclk = 1;
1859
1860         if (cfg->uart_flags & UPF_CONS_FLOW) {
1861                 dev_dbg(port->dev, "enabling flow control\n");
1862                 port->flags |= UPF_CONS_FLOW;
1863         }
1864
1865         /* sort our the physical and virtual addresses for each UART */
1866
1867         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1868         if (res == NULL) {
1869                 dev_err(port->dev, "failed to find memory resource for uart\n");
1870                 return -EINVAL;
1871         }
1872
1873         dev_dbg(port->dev, "resource %pR)\n", res);
1874
1875         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1876         if (!port->membase) {
1877                 dev_err(port->dev, "failed to remap controller address\n");
1878                 return -EBUSY;
1879         }
1880
1881         port->mapbase = res->start;
1882         ret = platform_get_irq(platdev, 0);
1883         if (ret < 0)
1884                 port->irq = 0;
1885         else {
1886                 port->irq = ret;
1887                 ourport->rx_irq = ret;
1888                 ourport->tx_irq = ret + 1;
1889         }
1890
1891         ret = platform_get_irq(platdev, 1);
1892         if (ret > 0)
1893                 ourport->tx_irq = ret;
1894         /*
1895          * DMA is currently supported only on DT platforms, if DMA properties
1896          * are specified.
1897          */
1898         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1899                                                      "dmas", NULL)) {
1900                 ourport->dma = devm_kzalloc(port->dev,
1901                                             sizeof(*ourport->dma),
1902                                             GFP_KERNEL);
1903                 if (!ourport->dma) {
1904                         ret = -ENOMEM;
1905                         goto err;
1906                 }
1907         }
1908
1909         ourport->clk    = clk_get(&platdev->dev, "uart");
1910         if (IS_ERR(ourport->clk)) {
1911                 pr_err("%s: Controller clock not found\n",
1912                                 dev_name(&platdev->dev));
1913                 ret = PTR_ERR(ourport->clk);
1914                 goto err;
1915         }
1916
1917         ret = clk_prepare_enable(ourport->clk);
1918         if (ret) {
1919                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1920                 clk_put(ourport->clk);
1921                 goto err;
1922         }
1923
1924         ret = s3c24xx_serial_enable_baudclk(ourport);
1925         if (ret)
1926                 pr_warn("uart: failed to enable baudclk\n");
1927
1928         /* Keep all interrupts masked and cleared */
1929         if (s3c24xx_serial_has_interrupt_mask(port)) {
1930                 wr_regl(port, S3C64XX_UINTM, 0xf);
1931                 wr_regl(port, S3C64XX_UINTP, 0xf);
1932                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1933         }
1934
1935         dev_dbg(port->dev, "port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1936                 &port->mapbase, port->membase, port->irq,
1937                 ourport->rx_irq, ourport->tx_irq, port->uartclk);
1938
1939         /* reset the fifos (and setup the uart) */
1940         s3c24xx_serial_resetport(port, cfg);
1941
1942         return 0;
1943
1944 err:
1945         port->mapbase = 0;
1946         return ret;
1947 }
1948
1949 /* Device driver serial port probe */
1950
1951 #ifdef CONFIG_OF
1952 static const struct of_device_id s3c24xx_uart_dt_match[];
1953 #endif
1954
1955 static int probe_index;
1956
1957 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1958                         struct platform_device *pdev)
1959 {
1960 #ifdef CONFIG_OF
1961         if (pdev->dev.of_node) {
1962                 const struct of_device_id *match;
1963
1964                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1965                 return (struct s3c24xx_serial_drv_data *)match->data;
1966         }
1967 #endif
1968         return (struct s3c24xx_serial_drv_data *)
1969                         platform_get_device_id(pdev)->driver_data;
1970 }
1971
1972 static int s3c24xx_serial_probe(struct platform_device *pdev)
1973 {
1974         struct device_node *np = pdev->dev.of_node;
1975         struct s3c24xx_uart_port *ourport;
1976         int index = probe_index;
1977         int ret;
1978
1979         if (np) {
1980                 ret = of_alias_get_id(np, "serial");
1981                 if (ret >= 0)
1982                         index = ret;
1983         }
1984
1985         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1986                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1987                 return -EINVAL;
1988         }
1989         ourport = &s3c24xx_serial_ports[index];
1990
1991         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1992         if (!ourport->drv_data) {
1993                 dev_err(&pdev->dev, "could not find driver data\n");
1994                 return -ENODEV;
1995         }
1996
1997         ourport->baudclk = ERR_PTR(-EINVAL);
1998         ourport->info = ourport->drv_data->info;
1999         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
2000                         dev_get_platdata(&pdev->dev) :
2001                         ourport->drv_data->def_cfg;
2002
2003         if (np)
2004                 of_property_read_u32(np,
2005                         "samsung,uart-fifosize", &ourport->port.fifosize);
2006
2007         if (ourport->drv_data->fifosize[index])
2008                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
2009         else if (ourport->info->fifosize)
2010                 ourport->port.fifosize = ourport->info->fifosize;
2011         ourport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_SAMSUNG_CONSOLE);
2012
2013         /*
2014          * DMA transfers must be aligned at least to cache line size,
2015          * so find minimal transfer size suitable for DMA mode
2016          */
2017         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
2018                                     dma_get_cache_alignment());
2019
2020         dev_dbg(&pdev->dev, "%s: initialising port %p...\n", __func__, ourport);
2021
2022         ret = s3c24xx_serial_init_port(ourport, pdev);
2023         if (ret < 0)
2024                 return ret;
2025
2026         if (!s3c24xx_uart_drv.state) {
2027                 ret = uart_register_driver(&s3c24xx_uart_drv);
2028                 if (ret < 0) {
2029                         pr_err("Failed to register Samsung UART driver\n");
2030                         return ret;
2031                 }
2032         }
2033
2034         dev_dbg(&pdev->dev, "%s: adding port\n", __func__);
2035         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
2036         platform_set_drvdata(pdev, &ourport->port);
2037
2038         /*
2039          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
2040          * so that a potential re-enablement through the pm-callback overlaps
2041          * and keeps the clock enabled in this case.
2042          */
2043         clk_disable_unprepare(ourport->clk);
2044         if (!IS_ERR(ourport->baudclk))
2045                 clk_disable_unprepare(ourport->baudclk);
2046
2047         ret = s3c24xx_serial_cpufreq_register(ourport);
2048         if (ret < 0)
2049                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
2050
2051         probe_index++;
2052
2053         return 0;
2054 }
2055
2056 static int s3c24xx_serial_remove(struct platform_device *dev)
2057 {
2058         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
2059
2060         if (port) {
2061                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
2062                 uart_remove_one_port(&s3c24xx_uart_drv, port);
2063         }
2064
2065         uart_unregister_driver(&s3c24xx_uart_drv);
2066
2067         return 0;
2068 }
2069
2070 /* UART power management code */
2071 #ifdef CONFIG_PM_SLEEP
2072 static int s3c24xx_serial_suspend(struct device *dev)
2073 {
2074         struct uart_port *port = s3c24xx_dev_to_port(dev);
2075
2076         if (port)
2077                 uart_suspend_port(&s3c24xx_uart_drv, port);
2078
2079         return 0;
2080 }
2081
2082 static int s3c24xx_serial_resume(struct device *dev)
2083 {
2084         struct uart_port *port = s3c24xx_dev_to_port(dev);
2085         struct s3c24xx_uart_port *ourport = to_ourport(port);
2086
2087         if (port) {
2088                 clk_prepare_enable(ourport->clk);
2089                 if (!IS_ERR(ourport->baudclk))
2090                         clk_prepare_enable(ourport->baudclk);
2091                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
2092                 if (!IS_ERR(ourport->baudclk))
2093                         clk_disable_unprepare(ourport->baudclk);
2094                 clk_disable_unprepare(ourport->clk);
2095
2096                 uart_resume_port(&s3c24xx_uart_drv, port);
2097         }
2098
2099         return 0;
2100 }
2101
2102 static int s3c24xx_serial_resume_noirq(struct device *dev)
2103 {
2104         struct uart_port *port = s3c24xx_dev_to_port(dev);
2105         struct s3c24xx_uart_port *ourport = to_ourport(port);
2106
2107         if (port) {
2108                 /* restore IRQ mask */
2109                 if (s3c24xx_serial_has_interrupt_mask(port)) {
2110                         unsigned int uintm = 0xf;
2111
2112                         if (ourport->tx_enabled)
2113                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
2114                         if (ourport->rx_enabled)
2115                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
2116                         clk_prepare_enable(ourport->clk);
2117                         if (!IS_ERR(ourport->baudclk))
2118                                 clk_prepare_enable(ourport->baudclk);
2119                         wr_regl(port, S3C64XX_UINTM, uintm);
2120                         if (!IS_ERR(ourport->baudclk))
2121                                 clk_disable_unprepare(ourport->baudclk);
2122                         clk_disable_unprepare(ourport->clk);
2123                 }
2124         }
2125
2126         return 0;
2127 }
2128
2129 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
2130         .suspend = s3c24xx_serial_suspend,
2131         .resume = s3c24xx_serial_resume,
2132         .resume_noirq = s3c24xx_serial_resume_noirq,
2133 };
2134 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
2135
2136 #else /* !CONFIG_PM_SLEEP */
2137
2138 #define SERIAL_SAMSUNG_PM_OPS   NULL
2139 #endif /* CONFIG_PM_SLEEP */
2140
2141 /* Console code */
2142
2143 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2144
2145 static struct uart_port *cons_uart;
2146
2147 static int
2148 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2149 {
2150         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2151         unsigned long ufstat, utrstat;
2152
2153         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2154                 /* fifo mode - check amount of data in fifo registers... */
2155
2156                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2157                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2158         }
2159
2160         /* in non-fifo mode, we go and use the tx buffer empty */
2161
2162         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2163         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2164 }
2165
2166 static bool
2167 s3c24xx_port_configured(unsigned int ucon)
2168 {
2169         /* consider the serial port configured if the tx/rx mode set */
2170         return (ucon & 0xf) != 0;
2171 }
2172
2173 #ifdef CONFIG_CONSOLE_POLL
2174 /*
2175  * Console polling routines for writing and reading from the uart while
2176  * in an interrupt or debug context.
2177  */
2178
2179 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2180 {
2181         struct s3c24xx_uart_port *ourport = to_ourport(port);
2182         unsigned int ufstat;
2183
2184         ufstat = rd_regl(port, S3C2410_UFSTAT);
2185         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2186                 return NO_POLL_CHAR;
2187
2188         return rd_regb(port, S3C2410_URXH);
2189 }
2190
2191 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2192                 unsigned char c)
2193 {
2194         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2195         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2196
2197         /* not possible to xmit on unconfigured port */
2198         if (!s3c24xx_port_configured(ucon))
2199                 return;
2200
2201         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2202                 cpu_relax();
2203         wr_regb(port, S3C2410_UTXH, c);
2204 }
2205
2206 #endif /* CONFIG_CONSOLE_POLL */
2207
2208 static void
2209 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2210 {
2211         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2212
2213         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2214                 cpu_relax();
2215         wr_regb(port, S3C2410_UTXH, ch);
2216 }
2217
2218 static void
2219 s3c24xx_serial_console_write(struct console *co, const char *s,
2220                              unsigned int count)
2221 {
2222         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2223
2224         /* not possible to xmit on unconfigured port */
2225         if (!s3c24xx_port_configured(ucon))
2226                 return;
2227
2228         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2229 }
2230
2231 static void __init
2232 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2233                            int *parity, int *bits)
2234 {
2235         struct clk *clk;
2236         unsigned int ulcon;
2237         unsigned int ucon;
2238         unsigned int ubrdiv;
2239         unsigned long rate;
2240         unsigned int clk_sel;
2241         char clk_name[MAX_CLK_NAME_LENGTH];
2242
2243         ulcon  = rd_regl(port, S3C2410_ULCON);
2244         ucon   = rd_regl(port, S3C2410_UCON);
2245         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2246
2247         if (s3c24xx_port_configured(ucon)) {
2248                 switch (ulcon & S3C2410_LCON_CSMASK) {
2249                 case S3C2410_LCON_CS5:
2250                         *bits = 5;
2251                         break;
2252                 case S3C2410_LCON_CS6:
2253                         *bits = 6;
2254                         break;
2255                 case S3C2410_LCON_CS7:
2256                         *bits = 7;
2257                         break;
2258                 case S3C2410_LCON_CS8:
2259                 default:
2260                         *bits = 8;
2261                         break;
2262                 }
2263
2264                 switch (ulcon & S3C2410_LCON_PMASK) {
2265                 case S3C2410_LCON_PEVEN:
2266                         *parity = 'e';
2267                         break;
2268
2269                 case S3C2410_LCON_PODD:
2270                         *parity = 'o';
2271                         break;
2272
2273                 case S3C2410_LCON_PNONE:
2274                 default:
2275                         *parity = 'n';
2276                 }
2277
2278                 /* now calculate the baud rate */
2279
2280                 clk_sel = s3c24xx_serial_getsource(port);
2281                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2282
2283                 clk = clk_get(port->dev, clk_name);
2284                 if (!IS_ERR(clk))
2285                         rate = clk_get_rate(clk);
2286                 else
2287                         rate = 1;
2288
2289                 *baud = rate / (16 * (ubrdiv + 1));
2290                 dev_dbg(port->dev, "calculated baud %d\n", *baud);
2291         }
2292
2293 }
2294
2295 static int __init
2296 s3c24xx_serial_console_setup(struct console *co, char *options)
2297 {
2298         struct uart_port *port;
2299         int baud = 9600;
2300         int bits = 8;
2301         int parity = 'n';
2302         int flow = 'n';
2303
2304         /* is this a valid port */
2305
2306         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2307                 co->index = 0;
2308
2309         port = &s3c24xx_serial_ports[co->index].port;
2310
2311         /* is the port configured? */
2312
2313         if (port->mapbase == 0x0)
2314                 return -ENODEV;
2315
2316         cons_uart = port;
2317
2318         /*
2319          * Check whether an invalid uart number has been specified, and
2320          * if so, search for the first available port that does have
2321          * console support.
2322          */
2323         if (options)
2324                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2325         else
2326                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2327
2328         dev_dbg(port->dev, "baud %d\n", baud);
2329
2330         return uart_set_options(port, co, baud, parity, bits, flow);
2331 }
2332
2333 static struct console s3c24xx_serial_console = {
2334         .name           = S3C24XX_SERIAL_NAME,
2335         .device         = uart_console_device,
2336         .flags          = CON_PRINTBUFFER,
2337         .index          = -1,
2338         .write          = s3c24xx_serial_console_write,
2339         .setup          = s3c24xx_serial_console_setup,
2340         .data           = &s3c24xx_uart_drv,
2341 };
2342 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2343
2344 #ifdef CONFIG_CPU_S3C2410
2345 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2346         .info = &(struct s3c24xx_uart_info) {
2347                 .name           = "Samsung S3C2410 UART",
2348                 .type           = PORT_S3C2410,
2349                 .fifosize       = 16,
2350                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2351                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2352                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2353                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2354                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2355                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2356                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2357                 .num_clks       = 2,
2358                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2359                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2360         },
2361         .def_cfg = &(struct s3c2410_uartcfg) {
2362                 .ucon           = S3C2410_UCON_DEFAULT,
2363                 .ufcon          = S3C2410_UFCON_DEFAULT,
2364         },
2365 };
2366 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2367 #else
2368 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2369 #endif
2370
2371 #ifdef CONFIG_CPU_S3C2412
2372 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2373         .info = &(struct s3c24xx_uart_info) {
2374                 .name           = "Samsung S3C2412 UART",
2375                 .type           = PORT_S3C2412,
2376                 .fifosize       = 64,
2377                 .has_divslot    = 1,
2378                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2379                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2380                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2381                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2382                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2383                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2384                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2385                 .num_clks       = 4,
2386                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2387                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2388         },
2389         .def_cfg = &(struct s3c2410_uartcfg) {
2390                 .ucon           = S3C2410_UCON_DEFAULT,
2391                 .ufcon          = S3C2410_UFCON_DEFAULT,
2392         },
2393 };
2394 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2395 #else
2396 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2397 #endif
2398
2399 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2400         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2401 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2402         .info = &(struct s3c24xx_uart_info) {
2403                 .name           = "Samsung S3C2440 UART",
2404                 .type           = PORT_S3C2440,
2405                 .fifosize       = 64,
2406                 .has_divslot    = 1,
2407                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2408                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2409                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2410                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2411                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2412                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2413                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2414                 .num_clks       = 4,
2415                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2416                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2417         },
2418         .def_cfg = &(struct s3c2410_uartcfg) {
2419                 .ucon           = S3C2410_UCON_DEFAULT,
2420                 .ufcon          = S3C2410_UFCON_DEFAULT,
2421         },
2422 };
2423 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2424 #else
2425 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2426 #endif
2427
2428 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2429 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2430         .info = &(struct s3c24xx_uart_info) {
2431                 .name           = "Samsung S3C6400 UART",
2432                 .type           = PORT_S3C6400,
2433                 .fifosize       = 64,
2434                 .has_divslot    = 1,
2435                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2436                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2437                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2438                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2439                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2440                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2441                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2442                 .num_clks       = 4,
2443                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2444                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2445         },
2446         .def_cfg = &(struct s3c2410_uartcfg) {
2447                 .ucon           = S3C2410_UCON_DEFAULT,
2448                 .ufcon          = S3C2410_UFCON_DEFAULT,
2449         },
2450 };
2451 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2452 #else
2453 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2454 #endif
2455
2456 #ifdef CONFIG_CPU_S5PV210
2457 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2458         .info = &(struct s3c24xx_uart_info) {
2459                 .name           = "Samsung S5PV210 UART",
2460                 .type           = PORT_S3C6400,
2461                 .has_divslot    = 1,
2462                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2463                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2464                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2465                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2466                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2467                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2468                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2469                 .num_clks       = 2,
2470                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2471                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2472         },
2473         .def_cfg = &(struct s3c2410_uartcfg) {
2474                 .ucon           = S5PV210_UCON_DEFAULT,
2475                 .ufcon          = S5PV210_UFCON_DEFAULT,
2476         },
2477         .fifosize = { 256, 64, 16, 16 },
2478 };
2479 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2480 #else
2481 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2482 #endif
2483
2484 #if defined(CONFIG_ARCH_EXYNOS)
2485 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2486         .info = &(struct s3c24xx_uart_info) {                   \
2487                 .name           = "Samsung Exynos UART",        \
2488                 .type           = PORT_S3C6400,                 \
2489                 .has_divslot    = 1,                            \
2490                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2491                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2492                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2493                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2494                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2495                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2496                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2497                 .num_clks       = 1,                            \
2498                 .clksel_mask    = 0,                            \
2499                 .clksel_shift   = 0,                            \
2500         },                                                      \
2501         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2502                 .ucon           = S5PV210_UCON_DEFAULT,         \
2503                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2504                 .has_fracval    = 1,                            \
2505         }                                                       \
2506
2507 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2508         EXYNOS_COMMON_SERIAL_DRV_DATA,
2509         .fifosize = { 256, 64, 16, 16 },
2510 };
2511
2512 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2513         EXYNOS_COMMON_SERIAL_DRV_DATA,
2514         .fifosize = { 64, 256, 16, 256 },
2515 };
2516
2517 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2518 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2519 #else
2520 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2521 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2522 #endif
2523
2524 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2525         {
2526                 .name           = "s3c2410-uart",
2527                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2528         }, {
2529                 .name           = "s3c2412-uart",
2530                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2531         }, {
2532                 .name           = "s3c2440-uart",
2533                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2534         }, {
2535                 .name           = "s3c6400-uart",
2536                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2537         }, {
2538                 .name           = "s5pv210-uart",
2539                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2540         }, {
2541                 .name           = "exynos4210-uart",
2542                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2543         }, {
2544                 .name           = "exynos5433-uart",
2545                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2546         },
2547         { },
2548 };
2549 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2550
2551 #ifdef CONFIG_OF
2552 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2553         { .compatible = "samsung,s3c2410-uart",
2554                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2555         { .compatible = "samsung,s3c2412-uart",
2556                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2557         { .compatible = "samsung,s3c2440-uart",
2558                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2559         { .compatible = "samsung,s3c6400-uart",
2560                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2561         { .compatible = "samsung,s5pv210-uart",
2562                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2563         { .compatible = "samsung,exynos4210-uart",
2564                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2565         { .compatible = "samsung,exynos5433-uart",
2566                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2567         {},
2568 };
2569 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2570 #endif
2571
2572 static struct platform_driver samsung_serial_driver = {
2573         .probe          = s3c24xx_serial_probe,
2574         .remove         = s3c24xx_serial_remove,
2575         .id_table       = s3c24xx_serial_driver_ids,
2576         .driver         = {
2577                 .name   = "samsung-uart",
2578                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2579                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2580         },
2581 };
2582
2583 module_platform_driver(samsung_serial_driver);
2584
2585 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2586 /*
2587  * Early console.
2588  */
2589
2590 struct samsung_early_console_data {
2591         u32 txfull_mask;
2592 };
2593
2594 static void samsung_early_busyuart(struct uart_port *port)
2595 {
2596         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2597                 ;
2598 }
2599
2600 static void samsung_early_busyuart_fifo(struct uart_port *port)
2601 {
2602         struct samsung_early_console_data *data = port->private_data;
2603
2604         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2605                 ;
2606 }
2607
2608 static void samsung_early_putc(struct uart_port *port, int c)
2609 {
2610         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2611                 samsung_early_busyuart_fifo(port);
2612         else
2613                 samsung_early_busyuart(port);
2614
2615         writeb(c, port->membase + S3C2410_UTXH);
2616 }
2617
2618 static void samsung_early_write(struct console *con, const char *s,
2619                                 unsigned int n)
2620 {
2621         struct earlycon_device *dev = con->data;
2622
2623         uart_console_write(&dev->port, s, n, samsung_early_putc);
2624 }
2625
2626 static int __init samsung_early_console_setup(struct earlycon_device *device,
2627                                               const char *opt)
2628 {
2629         if (!device->port.membase)
2630                 return -ENODEV;
2631
2632         device->con->write = samsung_early_write;
2633         return 0;
2634 }
2635
2636 /* S3C2410 */
2637 static struct samsung_early_console_data s3c2410_early_console_data = {
2638         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2639 };
2640
2641 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2642                                               const char *opt)
2643 {
2644         device->port.private_data = &s3c2410_early_console_data;
2645         return samsung_early_console_setup(device, opt);
2646 }
2647 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2648                         s3c2410_early_console_setup);
2649
2650 /* S3C2412, S3C2440, S3C64xx */
2651 static struct samsung_early_console_data s3c2440_early_console_data = {
2652         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2653 };
2654
2655 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2656                                               const char *opt)
2657 {
2658         device->port.private_data = &s3c2440_early_console_data;
2659         return samsung_early_console_setup(device, opt);
2660 }
2661 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2662                         s3c2440_early_console_setup);
2663 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2664                         s3c2440_early_console_setup);
2665 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2666                         s3c2440_early_console_setup);
2667
2668 /* S5PV210, Exynos */
2669 static struct samsung_early_console_data s5pv210_early_console_data = {
2670         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2671 };
2672
2673 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2674                                               const char *opt)
2675 {
2676         device->port.private_data = &s5pv210_early_console_data;
2677         return samsung_early_console_setup(device, opt);
2678 }
2679 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2680                         s5pv210_early_console_setup);
2681 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2682                         s5pv210_early_console_setup);
2683 #endif
2684
2685 MODULE_ALIAS("platform:samsung-uart");
2686 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2687 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2688 MODULE_LICENSE("GPL v2");