1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
9 * based off of the old drivers/char/sh-sci.c by:
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
18 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/clk.h>
25 #include <linux/console.h>
26 #include <linux/ctype.h>
27 #include <linux/cpufreq.h>
28 #include <linux/delay.h>
29 #include <linux/dmaengine.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/err.h>
32 #include <linux/errno.h>
33 #include <linux/init.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/ktime.h>
37 #include <linux/major.h>
38 #include <linux/module.h>
41 #include <linux/of_device.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/scatterlist.h>
45 #include <linux/serial.h>
46 #include <linux/serial_sci.h>
47 #include <linux/sh_dma.h>
48 #include <linux/slab.h>
49 #include <linux/string.h>
50 #include <linux/sysrq.h>
51 #include <linux/timer.h>
52 #include <linux/tty.h>
53 #include <linux/tty_flip.h>
56 #include <asm/sh_bios.h>
59 #include "serial_mctrl_gpio.h"
62 /* Offsets into the sci_port->irqs array */
72 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
75 #define SCIx_IRQ_IS_MUXED(port) \
76 ((port)->irqs[SCIx_ERI_IRQ] == \
77 (port)->irqs[SCIx_RXI_IRQ]) || \
78 ((port)->irqs[SCIx_ERI_IRQ] && \
79 ((port)->irqs[SCIx_RXI_IRQ] < 0))
82 SCI_FCK, /* Functional Clock */
83 SCI_SCK, /* Optional External Clock */
84 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
85 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
89 /* Bit x set means sampling rate x + 1 is supported */
90 #define SCI_SR(x) BIT((x) - 1)
91 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
93 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
94 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
95 SCI_SR(19) | SCI_SR(27)
97 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
98 #define max_sr(_port) fls((_port)->sampling_rate_mask)
100 /* Iterate over all supported sampling rates, from high to low */
101 #define for_each_sr(_sr, _port) \
102 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
103 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
105 struct plat_sci_reg {
109 struct sci_port_params {
110 const struct plat_sci_reg regs[SCIx_NR_REGS];
111 unsigned int fifosize;
112 unsigned int overrun_reg;
113 unsigned int overrun_mask;
114 unsigned int sampling_rate_mask;
115 unsigned int error_mask;
116 unsigned int error_clear;
120 struct uart_port port;
122 /* Platform configuration */
123 const struct sci_port_params *params;
124 const struct plat_sci_port *cfg;
125 unsigned int sampling_rate_mask;
126 resource_size_t reg_size;
127 struct mctrl_gpios *gpios;
130 struct clk *clks[SCI_NUM_CLKS];
131 unsigned long clk_rates[SCI_NUM_CLKS];
133 int irqs[SCIx_NR_IRQS];
134 char *irqstr[SCIx_NR_IRQS];
136 struct dma_chan *chan_tx;
137 struct dma_chan *chan_rx;
139 #ifdef CONFIG_SERIAL_SH_SCI_DMA
140 struct dma_chan *chan_tx_saved;
141 struct dma_chan *chan_rx_saved;
142 dma_cookie_t cookie_tx;
143 dma_cookie_t cookie_rx[2];
144 dma_cookie_t active_rx;
145 dma_addr_t tx_dma_addr;
146 unsigned int tx_dma_len;
147 struct scatterlist sg_rx[2];
150 struct work_struct work_tx;
151 struct hrtimer rx_timer;
152 unsigned int rx_timeout; /* microseconds */
154 unsigned int rx_frame;
156 struct timer_list rx_fifo_timer;
164 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
166 static struct sci_port sci_ports[SCI_NPORTS];
167 static unsigned long sci_ports_in_use;
168 static struct uart_driver sci_uart_driver;
170 static inline struct sci_port *
171 to_sci_port(struct uart_port *uart)
173 return container_of(uart, struct sci_port, port);
176 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
178 * Common SCI definitions, dependent on the port's regshift
181 [SCIx_SCI_REGTYPE] = {
183 [SCSMR] = { 0x00, 8 },
184 [SCBRR] = { 0x01, 8 },
185 [SCSCR] = { 0x02, 8 },
186 [SCxTDR] = { 0x03, 8 },
187 [SCxSR] = { 0x04, 8 },
188 [SCxRDR] = { 0x05, 8 },
191 .overrun_reg = SCxSR,
192 .overrun_mask = SCI_ORER,
193 .sampling_rate_mask = SCI_SR(32),
194 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
195 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
199 * Common definitions for legacy IrDA ports.
201 [SCIx_IRDA_REGTYPE] = {
203 [SCSMR] = { 0x00, 8 },
204 [SCBRR] = { 0x02, 8 },
205 [SCSCR] = { 0x04, 8 },
206 [SCxTDR] = { 0x06, 8 },
207 [SCxSR] = { 0x08, 16 },
208 [SCxRDR] = { 0x0a, 8 },
209 [SCFCR] = { 0x0c, 8 },
210 [SCFDR] = { 0x0e, 16 },
213 .overrun_reg = SCxSR,
214 .overrun_mask = SCI_ORER,
215 .sampling_rate_mask = SCI_SR(32),
216 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
217 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
221 * Common SCIFA definitions.
223 [SCIx_SCIFA_REGTYPE] = {
225 [SCSMR] = { 0x00, 16 },
226 [SCBRR] = { 0x04, 8 },
227 [SCSCR] = { 0x08, 16 },
228 [SCxTDR] = { 0x20, 8 },
229 [SCxSR] = { 0x14, 16 },
230 [SCxRDR] = { 0x24, 8 },
231 [SCFCR] = { 0x18, 16 },
232 [SCFDR] = { 0x1c, 16 },
233 [SCPCR] = { 0x30, 16 },
234 [SCPDR] = { 0x34, 16 },
237 .overrun_reg = SCxSR,
238 .overrun_mask = SCIFA_ORER,
239 .sampling_rate_mask = SCI_SR_SCIFAB,
240 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
241 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
245 * Common SCIFB definitions.
247 [SCIx_SCIFB_REGTYPE] = {
249 [SCSMR] = { 0x00, 16 },
250 [SCBRR] = { 0x04, 8 },
251 [SCSCR] = { 0x08, 16 },
252 [SCxTDR] = { 0x40, 8 },
253 [SCxSR] = { 0x14, 16 },
254 [SCxRDR] = { 0x60, 8 },
255 [SCFCR] = { 0x18, 16 },
256 [SCTFDR] = { 0x38, 16 },
257 [SCRFDR] = { 0x3c, 16 },
258 [SCPCR] = { 0x30, 16 },
259 [SCPDR] = { 0x34, 16 },
262 .overrun_reg = SCxSR,
263 .overrun_mask = SCIFA_ORER,
264 .sampling_rate_mask = SCI_SR_SCIFAB,
265 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
266 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
270 * Common SH-2(A) SCIF definitions for ports with FIFO data
273 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
275 [SCSMR] = { 0x00, 16 },
276 [SCBRR] = { 0x04, 8 },
277 [SCSCR] = { 0x08, 16 },
278 [SCxTDR] = { 0x0c, 8 },
279 [SCxSR] = { 0x10, 16 },
280 [SCxRDR] = { 0x14, 8 },
281 [SCFCR] = { 0x18, 16 },
282 [SCFDR] = { 0x1c, 16 },
283 [SCSPTR] = { 0x20, 16 },
284 [SCLSR] = { 0x24, 16 },
287 .overrun_reg = SCLSR,
288 .overrun_mask = SCLSR_ORER,
289 .sampling_rate_mask = SCI_SR(32),
290 .error_mask = SCIF_DEFAULT_ERROR_MASK,
291 .error_clear = SCIF_ERROR_CLEAR,
295 * The "SCIFA" that is in RZ/T and RZ/A2.
296 * It looks like a normal SCIF with FIFO data, but with a
297 * compressed address space. Also, the break out of interrupts
298 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
300 [SCIx_RZ_SCIFA_REGTYPE] = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x02, 8 },
304 [SCSCR] = { 0x04, 16 },
305 [SCxTDR] = { 0x06, 8 },
306 [SCxSR] = { 0x08, 16 },
307 [SCxRDR] = { 0x0A, 8 },
308 [SCFCR] = { 0x0C, 16 },
309 [SCFDR] = { 0x0E, 16 },
310 [SCSPTR] = { 0x10, 16 },
311 [SCLSR] = { 0x12, 16 },
314 .overrun_reg = SCLSR,
315 .overrun_mask = SCLSR_ORER,
316 .sampling_rate_mask = SCI_SR(32),
317 .error_mask = SCIF_DEFAULT_ERROR_MASK,
318 .error_clear = SCIF_ERROR_CLEAR,
322 * Common SH-3 SCIF definitions.
324 [SCIx_SH3_SCIF_REGTYPE] = {
326 [SCSMR] = { 0x00, 8 },
327 [SCBRR] = { 0x02, 8 },
328 [SCSCR] = { 0x04, 8 },
329 [SCxTDR] = { 0x06, 8 },
330 [SCxSR] = { 0x08, 16 },
331 [SCxRDR] = { 0x0a, 8 },
332 [SCFCR] = { 0x0c, 8 },
333 [SCFDR] = { 0x0e, 16 },
336 .overrun_reg = SCLSR,
337 .overrun_mask = SCLSR_ORER,
338 .sampling_rate_mask = SCI_SR(32),
339 .error_mask = SCIF_DEFAULT_ERROR_MASK,
340 .error_clear = SCIF_ERROR_CLEAR,
344 * Common SH-4(A) SCIF(B) definitions.
346 [SCIx_SH4_SCIF_REGTYPE] = {
348 [SCSMR] = { 0x00, 16 },
349 [SCBRR] = { 0x04, 8 },
350 [SCSCR] = { 0x08, 16 },
351 [SCxTDR] = { 0x0c, 8 },
352 [SCxSR] = { 0x10, 16 },
353 [SCxRDR] = { 0x14, 8 },
354 [SCFCR] = { 0x18, 16 },
355 [SCFDR] = { 0x1c, 16 },
356 [SCSPTR] = { 0x20, 16 },
357 [SCLSR] = { 0x24, 16 },
360 .overrun_reg = SCLSR,
361 .overrun_mask = SCLSR_ORER,
362 .sampling_rate_mask = SCI_SR(32),
363 .error_mask = SCIF_DEFAULT_ERROR_MASK,
364 .error_clear = SCIF_ERROR_CLEAR,
368 * Common SCIF definitions for ports with a Baud Rate Generator for
369 * External Clock (BRG).
371 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x0c, 8 },
377 [SCxSR] = { 0x10, 16 },
378 [SCxRDR] = { 0x14, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCSPTR] = { 0x20, 16 },
382 [SCLSR] = { 0x24, 16 },
383 [SCDL] = { 0x30, 16 },
384 [SCCKS] = { 0x34, 16 },
387 .overrun_reg = SCLSR,
388 .overrun_mask = SCLSR_ORER,
389 .sampling_rate_mask = SCI_SR(32),
390 .error_mask = SCIF_DEFAULT_ERROR_MASK,
391 .error_clear = SCIF_ERROR_CLEAR,
395 * Common HSCIF definitions.
397 [SCIx_HSCIF_REGTYPE] = {
399 [SCSMR] = { 0x00, 16 },
400 [SCBRR] = { 0x04, 8 },
401 [SCSCR] = { 0x08, 16 },
402 [SCxTDR] = { 0x0c, 8 },
403 [SCxSR] = { 0x10, 16 },
404 [SCxRDR] = { 0x14, 8 },
405 [SCFCR] = { 0x18, 16 },
406 [SCFDR] = { 0x1c, 16 },
407 [SCSPTR] = { 0x20, 16 },
408 [SCLSR] = { 0x24, 16 },
409 [HSSRR] = { 0x40, 16 },
410 [SCDL] = { 0x30, 16 },
411 [SCCKS] = { 0x34, 16 },
412 [HSRTRGR] = { 0x54, 16 },
413 [HSTTRGR] = { 0x58, 16 },
416 .overrun_reg = SCLSR,
417 .overrun_mask = SCLSR_ORER,
418 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
419 .error_mask = SCIF_DEFAULT_ERROR_MASK,
420 .error_clear = SCIF_ERROR_CLEAR,
424 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
427 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
429 [SCSMR] = { 0x00, 16 },
430 [SCBRR] = { 0x04, 8 },
431 [SCSCR] = { 0x08, 16 },
432 [SCxTDR] = { 0x0c, 8 },
433 [SCxSR] = { 0x10, 16 },
434 [SCxRDR] = { 0x14, 8 },
435 [SCFCR] = { 0x18, 16 },
436 [SCFDR] = { 0x1c, 16 },
437 [SCLSR] = { 0x24, 16 },
440 .overrun_reg = SCLSR,
441 .overrun_mask = SCLSR_ORER,
442 .sampling_rate_mask = SCI_SR(32),
443 .error_mask = SCIF_DEFAULT_ERROR_MASK,
444 .error_clear = SCIF_ERROR_CLEAR,
448 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
451 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
453 [SCSMR] = { 0x00, 16 },
454 [SCBRR] = { 0x04, 8 },
455 [SCSCR] = { 0x08, 16 },
456 [SCxTDR] = { 0x0c, 8 },
457 [SCxSR] = { 0x10, 16 },
458 [SCxRDR] = { 0x14, 8 },
459 [SCFCR] = { 0x18, 16 },
460 [SCFDR] = { 0x1c, 16 },
461 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
462 [SCRFDR] = { 0x20, 16 },
463 [SCSPTR] = { 0x24, 16 },
464 [SCLSR] = { 0x28, 16 },
467 .overrun_reg = SCLSR,
468 .overrun_mask = SCLSR_ORER,
469 .sampling_rate_mask = SCI_SR(32),
470 .error_mask = SCIF_DEFAULT_ERROR_MASK,
471 .error_clear = SCIF_ERROR_CLEAR,
475 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
478 [SCIx_SH7705_SCIF_REGTYPE] = {
480 [SCSMR] = { 0x00, 16 },
481 [SCBRR] = { 0x04, 8 },
482 [SCSCR] = { 0x08, 16 },
483 [SCxTDR] = { 0x20, 8 },
484 [SCxSR] = { 0x14, 16 },
485 [SCxRDR] = { 0x24, 8 },
486 [SCFCR] = { 0x18, 16 },
487 [SCFDR] = { 0x1c, 16 },
490 .overrun_reg = SCxSR,
491 .overrun_mask = SCIFA_ORER,
492 .sampling_rate_mask = SCI_SR(16),
493 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
494 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
498 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
501 * The "offset" here is rather misleading, in that it refers to an enum
502 * value relative to the port mapping rather than the fixed offset
503 * itself, which needs to be manually retrieved from the platform's
504 * register map for the given port.
506 static unsigned int sci_serial_in(struct uart_port *p, int offset)
508 const struct plat_sci_reg *reg = sci_getreg(p, offset);
511 return ioread8(p->membase + (reg->offset << p->regshift));
512 else if (reg->size == 16)
513 return ioread16(p->membase + (reg->offset << p->regshift));
515 WARN(1, "Invalid register access\n");
520 static void sci_serial_out(struct uart_port *p, int offset, int value)
522 const struct plat_sci_reg *reg = sci_getreg(p, offset);
525 iowrite8(value, p->membase + (reg->offset << p->regshift));
526 else if (reg->size == 16)
527 iowrite16(value, p->membase + (reg->offset << p->regshift));
529 WARN(1, "Invalid register access\n");
532 static void sci_port_enable(struct sci_port *sci_port)
536 if (!sci_port->port.dev)
539 pm_runtime_get_sync(sci_port->port.dev);
541 for (i = 0; i < SCI_NUM_CLKS; i++) {
542 clk_prepare_enable(sci_port->clks[i]);
543 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
545 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
548 static void sci_port_disable(struct sci_port *sci_port)
552 if (!sci_port->port.dev)
555 for (i = SCI_NUM_CLKS; i-- > 0; )
556 clk_disable_unprepare(sci_port->clks[i]);
558 pm_runtime_put_sync(sci_port->port.dev);
561 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
564 * Not all ports (such as SCIFA) will support REIE. Rather than
565 * special-casing the port type, we check the port initialization
566 * IRQ enable mask to see whether the IRQ is desired at all. If
567 * it's unset, it's logically inferred that there's no point in
570 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
573 static void sci_start_tx(struct uart_port *port)
575 struct sci_port *s = to_sci_port(port);
578 #ifdef CONFIG_SERIAL_SH_SCI_DMA
579 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
580 u16 new, scr = serial_port_in(port, SCSCR);
582 new = scr | SCSCR_TDRQE;
584 new = scr & ~SCSCR_TDRQE;
586 serial_port_out(port, SCSCR, new);
589 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
590 dma_submit_error(s->cookie_tx)) {
592 schedule_work(&s->work_tx);
596 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
597 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
598 ctrl = serial_port_in(port, SCSCR);
599 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
603 static void sci_stop_tx(struct uart_port *port)
607 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
608 ctrl = serial_port_in(port, SCSCR);
610 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
611 ctrl &= ~SCSCR_TDRQE;
615 serial_port_out(port, SCSCR, ctrl);
618 static void sci_start_rx(struct uart_port *port)
622 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
624 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
625 ctrl &= ~SCSCR_RDRQE;
627 serial_port_out(port, SCSCR, ctrl);
630 static void sci_stop_rx(struct uart_port *port)
634 ctrl = serial_port_in(port, SCSCR);
636 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
637 ctrl &= ~SCSCR_RDRQE;
639 ctrl &= ~port_rx_irq_mask(port);
641 serial_port_out(port, SCSCR, ctrl);
644 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
646 if (port->type == PORT_SCI) {
647 /* Just store the mask */
648 serial_port_out(port, SCxSR, mask);
649 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
650 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
651 /* Only clear the status bits we want to clear */
652 serial_port_out(port, SCxSR,
653 serial_port_in(port, SCxSR) & mask);
655 /* Store the mask, clear parity/framing errors */
656 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
660 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
661 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
663 #ifdef CONFIG_CONSOLE_POLL
664 static int sci_poll_get_char(struct uart_port *port)
666 unsigned short status;
670 status = serial_port_in(port, SCxSR);
671 if (status & SCxSR_ERRORS(port)) {
672 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
678 if (!(status & SCxSR_RDxF(port)))
681 c = serial_port_in(port, SCxRDR);
684 serial_port_in(port, SCxSR);
685 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
691 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
693 unsigned short status;
696 status = serial_port_in(port, SCxSR);
697 } while (!(status & SCxSR_TDxE(port)));
699 serial_port_out(port, SCxTDR, c);
700 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
702 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
703 CONFIG_SERIAL_SH_SCI_EARLYCON */
705 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
707 struct sci_port *s = to_sci_port(port);
710 * Use port-specific handler if provided.
712 if (s->cfg->ops && s->cfg->ops->init_pins) {
713 s->cfg->ops->init_pins(port, cflag);
717 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
718 u16 data = serial_port_in(port, SCPDR);
719 u16 ctrl = serial_port_in(port, SCPCR);
721 /* Enable RXD and TXD pin functions */
722 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
723 if (to_sci_port(port)->has_rtscts) {
724 /* RTS# is output, active low, unless autorts */
725 if (!(port->mctrl & TIOCM_RTS)) {
728 } else if (!s->autorts) {
732 /* Enable RTS# pin function */
735 /* Enable CTS# pin function */
738 serial_port_out(port, SCPDR, data);
739 serial_port_out(port, SCPCR, ctrl);
740 } else if (sci_getreg(port, SCSPTR)->size) {
741 u16 status = serial_port_in(port, SCSPTR);
743 /* RTS# is always output; and active low, unless autorts */
744 status |= SCSPTR_RTSIO;
745 if (!(port->mctrl & TIOCM_RTS))
746 status |= SCSPTR_RTSDT;
747 else if (!s->autorts)
748 status &= ~SCSPTR_RTSDT;
749 /* CTS# and SCK are inputs */
750 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
751 serial_port_out(port, SCSPTR, status);
755 static int sci_txfill(struct uart_port *port)
757 struct sci_port *s = to_sci_port(port);
758 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
759 const struct plat_sci_reg *reg;
761 reg = sci_getreg(port, SCTFDR);
763 return serial_port_in(port, SCTFDR) & fifo_mask;
765 reg = sci_getreg(port, SCFDR);
767 return serial_port_in(port, SCFDR) >> 8;
769 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
772 static int sci_txroom(struct uart_port *port)
774 return port->fifosize - sci_txfill(port);
777 static int sci_rxfill(struct uart_port *port)
779 struct sci_port *s = to_sci_port(port);
780 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
781 const struct plat_sci_reg *reg;
783 reg = sci_getreg(port, SCRFDR);
785 return serial_port_in(port, SCRFDR) & fifo_mask;
787 reg = sci_getreg(port, SCFDR);
789 return serial_port_in(port, SCFDR) & fifo_mask;
791 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
794 /* ********************************************************************** *
795 * the interrupt related routines *
796 * ********************************************************************** */
798 static void sci_transmit_chars(struct uart_port *port)
800 struct circ_buf *xmit = &port->state->xmit;
801 unsigned int stopped = uart_tx_stopped(port);
802 unsigned short status;
806 status = serial_port_in(port, SCxSR);
807 if (!(status & SCxSR_TDxE(port))) {
808 ctrl = serial_port_in(port, SCSCR);
809 if (uart_circ_empty(xmit))
813 serial_port_out(port, SCSCR, ctrl);
817 count = sci_txroom(port);
825 } else if (!uart_circ_empty(xmit) && !stopped) {
826 c = xmit->buf[xmit->tail];
827 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
832 serial_port_out(port, SCxTDR, c);
835 } while (--count > 0);
837 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
841 if (uart_circ_empty(xmit)) {
844 ctrl = serial_port_in(port, SCSCR);
846 if (port->type != PORT_SCI) {
847 serial_port_in(port, SCxSR); /* Dummy read */
848 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
852 serial_port_out(port, SCSCR, ctrl);
856 /* On SH3, SCIF may read end-of-break as a space->mark char */
857 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
859 static void sci_receive_chars(struct uart_port *port)
861 struct tty_port *tport = &port->state->port;
862 int i, count, copied = 0;
863 unsigned short status;
866 status = serial_port_in(port, SCxSR);
867 if (!(status & SCxSR_RDxF(port)))
871 /* Don't copy more bytes than there is room for in the buffer */
872 count = tty_buffer_request_room(tport, sci_rxfill(port));
874 /* If for any reason we can't copy more data, we're done! */
878 if (port->type == PORT_SCI) {
879 char c = serial_port_in(port, SCxRDR);
880 if (uart_handle_sysrq_char(port, c))
883 tty_insert_flip_char(tport, c, TTY_NORMAL);
885 for (i = 0; i < count; i++) {
886 char c = serial_port_in(port, SCxRDR);
888 status = serial_port_in(port, SCxSR);
889 if (uart_handle_sysrq_char(port, c)) {
894 /* Store data and status */
895 if (status & SCxSR_FER(port)) {
897 port->icount.frame++;
898 dev_notice(port->dev, "frame error\n");
899 } else if (status & SCxSR_PER(port)) {
901 port->icount.parity++;
902 dev_notice(port->dev, "parity error\n");
906 tty_insert_flip_char(tport, c, flag);
910 serial_port_in(port, SCxSR); /* dummy read */
911 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
914 port->icount.rx += count;
918 /* Tell the rest of the system the news. New characters! */
919 tty_flip_buffer_push(tport);
921 /* TTY buffers full; read from RX reg to prevent lockup */
922 serial_port_in(port, SCxRDR);
923 serial_port_in(port, SCxSR); /* dummy read */
924 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
928 static int sci_handle_errors(struct uart_port *port)
931 unsigned short status = serial_port_in(port, SCxSR);
932 struct tty_port *tport = &port->state->port;
933 struct sci_port *s = to_sci_port(port);
935 /* Handle overruns */
936 if (status & s->params->overrun_mask) {
937 port->icount.overrun++;
940 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
943 dev_notice(port->dev, "overrun error\n");
946 if (status & SCxSR_FER(port)) {
948 port->icount.frame++;
950 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
953 dev_notice(port->dev, "frame error\n");
956 if (status & SCxSR_PER(port)) {
958 port->icount.parity++;
960 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
963 dev_notice(port->dev, "parity error\n");
967 tty_flip_buffer_push(tport);
972 static int sci_handle_fifo_overrun(struct uart_port *port)
974 struct tty_port *tport = &port->state->port;
975 struct sci_port *s = to_sci_port(port);
976 const struct plat_sci_reg *reg;
980 reg = sci_getreg(port, s->params->overrun_reg);
984 status = serial_port_in(port, s->params->overrun_reg);
985 if (status & s->params->overrun_mask) {
986 status &= ~s->params->overrun_mask;
987 serial_port_out(port, s->params->overrun_reg, status);
989 port->icount.overrun++;
991 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
992 tty_flip_buffer_push(tport);
994 dev_dbg(port->dev, "overrun error\n");
1001 static int sci_handle_breaks(struct uart_port *port)
1004 unsigned short status = serial_port_in(port, SCxSR);
1005 struct tty_port *tport = &port->state->port;
1007 if (uart_handle_break(port))
1010 if (status & SCxSR_BRK(port)) {
1013 /* Notify of BREAK */
1014 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1017 dev_dbg(port->dev, "BREAK detected\n");
1021 tty_flip_buffer_push(tport);
1023 copied += sci_handle_fifo_overrun(port);
1028 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1034 if (rx_trig >= port->fifosize)
1035 rx_trig = port->fifosize;
1037 /* HSCIF can be set to an arbitrary level. */
1038 if (sci_getreg(port, HSRTRGR)->size) {
1039 serial_port_out(port, HSRTRGR, rx_trig);
1043 switch (port->type) {
1048 } else if (rx_trig < 8) {
1051 } else if (rx_trig < 14) {
1055 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1064 } else if (rx_trig < 32) {
1067 } else if (rx_trig < 48) {
1071 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1076 WARN(1, "unknown FIFO configuration");
1080 serial_port_out(port, SCFCR,
1081 (serial_port_in(port, SCFCR) &
1082 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1087 static int scif_rtrg_enabled(struct uart_port *port)
1089 if (sci_getreg(port, HSRTRGR)->size)
1090 return serial_port_in(port, HSRTRGR) != 0;
1092 return (serial_port_in(port, SCFCR) &
1093 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1096 static void rx_fifo_timer_fn(struct timer_list *t)
1098 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1099 struct uart_port *port = &s->port;
1101 dev_dbg(port->dev, "Rx timed out\n");
1102 scif_set_rtrg(port, 1);
1105 static ssize_t rx_trigger_show(struct device *dev,
1106 struct device_attribute *attr,
1109 struct uart_port *port = dev_get_drvdata(dev);
1110 struct sci_port *sci = to_sci_port(port);
1112 return sprintf(buf, "%d\n", sci->rx_trigger);
1115 static ssize_t rx_trigger_store(struct device *dev,
1116 struct device_attribute *attr,
1120 struct uart_port *port = dev_get_drvdata(dev);
1121 struct sci_port *sci = to_sci_port(port);
1125 ret = kstrtol(buf, 0, &r);
1129 sci->rx_trigger = scif_set_rtrg(port, r);
1130 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1131 scif_set_rtrg(port, 1);
1136 static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1138 static ssize_t rx_fifo_timeout_show(struct device *dev,
1139 struct device_attribute *attr,
1142 struct uart_port *port = dev_get_drvdata(dev);
1143 struct sci_port *sci = to_sci_port(port);
1146 if (port->type == PORT_HSCIF)
1147 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1149 v = sci->rx_fifo_timeout;
1151 return sprintf(buf, "%d\n", v);
1154 static ssize_t rx_fifo_timeout_store(struct device *dev,
1155 struct device_attribute *attr,
1159 struct uart_port *port = dev_get_drvdata(dev);
1160 struct sci_port *sci = to_sci_port(port);
1164 ret = kstrtol(buf, 0, &r);
1168 if (port->type == PORT_HSCIF) {
1171 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1173 sci->rx_fifo_timeout = r;
1174 scif_set_rtrg(port, 1);
1176 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1182 static DEVICE_ATTR_RW(rx_fifo_timeout);
1185 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1186 static void sci_dma_tx_complete(void *arg)
1188 struct sci_port *s = arg;
1189 struct uart_port *port = &s->port;
1190 struct circ_buf *xmit = &port->state->xmit;
1191 unsigned long flags;
1193 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1195 spin_lock_irqsave(&port->lock, flags);
1197 xmit->tail += s->tx_dma_len;
1198 xmit->tail &= UART_XMIT_SIZE - 1;
1200 port->icount.tx += s->tx_dma_len;
1202 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1203 uart_write_wakeup(port);
1205 if (!uart_circ_empty(xmit)) {
1207 schedule_work(&s->work_tx);
1209 s->cookie_tx = -EINVAL;
1210 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1211 u16 ctrl = serial_port_in(port, SCSCR);
1212 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1216 spin_unlock_irqrestore(&port->lock, flags);
1219 /* Locking: called with port lock held */
1220 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1222 struct uart_port *port = &s->port;
1223 struct tty_port *tport = &port->state->port;
1226 copied = tty_insert_flip_string(tport, buf, count);
1228 port->icount.buf_overrun++;
1230 port->icount.rx += copied;
1235 static int sci_dma_rx_find_active(struct sci_port *s)
1239 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1240 if (s->active_rx == s->cookie_rx[i])
1246 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1251 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1252 s->cookie_rx[i] = -EINVAL;
1256 static void sci_rx_dma_release(struct sci_port *s)
1258 struct dma_chan *chan = s->chan_rx_saved;
1260 s->chan_rx_saved = NULL;
1261 sci_dma_rx_chan_invalidate(s);
1262 dmaengine_terminate_sync(chan);
1263 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1264 sg_dma_address(&s->sg_rx[0]));
1265 dma_release_channel(chan);
1268 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1270 long sec = usec / 1000000;
1271 long nsec = (usec % 1000000) * 1000;
1272 ktime_t t = ktime_set(sec, nsec);
1274 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1277 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1279 struct uart_port *port = &s->port;
1282 /* Direct new serial port interrupts back to CPU */
1283 scr = serial_port_in(port, SCSCR);
1284 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1285 scr &= ~SCSCR_RDRQE;
1286 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1288 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1291 static void sci_dma_rx_complete(void *arg)
1293 struct sci_port *s = arg;
1294 struct dma_chan *chan = s->chan_rx;
1295 struct uart_port *port = &s->port;
1296 struct dma_async_tx_descriptor *desc;
1297 unsigned long flags;
1298 int active, count = 0;
1300 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1303 spin_lock_irqsave(&port->lock, flags);
1305 active = sci_dma_rx_find_active(s);
1307 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1309 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1312 tty_flip_buffer_push(&port->state->port);
1314 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1316 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1320 desc->callback = sci_dma_rx_complete;
1321 desc->callback_param = s;
1322 s->cookie_rx[active] = dmaengine_submit(desc);
1323 if (dma_submit_error(s->cookie_rx[active]))
1326 s->active_rx = s->cookie_rx[!active];
1328 dma_async_issue_pending(chan);
1330 spin_unlock_irqrestore(&port->lock, flags);
1331 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1332 __func__, s->cookie_rx[active], active, s->active_rx);
1336 spin_unlock_irqrestore(&port->lock, flags);
1337 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1339 spin_lock_irqsave(&port->lock, flags);
1340 dmaengine_terminate_async(chan);
1341 sci_dma_rx_chan_invalidate(s);
1342 sci_dma_rx_reenable_irq(s);
1343 spin_unlock_irqrestore(&port->lock, flags);
1346 static void sci_tx_dma_release(struct sci_port *s)
1348 struct dma_chan *chan = s->chan_tx_saved;
1350 cancel_work_sync(&s->work_tx);
1351 s->chan_tx_saved = s->chan_tx = NULL;
1352 s->cookie_tx = -EINVAL;
1353 dmaengine_terminate_sync(chan);
1354 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1356 dma_release_channel(chan);
1359 static int sci_submit_rx(struct sci_port *s, bool port_lock_held)
1361 struct dma_chan *chan = s->chan_rx;
1362 struct uart_port *port = &s->port;
1363 unsigned long flags;
1366 for (i = 0; i < 2; i++) {
1367 struct scatterlist *sg = &s->sg_rx[i];
1368 struct dma_async_tx_descriptor *desc;
1370 desc = dmaengine_prep_slave_sg(chan,
1371 sg, 1, DMA_DEV_TO_MEM,
1372 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1376 desc->callback = sci_dma_rx_complete;
1377 desc->callback_param = s;
1378 s->cookie_rx[i] = dmaengine_submit(desc);
1379 if (dma_submit_error(s->cookie_rx[i]))
1384 s->active_rx = s->cookie_rx[0];
1386 dma_async_issue_pending(chan);
1391 if (!port_lock_held)
1392 spin_lock_irqsave(&port->lock, flags);
1394 dmaengine_terminate_async(chan);
1395 sci_dma_rx_chan_invalidate(s);
1397 if (!port_lock_held)
1398 spin_unlock_irqrestore(&port->lock, flags);
1402 static void work_fn_tx(struct work_struct *work)
1404 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1405 struct dma_async_tx_descriptor *desc;
1406 struct dma_chan *chan = s->chan_tx;
1407 struct uart_port *port = &s->port;
1408 struct circ_buf *xmit = &port->state->xmit;
1409 unsigned long flags;
1414 * Port xmit buffer is already mapped, and it is one page... Just adjust
1415 * offsets and lengths. Since it is a circular buffer, we have to
1416 * transmit till the end, and then the rest. Take the port lock to get a
1417 * consistent xmit buffer state.
1419 spin_lock_irq(&port->lock);
1420 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1421 s->tx_dma_len = min_t(unsigned int,
1422 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1423 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1424 spin_unlock_irq(&port->lock);
1426 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1428 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1430 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1434 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1437 spin_lock_irq(&port->lock);
1438 desc->callback = sci_dma_tx_complete;
1439 desc->callback_param = s;
1440 spin_unlock_irq(&port->lock);
1441 s->cookie_tx = dmaengine_submit(desc);
1442 if (dma_submit_error(s->cookie_tx)) {
1443 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1447 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1448 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1450 dma_async_issue_pending(chan);
1454 spin_lock_irqsave(&port->lock, flags);
1457 spin_unlock_irqrestore(&port->lock, flags);
1461 static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1463 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1464 struct dma_chan *chan = s->chan_rx;
1465 struct uart_port *port = &s->port;
1466 struct dma_tx_state state;
1467 enum dma_status status;
1468 unsigned long flags;
1472 dev_dbg(port->dev, "DMA Rx timed out\n");
1474 spin_lock_irqsave(&port->lock, flags);
1476 active = sci_dma_rx_find_active(s);
1478 spin_unlock_irqrestore(&port->lock, flags);
1479 return HRTIMER_NORESTART;
1482 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1483 if (status == DMA_COMPLETE) {
1484 spin_unlock_irqrestore(&port->lock, flags);
1485 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1486 s->active_rx, active);
1488 /* Let packet complete handler take care of the packet */
1489 return HRTIMER_NORESTART;
1492 dmaengine_pause(chan);
1495 * sometimes DMA transfer doesn't stop even if it is stopped and
1496 * data keeps on coming until transaction is complete so check
1497 * for DMA_COMPLETE again
1498 * Let packet complete handler take care of the packet
1500 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1501 if (status == DMA_COMPLETE) {
1502 spin_unlock_irqrestore(&port->lock, flags);
1503 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1504 return HRTIMER_NORESTART;
1507 /* Handle incomplete DMA receive */
1508 dmaengine_terminate_async(s->chan_rx);
1509 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1512 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1514 tty_flip_buffer_push(&port->state->port);
1517 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1518 sci_submit_rx(s, true);
1520 sci_dma_rx_reenable_irq(s);
1522 spin_unlock_irqrestore(&port->lock, flags);
1524 return HRTIMER_NORESTART;
1527 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1528 enum dma_transfer_direction dir)
1530 struct dma_chan *chan;
1531 struct dma_slave_config cfg;
1534 chan = dma_request_slave_channel(port->dev,
1535 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1537 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1541 memset(&cfg, 0, sizeof(cfg));
1542 cfg.direction = dir;
1543 if (dir == DMA_MEM_TO_DEV) {
1544 cfg.dst_addr = port->mapbase +
1545 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1546 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1548 cfg.src_addr = port->mapbase +
1549 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1550 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1553 ret = dmaengine_slave_config(chan, &cfg);
1555 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1556 dma_release_channel(chan);
1563 static void sci_request_dma(struct uart_port *port)
1565 struct sci_port *s = to_sci_port(port);
1566 struct dma_chan *chan;
1568 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1570 if (!port->dev->of_node)
1573 s->cookie_tx = -EINVAL;
1576 * Don't request a dma channel if no channel was specified
1577 * in the device tree.
1579 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1582 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1583 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1585 /* UART circular tx buffer is an aligned page. */
1586 s->tx_dma_addr = dma_map_single(chan->device->dev,
1587 port->state->xmit.buf,
1590 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1591 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1592 dma_release_channel(chan);
1594 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1595 __func__, UART_XMIT_SIZE,
1596 port->state->xmit.buf, &s->tx_dma_addr);
1598 INIT_WORK(&s->work_tx, work_fn_tx);
1599 s->chan_tx_saved = s->chan_tx = chan;
1603 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1604 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1610 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1611 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1615 "Failed to allocate Rx dma buffer, using PIO\n");
1616 dma_release_channel(chan);
1620 for (i = 0; i < 2; i++) {
1621 struct scatterlist *sg = &s->sg_rx[i];
1623 sg_init_table(sg, 1);
1625 sg_dma_address(sg) = dma;
1626 sg_dma_len(sg) = s->buf_len_rx;
1628 buf += s->buf_len_rx;
1629 dma += s->buf_len_rx;
1632 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1633 s->rx_timer.function = rx_timer_fn;
1635 s->chan_rx_saved = s->chan_rx = chan;
1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1638 sci_submit_rx(s, false);
1642 static void sci_free_dma(struct uart_port *port)
1644 struct sci_port *s = to_sci_port(port);
1646 if (s->chan_tx_saved)
1647 sci_tx_dma_release(s);
1648 if (s->chan_rx_saved)
1649 sci_rx_dma_release(s);
1652 static void sci_flush_buffer(struct uart_port *port)
1655 * In uart_flush_buffer(), the xmit circular buffer has just been
1656 * cleared, so we have to reset tx_dma_len accordingly.
1658 to_sci_port(port)->tx_dma_len = 0;
1660 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
1661 static inline void sci_request_dma(struct uart_port *port)
1665 static inline void sci_free_dma(struct uart_port *port)
1669 #define sci_flush_buffer NULL
1670 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1672 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1674 struct uart_port *port = ptr;
1675 struct sci_port *s = to_sci_port(port);
1677 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1679 u16 scr = serial_port_in(port, SCSCR);
1680 u16 ssr = serial_port_in(port, SCxSR);
1682 /* Disable future Rx interrupts */
1683 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1684 disable_irq_nosync(irq);
1687 if (sci_submit_rx(s, false) < 0)
1692 serial_port_out(port, SCSCR, scr);
1693 /* Clear current interrupt */
1694 serial_port_out(port, SCxSR,
1695 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1696 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1697 jiffies, s->rx_timeout);
1698 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1706 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1707 if (!scif_rtrg_enabled(port))
1708 scif_set_rtrg(port, s->rx_trigger);
1710 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1711 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1714 /* I think sci_receive_chars has to be called irrespective
1715 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1718 sci_receive_chars(port);
1723 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1725 struct uart_port *port = ptr;
1726 unsigned long flags;
1728 spin_lock_irqsave(&port->lock, flags);
1729 sci_transmit_chars(port);
1730 spin_unlock_irqrestore(&port->lock, flags);
1735 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1737 struct uart_port *port = ptr;
1740 sci_handle_breaks(port);
1741 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1746 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1748 struct uart_port *port = ptr;
1749 struct sci_port *s = to_sci_port(port);
1751 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1752 /* Break and Error interrupts are muxed */
1753 unsigned short ssr_status = serial_port_in(port, SCxSR);
1755 /* Break Interrupt */
1756 if (ssr_status & SCxSR_BRK(port))
1757 sci_br_interrupt(irq, ptr);
1760 if (!(ssr_status & SCxSR_ERRORS(port)))
1765 if (port->type == PORT_SCI) {
1766 if (sci_handle_errors(port)) {
1767 /* discard character in rx buffer */
1768 serial_port_in(port, SCxSR);
1769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1772 sci_handle_fifo_overrun(port);
1774 sci_receive_chars(port);
1777 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1779 /* Kick the transmission */
1781 sci_tx_interrupt(irq, ptr);
1786 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1788 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1789 struct uart_port *port = ptr;
1790 struct sci_port *s = to_sci_port(port);
1791 irqreturn_t ret = IRQ_NONE;
1793 ssr_status = serial_port_in(port, SCxSR);
1794 scr_status = serial_port_in(port, SCSCR);
1795 if (s->params->overrun_reg == SCxSR)
1796 orer_status = ssr_status;
1797 else if (sci_getreg(port, s->params->overrun_reg)->size)
1798 orer_status = serial_port_in(port, s->params->overrun_reg);
1800 err_enabled = scr_status & port_rx_irq_mask(port);
1803 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1805 ret = sci_tx_interrupt(irq, ptr);
1808 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1811 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1812 (scr_status & SCSCR_RIE))
1813 ret = sci_rx_interrupt(irq, ptr);
1815 /* Error Interrupt */
1816 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1817 ret = sci_er_interrupt(irq, ptr);
1819 /* Break Interrupt */
1820 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1821 ret = sci_br_interrupt(irq, ptr);
1823 /* Overrun Interrupt */
1824 if (orer_status & s->params->overrun_mask) {
1825 sci_handle_fifo_overrun(port);
1832 static const struct sci_irq_desc {
1834 irq_handler_t handler;
1835 } sci_irq_desc[] = {
1837 * Split out handlers, the default case.
1841 .handler = sci_er_interrupt,
1846 .handler = sci_rx_interrupt,
1851 .handler = sci_tx_interrupt,
1856 .handler = sci_br_interrupt,
1861 .handler = sci_rx_interrupt,
1866 .handler = sci_tx_interrupt,
1870 * Special muxed handler.
1874 .handler = sci_mpxed_interrupt,
1878 static int sci_request_irq(struct sci_port *port)
1880 struct uart_port *up = &port->port;
1881 int i, j, w, ret = 0;
1883 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1884 const struct sci_irq_desc *desc;
1887 /* Check if already registered (muxed) */
1888 for (w = 0; w < i; w++)
1889 if (port->irqs[w] == port->irqs[i])
1894 if (SCIx_IRQ_IS_MUXED(port)) {
1898 irq = port->irqs[i];
1901 * Certain port types won't support all of the
1902 * available interrupt sources.
1904 if (unlikely(irq < 0))
1908 desc = sci_irq_desc + i;
1909 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1910 dev_name(up->dev), desc->desc);
1911 if (!port->irqstr[j]) {
1916 ret = request_irq(irq, desc->handler, up->irqflags,
1917 port->irqstr[j], port);
1918 if (unlikely(ret)) {
1919 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1928 free_irq(port->irqs[i], port);
1932 kfree(port->irqstr[j]);
1937 static void sci_free_irq(struct sci_port *port)
1942 * Intentionally in reverse order so we iterate over the muxed
1945 for (i = 0; i < SCIx_NR_IRQS; i++) {
1946 int irq = port->irqs[i];
1949 * Certain port types won't support all of the available
1950 * interrupt sources.
1952 if (unlikely(irq < 0))
1955 free_irq(port->irqs[i], port);
1956 kfree(port->irqstr[i]);
1958 if (SCIx_IRQ_IS_MUXED(port)) {
1959 /* If there's only one IRQ, we're done. */
1965 static unsigned int sci_tx_empty(struct uart_port *port)
1967 unsigned short status = serial_port_in(port, SCxSR);
1968 unsigned short in_tx_fifo = sci_txfill(port);
1970 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1973 static void sci_set_rts(struct uart_port *port, bool state)
1975 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1976 u16 data = serial_port_in(port, SCPDR);
1980 data &= ~SCPDR_RTSD;
1983 serial_port_out(port, SCPDR, data);
1985 /* RTS# is output */
1986 serial_port_out(port, SCPCR,
1987 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1988 } else if (sci_getreg(port, SCSPTR)->size) {
1989 u16 ctrl = serial_port_in(port, SCSPTR);
1993 ctrl &= ~SCSPTR_RTSDT;
1995 ctrl |= SCSPTR_RTSDT;
1996 serial_port_out(port, SCSPTR, ctrl);
2000 static bool sci_get_cts(struct uart_port *port)
2002 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2004 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2005 } else if (sci_getreg(port, SCSPTR)->size) {
2007 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2014 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2015 * CTS/RTS is supported in hardware by at least one port and controlled
2016 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2017 * handled via the ->init_pins() op, which is a bit of a one-way street,
2018 * lacking any ability to defer pin control -- this will later be
2019 * converted over to the GPIO framework).
2021 * Other modes (such as loopback) are supported generically on certain
2022 * port types, but not others. For these it's sufficient to test for the
2023 * existence of the support register and simply ignore the port type.
2025 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2027 struct sci_port *s = to_sci_port(port);
2029 if (mctrl & TIOCM_LOOP) {
2030 const struct plat_sci_reg *reg;
2033 * Standard loopback mode for SCFCR ports.
2035 reg = sci_getreg(port, SCFCR);
2037 serial_port_out(port, SCFCR,
2038 serial_port_in(port, SCFCR) |
2042 mctrl_gpio_set(s->gpios, mctrl);
2047 if (!(mctrl & TIOCM_RTS)) {
2048 /* Disable Auto RTS */
2049 serial_port_out(port, SCFCR,
2050 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2053 sci_set_rts(port, 0);
2054 } else if (s->autorts) {
2055 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2056 /* Enable RTS# pin function */
2057 serial_port_out(port, SCPCR,
2058 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2061 /* Enable Auto RTS */
2062 serial_port_out(port, SCFCR,
2063 serial_port_in(port, SCFCR) | SCFCR_MCE);
2066 sci_set_rts(port, 1);
2070 static unsigned int sci_get_mctrl(struct uart_port *port)
2072 struct sci_port *s = to_sci_port(port);
2073 struct mctrl_gpios *gpios = s->gpios;
2074 unsigned int mctrl = 0;
2076 mctrl_gpio_get(gpios, &mctrl);
2079 * CTS/RTS is handled in hardware when supported, while nothing
2083 if (sci_get_cts(port))
2085 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2088 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2090 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2096 static void sci_enable_ms(struct uart_port *port)
2098 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2101 static void sci_break_ctl(struct uart_port *port, int break_state)
2103 unsigned short scscr, scsptr;
2104 unsigned long flags;
2106 /* check wheter the port has SCSPTR */
2107 if (!sci_getreg(port, SCSPTR)->size) {
2109 * Not supported by hardware. Most parts couple break and rx
2110 * interrupts together, with break detection always enabled.
2115 spin_lock_irqsave(&port->lock, flags);
2116 scsptr = serial_port_in(port, SCSPTR);
2117 scscr = serial_port_in(port, SCSCR);
2119 if (break_state == -1) {
2120 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2123 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2127 serial_port_out(port, SCSPTR, scsptr);
2128 serial_port_out(port, SCSCR, scscr);
2129 spin_unlock_irqrestore(&port->lock, flags);
2132 static int sci_startup(struct uart_port *port)
2134 struct sci_port *s = to_sci_port(port);
2137 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2139 sci_request_dma(port);
2141 ret = sci_request_irq(s);
2142 if (unlikely(ret < 0)) {
2150 static void sci_shutdown(struct uart_port *port)
2152 struct sci_port *s = to_sci_port(port);
2153 unsigned long flags;
2156 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2159 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2161 spin_lock_irqsave(&port->lock, flags);
2165 * Stop RX and TX, disable related interrupts, keep clock source
2166 * and HSCIF TOT bits
2168 scr = serial_port_in(port, SCSCR);
2169 serial_port_out(port, SCSCR, scr &
2170 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2171 spin_unlock_irqrestore(&port->lock, flags);
2173 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2174 if (s->chan_rx_saved) {
2175 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2177 hrtimer_cancel(&s->rx_timer);
2181 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2182 del_timer_sync(&s->rx_fifo_timer);
2187 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2190 unsigned long freq = s->clk_rates[SCI_SCK];
2191 int err, min_err = INT_MAX;
2194 if (s->port.type != PORT_HSCIF)
2197 for_each_sr(sr, s) {
2198 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2199 if (abs(err) >= abs(min_err))
2209 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2214 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2215 unsigned long freq, unsigned int *dlr,
2218 int err, min_err = INT_MAX;
2219 unsigned int sr, dl;
2221 if (s->port.type != PORT_HSCIF)
2224 for_each_sr(sr, s) {
2225 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2226 dl = clamp(dl, 1U, 65535U);
2228 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2229 if (abs(err) >= abs(min_err))
2240 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2241 min_err, *dlr, *srr + 1);
2245 /* calculate sample rate, BRR, and clock select */
2246 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2247 unsigned int *brr, unsigned int *srr,
2250 unsigned long freq = s->clk_rates[SCI_FCK];
2251 unsigned int sr, br, prediv, scrate, c;
2252 int err, min_err = INT_MAX;
2254 if (s->port.type != PORT_HSCIF)
2258 * Find the combination of sample rate and clock select with the
2259 * smallest deviation from the desired baud rate.
2260 * Prefer high sample rates to maximise the receive margin.
2262 * M: Receive margin (%)
2263 * N: Ratio of bit rate to clock (N = sampling rate)
2264 * D: Clock duty (D = 0 to 1.0)
2265 * L: Frame length (L = 9 to 12)
2266 * F: Absolute value of clock frequency deviation
2268 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2269 * (|D - 0.5| / N * (1 + F))|
2270 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2272 for_each_sr(sr, s) {
2273 for (c = 0; c <= 3; c++) {
2274 /* integerized formulas from HSCIF documentation */
2275 prediv = sr * (1 << (2 * c + 1));
2278 * We need to calculate:
2280 * br = freq / (prediv * bps) clamped to [1..256]
2281 * err = freq / (br * prediv) - bps
2283 * Watch out for overflow when calculating the desired
2284 * sampling clock rate!
2286 if (bps > UINT_MAX / prediv)
2289 scrate = prediv * bps;
2290 br = DIV_ROUND_CLOSEST(freq, scrate);
2291 br = clamp(br, 1U, 256U);
2293 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2294 if (abs(err) >= abs(min_err))
2308 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2309 min_err, *brr, *srr + 1, *cks);
2313 static void sci_reset(struct uart_port *port)
2315 const struct plat_sci_reg *reg;
2316 unsigned int status;
2317 struct sci_port *s = to_sci_port(port);
2319 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2321 reg = sci_getreg(port, SCFCR);
2323 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2325 sci_clear_SCxSR(port,
2326 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2327 SCxSR_BREAK_CLEAR(port));
2328 if (sci_getreg(port, SCLSR)->size) {
2329 status = serial_port_in(port, SCLSR);
2330 status &= ~(SCLSR_TO | SCLSR_ORER);
2331 serial_port_out(port, SCLSR, status);
2334 if (s->rx_trigger > 1) {
2335 if (s->rx_fifo_timeout) {
2336 scif_set_rtrg(port, 1);
2337 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2339 if (port->type == PORT_SCIFA ||
2340 port->type == PORT_SCIFB)
2341 scif_set_rtrg(port, 1);
2343 scif_set_rtrg(port, s->rx_trigger);
2348 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2349 struct ktermios *old)
2351 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2352 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2353 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2354 struct sci_port *s = to_sci_port(port);
2355 const struct plat_sci_reg *reg;
2356 int min_err = INT_MAX, err;
2357 unsigned long max_freq = 0;
2359 unsigned long flags;
2361 if ((termios->c_cflag & CSIZE) == CS7)
2362 smr_val |= SCSMR_CHR;
2363 if (termios->c_cflag & PARENB)
2364 smr_val |= SCSMR_PE;
2365 if (termios->c_cflag & PARODD)
2366 smr_val |= SCSMR_PE | SCSMR_ODD;
2367 if (termios->c_cflag & CSTOPB)
2368 smr_val |= SCSMR_STOP;
2371 * earlyprintk comes here early on with port->uartclk set to zero.
2372 * the clock framework is not up and running at this point so here
2373 * we assume that 115200 is the maximum baud rate. please note that
2374 * the baud rate is not programmed during earlyprintk - it is assumed
2375 * that the previous boot loader has enabled required clocks and
2376 * setup the baud rate generator hardware for us already.
2378 if (!port->uartclk) {
2379 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2383 for (i = 0; i < SCI_NUM_CLKS; i++)
2384 max_freq = max(max_freq, s->clk_rates[i]);
2386 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2391 * There can be multiple sources for the sampling clock. Find the one
2392 * that gives us the smallest deviation from the desired baud rate.
2395 /* Optional Undivided External Clock */
2396 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2397 port->type != PORT_SCIFB) {
2398 err = sci_sck_calc(s, baud, &srr1);
2399 if (abs(err) < abs(min_err)) {
2401 scr_val = SCSCR_CKE1;
2410 /* Optional BRG Frequency Divided External Clock */
2411 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2412 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2414 if (abs(err) < abs(min_err)) {
2415 best_clk = SCI_SCIF_CLK;
2416 scr_val = SCSCR_CKE1;
2426 /* Optional BRG Frequency Divided Internal Clock */
2427 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2428 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2430 if (abs(err) < abs(min_err)) {
2431 best_clk = SCI_BRG_INT;
2432 scr_val = SCSCR_CKE1;
2442 /* Divided Functional Clock using standard Bit Rate Register */
2443 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2444 if (abs(err) < abs(min_err)) {
2455 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2456 s->clks[best_clk], baud, min_err);
2461 * Program the optional External Baud Rate Generator (BRG) first.
2462 * It controls the mux to select (H)SCK or frequency divided clock.
2464 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2465 serial_port_out(port, SCDL, dl);
2466 serial_port_out(port, SCCKS, sccks);
2469 spin_lock_irqsave(&port->lock, flags);
2473 uart_update_timeout(port, termios->c_cflag, baud);
2475 /* byte size and parity */
2476 switch (termios->c_cflag & CSIZE) {
2491 if (termios->c_cflag & CSTOPB)
2493 if (termios->c_cflag & PARENB)
2496 if (best_clk >= 0) {
2497 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2499 case 5: smr_val |= SCSMR_SRC_5; break;
2500 case 7: smr_val |= SCSMR_SRC_7; break;
2501 case 11: smr_val |= SCSMR_SRC_11; break;
2502 case 13: smr_val |= SCSMR_SRC_13; break;
2503 case 16: smr_val |= SCSMR_SRC_16; break;
2504 case 17: smr_val |= SCSMR_SRC_17; break;
2505 case 19: smr_val |= SCSMR_SRC_19; break;
2506 case 27: smr_val |= SCSMR_SRC_27; break;
2509 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2510 serial_port_out(port, SCSMR, smr_val);
2511 serial_port_out(port, SCBRR, brr);
2512 if (sci_getreg(port, HSSRR)->size) {
2513 unsigned int hssrr = srr | HSCIF_SRE;
2514 /* Calculate deviation from intended rate at the
2515 * center of the last stop bit in sampling clocks.
2517 int last_stop = bits * 2 - 1;
2518 int deviation = min_err * srr * last_stop / 2 / baud;
2520 if (abs(deviation) >= 2) {
2521 /* At least two sampling clocks off at the
2522 * last stop bit; we can increase the error
2523 * margin by shifting the sampling point.
2525 int shift = min(-8, max(7, deviation / 2));
2527 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2529 hssrr |= HSCIF_SRDE;
2531 serial_port_out(port, HSSRR, hssrr);
2534 /* Wait one bit interval */
2535 udelay((1000000 + (baud - 1)) / baud);
2537 /* Don't touch the bit rate configuration */
2538 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2539 smr_val |= serial_port_in(port, SCSMR) &
2540 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2541 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2542 serial_port_out(port, SCSMR, smr_val);
2545 sci_init_pins(port, termios->c_cflag);
2547 port->status &= ~UPSTAT_AUTOCTS;
2549 reg = sci_getreg(port, SCFCR);
2551 unsigned short ctrl = serial_port_in(port, SCFCR);
2553 if ((port->flags & UPF_HARD_FLOW) &&
2554 (termios->c_cflag & CRTSCTS)) {
2555 /* There is no CTS interrupt to restart the hardware */
2556 port->status |= UPSTAT_AUTOCTS;
2557 /* MCE is enabled when RTS is raised */
2562 * As we've done a sci_reset() above, ensure we don't
2563 * interfere with the FIFOs while toggling MCE. As the
2564 * reset values could still be set, simply mask them out.
2566 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2568 serial_port_out(port, SCFCR, ctrl);
2570 if (port->flags & UPF_HARD_FLOW) {
2571 /* Refresh (Auto) RTS */
2572 sci_set_mctrl(port, port->mctrl);
2575 scr_val |= SCSCR_RE | SCSCR_TE |
2576 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2577 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2578 if ((srr + 1 == 5) &&
2579 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2581 * In asynchronous mode, when the sampling rate is 1/5, first
2582 * received data may become invalid on some SCIFA and SCIFB.
2583 * To avoid this problem wait more than 1 serial data time (1
2584 * bit time x serial data number) after setting SCSCR.RE = 1.
2586 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2590 * Calculate delay for 2 DMA buffers (4 FIFO).
2591 * See serial_core.c::uart_update_timeout().
2592 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2593 * function calculates 1 jiffie for the data plus 5 jiffies for the
2594 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2595 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2596 * value obtained by this formula is too small. Therefore, if the value
2597 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2599 s->rx_frame = (10000 * bits) / (baud / 100);
2600 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2601 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2602 if (s->rx_timeout < 20)
2606 if ((termios->c_cflag & CREAD) != 0)
2609 spin_unlock_irqrestore(&port->lock, flags);
2611 sci_port_disable(s);
2613 if (UART_ENABLE_MS(port, termios->c_cflag))
2614 sci_enable_ms(port);
2617 static void sci_pm(struct uart_port *port, unsigned int state,
2618 unsigned int oldstate)
2620 struct sci_port *sci_port = to_sci_port(port);
2623 case UART_PM_STATE_OFF:
2624 sci_port_disable(sci_port);
2627 sci_port_enable(sci_port);
2632 static const char *sci_type(struct uart_port *port)
2634 switch (port->type) {
2652 static int sci_remap_port(struct uart_port *port)
2654 struct sci_port *sport = to_sci_port(port);
2657 * Nothing to do if there's already an established membase.
2662 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2663 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2664 if (unlikely(!port->membase)) {
2665 dev_err(port->dev, "can't remap port#%d\n", port->line);
2670 * For the simple (and majority of) cases where we don't
2671 * need to do any remapping, just cast the cookie
2674 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2680 static void sci_release_port(struct uart_port *port)
2682 struct sci_port *sport = to_sci_port(port);
2684 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2685 iounmap(port->membase);
2686 port->membase = NULL;
2689 release_mem_region(port->mapbase, sport->reg_size);
2692 static int sci_request_port(struct uart_port *port)
2694 struct resource *res;
2695 struct sci_port *sport = to_sci_port(port);
2698 res = request_mem_region(port->mapbase, sport->reg_size,
2699 dev_name(port->dev));
2700 if (unlikely(res == NULL)) {
2701 dev_err(port->dev, "request_mem_region failed.");
2705 ret = sci_remap_port(port);
2706 if (unlikely(ret != 0)) {
2707 release_resource(res);
2714 static void sci_config_port(struct uart_port *port, int flags)
2716 if (flags & UART_CONFIG_TYPE) {
2717 struct sci_port *sport = to_sci_port(port);
2719 port->type = sport->cfg->type;
2720 sci_request_port(port);
2724 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2726 if (ser->baud_base < 2400)
2727 /* No paper tape reader for Mitch.. */
2733 static const struct uart_ops sci_uart_ops = {
2734 .tx_empty = sci_tx_empty,
2735 .set_mctrl = sci_set_mctrl,
2736 .get_mctrl = sci_get_mctrl,
2737 .start_tx = sci_start_tx,
2738 .stop_tx = sci_stop_tx,
2739 .stop_rx = sci_stop_rx,
2740 .enable_ms = sci_enable_ms,
2741 .break_ctl = sci_break_ctl,
2742 .startup = sci_startup,
2743 .shutdown = sci_shutdown,
2744 .flush_buffer = sci_flush_buffer,
2745 .set_termios = sci_set_termios,
2748 .release_port = sci_release_port,
2749 .request_port = sci_request_port,
2750 .config_port = sci_config_port,
2751 .verify_port = sci_verify_port,
2752 #ifdef CONFIG_CONSOLE_POLL
2753 .poll_get_char = sci_poll_get_char,
2754 .poll_put_char = sci_poll_put_char,
2758 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2760 const char *clk_names[] = {
2763 [SCI_BRG_INT] = "brg_int",
2764 [SCI_SCIF_CLK] = "scif_clk",
2769 if (sci_port->cfg->type == PORT_HSCIF)
2770 clk_names[SCI_SCK] = "hsck";
2772 for (i = 0; i < SCI_NUM_CLKS; i++) {
2773 clk = devm_clk_get(dev, clk_names[i]);
2774 if (PTR_ERR(clk) == -EPROBE_DEFER)
2775 return -EPROBE_DEFER;
2777 if (IS_ERR(clk) && i == SCI_FCK) {
2779 * "fck" used to be called "sci_ick", and we need to
2780 * maintain DT backward compatibility.
2782 clk = devm_clk_get(dev, "sci_ick");
2783 if (PTR_ERR(clk) == -EPROBE_DEFER)
2784 return -EPROBE_DEFER;
2790 * Not all SH platforms declare a clock lookup entry
2791 * for SCI devices, in which case we need to get the
2792 * global "peripheral_clk" clock.
2794 clk = devm_clk_get(dev, "peripheral_clk");
2798 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2800 return PTR_ERR(clk);
2805 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2808 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2809 clk, clk_get_rate(clk));
2810 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2815 static const struct sci_port_params *
2816 sci_probe_regmap(const struct plat_sci_port *cfg)
2818 unsigned int regtype;
2820 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2821 return &sci_port_params[cfg->regtype];
2823 switch (cfg->type) {
2825 regtype = SCIx_SCI_REGTYPE;
2828 regtype = SCIx_IRDA_REGTYPE;
2831 regtype = SCIx_SCIFA_REGTYPE;
2834 regtype = SCIx_SCIFB_REGTYPE;
2838 * The SH-4 is a bit of a misnomer here, although that's
2839 * where this particular port layout originated. This
2840 * configuration (or some slight variation thereof)
2841 * remains the dominant model for all SCIFs.
2843 regtype = SCIx_SH4_SCIF_REGTYPE;
2846 regtype = SCIx_HSCIF_REGTYPE;
2849 pr_err("Can't probe register map for given port\n");
2853 return &sci_port_params[regtype];
2856 static int sci_init_single(struct platform_device *dev,
2857 struct sci_port *sci_port, unsigned int index,
2858 const struct plat_sci_port *p, bool early)
2860 struct uart_port *port = &sci_port->port;
2861 const struct resource *res;
2867 port->ops = &sci_uart_ops;
2868 port->iotype = UPIO_MEM;
2871 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2875 port->mapbase = res->start;
2876 sci_port->reg_size = resource_size(res);
2878 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2879 sci_port->irqs[i] = platform_get_irq(dev, i);
2881 /* The SCI generates several interrupts. They can be muxed together or
2882 * connected to different interrupt lines. In the muxed case only one
2883 * interrupt resource is specified as there is only one interrupt ID.
2884 * In the non-muxed case, up to 6 interrupt signals might be generated
2885 * from the SCI, however those signals might have their own individual
2886 * interrupt ID numbers, or muxed together with another interrupt.
2888 if (sci_port->irqs[0] < 0)
2891 if (sci_port->irqs[1] < 0)
2892 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
2893 sci_port->irqs[i] = sci_port->irqs[0];
2895 sci_port->params = sci_probe_regmap(p);
2896 if (unlikely(sci_port->params == NULL))
2901 sci_port->rx_trigger = 48;
2904 sci_port->rx_trigger = 64;
2907 sci_port->rx_trigger = 32;
2910 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2911 /* RX triggering not implemented for this IP */
2912 sci_port->rx_trigger = 1;
2914 sci_port->rx_trigger = 8;
2917 sci_port->rx_trigger = 1;
2921 sci_port->rx_fifo_timeout = 0;
2922 sci_port->hscif_tot = 0;
2924 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2925 * match the SoC datasheet, this should be investigated. Let platform
2926 * data override the sampling rate for now.
2928 sci_port->sampling_rate_mask = p->sampling_rate
2929 ? SCI_SR(p->sampling_rate)
2930 : sci_port->params->sampling_rate_mask;
2933 ret = sci_init_clocks(sci_port, &dev->dev);
2937 port->dev = &dev->dev;
2939 pm_runtime_enable(&dev->dev);
2942 port->type = p->type;
2943 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2944 port->fifosize = sci_port->params->fifosize;
2946 if (port->type == PORT_SCI) {
2947 if (sci_port->reg_size >= 0x20)
2954 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2955 * for the multi-IRQ ports, which is where we are primarily
2956 * concerned with the shutdown path synchronization.
2958 * For the muxed case there's nothing more to do.
2960 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2963 port->serial_in = sci_serial_in;
2964 port->serial_out = sci_serial_out;
2969 static void sci_cleanup_single(struct sci_port *port)
2971 pm_runtime_disable(port->port.dev);
2974 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2975 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2976 static void serial_console_putchar(struct uart_port *port, int ch)
2978 sci_poll_put_char(port, ch);
2982 * Print a string to the serial port trying not to disturb
2983 * any possible real use of the port...
2985 static void serial_console_write(struct console *co, const char *s,
2988 struct sci_port *sci_port = &sci_ports[co->index];
2989 struct uart_port *port = &sci_port->port;
2990 unsigned short bits, ctrl, ctrl_temp;
2991 unsigned long flags;
2994 #if defined(SUPPORT_SYSRQ)
2999 if (oops_in_progress)
3000 locked = spin_trylock_irqsave(&port->lock, flags);
3002 spin_lock_irqsave(&port->lock, flags);
3004 /* first save SCSCR then disable interrupts, keep clock source */
3005 ctrl = serial_port_in(port, SCSCR);
3006 ctrl_temp = SCSCR_RE | SCSCR_TE |
3007 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3008 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3009 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3011 uart_console_write(port, s, count, serial_console_putchar);
3013 /* wait until fifo is empty and last bit has been transmitted */
3014 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3015 while ((serial_port_in(port, SCxSR) & bits) != bits)
3018 /* restore the SCSCR */
3019 serial_port_out(port, SCSCR, ctrl);
3022 spin_unlock_irqrestore(&port->lock, flags);
3025 static int serial_console_setup(struct console *co, char *options)
3027 struct sci_port *sci_port;
3028 struct uart_port *port;
3036 * Refuse to handle any bogus ports.
3038 if (co->index < 0 || co->index >= SCI_NPORTS)
3041 sci_port = &sci_ports[co->index];
3042 port = &sci_port->port;
3045 * Refuse to handle uninitialized ports.
3050 ret = sci_remap_port(port);
3051 if (unlikely(ret != 0))
3055 uart_parse_options(options, &baud, &parity, &bits, &flow);
3057 return uart_set_options(port, co, baud, parity, bits, flow);
3060 static struct console serial_console = {
3062 .device = uart_console_device,
3063 .write = serial_console_write,
3064 .setup = serial_console_setup,
3065 .flags = CON_PRINTBUFFER,
3067 .data = &sci_uart_driver,
3070 static struct console early_serial_console = {
3071 .name = "early_ttySC",
3072 .write = serial_console_write,
3073 .flags = CON_PRINTBUFFER,
3077 static char early_serial_buf[32];
3079 static int sci_probe_earlyprintk(struct platform_device *pdev)
3081 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3083 if (early_serial_console.data)
3086 early_serial_console.index = pdev->id;
3088 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3090 serial_console_setup(&early_serial_console, early_serial_buf);
3092 if (!strstr(early_serial_buf, "keep"))
3093 early_serial_console.flags |= CON_BOOT;
3095 register_console(&early_serial_console);
3099 #define SCI_CONSOLE (&serial_console)
3102 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3107 #define SCI_CONSOLE NULL
3109 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3111 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3113 static DEFINE_MUTEX(sci_uart_registration_lock);
3114 static struct uart_driver sci_uart_driver = {
3115 .owner = THIS_MODULE,
3116 .driver_name = "sci",
3117 .dev_name = "ttySC",
3119 .minor = SCI_MINOR_START,
3121 .cons = SCI_CONSOLE,
3124 static int sci_remove(struct platform_device *dev)
3126 struct sci_port *port = platform_get_drvdata(dev);
3127 unsigned int type = port->port.type; /* uart_remove_... clears it */
3129 sci_ports_in_use &= ~BIT(port->port.line);
3130 uart_remove_one_port(&sci_uart_driver, &port->port);
3132 sci_cleanup_single(port);
3134 if (port->port.fifosize > 1) {
3135 sysfs_remove_file(&dev->dev.kobj,
3136 &dev_attr_rx_fifo_trigger.attr);
3138 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF) {
3139 sysfs_remove_file(&dev->dev.kobj,
3140 &dev_attr_rx_fifo_timeout.attr);
3147 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3148 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3149 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3151 static const struct of_device_id of_sci_match[] = {
3152 /* SoC-specific types */
3154 .compatible = "renesas,scif-r7s72100",
3155 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3158 .compatible = "renesas,scif-r7s9210",
3159 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3161 /* Family-specific types */
3163 .compatible = "renesas,rcar-gen1-scif",
3164 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3166 .compatible = "renesas,rcar-gen2-scif",
3167 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3169 .compatible = "renesas,rcar-gen3-scif",
3170 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3174 .compatible = "renesas,scif",
3175 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3177 .compatible = "renesas,scifa",
3178 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3180 .compatible = "renesas,scifb",
3181 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3183 .compatible = "renesas,hscif",
3184 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3186 .compatible = "renesas,sci",
3187 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3192 MODULE_DEVICE_TABLE(of, of_sci_match);
3194 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3195 unsigned int *dev_id)
3197 struct device_node *np = pdev->dev.of_node;
3198 struct plat_sci_port *p;
3199 struct sci_port *sp;
3203 if (!IS_ENABLED(CONFIG_OF) || !np)
3206 data = of_device_get_match_data(&pdev->dev);
3208 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3212 /* Get the line number from the aliases node. */
3213 id = of_alias_get_id(np, "serial");
3214 if (id < 0 && ~sci_ports_in_use)
3215 id = ffz(sci_ports_in_use);
3217 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3220 if (id >= ARRAY_SIZE(sci_ports)) {
3221 dev_err(&pdev->dev, "serial%d out of range\n", id);
3225 sp = &sci_ports[id];
3228 p->type = SCI_OF_TYPE(data);
3229 p->regtype = SCI_OF_REGTYPE(data);
3231 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3236 static int sci_probe_single(struct platform_device *dev,
3238 struct plat_sci_port *p,
3239 struct sci_port *sciport)
3244 if (unlikely(index >= SCI_NPORTS)) {
3245 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3246 index+1, SCI_NPORTS);
3247 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3250 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3251 if (sci_ports_in_use & BIT(index))
3254 mutex_lock(&sci_uart_registration_lock);
3255 if (!sci_uart_driver.state) {
3256 ret = uart_register_driver(&sci_uart_driver);
3258 mutex_unlock(&sci_uart_registration_lock);
3262 mutex_unlock(&sci_uart_registration_lock);
3264 ret = sci_init_single(dev, sciport, index, p, false);
3268 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3269 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3270 return PTR_ERR(sciport->gpios);
3272 if (sciport->has_rtscts) {
3273 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3275 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3277 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3280 sciport->port.flags |= UPF_HARD_FLOW;
3283 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3285 sci_cleanup_single(sciport);
3292 static int sci_probe(struct platform_device *dev)
3294 struct plat_sci_port *p;
3295 struct sci_port *sp;
3296 unsigned int dev_id;
3300 * If we've come here via earlyprintk initialization, head off to
3301 * the special early probe. We don't have sufficient device state
3302 * to make it beyond this yet.
3304 if (is_early_platform_device(dev))
3305 return sci_probe_earlyprintk(dev);
3307 if (dev->dev.of_node) {
3308 p = sci_parse_dt(dev, &dev_id);
3312 p = dev->dev.platform_data;
3314 dev_err(&dev->dev, "no platform data supplied\n");
3321 sp = &sci_ports[dev_id];
3322 platform_set_drvdata(dev, sp);
3324 ret = sci_probe_single(dev, dev_id, p, sp);
3328 if (sp->port.fifosize > 1) {
3329 ret = sysfs_create_file(&dev->dev.kobj,
3330 &dev_attr_rx_fifo_trigger.attr);
3334 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3335 sp->port.type == PORT_HSCIF) {
3336 ret = sysfs_create_file(&dev->dev.kobj,
3337 &dev_attr_rx_fifo_timeout.attr);
3339 if (sp->port.fifosize > 1) {
3340 sysfs_remove_file(&dev->dev.kobj,
3341 &dev_attr_rx_fifo_trigger.attr);
3347 #ifdef CONFIG_SH_STANDARD_BIOS
3348 sh_bios_gdb_detach();
3351 sci_ports_in_use |= BIT(dev_id);
3355 static __maybe_unused int sci_suspend(struct device *dev)
3357 struct sci_port *sport = dev_get_drvdata(dev);
3360 uart_suspend_port(&sci_uart_driver, &sport->port);
3365 static __maybe_unused int sci_resume(struct device *dev)
3367 struct sci_port *sport = dev_get_drvdata(dev);
3370 uart_resume_port(&sci_uart_driver, &sport->port);
3375 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3377 static struct platform_driver sci_driver = {
3379 .remove = sci_remove,
3382 .pm = &sci_dev_pm_ops,
3383 .of_match_table = of_match_ptr(of_sci_match),
3387 static int __init sci_init(void)
3389 pr_info("%s\n", banner);
3391 return platform_driver_register(&sci_driver);
3394 static void __exit sci_exit(void)
3396 platform_driver_unregister(&sci_driver);
3398 if (sci_uart_driver.state)
3399 uart_unregister_driver(&sci_uart_driver);
3402 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3403 early_platform_init_buffer("earlyprintk", &sci_driver,
3404 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3406 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3407 static struct plat_sci_port port_cfg __initdata;
3409 static int __init early_console_setup(struct earlycon_device *device,
3412 if (!device->port.membase)
3415 device->port.serial_in = sci_serial_in;
3416 device->port.serial_out = sci_serial_out;
3417 device->port.type = type;
3418 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3419 port_cfg.type = type;
3420 sci_ports[0].cfg = &port_cfg;
3421 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3422 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3423 sci_serial_out(&sci_ports[0].port, SCSCR,
3424 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3426 device->con->write = serial_console_write;
3429 static int __init sci_early_console_setup(struct earlycon_device *device,
3432 return early_console_setup(device, PORT_SCI);
3434 static int __init scif_early_console_setup(struct earlycon_device *device,
3437 return early_console_setup(device, PORT_SCIF);
3439 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3442 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3443 return early_console_setup(device, PORT_SCIF);
3445 static int __init scifa_early_console_setup(struct earlycon_device *device,
3448 return early_console_setup(device, PORT_SCIFA);
3450 static int __init scifb_early_console_setup(struct earlycon_device *device,
3453 return early_console_setup(device, PORT_SCIFB);
3455 static int __init hscif_early_console_setup(struct earlycon_device *device,
3458 return early_console_setup(device, PORT_HSCIF);
3461 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3462 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3463 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3464 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3465 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3466 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3467 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3469 module_init(sci_init);
3470 module_exit(sci_exit);
3472 MODULE_LICENSE("GPL");
3473 MODULE_ALIAS("platform:sh-sci");
3474 MODULE_AUTHOR("Paul Mundt");
3475 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");