1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Maxime Coquelin 2015
4 * Copyright (C) STMicroelectronics SA 2017
5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com>
6 * Gerald Baeza <gerald.baeza@st.com>
8 * Inspired by st-asc.c from STMicroelectronics (c)
11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
15 #include <linux/clk.h>
16 #include <linux/console.h>
17 #include <linux/delay.h>
18 #include <linux/dma-direction.h>
19 #include <linux/dmaengine.h>
20 #include <linux/dma-mapping.h>
22 #include <linux/iopoll.h>
23 #include <linux/irq.h>
24 #include <linux/module.h>
26 #include <linux/of_platform.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pm_wakeirq.h>
30 #include <linux/serial_core.h>
31 #include <linux/serial.h>
32 #include <linux/spinlock.h>
33 #include <linux/sysrq.h>
34 #include <linux/tty_flip.h>
35 #include <linux/tty.h>
37 #include "stm32-usart.h"
39 static void stm32_stop_tx(struct uart_port *port);
40 static void stm32_transmit_chars(struct uart_port *port);
42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
44 return container_of(port, struct stm32_port, port);
47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
51 val = readl_relaxed(port->membase + reg);
53 writel_relaxed(val, port->membase + reg);
56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
60 val = readl_relaxed(port->membase + reg);
62 writel_relaxed(val, port->membase + reg);
65 static void stm32_config_reg_rs485(u32 *cr1, u32 *cr3, u32 delay_ADE,
66 u32 delay_DDE, u32 baud)
69 u32 rs485_deat_dedt_max = (USART_CR1_DEAT_MASK >> USART_CR1_DEAT_SHIFT);
72 *cr3 |= USART_CR3_DEM;
73 over8 = *cr1 & USART_CR1_OVER8;
76 rs485_deat_dedt = delay_ADE * baud * 8;
78 rs485_deat_dedt = delay_ADE * baud * 16;
80 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
81 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
82 rs485_deat_dedt_max : rs485_deat_dedt;
83 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEAT_SHIFT) &
85 *cr1 |= rs485_deat_dedt;
88 rs485_deat_dedt = delay_DDE * baud * 8;
90 rs485_deat_dedt = delay_DDE * baud * 16;
92 rs485_deat_dedt = DIV_ROUND_CLOSEST(rs485_deat_dedt, 1000);
93 rs485_deat_dedt = rs485_deat_dedt > rs485_deat_dedt_max ?
94 rs485_deat_dedt_max : rs485_deat_dedt;
95 rs485_deat_dedt = (rs485_deat_dedt << USART_CR1_DEDT_SHIFT) &
97 *cr1 |= rs485_deat_dedt;
100 static int stm32_config_rs485(struct uart_port *port,
101 struct serial_rs485 *rs485conf)
103 struct stm32_port *stm32_port = to_stm32_port(port);
104 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
105 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
106 u32 usartdiv, baud, cr1, cr3;
109 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
111 port->rs485 = *rs485conf;
113 rs485conf->flags |= SER_RS485_RX_DURING_TX;
115 if (rs485conf->flags & SER_RS485_ENABLED) {
116 cr1 = readl_relaxed(port->membase + ofs->cr1);
117 cr3 = readl_relaxed(port->membase + ofs->cr3);
118 usartdiv = readl_relaxed(port->membase + ofs->brr);
119 usartdiv = usartdiv & GENMASK(15, 0);
120 over8 = cr1 & USART_CR1_OVER8;
123 usartdiv = usartdiv | (usartdiv & GENMASK(4, 0))
124 << USART_BRR_04_R_SHIFT;
126 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv);
127 stm32_config_reg_rs485(&cr1, &cr3,
128 rs485conf->delay_rts_before_send,
129 rs485conf->delay_rts_after_send, baud);
131 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
132 cr3 &= ~USART_CR3_DEP;
133 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
135 cr3 |= USART_CR3_DEP;
136 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
139 writel_relaxed(cr3, port->membase + ofs->cr3);
140 writel_relaxed(cr1, port->membase + ofs->cr1);
142 stm32_clr_bits(port, ofs->cr3, USART_CR3_DEM | USART_CR3_DEP);
143 stm32_clr_bits(port, ofs->cr1,
144 USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
147 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
152 static int stm32_init_rs485(struct uart_port *port,
153 struct platform_device *pdev)
155 struct serial_rs485 *rs485conf = &port->rs485;
157 rs485conf->flags = 0;
158 rs485conf->delay_rts_before_send = 0;
159 rs485conf->delay_rts_after_send = 0;
161 if (!pdev->dev.of_node)
164 uart_get_rs485_mode(&pdev->dev, rs485conf);
169 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
172 struct stm32_port *stm32_port = to_stm32_port(port);
173 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
174 enum dma_status status;
175 struct dma_tx_state state;
177 *sr = readl_relaxed(port->membase + ofs->isr);
179 if (threaded && stm32_port->rx_ch) {
180 status = dmaengine_tx_status(stm32_port->rx_ch,
181 stm32_port->rx_ch->cookie,
183 if ((status == DMA_IN_PROGRESS) &&
184 (*last_res != state.residue))
188 } else if (*sr & USART_SR_RXNE) {
194 static unsigned long stm32_get_char(struct uart_port *port, u32 *sr,
197 struct stm32_port *stm32_port = to_stm32_port(port);
198 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
201 if (stm32_port->rx_ch) {
202 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
203 if ((*last_res) == 0)
204 *last_res = RX_BUF_L;
206 c = readl_relaxed(port->membase + ofs->rdr);
207 /* apply RDR data mask */
208 c &= stm32_port->rdr_mask;
214 static void stm32_receive_chars(struct uart_port *port, bool threaded)
216 struct tty_port *tport = &port->state->port;
217 struct stm32_port *stm32_port = to_stm32_port(port);
218 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
223 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
224 pm_wakeup_event(tport->tty->dev, 0);
226 while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
227 sr |= USART_SR_DUMMY_RX;
231 * Status bits has to be cleared before reading the RDR:
232 * In FIFO mode, reading the RDR will pop the next data
233 * (if any) along with its status bits into the SR.
234 * Not doing so leads to misalignement between RDR and SR,
235 * and clear status bits of the next rx data.
237 * Clear errors flags for stm32f7 and stm32h7 compatible
238 * devices. On stm32f4 compatible devices, the error bit is
239 * cleared by the sequence [read SR - read DR].
241 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
242 stm32_clr_bits(port, ofs->icr, USART_ICR_ORECF |
243 USART_ICR_PECF | USART_ICR_FECF);
245 c = stm32_get_char(port, &sr, &stm32_port->last_res);
247 if (sr & USART_SR_ERR_MASK) {
248 if (sr & USART_SR_ORE) {
249 port->icount.overrun++;
250 } else if (sr & USART_SR_PE) {
251 port->icount.parity++;
252 } else if (sr & USART_SR_FE) {
253 /* Break detection if character is null */
256 if (uart_handle_break(port))
259 port->icount.frame++;
263 sr &= port->read_status_mask;
265 if (sr & USART_SR_PE) {
267 } else if (sr & USART_SR_FE) {
275 if (uart_handle_sysrq_char(port, c))
277 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
280 spin_unlock(&port->lock);
281 tty_flip_buffer_push(tport);
282 spin_lock(&port->lock);
285 static void stm32_tx_dma_complete(void *arg)
287 struct uart_port *port = arg;
288 struct stm32_port *stm32port = to_stm32_port(port);
289 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
291 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
292 stm32port->tx_dma_busy = false;
294 /* Let's see if we have pending data to send */
295 stm32_transmit_chars(port);
298 static void stm32_transmit_chars_pio(struct uart_port *port)
300 struct stm32_port *stm32_port = to_stm32_port(port);
301 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
302 struct circ_buf *xmit = &port->state->xmit;
306 if (stm32_port->tx_dma_busy) {
307 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
308 stm32_port->tx_dma_busy = false;
311 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
313 (isr & USART_SR_TXE),
317 dev_err(port->dev, "tx empty not set\n");
319 stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
321 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
322 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
326 static void stm32_transmit_chars_dma(struct uart_port *port)
328 struct stm32_port *stm32port = to_stm32_port(port);
329 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
330 struct circ_buf *xmit = &port->state->xmit;
331 struct dma_async_tx_descriptor *desc = NULL;
333 unsigned int count, i;
335 if (stm32port->tx_dma_busy)
338 stm32port->tx_dma_busy = true;
340 count = uart_circ_chars_pending(xmit);
342 if (count > TX_BUF_L)
345 if (xmit->tail < xmit->head) {
346 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
348 size_t one = UART_XMIT_SIZE - xmit->tail;
355 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
357 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
360 desc = dmaengine_prep_slave_single(stm32port->tx_ch,
361 stm32port->tx_dma_buf,
367 for (i = count; i > 0; i--)
368 stm32_transmit_chars_pio(port);
372 desc->callback = stm32_tx_dma_complete;
373 desc->callback_param = port;
375 /* Push current DMA TX transaction in the pending queue */
376 cookie = dmaengine_submit(desc);
378 /* Issue pending DMA TX requests */
379 dma_async_issue_pending(stm32port->tx_ch);
381 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
383 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
384 port->icount.tx += count;
387 static void stm32_transmit_chars(struct uart_port *port)
389 struct stm32_port *stm32_port = to_stm32_port(port);
390 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
391 struct circ_buf *xmit = &port->state->xmit;
394 if (stm32_port->tx_dma_busy)
395 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
396 writel_relaxed(port->x_char, port->membase + ofs->tdr);
399 if (stm32_port->tx_dma_busy)
400 stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
404 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
405 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
409 if (ofs->icr == UNDEF_REG)
410 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
412 stm32_set_bits(port, ofs->icr, USART_ICR_TCCF);
414 if (stm32_port->tx_ch)
415 stm32_transmit_chars_dma(port);
417 stm32_transmit_chars_pio(port);
419 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
420 uart_write_wakeup(port);
422 if (uart_circ_empty(xmit))
423 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
426 static irqreturn_t stm32_interrupt(int irq, void *ptr)
428 struct uart_port *port = ptr;
429 struct stm32_port *stm32_port = to_stm32_port(port);
430 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
433 spin_lock(&port->lock);
435 sr = readl_relaxed(port->membase + ofs->isr);
437 if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
438 writel_relaxed(USART_ICR_WUCF,
439 port->membase + ofs->icr);
441 if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
442 stm32_receive_chars(port, false);
444 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
445 stm32_transmit_chars(port);
447 spin_unlock(&port->lock);
449 if (stm32_port->rx_ch)
450 return IRQ_WAKE_THREAD;
455 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
457 struct uart_port *port = ptr;
458 struct stm32_port *stm32_port = to_stm32_port(port);
460 spin_lock(&port->lock);
462 if (stm32_port->rx_ch)
463 stm32_receive_chars(port, true);
465 spin_unlock(&port->lock);
470 static unsigned int stm32_tx_empty(struct uart_port *port)
472 struct stm32_port *stm32_port = to_stm32_port(port);
473 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
475 return readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE;
478 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
480 struct stm32_port *stm32_port = to_stm32_port(port);
481 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
483 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
484 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
486 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
489 static unsigned int stm32_get_mctrl(struct uart_port *port)
491 /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
492 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
496 static void stm32_stop_tx(struct uart_port *port)
498 struct stm32_port *stm32_port = to_stm32_port(port);
499 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
501 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
504 /* There are probably characters waiting to be transmitted. */
505 static void stm32_start_tx(struct uart_port *port)
507 struct circ_buf *xmit = &port->state->xmit;
509 if (uart_circ_empty(xmit))
512 stm32_transmit_chars(port);
515 /* Throttle the remote when input buffer is about to overflow. */
516 static void stm32_throttle(struct uart_port *port)
518 struct stm32_port *stm32_port = to_stm32_port(port);
519 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
522 spin_lock_irqsave(&port->lock, flags);
523 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
524 spin_unlock_irqrestore(&port->lock, flags);
527 /* Unthrottle the remote, the input buffer can now accept data. */
528 static void stm32_unthrottle(struct uart_port *port)
530 struct stm32_port *stm32_port = to_stm32_port(port);
531 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
534 spin_lock_irqsave(&port->lock, flags);
535 stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
536 spin_unlock_irqrestore(&port->lock, flags);
540 static void stm32_stop_rx(struct uart_port *port)
542 struct stm32_port *stm32_port = to_stm32_port(port);
543 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
545 stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
548 /* Handle breaks - ignored by us */
549 static void stm32_break_ctl(struct uart_port *port, int break_state)
553 static int stm32_startup(struct uart_port *port)
555 struct stm32_port *stm32_port = to_stm32_port(port);
556 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
557 const char *name = to_platform_device(port->dev)->name;
561 ret = request_threaded_irq(port->irq, stm32_interrupt,
562 stm32_threaded_interrupt,
563 IRQF_NO_SUSPEND, name, port);
567 val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
568 if (stm32_port->fifoen)
569 val |= USART_CR1_FIFOEN;
570 stm32_set_bits(port, ofs->cr1, val);
575 static void stm32_shutdown(struct uart_port *port)
577 struct stm32_port *stm32_port = to_stm32_port(port);
578 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
579 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
583 val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
584 val |= BIT(cfg->uart_enable_bit);
585 if (stm32_port->fifoen)
586 val |= USART_CR1_FIFOEN;
588 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
589 isr, (isr & USART_SR_TC),
593 dev_err(port->dev, "transmission complete not set\n");
595 stm32_clr_bits(port, ofs->cr1, val);
597 free_irq(port->irq, port);
600 static unsigned int stm32_get_databits(struct ktermios *termios)
604 tcflag_t cflag = termios->c_cflag;
606 switch (cflag & CSIZE) {
608 * CSIZE settings are not necessarily supported in hardware.
609 * CSIZE unsupported configurations are handled here to set word length
610 * to 8 bits word as default configuration and to print debug message.
621 /* default including CS8 */
630 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
631 struct ktermios *old)
633 struct stm32_port *stm32_port = to_stm32_port(port);
634 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
635 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
636 struct serial_rs485 *rs485conf = &port->rs485;
637 unsigned int baud, bits;
638 u32 usartdiv, mantissa, fraction, oversampling;
639 tcflag_t cflag = termios->c_cflag;
643 if (!stm32_port->hw_flow_control)
646 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
648 spin_lock_irqsave(&port->lock, flags);
650 /* Stop serial port and reset value */
651 writel_relaxed(0, port->membase + ofs->cr1);
653 cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
655 if (stm32_port->fifoen)
656 cr1 |= USART_CR1_FIFOEN;
661 cr2 |= USART_CR2_STOP_2B;
663 bits = stm32_get_databits(termios);
664 stm32_port->rdr_mask = (BIT(bits) - 1);
666 if (cflag & PARENB) {
668 cr1 |= USART_CR1_PCE;
672 * Word length configuration:
673 * CS8 + parity, 9 bits word aka [M1:M0] = 0b01
674 * CS7 or (CS6 + parity), 7 bits word aka [M1:M0] = 0b10
675 * CS8 or (CS7 + parity), 8 bits word aka [M1:M0] = 0b00
676 * M0 and M1 already cleared by cr1 initialization.
680 else if ((bits == 7) && cfg->has_7bits_data)
683 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n"
689 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
690 if (cflag & CRTSCTS) {
691 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
692 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
695 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
698 * The USART supports 16 or 8 times oversampling.
699 * By default we prefer 16 times oversampling, so that the receiver
700 * has a better tolerance to clock deviations.
701 * 8 times oversampling is only used to achieve higher speeds.
705 cr1 |= USART_CR1_OVER8;
706 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
709 cr1 &= ~USART_CR1_OVER8;
710 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
713 mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
714 fraction = usartdiv % oversampling;
715 writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
717 uart_update_timeout(port, cflag, baud);
719 port->read_status_mask = USART_SR_ORE;
720 if (termios->c_iflag & INPCK)
721 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
722 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
723 port->read_status_mask |= USART_SR_FE;
725 /* Characters to ignore */
726 port->ignore_status_mask = 0;
727 if (termios->c_iflag & IGNPAR)
728 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
729 if (termios->c_iflag & IGNBRK) {
730 port->ignore_status_mask |= USART_SR_FE;
732 * If we're ignoring parity and break indicators,
733 * ignore overruns too (for real raw support).
735 if (termios->c_iflag & IGNPAR)
736 port->ignore_status_mask |= USART_SR_ORE;
739 /* Ignore all characters if CREAD is not set */
740 if ((termios->c_cflag & CREAD) == 0)
741 port->ignore_status_mask |= USART_SR_DUMMY_RX;
743 if (stm32_port->rx_ch)
744 cr3 |= USART_CR3_DMAR;
746 if (rs485conf->flags & SER_RS485_ENABLED) {
747 stm32_config_reg_rs485(&cr1, &cr3,
748 rs485conf->delay_rts_before_send,
749 rs485conf->delay_rts_after_send, baud);
750 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) {
751 cr3 &= ~USART_CR3_DEP;
752 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
754 cr3 |= USART_CR3_DEP;
755 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
759 cr3 &= ~(USART_CR3_DEM | USART_CR3_DEP);
760 cr1 &= ~(USART_CR1_DEDT_MASK | USART_CR1_DEAT_MASK);
763 writel_relaxed(cr3, port->membase + ofs->cr3);
764 writel_relaxed(cr2, port->membase + ofs->cr2);
765 writel_relaxed(cr1, port->membase + ofs->cr1);
767 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
768 spin_unlock_irqrestore(&port->lock, flags);
771 static const char *stm32_type(struct uart_port *port)
773 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
776 static void stm32_release_port(struct uart_port *port)
780 static int stm32_request_port(struct uart_port *port)
785 static void stm32_config_port(struct uart_port *port, int flags)
787 if (flags & UART_CONFIG_TYPE)
788 port->type = PORT_STM32;
792 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
794 /* No user changeable parameters */
798 static void stm32_pm(struct uart_port *port, unsigned int state,
799 unsigned int oldstate)
801 struct stm32_port *stm32port = container_of(port,
802 struct stm32_port, port);
803 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
804 struct stm32_usart_config *cfg = &stm32port->info->cfg;
805 unsigned long flags = 0;
808 case UART_PM_STATE_ON:
809 clk_prepare_enable(stm32port->clk);
811 case UART_PM_STATE_OFF:
812 spin_lock_irqsave(&port->lock, flags);
813 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
814 spin_unlock_irqrestore(&port->lock, flags);
815 clk_disable_unprepare(stm32port->clk);
820 static const struct uart_ops stm32_uart_ops = {
821 .tx_empty = stm32_tx_empty,
822 .set_mctrl = stm32_set_mctrl,
823 .get_mctrl = stm32_get_mctrl,
824 .stop_tx = stm32_stop_tx,
825 .start_tx = stm32_start_tx,
826 .throttle = stm32_throttle,
827 .unthrottle = stm32_unthrottle,
828 .stop_rx = stm32_stop_rx,
829 .break_ctl = stm32_break_ctl,
830 .startup = stm32_startup,
831 .shutdown = stm32_shutdown,
832 .set_termios = stm32_set_termios,
835 .release_port = stm32_release_port,
836 .request_port = stm32_request_port,
837 .config_port = stm32_config_port,
838 .verify_port = stm32_verify_port,
841 static int stm32_init_port(struct stm32_port *stm32port,
842 struct platform_device *pdev)
844 struct uart_port *port = &stm32port->port;
845 struct resource *res;
848 port->iotype = UPIO_MEM;
849 port->flags = UPF_BOOT_AUTOCONF;
850 port->ops = &stm32_uart_ops;
851 port->dev = &pdev->dev;
853 ret = platform_get_irq(pdev, 0);
855 if (ret != -EPROBE_DEFER)
856 dev_err(&pdev->dev, "Can't get event IRQ: %d\n", ret);
857 return ret ? ret : -ENODEV;
861 port->rs485_config = stm32_config_rs485;
863 stm32_init_rs485(port, pdev);
865 if (stm32port->info->cfg.has_wakeup) {
866 stm32port->wakeirq = platform_get_irq(pdev, 1);
867 if (stm32port->wakeirq <= 0 && stm32port->wakeirq != -ENXIO) {
868 if (stm32port->wakeirq != -EPROBE_DEFER)
870 "Can't get event wake IRQ: %d\n",
872 return stm32port->wakeirq ? stm32port->wakeirq :
877 stm32port->fifoen = stm32port->info->cfg.has_fifo;
879 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
880 port->membase = devm_ioremap_resource(&pdev->dev, res);
881 if (IS_ERR(port->membase))
882 return PTR_ERR(port->membase);
883 port->mapbase = res->start;
885 spin_lock_init(&port->lock);
887 stm32port->clk = devm_clk_get(&pdev->dev, NULL);
888 if (IS_ERR(stm32port->clk))
889 return PTR_ERR(stm32port->clk);
891 /* Ensure that clk rate is correct by enabling the clk */
892 ret = clk_prepare_enable(stm32port->clk);
896 stm32port->port.uartclk = clk_get_rate(stm32port->clk);
897 if (!stm32port->port.uartclk) {
898 clk_disable_unprepare(stm32port->clk);
905 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
907 struct device_node *np = pdev->dev.of_node;
913 id = of_alias_get_id(np, "serial");
915 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
919 if (WARN_ON(id >= STM32_MAX_PORTS))
922 stm32_ports[id].hw_flow_control = of_property_read_bool(np,
924 stm32_ports[id].port.line = id;
925 stm32_ports[id].last_res = RX_BUF_L;
926 return &stm32_ports[id];
930 static const struct of_device_id stm32_match[] = {
931 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
932 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
933 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
937 MODULE_DEVICE_TABLE(of, stm32_match);
940 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
941 struct platform_device *pdev)
943 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
944 struct uart_port *port = &stm32port->port;
945 struct device *dev = &pdev->dev;
946 struct dma_slave_config config;
947 struct dma_async_tx_descriptor *desc = NULL;
951 /* Request DMA RX channel */
952 stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
953 if (!stm32port->rx_ch) {
954 dev_info(dev, "rx dma alloc failed\n");
957 stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
958 &stm32port->rx_dma_buf,
960 if (!stm32port->rx_buf) {
965 /* Configure DMA channel */
966 memset(&config, 0, sizeof(config));
967 config.src_addr = port->mapbase + ofs->rdr;
968 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
970 ret = dmaengine_slave_config(stm32port->rx_ch, &config);
972 dev_err(dev, "rx dma channel config failed\n");
977 /* Prepare a DMA cyclic transaction */
978 desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
979 stm32port->rx_dma_buf,
980 RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
983 dev_err(dev, "rx dma prep cyclic failed\n");
988 /* No callback as dma buffer is drained on usart interrupt */
989 desc->callback = NULL;
990 desc->callback_param = NULL;
992 /* Push current DMA transaction in the pending queue */
993 cookie = dmaengine_submit(desc);
995 /* Issue pending DMA requests */
996 dma_async_issue_pending(stm32port->rx_ch);
1001 dma_free_coherent(&pdev->dev,
1002 RX_BUF_L, stm32port->rx_buf,
1003 stm32port->rx_dma_buf);
1006 dma_release_channel(stm32port->rx_ch);
1007 stm32port->rx_ch = NULL;
1012 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
1013 struct platform_device *pdev)
1015 struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
1016 struct uart_port *port = &stm32port->port;
1017 struct device *dev = &pdev->dev;
1018 struct dma_slave_config config;
1021 stm32port->tx_dma_busy = false;
1023 /* Request DMA TX channel */
1024 stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
1025 if (!stm32port->tx_ch) {
1026 dev_info(dev, "tx dma alloc failed\n");
1029 stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
1030 &stm32port->tx_dma_buf,
1032 if (!stm32port->tx_buf) {
1037 /* Configure DMA channel */
1038 memset(&config, 0, sizeof(config));
1039 config.dst_addr = port->mapbase + ofs->tdr;
1040 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1042 ret = dmaengine_slave_config(stm32port->tx_ch, &config);
1044 dev_err(dev, "tx dma channel config failed\n");
1052 dma_free_coherent(&pdev->dev,
1053 TX_BUF_L, stm32port->tx_buf,
1054 stm32port->tx_dma_buf);
1057 dma_release_channel(stm32port->tx_ch);
1058 stm32port->tx_ch = NULL;
1063 static int stm32_serial_probe(struct platform_device *pdev)
1065 const struct of_device_id *match;
1066 struct stm32_port *stm32port;
1069 stm32port = stm32_of_get_stm32_port(pdev);
1073 match = of_match_device(stm32_match, &pdev->dev);
1074 if (match && match->data)
1075 stm32port->info = (struct stm32_usart_info *)match->data;
1079 ret = stm32_init_port(stm32port, pdev);
1083 if (stm32port->wakeirq > 0) {
1084 ret = device_init_wakeup(&pdev->dev, true);
1088 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1089 stm32port->wakeirq);
1093 device_set_wakeup_enable(&pdev->dev, false);
1096 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
1100 ret = stm32_of_dma_rx_probe(stm32port, pdev);
1102 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
1104 ret = stm32_of_dma_tx_probe(stm32port, pdev);
1106 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
1108 platform_set_drvdata(pdev, &stm32port->port);
1113 if (stm32port->wakeirq > 0)
1114 dev_pm_clear_wake_irq(&pdev->dev);
1117 if (stm32port->wakeirq > 0)
1118 device_init_wakeup(&pdev->dev, false);
1121 clk_disable_unprepare(stm32port->clk);
1126 static int stm32_serial_remove(struct platform_device *pdev)
1128 struct uart_port *port = platform_get_drvdata(pdev);
1129 struct stm32_port *stm32_port = to_stm32_port(port);
1130 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1132 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
1134 if (stm32_port->rx_ch)
1135 dma_release_channel(stm32_port->rx_ch);
1137 if (stm32_port->rx_dma_buf)
1138 dma_free_coherent(&pdev->dev,
1139 RX_BUF_L, stm32_port->rx_buf,
1140 stm32_port->rx_dma_buf);
1142 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
1144 if (stm32_port->tx_ch)
1145 dma_release_channel(stm32_port->tx_ch);
1147 if (stm32_port->tx_dma_buf)
1148 dma_free_coherent(&pdev->dev,
1149 TX_BUF_L, stm32_port->tx_buf,
1150 stm32_port->tx_dma_buf);
1152 if (stm32_port->wakeirq > 0) {
1153 dev_pm_clear_wake_irq(&pdev->dev);
1154 device_init_wakeup(&pdev->dev, false);
1157 clk_disable_unprepare(stm32_port->clk);
1159 return uart_remove_one_port(&stm32_usart_driver, port);
1163 #ifdef CONFIG_SERIAL_STM32_CONSOLE
1164 static void stm32_console_putchar(struct uart_port *port, int ch)
1166 struct stm32_port *stm32_port = to_stm32_port(port);
1167 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1169 while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
1172 writel_relaxed(ch, port->membase + ofs->tdr);
1175 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
1177 struct uart_port *port = &stm32_ports[co->index].port;
1178 struct stm32_port *stm32_port = to_stm32_port(port);
1179 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1180 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1181 unsigned long flags;
1182 u32 old_cr1, new_cr1;
1185 local_irq_save(flags);
1188 else if (oops_in_progress)
1189 locked = spin_trylock(&port->lock);
1191 spin_lock(&port->lock);
1193 /* Save and disable interrupts, enable the transmitter */
1194 old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1195 new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1196 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit);
1197 writel_relaxed(new_cr1, port->membase + ofs->cr1);
1199 uart_console_write(port, s, cnt, stm32_console_putchar);
1201 /* Restore interrupt state */
1202 writel_relaxed(old_cr1, port->membase + ofs->cr1);
1205 spin_unlock(&port->lock);
1206 local_irq_restore(flags);
1209 static int stm32_console_setup(struct console *co, char *options)
1211 struct stm32_port *stm32port;
1217 if (co->index >= STM32_MAX_PORTS)
1220 stm32port = &stm32_ports[co->index];
1223 * This driver does not support early console initialization
1224 * (use ARM early printk support instead), so we only expect
1225 * this to be called during the uart port registration when the
1226 * driver gets probed and the port should be mapped at that point.
1228 if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1232 uart_parse_options(options, &baud, &parity, &bits, &flow);
1234 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1237 static struct console stm32_console = {
1238 .name = STM32_SERIAL_NAME,
1239 .device = uart_console_device,
1240 .write = stm32_console_write,
1241 .setup = stm32_console_setup,
1242 .flags = CON_PRINTBUFFER,
1244 .data = &stm32_usart_driver,
1247 #define STM32_SERIAL_CONSOLE (&stm32_console)
1250 #define STM32_SERIAL_CONSOLE NULL
1251 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1253 static struct uart_driver stm32_usart_driver = {
1254 .driver_name = DRIVER_NAME,
1255 .dev_name = STM32_SERIAL_NAME,
1258 .nr = STM32_MAX_PORTS,
1259 .cons = STM32_SERIAL_CONSOLE,
1262 #ifdef CONFIG_PM_SLEEP
1263 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1265 struct stm32_port *stm32_port = to_stm32_port(port);
1266 struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1267 struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1270 if (stm32_port->wakeirq <= 0)
1274 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1275 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1276 val = readl_relaxed(port->membase + ofs->cr3);
1277 val &= ~USART_CR3_WUS_MASK;
1278 /* Enable Wake up interrupt from low power on start bit */
1279 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1280 writel_relaxed(val, port->membase + ofs->cr3);
1281 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1283 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1287 static int stm32_serial_suspend(struct device *dev)
1289 struct uart_port *port = dev_get_drvdata(dev);
1291 uart_suspend_port(&stm32_usart_driver, port);
1293 if (device_may_wakeup(dev))
1294 stm32_serial_enable_wakeup(port, true);
1296 stm32_serial_enable_wakeup(port, false);
1301 static int stm32_serial_resume(struct device *dev)
1303 struct uart_port *port = dev_get_drvdata(dev);
1305 if (device_may_wakeup(dev))
1306 stm32_serial_enable_wakeup(port, false);
1308 return uart_resume_port(&stm32_usart_driver, port);
1310 #endif /* CONFIG_PM_SLEEP */
1312 static const struct dev_pm_ops stm32_serial_pm_ops = {
1313 SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1316 static struct platform_driver stm32_serial_driver = {
1317 .probe = stm32_serial_probe,
1318 .remove = stm32_serial_remove,
1320 .name = DRIVER_NAME,
1321 .pm = &stm32_serial_pm_ops,
1322 .of_match_table = of_match_ptr(stm32_match),
1326 static int __init usart_init(void)
1328 static char banner[] __initdata = "STM32 USART driver initialized";
1331 pr_info("%s\n", banner);
1333 ret = uart_register_driver(&stm32_usart_driver);
1337 ret = platform_driver_register(&stm32_serial_driver);
1339 uart_unregister_driver(&stm32_usart_driver);
1344 static void __exit usart_exit(void)
1346 platform_driver_unregister(&stm32_serial_driver);
1347 uart_unregister_driver(&stm32_usart_driver);
1350 module_init(usart_init);
1351 module_exit(usart_exit);
1353 MODULE_ALIAS("platform:" DRIVER_NAME);
1354 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1355 MODULE_LICENSE("GPL v2");