drivers/tty/serial/xilinx_uartps.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11
  12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  13 #define SUPPORT_SYSRQ
  14 #endif
  15
  16 #include <linux/platform_device.h>
  17 #include <linux/serial.h>
  18 #include <linux/console.h>
  19 #include <linux/serial_core.h>
  20 #include <linux/slab.h>
  21 #include <linux/tty.h>
  22 #include <linux/tty_flip.h>
  23 #include <linux/clk.h>
  24 #include <linux/irq.h>
  25 #include <linux/io.h>
  26 #include <linux/of.h>
  27 #include <linux/module.h>
  28 #include <linux/pm_runtime.h>
  29
  30 #define CDNS_UART_TTY_NAME      "ttyPS"
  31 #define CDNS_UART_NAME          "xuartps"
  32 #define CDNS_UART_MAJOR         0       /* use dynamic node allocation */
  33 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  34 #define CDNS_UART_REGISTER_SPACE        0x1000
  35
  36 /* Rx Trigger level */
  37 static int rx_trigger_level = 56;
  38 module_param(rx_trigger_level, uint, S_IRUGO);
  39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  40
  41 /* Rx Timeout */
  42 static int rx_timeout = 10;
  43 module_param(rx_timeout, uint, S_IRUGO);
  44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  45
  46 /* Register offsets for the UART. */
  47 #define CDNS_UART_CR            0x00  /* Control Register */
  48 #define CDNS_UART_MR            0x04  /* Mode Register */
  49 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  50 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  51 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  52 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  53 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  54 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  55 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  56 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  57 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  58 #define CDNS_UART_SR            0x2C  /* Channel Status */
  59 #define CDNS_UART_FIFO          0x30  /* FIFO */
  60 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  61 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  62 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  63 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  64 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  65 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  66
  67 /* Control Register Bit Definitions */
  68 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  69 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  70 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  71 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  72 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  73 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  74 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  75 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  76 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  77 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  78 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  79 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  80
  81 /*
  82  * Mode Register:
  83  * The mode register (MR) defines the mode of transfer as well as the data
  84  * format. If this register is modified during transmission or reception,
  85  * data validity cannot be guaranteed.
  86  */
  87 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  88 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  89 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  90 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  91
  92 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  93 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  94
  95 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  96 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
  97 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
  98 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
  99 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
 100
 101 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 102 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 103 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 104
 105 /*
 106  * Interrupt Registers:
 107  * Interrupt control logic uses the interrupt enable register (IER) and the
 108  * interrupt disable register (IDR) to set the value of the bits in the
 109  * interrupt mask register (IMR). The IMR determines whether to pass an
 110  * interrupt to the interrupt status register (ISR).
 111  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 112  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 113  * Reading either IER or IDR returns 0x00.
 114  * All four registers have the same bit definitions.
 115  */
 116 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 117 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 118 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 119 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 120 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 121 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 122 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 123 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 124 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 125 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 126 #define CDNS_UART_IXR_RXMASK    0x000021e7 /* Valid RX bit mask */
 127
 128         /*
 129          * Do not enable parity error interrupt for the following
 130          * reason: When parity error interrupt is enabled, each Rx
 131          * parity error always results in 2 events. The first one
 132          * being parity error interrupt and the second one with a
 133          * proper Rx interrupt with the incoming data.  Disabling
 134          * parity error interrupt ensures better handling of parity
 135          * error events. With this change, for a parity error case, we
 136          * get a Rx interrupt with parity error set in ISR register
 137          * and we still handle parity errors in the desired way.
 138          */
 139
 140 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 141                                  CDNS_UART_IXR_OVERRUN | \
 142                                  CDNS_UART_IXR_RXTRIG |  \
 143                                  CDNS_UART_IXR_TOUT)
 144
 145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 146 #define CDNS_UART_IXR_BRK       0x00002000
 147
 148 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 149 /*
 150  * Modem Control register:
 151  * The read/write Modem Control register controls the interface with the modem
 152  * or data set, or a peripheral device emulating a modem.
 153  */
 154 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 155 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 156 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 157
 158 /*
 159  * Channel Status Register:
 160  * The channel status register (CSR) is provided to enable the control logic
 161  * to monitor the status of bits in the channel interrupt status register,
 162  * even if these are masked out by the interrupt mask register.
 163  */
 164 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 165 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 166 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 167 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 168 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 169
 170 /* baud dividers min/max values */
 171 #define CDNS_UART_BDIV_MIN      4
 172 #define CDNS_UART_BDIV_MAX      255
 173 #define CDNS_UART_CD_MAX        65535
 174 #define UART_AUTOSUSPEND_TIMEOUT        3000
 175
 176 /**
 177  * struct cdns_uart - device data
 178  * @port:               Pointer to the UART port
 179  * @uartclk:            Reference clock
 180  * @pclk:               APB clock
 181  * @cdns_uart_driver:   Pointer to UART driver
 182  * @baud:               Current baud rate
 183  * @id:                 Port ID
 184  * @clk_rate_change_nb: Notifier block for clock changes
 185  * @quirks:             Flags for RXBS support.
 186  */
 187 struct cdns_uart {
 188         struct uart_port        *port;
 189         struct clk              *uartclk;
 190         struct clk              *pclk;
 191         struct uart_driver      *cdns_uart_driver;
 192         unsigned int            baud;
 193         int                     id;
 194         struct notifier_block   clk_rate_change_nb;
 195         u32                     quirks;
 196 };
 197 struct cdns_platform_data {
 198         u32 quirks;
 199 };
 200 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 201                 clk_rate_change_nb);
 202
 203 /**
 204  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 205  * @dev_id: Id of the UART port
 206  * @isrstatus: The interrupt status register value as read
 207  * Return: None
 208  */
 209 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 210 {
 211         struct uart_port *port = (struct uart_port *)dev_id;
 212         struct cdns_uart *cdns_uart = port->private_data;
 213         unsigned int data;
 214         unsigned int rxbs_status = 0;
 215         unsigned int status_mask;
 216         unsigned int framerrprocessed = 0;
 217         char status = TTY_NORMAL;
 218         bool is_rxbs_support;
 219
 220         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 221
 222         while ((readl(port->membase + CDNS_UART_SR) &
 223                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 224                 if (is_rxbs_support)
 225                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 226                 data = readl(port->membase + CDNS_UART_FIFO);
 227                 port->icount.rx++;
 228                 /*
 229                  * There is no hardware break detection in Zynq, so we interpret
 230                  * framing error with all-zeros data as a break sequence.
 231                  * Most of the time, there's another non-zero byte at the
 232                  * end of the sequence.
 233                  */
 234                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 235                         if (!data) {
 236                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 237                                 framerrprocessed = 1;
 238                                 continue;
 239                         }
 240                 }
 241                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 242                         port->icount.brk++;
 243                         status = TTY_BREAK;
 244                         if (uart_handle_break(port))
 245                                 continue;
 246                 }
 247
 248                 isrstatus &= port->read_status_mask;
 249                 isrstatus &= ~port->ignore_status_mask;
 250                 status_mask = port->read_status_mask;
 251                 status_mask &= ~port->ignore_status_mask;
 252
 253                 if (data &&
 254                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 255                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 256                         port->icount.brk++;
 257                         if (uart_handle_break(port))
 258                                 continue;
 259                 }
 260
 261                 if (uart_handle_sysrq_char(port, data))
 262                         continue;
 263
 264                 if (is_rxbs_support) {
 265                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 266                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 267                                 port->icount.parity++;
 268                                 status = TTY_PARITY;
 269                         }
 270                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 271                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 272                                 port->icount.frame++;
 273                                 status = TTY_FRAME;
 274                         }
 275                 } else {
 276                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 277                                 port->icount.parity++;
 278                                 status = TTY_PARITY;
 279                         }
 280                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 281                             !framerrprocessed) {
 282                                 port->icount.frame++;
 283                                 status = TTY_FRAME;
 284                         }
 285                 }
 286                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 287                         port->icount.overrun++;
 288                         tty_insert_flip_char(&port->state->port, 0,
 289                                              TTY_OVERRUN);
 290                 }
 291                 tty_insert_flip_char(&port->state->port, data, status);
 292                 isrstatus = 0;
 293         }
 294         spin_unlock(&port->lock);
 295         tty_flip_buffer_push(&port->state->port);
 296         spin_lock(&port->lock);
 297 }
 298
 299 /**
 300  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 301  * @dev_id: Id of the UART port
 302  * Return: None
 303  */
 304 static void cdns_uart_handle_tx(void *dev_id)
 305 {
 306         struct uart_port *port = (struct uart_port *)dev_id;
 307         unsigned int numbytes;
 308
 309         if (uart_circ_empty(&port->state->xmit)) {
 310                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 311         } else {
 312                 numbytes = port->fifosize;
 313                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 314                        !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
 315                         /*
 316                          * Get the data from the UART circular buffer
 317                          * and write it to the cdns_uart's TX_FIFO
 318                          * register.
 319                          */
 320                         writel(
 321                                 port->state->xmit.buf[port->state->xmit.
 322                                 tail], port->membase + CDNS_UART_FIFO);
 323
 324                         port->icount.tx++;
 325
 326                         /*
 327                          * Adjust the tail of the UART buffer and wrap
 328                          * the buffer if it reaches limit.
 329                          */
 330                         port->state->xmit.tail =
 331                                 (port->state->xmit.tail + 1) &
 332                                         (UART_XMIT_SIZE - 1);
 333
 334                         numbytes--;
 335                 }
 336
 337                 if (uart_circ_chars_pending(
 338                                 &port->state->xmit) < WAKEUP_CHARS)
 339                         uart_write_wakeup(port);
 340         }
 341 }
 342
 343 /**
 344  * cdns_uart_isr - Interrupt handler
 345  * @irq: Irq number
 346  * @dev_id: Id of the port
 347  *
 348  * Return: IRQHANDLED
 349  */
 350 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 351 {
 352         struct uart_port *port = (struct uart_port *)dev_id;
 353         unsigned int isrstatus;
 354
 355         spin_lock(&port->lock);
 356
 357         /* Read the interrupt status register to determine which
 358          * interrupt(s) is/are active and clear them.
 359          */
 360         isrstatus = readl(port->membase + CDNS_UART_ISR);
 361         writel(isrstatus, port->membase + CDNS_UART_ISR);
 362
 363         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 364                 cdns_uart_handle_tx(dev_id);
 365                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 366         }
 367
 368         /*
 369          * Skip RX processing if RX is disabled as RXEMPTY will never be set
 370          * as read bytes will not be removed from the FIFO.
 371          */
 372         if (isrstatus & CDNS_UART_IXR_RXMASK &&
 373             !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
 374                 cdns_uart_handle_rx(dev_id, isrstatus);
 375
 376         spin_unlock(&port->lock);
 377         return IRQ_HANDLED;
 378 }
 379
 380 /**
 381  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 382  * @clk: UART module input clock
 383  * @baud: Desired baud rate
 384  * @rbdiv: BDIV value (return value)
 385  * @rcd: CD value (return value)
 386  * @div8: Value for clk_sel bit in mod (return value)
 387  * Return: baud rate, requested baud when possible, or actual baud when there
 388  *      was too much error, zero if no valid divisors are found.
 389  *
 390  * Formula to obtain baud rate is
 391  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 392  *      input_clk = (Uart User Defined Clock or Apb Clock)
 393  *              depends on UCLKEN in MR Reg
 394  *      clk = input_clk or input_clk/8;
 395  *              depends on CLKS in MR reg
 396  *      CD and BDIV depends on values in
 397  *                      baud rate generate register
 398  *                      baud rate clock divisor register
 399  */
 400 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 401                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 402 {
 403         u32 cd, bdiv;
 404         unsigned int calc_baud;
 405         unsigned int bestbaud = 0;
 406         unsigned int bauderror;
 407         unsigned int besterror = ~0;
 408
 409         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 410                 *div8 = 1;
 411                 clk /= 8;
 412         } else {
 413                 *div8 = 0;
 414         }
 415
 416         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 417                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 418                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 419                         continue;
 420
 421                 calc_baud = clk / (cd * (bdiv + 1));
 422
 423                 if (baud > calc_baud)
 424                         bauderror = baud - calc_baud;
 425                 else
 426                         bauderror = calc_baud - baud;
 427
 428                 if (besterror > bauderror) {
 429                         *rbdiv = bdiv;
 430                         *rcd = cd;
 431                         bestbaud = calc_baud;
 432                         besterror = bauderror;
 433                 }
 434         }
 435         /* use the values when percent error is acceptable */
 436         if (((besterror * 100) / baud) < 3)
 437                 bestbaud = baud;
 438
 439         return bestbaud;
 440 }
 441
 442 /**
 443  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 444  * @port: Handle to the uart port structure
 445  * @baud: Baud rate to set
 446  * Return: baud rate, requested baud when possible, or actual baud when there
 447  *         was too much error, zero if no valid divisors are found.
 448  */
 449 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 450                 unsigned int baud)
 451 {
 452         unsigned int calc_baud;
 453         u32 cd = 0, bdiv = 0;
 454         u32 mreg;
 455         int div8;
 456         struct cdns_uart *cdns_uart = port->private_data;
 457
 458         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 459                         &div8);
 460
 461         /* Write new divisors to hardware */
 462         mreg = readl(port->membase + CDNS_UART_MR);
 463         if (div8)
 464                 mreg |= CDNS_UART_MR_CLKSEL;
 465         else
 466                 mreg &= ~CDNS_UART_MR_CLKSEL;
 467         writel(mreg, port->membase + CDNS_UART_MR);
 468         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 469         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 470         cdns_uart->baud = baud;
 471
 472         return calc_baud;
 473 }
 474
 475 #ifdef CONFIG_COMMON_CLK
 476 /**
 477  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 478  * @nb:         Notifier block
 479  * @event:      Notify event
 480  * @data:       Notifier data
 481  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 482  */
 483 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 484                 unsigned long event, void *data)
 485 {
 486         u32 ctrl_reg;
 487         struct uart_port *port;
 488         int locked = 0;
 489         struct clk_notifier_data *ndata = data;
 490         unsigned long flags = 0;
 491         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 492
 493         port = cdns_uart->port;
 494         if (port->suspended)
 495                 return NOTIFY_OK;
 496
 497         switch (event) {
 498         case PRE_RATE_CHANGE:
 499         {
 500                 u32 bdiv, cd;
 501                 int div8;
 502
 503                 /*
 504                  * Find out if current baud-rate can be achieved with new clock
 505                  * frequency.
 506                  */
 507                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 508                                         &bdiv, &cd, &div8)) {
 509                         dev_warn(port->dev, "clock rate change rejected\n");
 510                         return NOTIFY_BAD;
 511                 }
 512
 513                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 514
 515                 /* Disable the TX and RX to set baud rate */
 516                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 517                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 518                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 519
 520                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 521
 522                 return NOTIFY_OK;
 523         }
 524         case POST_RATE_CHANGE:
 525                 /*
 526                  * Set clk dividers to generate correct baud with new clock
 527                  * frequency.
 528                  */
 529
 530                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 531
 532                 locked = 1;
 533                 port->uartclk = ndata->new_rate;
 534
 535                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 536                                 cdns_uart->baud);
 537                 /* fall through */
 538         case ABORT_RATE_CHANGE:
 539                 if (!locked)
 540                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 541
 542                 /* Set TX/RX Reset */
 543                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 544                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 545                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 546
 547                 while (readl(port->membase + CDNS_UART_CR) &
 548                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 549                         cpu_relax();
 550
 551                 /*
 552                  * Clear the RX disable and TX disable bits and then set the TX
 553                  * enable bit and RX enable bit to enable the transmitter and
 554                  * receiver.
 555                  */
 556                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 557                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 558                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 559                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 560                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 561
 562                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 563
 564                 return NOTIFY_OK;
 565         default:
 566                 return NOTIFY_DONE;
 567         }
 568 }
 569 #endif
 570
 571 /**
 572  * cdns_uart_start_tx -  Start transmitting bytes
 573  * @port: Handle to the uart port structure
 574  */
 575 static void cdns_uart_start_tx(struct uart_port *port)
 576 {
 577         unsigned int status;
 578
 579         if (uart_tx_stopped(port))
 580                 return;
 581
 582         /*
 583          * Set the TX enable bit and clear the TX disable bit to enable the
 584          * transmitter.
 585          */
 586         status = readl(port->membase + CDNS_UART_CR);
 587         status &= ~CDNS_UART_CR_TX_DIS;
 588         status |= CDNS_UART_CR_TX_EN;
 589         writel(status, port->membase + CDNS_UART_CR);
 590
 591         if (uart_circ_empty(&port->state->xmit))
 592                 return;
 593
 594         cdns_uart_handle_tx(port);
 595
 596         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 597         /* Enable the TX Empty interrupt */
 598         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 599 }
 600
 601 /**
 602  * cdns_uart_stop_tx - Stop TX
 603  * @port: Handle to the uart port structure
 604  */
 605 static void cdns_uart_stop_tx(struct uart_port *port)
 606 {
 607         unsigned int regval;
 608
 609         regval = readl(port->membase + CDNS_UART_CR);
 610         regval |= CDNS_UART_CR_TX_DIS;
 611         /* Disable the transmitter */
 612         writel(regval, port->membase + CDNS_UART_CR);
 613 }
 614
 615 /**
 616  * cdns_uart_stop_rx - Stop RX
 617  * @port: Handle to the uart port structure
 618  */
 619 static void cdns_uart_stop_rx(struct uart_port *port)
 620 {
 621         unsigned int regval;
 622
 623         /* Disable RX IRQs */
 624         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 625
 626         /* Disable the receiver */
 627         regval = readl(port->membase + CDNS_UART_CR);
 628         regval |= CDNS_UART_CR_RX_DIS;
 629         writel(regval, port->membase + CDNS_UART_CR);
 630 }
 631
 632 /**
 633  * cdns_uart_tx_empty -  Check whether TX is empty
 634  * @port: Handle to the uart port structure
 635  *
 636  * Return: TIOCSER_TEMT on success, 0 otherwise
 637  */
 638 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 639 {
 640         unsigned int status;
 641
 642         status = readl(port->membase + CDNS_UART_SR) &
 643                                 CDNS_UART_SR_TXEMPTY;
 644         return status ? TIOCSER_TEMT : 0;
 645 }
 646
 647 /**
 648  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 649  *                      transmitting char breaks
 650  * @port: Handle to the uart port structure
 651  * @ctl: Value based on which start or stop decision is taken
 652  */
 653 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 654 {
 655         unsigned int status;
 656         unsigned long flags;
 657
 658         spin_lock_irqsave(&port->lock, flags);
 659
 660         status = readl(port->membase + CDNS_UART_CR);
 661
 662         if (ctl == -1)
 663                 writel(CDNS_UART_CR_STARTBRK | status,
 664                                 port->membase + CDNS_UART_CR);
 665         else {
 666                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 667                         writel(CDNS_UART_CR_STOPBRK | status,
 668                                         port->membase + CDNS_UART_CR);
 669         }
 670         spin_unlock_irqrestore(&port->lock, flags);
 671 }
 672
 673 /**
 674  * cdns_uart_set_termios - termios operations, handling data length, parity,
 675  *                              stop bits, flow control, baud rate
 676  * @port: Handle to the uart port structure
 677  * @termios: Handle to the input termios structure
 678  * @old: Values of the previously saved termios structure
 679  */
 680 static void cdns_uart_set_termios(struct uart_port *port,
 681                                 struct ktermios *termios, struct ktermios *old)
 682 {
 683         unsigned int cval = 0;
 684         unsigned int baud, minbaud, maxbaud;
 685         unsigned long flags;
 686         unsigned int ctrl_reg, mode_reg;
 687
 688         spin_lock_irqsave(&port->lock, flags);
 689
 690         /* Wait for the transmit FIFO to empty before making changes */
 691         if (!(readl(port->membase + CDNS_UART_CR) &
 692                                 CDNS_UART_CR_TX_DIS)) {
 693                 while (!(readl(port->membase + CDNS_UART_SR) &
 694                                 CDNS_UART_SR_TXEMPTY)) {
 695                         cpu_relax();
 696                 }
 697         }
 698
 699         /* Disable the TX and RX to set baud rate */
 700         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 701         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 702         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 703
 704         /*
 705          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 706          * min and max baud should be calculated here based on port->uartclk.
 707          * this way we get a valid baud and can safely call set_baud()
 708          */
 709         minbaud = port->uartclk /
 710                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 711         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 712         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 713         baud = cdns_uart_set_baud_rate(port, baud);
 714         if (tty_termios_baud_rate(termios))
 715                 tty_termios_encode_baud_rate(termios, baud, baud);
 716
 717         /* Update the per-port timeout. */
 718         uart_update_timeout(port, termios->c_cflag, baud);
 719
 720         /* Set TX/RX Reset */
 721         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 722         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 723         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 724
 725         while (readl(port->membase + CDNS_UART_CR) &
 726                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 727                 cpu_relax();
 728
 729         /*
 730          * Clear the RX disable and TX disable bits and then set the TX enable
 731          * bit and RX enable bit to enable the transmitter and receiver.
 732          */
 733         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 734         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 735         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 736         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 737
 738         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 739
 740         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 741                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 742         port->ignore_status_mask = 0;
 743
 744         if (termios->c_iflag & INPCK)
 745                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 746                 CDNS_UART_IXR_FRAMING;
 747
 748         if (termios->c_iflag & IGNPAR)
 749                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 750                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 751
 752         /* ignore all characters if CREAD is not set */
 753         if ((termios->c_cflag & CREAD) == 0)
 754                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 755                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 756                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 757
 758         mode_reg = readl(port->membase + CDNS_UART_MR);
 759
 760         /* Handling Data Size */
 761         switch (termios->c_cflag & CSIZE) {
 762         case CS6:
 763                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 764                 break;
 765         case CS7:
 766                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 767                 break;
 768         default:
 769         case CS8:
 770                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 771                 termios->c_cflag &= ~CSIZE;
 772                 termios->c_cflag |= CS8;
 773                 break;
 774         }
 775
 776         /* Handling Parity and Stop Bits length */
 777         if (termios->c_cflag & CSTOPB)
 778                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 779         else
 780                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 781
 782         if (termios->c_cflag & PARENB) {
 783                 /* Mark or Space parity */
 784                 if (termios->c_cflag & CMSPAR) {
 785                         if (termios->c_cflag & PARODD)
 786                                 cval |= CDNS_UART_MR_PARITY_MARK;
 787                         else
 788                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 789                 } else {
 790                         if (termios->c_cflag & PARODD)
 791                                 cval |= CDNS_UART_MR_PARITY_ODD;
 792                         else
 793                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 794                 }
 795         } else {
 796                 cval |= CDNS_UART_MR_PARITY_NONE;
 797         }
 798         cval |= mode_reg & 1;
 799         writel(cval, port->membase + CDNS_UART_MR);
 800
 801         spin_unlock_irqrestore(&port->lock, flags);
 802 }
 803
 804 /**
 805  * cdns_uart_startup - Called when an application opens a cdns_uart port
 806  * @port: Handle to the uart port structure
 807  *
 808  * Return: 0 on success, negative errno otherwise
 809  */
 810 static int cdns_uart_startup(struct uart_port *port)
 811 {
 812         struct cdns_uart *cdns_uart = port->private_data;
 813         bool is_brk_support;
 814         int ret;
 815         unsigned long flags;
 816         unsigned int status = 0;
 817
 818         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 819
 820         spin_lock_irqsave(&port->lock, flags);
 821
 822         /* Disable the TX and RX */
 823         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 824                         port->membase + CDNS_UART_CR);
 825
 826         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 827          * no break chars.
 828          */
 829         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 830                         port->membase + CDNS_UART_CR);
 831
 832         while (readl(port->membase + CDNS_UART_CR) &
 833                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 834                 cpu_relax();
 835
 836         /*
 837          * Clear the RX disable bit and then set the RX enable bit to enable
 838          * the receiver.
 839          */
 840         status = readl(port->membase + CDNS_UART_CR);
 841         status &= ~CDNS_UART_CR_RX_DIS;
 842         status |= CDNS_UART_CR_RX_EN;
 843         writel(status, port->membase + CDNS_UART_CR);
 844
 845         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 846          * no parity.
 847          */
 848         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 849                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 850                 port->membase + CDNS_UART_MR);
 851
 852         /*
 853          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 854          * can be tuned with a module parameter
 855          */
 856         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 857
 858         /*
 859          * Receive Timeout register is enabled but it
 860          * can be tuned with a module parameter
 861          */
 862         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 863
 864         /* Clear out any pending interrupts before enabling them */
 865         writel(readl(port->membase + CDNS_UART_ISR),
 866                         port->membase + CDNS_UART_ISR);
 867
 868         spin_unlock_irqrestore(&port->lock, flags);
 869
 870         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 871         if (ret) {
 872                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 873                         port->irq, ret);
 874                 return ret;
 875         }
 876
 877         /* Set the Interrupt Registers with desired interrupts */
 878         if (is_brk_support)
 879                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 880                                         port->membase + CDNS_UART_IER);
 881         else
 882                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 883
 884         return 0;
 885 }
 886
 887 /**
 888  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 889  * @port: Handle to the uart port structure
 890  */
 891 static void cdns_uart_shutdown(struct uart_port *port)
 892 {
 893         int status;
 894         unsigned long flags;
 895
 896         spin_lock_irqsave(&port->lock, flags);
 897
 898         /* Disable interrupts */
 899         status = readl(port->membase + CDNS_UART_IMR);
 900         writel(status, port->membase + CDNS_UART_IDR);
 901         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 902
 903         /* Disable the TX and RX */
 904         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 905                         port->membase + CDNS_UART_CR);
 906
 907         spin_unlock_irqrestore(&port->lock, flags);
 908
 909         free_irq(port->irq, port);
 910 }
 911
 912 /**
 913  * cdns_uart_type - Set UART type to cdns_uart port
 914  * @port: Handle to the uart port structure
 915  *
 916  * Return: string on success, NULL otherwise
 917  */
 918 static const char *cdns_uart_type(struct uart_port *port)
 919 {
 920         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 921 }
 922
 923 /**
 924  * cdns_uart_verify_port - Verify the port params
 925  * @port: Handle to the uart port structure
 926  * @ser: Handle to the structure whose members are compared
 927  *
 928  * Return: 0 on success, negative errno otherwise.
 929  */
 930 static int cdns_uart_verify_port(struct uart_port *port,
 931                                         struct serial_struct *ser)
 932 {
 933         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 934                 return -EINVAL;
 935         if (port->irq != ser->irq)
 936                 return -EINVAL;
 937         if (ser->io_type != UPIO_MEM)
 938                 return -EINVAL;
 939         if (port->iobase != ser->port)
 940                 return -EINVAL;
 941         if (ser->hub6 != 0)
 942                 return -EINVAL;
 943         return 0;
 944 }
 945
 946 /**
 947  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 948  *                              called when the driver adds a cdns_uart port via
 949  *                              uart_add_one_port()
 950  * @port: Handle to the uart port structure
 951  *
 952  * Return: 0 on success, negative errno otherwise.
 953  */
 954 static int cdns_uart_request_port(struct uart_port *port)
 955 {
 956         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 957                                          CDNS_UART_NAME)) {
 958                 return -ENOMEM;
 959         }
 960
 961         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 962         if (!port->membase) {
 963                 dev_err(port->dev, "Unable to map registers\n");
 964                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 965                 return -ENOMEM;
 966         }
 967         return 0;
 968 }
 969
 970 /**
 971  * cdns_uart_release_port - Release UART port
 972  * @port: Handle to the uart port structure
 973  *
 974  * Release the memory region attached to a cdns_uart port. Called when the
 975  * driver removes a cdns_uart port via uart_remove_one_port().
 976  */
 977 static void cdns_uart_release_port(struct uart_port *port)
 978 {
 979         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 980         iounmap(port->membase);
 981         port->membase = NULL;
 982 }
 983
 984 /**
 985  * cdns_uart_config_port - Configure UART port
 986  * @port: Handle to the uart port structure
 987  * @flags: If any
 988  */
 989 static void cdns_uart_config_port(struct uart_port *port, int flags)
 990 {
 991         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
 992                 port->type = PORT_XUARTPS;
 993 }
 994
 995 /**
 996  * cdns_uart_get_mctrl - Get the modem control state
 997  * @port: Handle to the uart port structure
 998  *
 999  * Return: the modem control state
1000  */
1001 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1002 {
1003         return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1004 }
1005
1006 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1007 {
1008         u32 val;
1009         u32 mode_reg;
1010
1011         val = readl(port->membase + CDNS_UART_MODEMCR);
1012         mode_reg = readl(port->membase + CDNS_UART_MR);
1013
1014         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1015                  CDNS_UART_MODEMCR_FCM);
1016         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1017
1018         if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1019                 val |= CDNS_UART_MODEMCR_FCM;
1020         if (mctrl & TIOCM_LOOP)
1021                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1022         else
1023                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1024
1025         writel(val, port->membase + CDNS_UART_MODEMCR);
1026         writel(mode_reg, port->membase + CDNS_UART_MR);
1027 }
1028
1029 #ifdef CONFIG_CONSOLE_POLL
1030 static int cdns_uart_poll_get_char(struct uart_port *port)
1031 {
1032         int c;
1033         unsigned long flags;
1034
1035         spin_lock_irqsave(&port->lock, flags);
1036
1037         /* Check if FIFO is empty */
1038         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1039                 c = NO_POLL_CHAR;
1040         else /* Read a character */
1041                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1042
1043         spin_unlock_irqrestore(&port->lock, flags);
1044
1045         return c;
1046 }
1047
1048 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1049 {
1050         unsigned long flags;
1051
1052         spin_lock_irqsave(&port->lock, flags);
1053
1054         /* Wait until FIFO is empty */
1055         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1056                 cpu_relax();
1057
1058         /* Write a character */
1059         writel(c, port->membase + CDNS_UART_FIFO);
1060
1061         /* Wait until FIFO is empty */
1062         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1063                 cpu_relax();
1064
1065         spin_unlock_irqrestore(&port->lock, flags);
1066
1067         return;
1068 }
1069 #endif
1070
1071 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1072                    unsigned int oldstate)
1073 {
1074         switch (state) {
1075         case UART_PM_STATE_OFF:
1076                 pm_runtime_mark_last_busy(port->dev);
1077                 pm_runtime_put_autosuspend(port->dev);
1078                 break;
1079         default:
1080                 pm_runtime_get_sync(port->dev);
1081                 break;
1082         }
1083 }
1084
1085 static const struct uart_ops cdns_uart_ops = {
1086         .set_mctrl      = cdns_uart_set_mctrl,
1087         .get_mctrl      = cdns_uart_get_mctrl,
1088         .start_tx       = cdns_uart_start_tx,
1089         .stop_tx        = cdns_uart_stop_tx,
1090         .stop_rx        = cdns_uart_stop_rx,
1091         .tx_empty       = cdns_uart_tx_empty,
1092         .break_ctl      = cdns_uart_break_ctl,
1093         .set_termios    = cdns_uart_set_termios,
1094         .startup        = cdns_uart_startup,
1095         .shutdown       = cdns_uart_shutdown,
1096         .pm             = cdns_uart_pm,
1097         .type           = cdns_uart_type,
1098         .verify_port    = cdns_uart_verify_port,
1099         .request_port   = cdns_uart_request_port,
1100         .release_port   = cdns_uart_release_port,
1101         .config_port    = cdns_uart_config_port,
1102 #ifdef CONFIG_CONSOLE_POLL
1103         .poll_get_char  = cdns_uart_poll_get_char,
1104         .poll_put_char  = cdns_uart_poll_put_char,
1105 #endif
1106 };
1107
1108 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1109 /**
1110  * cdns_uart_console_putchar - write the character to the FIFO buffer
1111  * @port: Handle to the uart port structure
1112  * @ch: Character to be written
1113  */
1114 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1115 {
1116         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1117                 cpu_relax();
1118         writel(ch, port->membase + CDNS_UART_FIFO);
1119 }
1120
1121 static void cdns_early_write(struct console *con, const char *s,
1122                                     unsigned n)
1123 {
1124         struct earlycon_device *dev = con->data;
1125
1126         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1127 }
1128
1129 static int __init cdns_early_console_setup(struct earlycon_device *device,
1130                                            const char *opt)
1131 {
1132         struct uart_port *port = &device->port;
1133
1134         if (!port->membase)
1135                 return -ENODEV;
1136
1137         /* initialise control register */
1138         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1139                port->membase + CDNS_UART_CR);
1140
1141         /* only set baud if specified on command line - otherwise
1142          * assume it has been initialized by a boot loader.
1143          */
1144         if (port->uartclk && device->baud) {
1145                 u32 cd = 0, bdiv = 0;
1146                 u32 mr;
1147                 int div8;
1148
1149                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1150                                          &bdiv, &cd, &div8);
1151                 mr = CDNS_UART_MR_PARITY_NONE;
1152                 if (div8)
1153                         mr |= CDNS_UART_MR_CLKSEL;
1154
1155                 writel(mr,   port->membase + CDNS_UART_MR);
1156                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1157                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1158         }
1159
1160         device->con->write = cdns_early_write;
1161
1162         return 0;
1163 }
1164 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1165 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1166 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1167 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1168
1169
1170 /* Static pointer to console port */
1171 static struct uart_port *console_port;
1172
1173 /**
1174  * cdns_uart_console_write - perform write operation
1175  * @co: Console handle
1176  * @s: Pointer to character array
1177  * @count: No of characters
1178  */
1179 static void cdns_uart_console_write(struct console *co, const char *s,
1180                                 unsigned int count)
1181 {
1182         struct uart_port *port = console_port;
1183         unsigned long flags;
1184         unsigned int imr, ctrl;
1185         int locked = 1;
1186
1187         if (port->sysrq)
1188                 locked = 0;
1189         else if (oops_in_progress)
1190                 locked = spin_trylock_irqsave(&port->lock, flags);
1191         else
1192                 spin_lock_irqsave(&port->lock, flags);
1193
1194         /* save and disable interrupt */
1195         imr = readl(port->membase + CDNS_UART_IMR);
1196         writel(imr, port->membase + CDNS_UART_IDR);
1197
1198         /*
1199          * Make sure that the tx part is enabled. Set the TX enable bit and
1200          * clear the TX disable bit to enable the transmitter.
1201          */
1202         ctrl = readl(port->membase + CDNS_UART_CR);
1203         ctrl &= ~CDNS_UART_CR_TX_DIS;
1204         ctrl |= CDNS_UART_CR_TX_EN;
1205         writel(ctrl, port->membase + CDNS_UART_CR);
1206
1207         uart_console_write(port, s, count, cdns_uart_console_putchar);
1208         while ((readl(port->membase + CDNS_UART_SR) &
1209                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1210                         CDNS_UART_SR_TXEMPTY)
1211                 cpu_relax();
1212
1213         /* restore interrupt state */
1214         writel(imr, port->membase + CDNS_UART_IER);
1215
1216         if (locked)
1217                 spin_unlock_irqrestore(&port->lock, flags);
1218 }
1219
1220 /**
1221  * cdns_uart_console_setup - Initialize the uart to default config
1222  * @co: Console handle
1223  * @options: Initial settings of uart
1224  *
1225  * Return: 0 on success, negative errno otherwise.
1226  */
1227 static int cdns_uart_console_setup(struct console *co, char *options)
1228 {
1229         struct uart_port *port = console_port;
1230
1231         int baud = 9600;
1232         int bits = 8;
1233         int parity = 'n';
1234         int flow = 'n';
1235
1236         if (!port->membase) {
1237                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1238                          co->index);
1239                 return -ENODEV;
1240         }
1241
1242         if (options)
1243                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1244
1245         return uart_set_options(port, co, baud, parity, bits, flow);
1246 }
1247 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1248
1249 #ifdef CONFIG_PM_SLEEP
1250 /**
1251  * cdns_uart_suspend - suspend event
1252  * @device: Pointer to the device structure
1253  *
1254  * Return: 0
1255  */
1256 static int cdns_uart_suspend(struct device *device)
1257 {
1258         struct uart_port *port = dev_get_drvdata(device);
1259         struct cdns_uart *cdns_uart = port->private_data;
1260         int may_wake;
1261
1262         may_wake = device_may_wakeup(device);
1263
1264         if (console_suspend_enabled && uart_console(port) && may_wake) {
1265                 unsigned long flags = 0;
1266
1267                 spin_lock_irqsave(&port->lock, flags);
1268                 /* Empty the receive FIFO 1st before making changes */
1269                 while (!(readl(port->membase + CDNS_UART_SR) &
1270                                         CDNS_UART_SR_RXEMPTY))
1271                         readl(port->membase + CDNS_UART_FIFO);
1272                 /* set RX trigger level to 1 */
1273                 writel(1, port->membase + CDNS_UART_RXWM);
1274                 /* disable RX timeout interrups */
1275                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1276                 spin_unlock_irqrestore(&port->lock, flags);
1277         }
1278
1279         /*
1280          * Call the API provided in serial_core.c file which handles
1281          * the suspend.
1282          */
1283         return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1284 }
1285
1286 /**
1287  * cdns_uart_resume - Resume after a previous suspend
1288  * @device: Pointer to the device structure
1289  *
1290  * Return: 0
1291  */
1292 static int cdns_uart_resume(struct device *device)
1293 {
1294         struct uart_port *port = dev_get_drvdata(device);
1295         struct cdns_uart *cdns_uart = port->private_data;
1296         unsigned long flags = 0;
1297         u32 ctrl_reg;
1298         int may_wake;
1299
1300         may_wake = device_may_wakeup(device);
1301
1302         if (console_suspend_enabled && uart_console(port) && !may_wake) {
1303                 clk_enable(cdns_uart->pclk);
1304                 clk_enable(cdns_uart->uartclk);
1305
1306                 spin_lock_irqsave(&port->lock, flags);
1307
1308                 /* Set TX/RX Reset */
1309                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1310                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1311                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1312                 while (readl(port->membase + CDNS_UART_CR) &
1313                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1314                         cpu_relax();
1315
1316                 /* restore rx timeout value */
1317                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1318                 /* Enable Tx/Rx */
1319                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1320                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1321                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1322                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1323
1324                 clk_disable(cdns_uart->uartclk);
1325                 clk_disable(cdns_uart->pclk);
1326                 spin_unlock_irqrestore(&port->lock, flags);
1327         } else {
1328                 spin_lock_irqsave(&port->lock, flags);
1329                 /* restore original rx trigger level */
1330                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1331                 /* enable RX timeout interrupt */
1332                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1333                 spin_unlock_irqrestore(&port->lock, flags);
1334         }
1335
1336         return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1337 }
1338 #endif /* ! CONFIG_PM_SLEEP */
1339 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1340 {
1341         struct uart_port *port = dev_get_drvdata(dev);
1342         struct cdns_uart *cdns_uart = port->private_data;
1343
1344         clk_disable(cdns_uart->uartclk);
1345         clk_disable(cdns_uart->pclk);
1346         return 0;
1347 };
1348
1349 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1350 {
1351         struct uart_port *port = dev_get_drvdata(dev);
1352         struct cdns_uart *cdns_uart = port->private_data;
1353
1354         clk_enable(cdns_uart->pclk);
1355         clk_enable(cdns_uart->uartclk);
1356         return 0;
1357 };
1358
1359 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1360         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1361         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1362                            cdns_runtime_resume, NULL)
1363 };
1364
1365 static const struct cdns_platform_data zynqmp_uart_def = {
1366                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1367
1368 /* Match table for of_platform binding */
1369 static const struct of_device_id cdns_uart_of_match[] = {
1370         { .compatible = "xlnx,xuartps", },
1371         { .compatible = "cdns,uart-r1p8", },
1372         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1373         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1374         {}
1375 };
1376 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1377
1378 /*
1379  * Maximum number of instances without alias IDs but if there is alias
1380  * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1381  */
1382 #define MAX_UART_INSTANCES      32
1383
1384 /* Stores static aliases list */
1385 static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1386 static int alias_bitmap_initialized;
1387
1388 /* Stores actual bitmap of allocated IDs with alias IDs together */
1389 static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1390 /* Protect bitmap operations to have unique IDs */
1391 static DEFINE_MUTEX(bitmap_lock);
1392
1393 static int cdns_get_id(struct platform_device *pdev)
1394 {
1395         int id, ret;
1396
1397         mutex_lock(&bitmap_lock);
1398
1399         /* Alias list is stable that's why get alias bitmap only once */
1400         if (!alias_bitmap_initialized) {
1401                 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1402                                               alias_bitmap, MAX_UART_INSTANCES);
1403                 if (ret && ret != -EOVERFLOW) {
1404                         mutex_unlock(&bitmap_lock);
1405                         return ret;
1406                 }
1407
1408                 alias_bitmap_initialized++;
1409         }
1410
1411         /* Make sure that alias ID is not taken by instance without alias */
1412         bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1413
1414         dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1415                 MAX_UART_INSTANCES, bitmap);
1416
1417         /* Look for a serialN alias */
1418         id = of_alias_get_id(pdev->dev.of_node, "serial");
1419         if (id < 0) {
1420                 dev_warn(&pdev->dev,
1421                          "No serial alias passed. Using the first free id\n");
1422
1423                 /*
1424                  * Start with id 0 and check if there is no serial0 alias
1425                  * which points to device which is compatible with this driver.
1426                  * If alias exists then try next free position.
1427                  */
1428                 id = 0;
1429
1430                 for (;;) {
1431                         dev_info(&pdev->dev, "Checking id %d\n", id);
1432                         id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1433
1434                         /* No free empty instance */
1435                         if (id == MAX_UART_INSTANCES) {
1436                                 dev_err(&pdev->dev, "No free ID\n");
1437                                 mutex_unlock(&bitmap_lock);
1438                                 return -EINVAL;
1439                         }
1440
1441                         dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1442                         /* Check if ID is empty */
1443                         if (!test_and_set_bit(id, bitmap)) {
1444                                 /* Break the loop if bit is taken */
1445                                 dev_dbg(&pdev->dev,
1446                                         "Selected ID %d allocation passed\n",
1447                                         id);
1448                                 break;
1449                         }
1450                         dev_dbg(&pdev->dev,
1451                                 "Selected ID %d allocation failed\n", id);
1452                         /* if taking bit fails then try next one */
1453                         id++;
1454                 }
1455         }
1456
1457         mutex_unlock(&bitmap_lock);
1458
1459         return id;
1460 }
1461
1462 /**
1463  * cdns_uart_probe - Platform driver probe
1464  * @pdev: Pointer to the platform device structure
1465  *
1466  * Return: 0 on success, negative errno otherwise
1467  */
1468 static int cdns_uart_probe(struct platform_device *pdev)
1469 {
1470         int rc, irq;
1471         struct uart_port *port;
1472         struct resource *res;
1473         struct cdns_uart *cdns_uart_data;
1474         const struct of_device_id *match;
1475         struct uart_driver *cdns_uart_uart_driver;
1476         char *driver_name;
1477 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1478         struct console *cdns_uart_console;
1479 #endif
1480
1481         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1482                         GFP_KERNEL);
1483         if (!cdns_uart_data)
1484                 return -ENOMEM;
1485         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1486         if (!port)
1487                 return -ENOMEM;
1488
1489         cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1490                                              sizeof(*cdns_uart_uart_driver),
1491                                              GFP_KERNEL);
1492         if (!cdns_uart_uart_driver)
1493                 return -ENOMEM;
1494
1495         cdns_uart_data->id = cdns_get_id(pdev);
1496         if (cdns_uart_data->id < 0)
1497                 return cdns_uart_data->id;
1498
1499         /* There is a need to use unique driver name */
1500         driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1501                                      CDNS_UART_NAME, cdns_uart_data->id);
1502         if (!driver_name) {
1503                 rc = -ENOMEM;
1504                 goto err_out_id;
1505         }
1506
1507         cdns_uart_uart_driver->owner = THIS_MODULE;
1508         cdns_uart_uart_driver->driver_name = driver_name;
1509         cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1510         cdns_uart_uart_driver->major = CDNS_UART_MAJOR;
1511         cdns_uart_uart_driver->minor = cdns_uart_data->id;
1512         cdns_uart_uart_driver->nr = 1;
1513
1514 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1515         cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1516                                          GFP_KERNEL);
1517         if (!cdns_uart_console) {
1518                 rc = -ENOMEM;
1519                 goto err_out_id;
1520         }
1521
1522         strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1523                 sizeof(cdns_uart_console->name));
1524         cdns_uart_console->index = cdns_uart_data->id;
1525         cdns_uart_console->write = cdns_uart_console_write;
1526         cdns_uart_console->device = uart_console_device;
1527         cdns_uart_console->setup = cdns_uart_console_setup;
1528         cdns_uart_console->flags = CON_PRINTBUFFER;
1529         cdns_uart_console->data = cdns_uart_uart_driver;
1530         cdns_uart_uart_driver->cons = cdns_uart_console;
1531 #endif
1532
1533         rc = uart_register_driver(cdns_uart_uart_driver);
1534         if (rc < 0) {
1535                 dev_err(&pdev->dev, "Failed to register driver\n");
1536                 goto err_out_id;
1537         }
1538
1539         cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1540
1541         /*
1542          * Setting up proper name_base needs to be done after uart
1543          * registration because tty_driver structure is not filled.
1544          * name_base is 0 by default.
1545          */
1546         cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1547
1548         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1549         if (match && match->data) {
1550                 const struct cdns_platform_data *data = match->data;
1551
1552                 cdns_uart_data->quirks = data->quirks;
1553         }
1554
1555         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1556         if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1557                 rc = PTR_ERR(cdns_uart_data->pclk);
1558                 goto err_out_unregister_driver;
1559         }
1560
1561         if (IS_ERR(cdns_uart_data->pclk)) {
1562                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1563                 if (IS_ERR(cdns_uart_data->pclk)) {
1564                         rc = PTR_ERR(cdns_uart_data->pclk);
1565                         goto err_out_unregister_driver;
1566                 }
1567                 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1568         }
1569
1570         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1571         if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1572                 rc = PTR_ERR(cdns_uart_data->uartclk);
1573                 goto err_out_unregister_driver;
1574         }
1575
1576         if (IS_ERR(cdns_uart_data->uartclk)) {
1577                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1578                 if (IS_ERR(cdns_uart_data->uartclk)) {
1579                         rc = PTR_ERR(cdns_uart_data->uartclk);
1580                         goto err_out_unregister_driver;
1581                 }
1582                 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1583         }
1584
1585         rc = clk_prepare_enable(cdns_uart_data->pclk);
1586         if (rc) {
1587                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1588                 goto err_out_unregister_driver;
1589         }
1590         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1591         if (rc) {
1592                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1593                 goto err_out_clk_dis_pclk;
1594         }
1595
1596         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1597         if (!res) {
1598                 rc = -ENODEV;
1599                 goto err_out_clk_disable;
1600         }
1601
1602         irq = platform_get_irq(pdev, 0);
1603         if (irq <= 0) {
1604                 rc = -ENXIO;
1605                 goto err_out_clk_disable;
1606         }
1607
1608 #ifdef CONFIG_COMMON_CLK
1609         cdns_uart_data->clk_rate_change_nb.notifier_call =
1610                         cdns_uart_clk_notifier_cb;
1611         if (clk_notifier_register(cdns_uart_data->uartclk,
1612                                 &cdns_uart_data->clk_rate_change_nb))
1613                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1614 #endif
1615
1616         /* At this point, we've got an empty uart_port struct, initialize it */
1617         spin_lock_init(&port->lock);
1618         port->type      = PORT_UNKNOWN;
1619         port->iotype    = UPIO_MEM32;
1620         port->flags     = UPF_BOOT_AUTOCONF;
1621         port->ops       = &cdns_uart_ops;
1622         port->fifosize  = CDNS_UART_FIFO_SIZE;
1623
1624         /*
1625          * Register the port.
1626          * This function also registers this device with the tty layer
1627          * and triggers invocation of the config_port() entry point.
1628          */
1629         port->mapbase = res->start;
1630         port->irq = irq;
1631         port->dev = &pdev->dev;
1632         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1633         port->private_data = cdns_uart_data;
1634         cdns_uart_data->port = port;
1635         platform_set_drvdata(pdev, port);
1636
1637         pm_runtime_use_autosuspend(&pdev->dev);
1638         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1639         pm_runtime_set_active(&pdev->dev);
1640         pm_runtime_enable(&pdev->dev);
1641         device_init_wakeup(port->dev, true);
1642
1643 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1644         /*
1645          * If console hasn't been found yet try to assign this port
1646          * because it is required to be assigned for console setup function.
1647          * If register_console() don't assign value, then console_port pointer
1648          * is cleanup.
1649          */
1650         if (!console_port)
1651                 console_port = port;
1652 #endif
1653
1654         rc = uart_add_one_port(cdns_uart_uart_driver, port);
1655         if (rc) {
1656                 dev_err(&pdev->dev,
1657                         "uart_add_one_port() failed; err=%i\n", rc);
1658                 goto err_out_pm_disable;
1659         }
1660
1661 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1662         /* This is not port which is used for console that's why clean it up */
1663         if (console_port == port &&
1664             !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1665                 console_port = NULL;
1666 #endif
1667
1668         return 0;
1669
1670 err_out_pm_disable:
1671         pm_runtime_disable(&pdev->dev);
1672         pm_runtime_set_suspended(&pdev->dev);
1673         pm_runtime_dont_use_autosuspend(&pdev->dev);
1674 #ifdef CONFIG_COMMON_CLK
1675         clk_notifier_unregister(cdns_uart_data->uartclk,
1676                         &cdns_uart_data->clk_rate_change_nb);
1677 #endif
1678 err_out_clk_disable:
1679         clk_disable_unprepare(cdns_uart_data->uartclk);
1680 err_out_clk_dis_pclk:
1681         clk_disable_unprepare(cdns_uart_data->pclk);
1682 err_out_unregister_driver:
1683         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1684 err_out_id:
1685         mutex_lock(&bitmap_lock);
1686         if (cdns_uart_data->id < MAX_UART_INSTANCES)
1687                 clear_bit(cdns_uart_data->id, bitmap);
1688         mutex_unlock(&bitmap_lock);
1689         return rc;
1690 }
1691
1692 /**
1693  * cdns_uart_remove - called when the platform driver is unregistered
1694  * @pdev: Pointer to the platform device structure
1695  *
1696  * Return: 0 on success, negative errno otherwise
1697  */
1698 static int cdns_uart_remove(struct platform_device *pdev)
1699 {
1700         struct uart_port *port = platform_get_drvdata(pdev);
1701         struct cdns_uart *cdns_uart_data = port->private_data;
1702         int rc;
1703
1704         /* Remove the cdns_uart port from the serial core */
1705 #ifdef CONFIG_COMMON_CLK
1706         clk_notifier_unregister(cdns_uart_data->uartclk,
1707                         &cdns_uart_data->clk_rate_change_nb);
1708 #endif
1709         rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1710         port->mapbase = 0;
1711         mutex_lock(&bitmap_lock);
1712         if (cdns_uart_data->id < MAX_UART_INSTANCES)
1713                 clear_bit(cdns_uart_data->id, bitmap);
1714         mutex_unlock(&bitmap_lock);
1715         clk_disable_unprepare(cdns_uart_data->uartclk);
1716         clk_disable_unprepare(cdns_uart_data->pclk);
1717         pm_runtime_disable(&pdev->dev);
1718         pm_runtime_set_suspended(&pdev->dev);
1719         pm_runtime_dont_use_autosuspend(&pdev->dev);
1720         device_init_wakeup(&pdev->dev, false);
1721
1722 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1723         if (console_port == port)
1724                 console_port = NULL;
1725 #endif
1726
1727         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1728         return rc;
1729 }
1730
1731 static struct platform_driver cdns_uart_platform_driver = {
1732         .probe   = cdns_uart_probe,
1733         .remove  = cdns_uart_remove,
1734         .driver  = {
1735                 .name = CDNS_UART_NAME,
1736                 .of_match_table = cdns_uart_of_match,
1737                 .pm = &cdns_uart_dev_pm_ops,
1738                 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1739                 },
1740 };
1741
1742 static int __init cdns_uart_init(void)
1743 {
1744         /* Register the platform driver */
1745         return platform_driver_register(&cdns_uart_platform_driver);
1746 }
1747
1748 static void __exit cdns_uart_exit(void)
1749 {
1750         /* Unregister the platform driver */
1751         platform_driver_unregister(&cdns_uart_platform_driver);
1752 }
1753
1754 arch_initcall(cdns_uart_init);
1755 module_exit(cdns_uart_exit);
1756
1757 MODULE_DESCRIPTION("Driver for Cadence UART");
1758 MODULE_AUTHOR("Xilinx Inc.");
1759 MODULE_LICENSE("GPL");