drivers/tty/serial/xilinx_uartps.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Cadence UART driver (found in Xilinx Zynq)
   4  *
   5  * 2011 - 2014 (C) Xilinx Inc.
   6  *
   7  * This driver has originally been pushed by Xilinx using a Zynq-branding. This
   8  * still shows in the naming of this file, the kconfig symbols and some symbols
   9  * in the code.
  10  */
  11
  12 #include <linux/platform_device.h>
  13 #include <linux/serial.h>
  14 #include <linux/console.h>
  15 #include <linux/serial_core.h>
  16 #include <linux/slab.h>
  17 #include <linux/tty.h>
  18 #include <linux/tty_flip.h>
  19 #include <linux/clk.h>
  20 #include <linux/irq.h>
  21 #include <linux/io.h>
  22 #include <linux/of.h>
  23 #include <linux/module.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/iopoll.h>
  26
  27 #define CDNS_UART_TTY_NAME      "ttyPS"
  28 #define CDNS_UART_NAME          "xuartps"
  29 #define CDNS_UART_FIFO_SIZE     64      /* FIFO size */
  30 #define CDNS_UART_REGISTER_SPACE        0x1000
  31 #define TX_TIMEOUT              500000
  32
  33 /* Rx Trigger level */
  34 static int rx_trigger_level = 56;
  35 static int uartps_major;
  36 module_param(rx_trigger_level, uint, 0444);
  37 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
  38
  39 /* Rx Timeout */
  40 static int rx_timeout = 10;
  41 module_param(rx_timeout, uint, 0444);
  42 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  43
  44 /* Register offsets for the UART. */
  45 #define CDNS_UART_CR            0x00  /* Control Register */
  46 #define CDNS_UART_MR            0x04  /* Mode Register */
  47 #define CDNS_UART_IER           0x08  /* Interrupt Enable */
  48 #define CDNS_UART_IDR           0x0C  /* Interrupt Disable */
  49 #define CDNS_UART_IMR           0x10  /* Interrupt Mask */
  50 #define CDNS_UART_ISR           0x14  /* Interrupt Status */
  51 #define CDNS_UART_BAUDGEN       0x18  /* Baud Rate Generator */
  52 #define CDNS_UART_RXTOUT        0x1C  /* RX Timeout */
  53 #define CDNS_UART_RXWM          0x20  /* RX FIFO Trigger Level */
  54 #define CDNS_UART_MODEMCR       0x24  /* Modem Control */
  55 #define CDNS_UART_MODEMSR       0x28  /* Modem Status */
  56 #define CDNS_UART_SR            0x2C  /* Channel Status */
  57 #define CDNS_UART_FIFO          0x30  /* FIFO */
  58 #define CDNS_UART_BAUDDIV       0x34  /* Baud Rate Divider */
  59 #define CDNS_UART_FLOWDEL       0x38  /* Flow Delay */
  60 #define CDNS_UART_IRRX_PWIDTH   0x3C  /* IR Min Received Pulse Width */
  61 #define CDNS_UART_IRTX_PWIDTH   0x40  /* IR Transmitted pulse Width */
  62 #define CDNS_UART_TXWM          0x44  /* TX FIFO Trigger Level */
  63 #define CDNS_UART_RXBS          0x48  /* RX FIFO byte status register */
  64
  65 /* Control Register Bit Definitions */
  66 #define CDNS_UART_CR_STOPBRK    0x00000100  /* Stop TX break */
  67 #define CDNS_UART_CR_STARTBRK   0x00000080  /* Set TX break */
  68 #define CDNS_UART_CR_TX_DIS     0x00000020  /* TX disabled. */
  69 #define CDNS_UART_CR_TX_EN      0x00000010  /* TX enabled */
  70 #define CDNS_UART_CR_RX_DIS     0x00000008  /* RX disabled. */
  71 #define CDNS_UART_CR_RX_EN      0x00000004  /* RX enabled */
  72 #define CDNS_UART_CR_TXRST      0x00000002  /* TX logic reset */
  73 #define CDNS_UART_CR_RXRST      0x00000001  /* RX logic reset */
  74 #define CDNS_UART_CR_RST_TO     0x00000040  /* Restart Timeout Counter */
  75 #define CDNS_UART_RXBS_PARITY    0x00000001 /* Parity error status */
  76 #define CDNS_UART_RXBS_FRAMING   0x00000002 /* Framing error status */
  77 #define CDNS_UART_RXBS_BRK       0x00000004 /* Overrun error status */
  78
  79 /*
  80  * Mode Register:
  81  * The mode register (MR) defines the mode of transfer as well as the data
  82  * format. If this register is modified during transmission or reception,
  83  * data validity cannot be guaranteed.
  84  */
  85 #define CDNS_UART_MR_CLKSEL             0x00000001  /* Pre-scalar selection */
  86 #define CDNS_UART_MR_CHMODE_L_LOOP      0x00000200  /* Local loop back mode */
  87 #define CDNS_UART_MR_CHMODE_NORM        0x00000000  /* Normal mode */
  88 #define CDNS_UART_MR_CHMODE_MASK        0x00000300  /* Mask for mode bits */
  89
  90 #define CDNS_UART_MR_STOPMODE_2_BIT     0x00000080  /* 2 stop bits */
  91 #define CDNS_UART_MR_STOPMODE_1_BIT     0x00000000  /* 1 stop bit */
  92
  93 #define CDNS_UART_MR_PARITY_NONE        0x00000020  /* No parity mode */
  94 #define CDNS_UART_MR_PARITY_MARK        0x00000018  /* Mark parity mode */
  95 #define CDNS_UART_MR_PARITY_SPACE       0x00000010  /* Space parity mode */
  96 #define CDNS_UART_MR_PARITY_ODD         0x00000008  /* Odd parity mode */
  97 #define CDNS_UART_MR_PARITY_EVEN        0x00000000  /* Even parity mode */
  98
  99 #define CDNS_UART_MR_CHARLEN_6_BIT      0x00000006  /* 6 bits data */
 100 #define CDNS_UART_MR_CHARLEN_7_BIT      0x00000004  /* 7 bits data */
 101 #define CDNS_UART_MR_CHARLEN_8_BIT      0x00000000  /* 8 bits data */
 102
 103 /*
 104  * Interrupt Registers:
 105  * Interrupt control logic uses the interrupt enable register (IER) and the
 106  * interrupt disable register (IDR) to set the value of the bits in the
 107  * interrupt mask register (IMR). The IMR determines whether to pass an
 108  * interrupt to the interrupt status register (ISR).
 109  * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
 110  * interrupt. IMR and ISR are read only, and IER and IDR are write only.
 111  * Reading either IER or IDR returns 0x00.
 112  * All four registers have the same bit definitions.
 113  */
 114 #define CDNS_UART_IXR_TOUT      0x00000100 /* RX Timeout error interrupt */
 115 #define CDNS_UART_IXR_PARITY    0x00000080 /* Parity error interrupt */
 116 #define CDNS_UART_IXR_FRAMING   0x00000040 /* Framing error interrupt */
 117 #define CDNS_UART_IXR_OVERRUN   0x00000020 /* Overrun error interrupt */
 118 #define CDNS_UART_IXR_TXFULL    0x00000010 /* TX FIFO Full interrupt */
 119 #define CDNS_UART_IXR_TXEMPTY   0x00000008 /* TX FIFO empty interrupt */
 120 #define CDNS_UART_ISR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt */
 121 #define CDNS_UART_IXR_RXTRIG    0x00000001 /* RX FIFO trigger interrupt */
 122 #define CDNS_UART_IXR_RXFULL    0x00000004 /* RX FIFO full interrupt. */
 123 #define CDNS_UART_IXR_RXEMPTY   0x00000002 /* RX FIFO empty interrupt. */
 124 #define CDNS_UART_IXR_RXMASK    0x000021e7 /* Valid RX bit mask */
 125
 126         /*
 127          * Do not enable parity error interrupt for the following
 128          * reason: When parity error interrupt is enabled, each Rx
 129          * parity error always results in 2 events. The first one
 130          * being parity error interrupt and the second one with a
 131          * proper Rx interrupt with the incoming data.  Disabling
 132          * parity error interrupt ensures better handling of parity
 133          * error events. With this change, for a parity error case, we
 134          * get a Rx interrupt with parity error set in ISR register
 135          * and we still handle parity errors in the desired way.
 136          */
 137
 138 #define CDNS_UART_RX_IRQS       (CDNS_UART_IXR_FRAMING | \
 139                                  CDNS_UART_IXR_OVERRUN | \
 140                                  CDNS_UART_IXR_RXTRIG |  \
 141                                  CDNS_UART_IXR_TOUT)
 142
 143 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
 144 #define CDNS_UART_IXR_BRK       0x00002000
 145
 146 #define CDNS_UART_RXBS_SUPPORT BIT(1)
 147 /*
 148  * Modem Control register:
 149  * The read/write Modem Control register controls the interface with the modem
 150  * or data set, or a peripheral device emulating a modem.
 151  */
 152 #define CDNS_UART_MODEMCR_FCM   0x00000020 /* Automatic flow control mode */
 153 #define CDNS_UART_MODEMCR_RTS   0x00000002 /* Request to send output control */
 154 #define CDNS_UART_MODEMCR_DTR   0x00000001 /* Data Terminal Ready */
 155
 156 /*
 157  * Modem Status register:
 158  * The read/write Modem Status register reports the interface with the modem
 159  * or data set, or a peripheral device emulating a modem.
 160  */
 161 #define CDNS_UART_MODEMSR_DCD   BIT(7) /* Data Carrier Detect */
 162 #define CDNS_UART_MODEMSR_RI    BIT(6) /* Ting Indicator */
 163 #define CDNS_UART_MODEMSR_DSR   BIT(5) /* Data Set Ready */
 164 #define CDNS_UART_MODEMSR_CTS   BIT(4) /* Clear To Send */
 165
 166 /*
 167  * Channel Status Register:
 168  * The channel status register (CSR) is provided to enable the control logic
 169  * to monitor the status of bits in the channel interrupt status register,
 170  * even if these are masked out by the interrupt mask register.
 171  */
 172 #define CDNS_UART_SR_RXEMPTY    0x00000002 /* RX FIFO empty */
 173 #define CDNS_UART_SR_TXEMPTY    0x00000008 /* TX FIFO empty */
 174 #define CDNS_UART_SR_TXFULL     0x00000010 /* TX FIFO full */
 175 #define CDNS_UART_SR_RXTRIG     0x00000001 /* Rx Trigger */
 176 #define CDNS_UART_SR_TACTIVE    0x00000800 /* TX state machine active */
 177
 178 /* baud dividers min/max values */
 179 #define CDNS_UART_BDIV_MIN      4
 180 #define CDNS_UART_BDIV_MAX      255
 181 #define CDNS_UART_CD_MAX        65535
 182 #define UART_AUTOSUSPEND_TIMEOUT        3000
 183
 184 /**
 185  * struct cdns_uart - device data
 186  * @port:               Pointer to the UART port
 187  * @uartclk:            Reference clock
 188  * @pclk:               APB clock
 189  * @cdns_uart_driver:   Pointer to UART driver
 190  * @baud:               Current baud rate
 191  * @id:                 Port ID
 192  * @clk_rate_change_nb: Notifier block for clock changes
 193  * @quirks:             Flags for RXBS support.
 194  */
 195 struct cdns_uart {
 196         struct uart_port        *port;
 197         struct clk              *uartclk;
 198         struct clk              *pclk;
 199         struct uart_driver      *cdns_uart_driver;
 200         unsigned int            baud;
 201         int                     id;
 202         struct notifier_block   clk_rate_change_nb;
 203         u32                     quirks;
 204         bool cts_override;
 205 };
 206 struct cdns_platform_data {
 207         u32 quirks;
 208 };
 209 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
 210                 clk_rate_change_nb)
 211
 212 /**
 213  * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
 214  * @dev_id: Id of the UART port
 215  * @isrstatus: The interrupt status register value as read
 216  * Return: None
 217  */
 218 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
 219 {
 220         struct uart_port *port = (struct uart_port *)dev_id;
 221         struct cdns_uart *cdns_uart = port->private_data;
 222         unsigned int data;
 223         unsigned int rxbs_status = 0;
 224         unsigned int status_mask;
 225         unsigned int framerrprocessed = 0;
 226         char status = TTY_NORMAL;
 227         bool is_rxbs_support;
 228
 229         is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 230
 231         while ((readl(port->membase + CDNS_UART_SR) &
 232                 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
 233                 if (is_rxbs_support)
 234                         rxbs_status = readl(port->membase + CDNS_UART_RXBS);
 235                 data = readl(port->membase + CDNS_UART_FIFO);
 236                 port->icount.rx++;
 237                 /*
 238                  * There is no hardware break detection in Zynq, so we interpret
 239                  * framing error with all-zeros data as a break sequence.
 240                  * Most of the time, there's another non-zero byte at the
 241                  * end of the sequence.
 242                  */
 243                 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
 244                         if (!data) {
 245                                 port->read_status_mask |= CDNS_UART_IXR_BRK;
 246                                 framerrprocessed = 1;
 247                                 continue;
 248                         }
 249                 }
 250                 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
 251                         port->icount.brk++;
 252                         status = TTY_BREAK;
 253                         if (uart_handle_break(port))
 254                                 continue;
 255                 }
 256
 257                 isrstatus &= port->read_status_mask;
 258                 isrstatus &= ~port->ignore_status_mask;
 259                 status_mask = port->read_status_mask;
 260                 status_mask &= ~port->ignore_status_mask;
 261
 262                 if (data &&
 263                     (port->read_status_mask & CDNS_UART_IXR_BRK)) {
 264                         port->read_status_mask &= ~CDNS_UART_IXR_BRK;
 265                         port->icount.brk++;
 266                         if (uart_handle_break(port))
 267                                 continue;
 268                 }
 269
 270                 if (uart_handle_sysrq_char(port, data))
 271                         continue;
 272
 273                 if (is_rxbs_support) {
 274                         if ((rxbs_status & CDNS_UART_RXBS_PARITY)
 275                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 276                                 port->icount.parity++;
 277                                 status = TTY_PARITY;
 278                         }
 279                         if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
 280                             && (status_mask & CDNS_UART_IXR_PARITY)) {
 281                                 port->icount.frame++;
 282                                 status = TTY_FRAME;
 283                         }
 284                 } else {
 285                         if (isrstatus & CDNS_UART_IXR_PARITY) {
 286                                 port->icount.parity++;
 287                                 status = TTY_PARITY;
 288                         }
 289                         if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
 290                             !framerrprocessed) {
 291                                 port->icount.frame++;
 292                                 status = TTY_FRAME;
 293                         }
 294                 }
 295                 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
 296                         port->icount.overrun++;
 297                         tty_insert_flip_char(&port->state->port, 0,
 298                                              TTY_OVERRUN);
 299                 }
 300                 tty_insert_flip_char(&port->state->port, data, status);
 301                 isrstatus = 0;
 302         }
 303         spin_unlock(&port->lock);
 304         tty_flip_buffer_push(&port->state->port);
 305         spin_lock(&port->lock);
 306 }
 307
 308 /**
 309  * cdns_uart_handle_tx - Handle the bytes to be Txed.
 310  * @dev_id: Id of the UART port
 311  * Return: None
 312  */
 313 static void cdns_uart_handle_tx(void *dev_id)
 314 {
 315         struct uart_port *port = (struct uart_port *)dev_id;
 316         unsigned int numbytes;
 317
 318         if (uart_circ_empty(&port->state->xmit)) {
 319                 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
 320         } else {
 321                 numbytes = port->fifosize;
 322                 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
 323                        !(readl(port->membase + CDNS_UART_SR) &
 324                                                 CDNS_UART_SR_TXFULL)) {
 325                         /*
 326                          * Get the data from the UART circular buffer
 327                          * and write it to the cdns_uart's TX_FIFO
 328                          * register.
 329                          */
 330                         writel(
 331                                 port->state->xmit.buf[port->state->xmit.tail],
 332                                         port->membase + CDNS_UART_FIFO);
 333
 334                         port->icount.tx++;
 335
 336                         /*
 337                          * Adjust the tail of the UART buffer and wrap
 338                          * the buffer if it reaches limit.
 339                          */
 340                         port->state->xmit.tail =
 341                                 (port->state->xmit.tail + 1) &
 342                                         (UART_XMIT_SIZE - 1);
 343
 344                         numbytes--;
 345                 }
 346
 347                 if (uart_circ_chars_pending(
 348                                 &port->state->xmit) < WAKEUP_CHARS)
 349                         uart_write_wakeup(port);
 350         }
 351 }
 352
 353 /**
 354  * cdns_uart_isr - Interrupt handler
 355  * @irq: Irq number
 356  * @dev_id: Id of the port
 357  *
 358  * Return: IRQHANDLED
 359  */
 360 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
 361 {
 362         struct uart_port *port = (struct uart_port *)dev_id;
 363         unsigned int isrstatus;
 364
 365         spin_lock(&port->lock);
 366
 367         /* Read the interrupt status register to determine which
 368          * interrupt(s) is/are active and clear them.
 369          */
 370         isrstatus = readl(port->membase + CDNS_UART_ISR);
 371         writel(isrstatus, port->membase + CDNS_UART_ISR);
 372
 373         if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
 374                 cdns_uart_handle_tx(dev_id);
 375                 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
 376         }
 377
 378         /*
 379          * Skip RX processing if RX is disabled as RXEMPTY will never be set
 380          * as read bytes will not be removed from the FIFO.
 381          */
 382         if (isrstatus & CDNS_UART_IXR_RXMASK &&
 383             !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
 384                 cdns_uart_handle_rx(dev_id, isrstatus);
 385
 386         spin_unlock(&port->lock);
 387         return IRQ_HANDLED;
 388 }
 389
 390 /**
 391  * cdns_uart_calc_baud_divs - Calculate baud rate divisors
 392  * @clk: UART module input clock
 393  * @baud: Desired baud rate
 394  * @rbdiv: BDIV value (return value)
 395  * @rcd: CD value (return value)
 396  * @div8: Value for clk_sel bit in mod (return value)
 397  * Return: baud rate, requested baud when possible, or actual baud when there
 398  *      was too much error, zero if no valid divisors are found.
 399  *
 400  * Formula to obtain baud rate is
 401  *      baud_tx/rx rate = clk/CD * (BDIV + 1)
 402  *      input_clk = (Uart User Defined Clock or Apb Clock)
 403  *              depends on UCLKEN in MR Reg
 404  *      clk = input_clk or input_clk/8;
 405  *              depends on CLKS in MR reg
 406  *      CD and BDIV depends on values in
 407  *                      baud rate generate register
 408  *                      baud rate clock divisor register
 409  */
 410 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
 411                 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
 412 {
 413         u32 cd, bdiv;
 414         unsigned int calc_baud;
 415         unsigned int bestbaud = 0;
 416         unsigned int bauderror;
 417         unsigned int besterror = ~0;
 418
 419         if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
 420                 *div8 = 1;
 421                 clk /= 8;
 422         } else {
 423                 *div8 = 0;
 424         }
 425
 426         for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
 427                 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
 428                 if (cd < 1 || cd > CDNS_UART_CD_MAX)
 429                         continue;
 430
 431                 calc_baud = clk / (cd * (bdiv + 1));
 432
 433                 if (baud > calc_baud)
 434                         bauderror = baud - calc_baud;
 435                 else
 436                         bauderror = calc_baud - baud;
 437
 438                 if (besterror > bauderror) {
 439                         *rbdiv = bdiv;
 440                         *rcd = cd;
 441                         bestbaud = calc_baud;
 442                         besterror = bauderror;
 443                 }
 444         }
 445         /* use the values when percent error is acceptable */
 446         if (((besterror * 100) / baud) < 3)
 447                 bestbaud = baud;
 448
 449         return bestbaud;
 450 }
 451
 452 /**
 453  * cdns_uart_set_baud_rate - Calculate and set the baud rate
 454  * @port: Handle to the uart port structure
 455  * @baud: Baud rate to set
 456  * Return: baud rate, requested baud when possible, or actual baud when there
 457  *         was too much error, zero if no valid divisors are found.
 458  */
 459 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
 460                 unsigned int baud)
 461 {
 462         unsigned int calc_baud;
 463         u32 cd = 0, bdiv = 0;
 464         u32 mreg;
 465         int div8;
 466         struct cdns_uart *cdns_uart = port->private_data;
 467
 468         calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
 469                         &div8);
 470
 471         /* Write new divisors to hardware */
 472         mreg = readl(port->membase + CDNS_UART_MR);
 473         if (div8)
 474                 mreg |= CDNS_UART_MR_CLKSEL;
 475         else
 476                 mreg &= ~CDNS_UART_MR_CLKSEL;
 477         writel(mreg, port->membase + CDNS_UART_MR);
 478         writel(cd, port->membase + CDNS_UART_BAUDGEN);
 479         writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
 480         cdns_uart->baud = baud;
 481
 482         return calc_baud;
 483 }
 484
 485 #ifdef CONFIG_COMMON_CLK
 486 /**
 487  * cdns_uart_clk_notitifer_cb - Clock notifier callback
 488  * @nb:         Notifier block
 489  * @event:      Notify event
 490  * @data:       Notifier data
 491  * Return:      NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
 492  */
 493 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
 494                 unsigned long event, void *data)
 495 {
 496         u32 ctrl_reg;
 497         struct uart_port *port;
 498         int locked = 0;
 499         struct clk_notifier_data *ndata = data;
 500         unsigned long flags = 0;
 501         struct cdns_uart *cdns_uart = to_cdns_uart(nb);
 502
 503         port = cdns_uart->port;
 504         if (port->suspended)
 505                 return NOTIFY_OK;
 506
 507         switch (event) {
 508         case PRE_RATE_CHANGE:
 509         {
 510                 u32 bdiv, cd;
 511                 int div8;
 512
 513                 /*
 514                  * Find out if current baud-rate can be achieved with new clock
 515                  * frequency.
 516                  */
 517                 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
 518                                         &bdiv, &cd, &div8)) {
 519                         dev_warn(port->dev, "clock rate change rejected\n");
 520                         return NOTIFY_BAD;
 521                 }
 522
 523                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 524
 525                 /* Disable the TX and RX to set baud rate */
 526                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 527                 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 528                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 529
 530                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 531
 532                 return NOTIFY_OK;
 533         }
 534         case POST_RATE_CHANGE:
 535                 /*
 536                  * Set clk dividers to generate correct baud with new clock
 537                  * frequency.
 538                  */
 539
 540                 spin_lock_irqsave(&cdns_uart->port->lock, flags);
 541
 542                 locked = 1;
 543                 port->uartclk = ndata->new_rate;
 544
 545                 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
 546                                 cdns_uart->baud);
 547                 /* fall through */
 548         case ABORT_RATE_CHANGE:
 549                 if (!locked)
 550                         spin_lock_irqsave(&cdns_uart->port->lock, flags);
 551
 552                 /* Set TX/RX Reset */
 553                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 554                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 555                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 556
 557                 while (readl(port->membase + CDNS_UART_CR) &
 558                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 559                         cpu_relax();
 560
 561                 /*
 562                  * Clear the RX disable and TX disable bits and then set the TX
 563                  * enable bit and RX enable bit to enable the transmitter and
 564                  * receiver.
 565                  */
 566                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 567                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
 568                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 569                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 570                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
 571
 572                 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
 573
 574                 return NOTIFY_OK;
 575         default:
 576                 return NOTIFY_DONE;
 577         }
 578 }
 579 #endif
 580
 581 /**
 582  * cdns_uart_start_tx -  Start transmitting bytes
 583  * @port: Handle to the uart port structure
 584  */
 585 static void cdns_uart_start_tx(struct uart_port *port)
 586 {
 587         unsigned int status;
 588
 589         if (uart_tx_stopped(port))
 590                 return;
 591
 592         /*
 593          * Set the TX enable bit and clear the TX disable bit to enable the
 594          * transmitter.
 595          */
 596         status = readl(port->membase + CDNS_UART_CR);
 597         status &= ~CDNS_UART_CR_TX_DIS;
 598         status |= CDNS_UART_CR_TX_EN;
 599         writel(status, port->membase + CDNS_UART_CR);
 600
 601         if (uart_circ_empty(&port->state->xmit))
 602                 return;
 603
 604         cdns_uart_handle_tx(port);
 605
 606         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
 607         /* Enable the TX Empty interrupt */
 608         writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
 609 }
 610
 611 /**
 612  * cdns_uart_stop_tx - Stop TX
 613  * @port: Handle to the uart port structure
 614  */
 615 static void cdns_uart_stop_tx(struct uart_port *port)
 616 {
 617         unsigned int regval;
 618
 619         regval = readl(port->membase + CDNS_UART_CR);
 620         regval |= CDNS_UART_CR_TX_DIS;
 621         /* Disable the transmitter */
 622         writel(regval, port->membase + CDNS_UART_CR);
 623 }
 624
 625 /**
 626  * cdns_uart_stop_rx - Stop RX
 627  * @port: Handle to the uart port structure
 628  */
 629 static void cdns_uart_stop_rx(struct uart_port *port)
 630 {
 631         unsigned int regval;
 632
 633         /* Disable RX IRQs */
 634         writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
 635
 636         /* Disable the receiver */
 637         regval = readl(port->membase + CDNS_UART_CR);
 638         regval |= CDNS_UART_CR_RX_DIS;
 639         writel(regval, port->membase + CDNS_UART_CR);
 640 }
 641
 642 /**
 643  * cdns_uart_tx_empty -  Check whether TX is empty
 644  * @port: Handle to the uart port structure
 645  *
 646  * Return: TIOCSER_TEMT on success, 0 otherwise
 647  */
 648 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
 649 {
 650         unsigned int status;
 651
 652         status = readl(port->membase + CDNS_UART_SR) &
 653                                 CDNS_UART_SR_TXEMPTY;
 654         return status ? TIOCSER_TEMT : 0;
 655 }
 656
 657 /**
 658  * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
 659  *                      transmitting char breaks
 660  * @port: Handle to the uart port structure
 661  * @ctl: Value based on which start or stop decision is taken
 662  */
 663 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
 664 {
 665         unsigned int status;
 666         unsigned long flags;
 667
 668         spin_lock_irqsave(&port->lock, flags);
 669
 670         status = readl(port->membase + CDNS_UART_CR);
 671
 672         if (ctl == -1)
 673                 writel(CDNS_UART_CR_STARTBRK | status,
 674                                 port->membase + CDNS_UART_CR);
 675         else {
 676                 if ((status & CDNS_UART_CR_STOPBRK) == 0)
 677                         writel(CDNS_UART_CR_STOPBRK | status,
 678                                         port->membase + CDNS_UART_CR);
 679         }
 680         spin_unlock_irqrestore(&port->lock, flags);
 681 }
 682
 683 /**
 684  * cdns_uart_set_termios - termios operations, handling data length, parity,
 685  *                              stop bits, flow control, baud rate
 686  * @port: Handle to the uart port structure
 687  * @termios: Handle to the input termios structure
 688  * @old: Values of the previously saved termios structure
 689  */
 690 static void cdns_uart_set_termios(struct uart_port *port,
 691                                 struct ktermios *termios, struct ktermios *old)
 692 {
 693         u32 cval = 0;
 694         unsigned int baud, minbaud, maxbaud;
 695         unsigned long flags;
 696         unsigned int ctrl_reg, mode_reg, val;
 697         int err;
 698
 699         /* Wait for the transmit FIFO to empty before making changes */
 700         if (!(readl(port->membase + CDNS_UART_CR) &
 701                                 CDNS_UART_CR_TX_DIS)) {
 702                 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
 703                                          val, (val & CDNS_UART_SR_TXEMPTY),
 704                                          1000, TX_TIMEOUT);
 705                 if (err) {
 706                         dev_err(port->dev, "timed out waiting for tx empty");
 707                         return;
 708                 }
 709         }
 710         spin_lock_irqsave(&port->lock, flags);
 711
 712         /* Disable the TX and RX to set baud rate */
 713         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 714         ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
 715         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 716
 717         /*
 718          * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
 719          * min and max baud should be calculated here based on port->uartclk.
 720          * this way we get a valid baud and can safely call set_baud()
 721          */
 722         minbaud = port->uartclk /
 723                         ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
 724         maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
 725         baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
 726         baud = cdns_uart_set_baud_rate(port, baud);
 727         if (tty_termios_baud_rate(termios))
 728                 tty_termios_encode_baud_rate(termios, baud, baud);
 729
 730         /* Update the per-port timeout. */
 731         uart_update_timeout(port, termios->c_cflag, baud);
 732
 733         /* Set TX/RX Reset */
 734         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 735         ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
 736         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 737
 738         while (readl(port->membase + CDNS_UART_CR) &
 739                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 740                 cpu_relax();
 741
 742         /*
 743          * Clear the RX disable and TX disable bits and then set the TX enable
 744          * bit and RX enable bit to enable the transmitter and receiver.
 745          */
 746         ctrl_reg = readl(port->membase + CDNS_UART_CR);
 747         ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
 748         ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
 749         writel(ctrl_reg, port->membase + CDNS_UART_CR);
 750
 751         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 752
 753         port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
 754                         CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
 755         port->ignore_status_mask = 0;
 756
 757         if (termios->c_iflag & INPCK)
 758                 port->read_status_mask |= CDNS_UART_IXR_PARITY |
 759                 CDNS_UART_IXR_FRAMING;
 760
 761         if (termios->c_iflag & IGNPAR)
 762                 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
 763                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 764
 765         /* ignore all characters if CREAD is not set */
 766         if ((termios->c_cflag & CREAD) == 0)
 767                 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
 768                         CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
 769                         CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
 770
 771         mode_reg = readl(port->membase + CDNS_UART_MR);
 772
 773         /* Handling Data Size */
 774         switch (termios->c_cflag & CSIZE) {
 775         case CS6:
 776                 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
 777                 break;
 778         case CS7:
 779                 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
 780                 break;
 781         default:
 782         case CS8:
 783                 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
 784                 termios->c_cflag &= ~CSIZE;
 785                 termios->c_cflag |= CS8;
 786                 break;
 787         }
 788
 789         /* Handling Parity and Stop Bits length */
 790         if (termios->c_cflag & CSTOPB)
 791                 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
 792         else
 793                 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
 794
 795         if (termios->c_cflag & PARENB) {
 796                 /* Mark or Space parity */
 797                 if (termios->c_cflag & CMSPAR) {
 798                         if (termios->c_cflag & PARODD)
 799                                 cval |= CDNS_UART_MR_PARITY_MARK;
 800                         else
 801                                 cval |= CDNS_UART_MR_PARITY_SPACE;
 802                 } else {
 803                         if (termios->c_cflag & PARODD)
 804                                 cval |= CDNS_UART_MR_PARITY_ODD;
 805                         else
 806                                 cval |= CDNS_UART_MR_PARITY_EVEN;
 807                 }
 808         } else {
 809                 cval |= CDNS_UART_MR_PARITY_NONE;
 810         }
 811         cval |= mode_reg & 1;
 812         writel(cval, port->membase + CDNS_UART_MR);
 813
 814         cval = readl(port->membase + CDNS_UART_MODEMCR);
 815         if (termios->c_cflag & CRTSCTS)
 816                 cval |= CDNS_UART_MODEMCR_FCM;
 817         else
 818                 cval &= ~CDNS_UART_MODEMCR_FCM;
 819         writel(cval, port->membase + CDNS_UART_MODEMCR);
 820
 821         spin_unlock_irqrestore(&port->lock, flags);
 822 }
 823
 824 /**
 825  * cdns_uart_startup - Called when an application opens a cdns_uart port
 826  * @port: Handle to the uart port structure
 827  *
 828  * Return: 0 on success, negative errno otherwise
 829  */
 830 static int cdns_uart_startup(struct uart_port *port)
 831 {
 832         struct cdns_uart *cdns_uart = port->private_data;
 833         bool is_brk_support;
 834         int ret;
 835         unsigned long flags;
 836         unsigned int status = 0;
 837
 838         is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 839
 840         spin_lock_irqsave(&port->lock, flags);
 841
 842         /* Disable the TX and RX */
 843         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 844                         port->membase + CDNS_UART_CR);
 845
 846         /* Set the Control Register with TX/RX Enable, TX/RX Reset,
 847          * no break chars.
 848          */
 849         writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
 850                         port->membase + CDNS_UART_CR);
 851
 852         while (readl(port->membase + CDNS_UART_CR) &
 853                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
 854                 cpu_relax();
 855
 856         /*
 857          * Clear the RX disable bit and then set the RX enable bit to enable
 858          * the receiver.
 859          */
 860         status = readl(port->membase + CDNS_UART_CR);
 861         status &= ~CDNS_UART_CR_RX_DIS;
 862         status |= CDNS_UART_CR_RX_EN;
 863         writel(status, port->membase + CDNS_UART_CR);
 864
 865         /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
 866          * no parity.
 867          */
 868         writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
 869                 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
 870                 port->membase + CDNS_UART_MR);
 871
 872         /*
 873          * Set the RX FIFO Trigger level to use most of the FIFO, but it
 874          * can be tuned with a module parameter
 875          */
 876         writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
 877
 878         /*
 879          * Receive Timeout register is enabled but it
 880          * can be tuned with a module parameter
 881          */
 882         writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
 883
 884         /* Clear out any pending interrupts before enabling them */
 885         writel(readl(port->membase + CDNS_UART_ISR),
 886                         port->membase + CDNS_UART_ISR);
 887
 888         spin_unlock_irqrestore(&port->lock, flags);
 889
 890         ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
 891         if (ret) {
 892                 dev_err(port->dev, "request_irq '%d' failed with %d\n",
 893                         port->irq, ret);
 894                 return ret;
 895         }
 896
 897         /* Set the Interrupt Registers with desired interrupts */
 898         if (is_brk_support)
 899                 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
 900                                         port->membase + CDNS_UART_IER);
 901         else
 902                 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
 903
 904         return 0;
 905 }
 906
 907 /**
 908  * cdns_uart_shutdown - Called when an application closes a cdns_uart port
 909  * @port: Handle to the uart port structure
 910  */
 911 static void cdns_uart_shutdown(struct uart_port *port)
 912 {
 913         int status;
 914         unsigned long flags;
 915
 916         spin_lock_irqsave(&port->lock, flags);
 917
 918         /* Disable interrupts */
 919         status = readl(port->membase + CDNS_UART_IMR);
 920         writel(status, port->membase + CDNS_UART_IDR);
 921         writel(0xffffffff, port->membase + CDNS_UART_ISR);
 922
 923         /* Disable the TX and RX */
 924         writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
 925                         port->membase + CDNS_UART_CR);
 926
 927         spin_unlock_irqrestore(&port->lock, flags);
 928
 929         free_irq(port->irq, port);
 930 }
 931
 932 /**
 933  * cdns_uart_type - Set UART type to cdns_uart port
 934  * @port: Handle to the uart port structure
 935  *
 936  * Return: string on success, NULL otherwise
 937  */
 938 static const char *cdns_uart_type(struct uart_port *port)
 939 {
 940         return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
 941 }
 942
 943 /**
 944  * cdns_uart_verify_port - Verify the port params
 945  * @port: Handle to the uart port structure
 946  * @ser: Handle to the structure whose members are compared
 947  *
 948  * Return: 0 on success, negative errno otherwise.
 949  */
 950 static int cdns_uart_verify_port(struct uart_port *port,
 951                                         struct serial_struct *ser)
 952 {
 953         if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
 954                 return -EINVAL;
 955         if (port->irq != ser->irq)
 956                 return -EINVAL;
 957         if (ser->io_type != UPIO_MEM)
 958                 return -EINVAL;
 959         if (port->iobase != ser->port)
 960                 return -EINVAL;
 961         if (ser->hub6 != 0)
 962                 return -EINVAL;
 963         return 0;
 964 }
 965
 966 /**
 967  * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
 968  *                              called when the driver adds a cdns_uart port via
 969  *                              uart_add_one_port()
 970  * @port: Handle to the uart port structure
 971  *
 972  * Return: 0 on success, negative errno otherwise.
 973  */
 974 static int cdns_uart_request_port(struct uart_port *port)
 975 {
 976         if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
 977                                          CDNS_UART_NAME)) {
 978                 return -ENOMEM;
 979         }
 980
 981         port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
 982         if (!port->membase) {
 983                 dev_err(port->dev, "Unable to map registers\n");
 984                 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
 985                 return -ENOMEM;
 986         }
 987         return 0;
 988 }
 989
 990 /**
 991  * cdns_uart_release_port - Release UART port
 992  * @port: Handle to the uart port structure
 993  *
 994  * Release the memory region attached to a cdns_uart port. Called when the
 995  * driver removes a cdns_uart port via uart_remove_one_port().
 996  */
 997 static void cdns_uart_release_port(struct uart_port *port)
 998 {
 999         release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
1000         iounmap(port->membase);
1001         port->membase = NULL;
1002 }
1003
1004 /**
1005  * cdns_uart_config_port - Configure UART port
1006  * @port: Handle to the uart port structure
1007  * @flags: If any
1008  */
1009 static void cdns_uart_config_port(struct uart_port *port, int flags)
1010 {
1011         if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1012                 port->type = PORT_XUARTPS;
1013 }
1014
1015 /**
1016  * cdns_uart_get_mctrl - Get the modem control state
1017  * @port: Handle to the uart port structure
1018  *
1019  * Return: the modem control state
1020  */
1021 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1022 {
1023         u32 val;
1024         unsigned int mctrl = 0;
1025         struct cdns_uart *cdns_uart_data = port->private_data;
1026
1027         if (cdns_uart_data->cts_override)
1028                 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1029
1030         val = readl(port->membase + CDNS_UART_MODEMSR);
1031         if (val & CDNS_UART_MODEMSR_CTS)
1032                 mctrl |= TIOCM_CTS;
1033         if (val & CDNS_UART_MODEMSR_DSR)
1034                 mctrl |= TIOCM_DSR;
1035         if (val & CDNS_UART_MODEMSR_RI)
1036                 mctrl |= TIOCM_RNG;
1037         if (val & CDNS_UART_MODEMSR_DCD)
1038                 mctrl |= TIOCM_CAR;
1039
1040         return mctrl;
1041 }
1042
1043 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1044 {
1045         u32 val;
1046         u32 mode_reg;
1047         struct cdns_uart *cdns_uart_data = port->private_data;
1048
1049         if (cdns_uart_data->cts_override)
1050                 return;
1051
1052         val = readl(port->membase + CDNS_UART_MODEMCR);
1053         mode_reg = readl(port->membase + CDNS_UART_MR);
1054
1055         val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1056         mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1057
1058         if (mctrl & TIOCM_RTS)
1059                 val |= CDNS_UART_MODEMCR_RTS;
1060         if (mctrl & TIOCM_DTR)
1061                 val |= CDNS_UART_MODEMCR_DTR;
1062         if (mctrl & TIOCM_LOOP)
1063                 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1064         else
1065                 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1066
1067         writel(val, port->membase + CDNS_UART_MODEMCR);
1068         writel(mode_reg, port->membase + CDNS_UART_MR);
1069 }
1070
1071 #ifdef CONFIG_CONSOLE_POLL
1072 static int cdns_uart_poll_get_char(struct uart_port *port)
1073 {
1074         int c;
1075         unsigned long flags;
1076
1077         spin_lock_irqsave(&port->lock, flags);
1078
1079         /* Check if FIFO is empty */
1080         if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1081                 c = NO_POLL_CHAR;
1082         else /* Read a character */
1083                 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1084
1085         spin_unlock_irqrestore(&port->lock, flags);
1086
1087         return c;
1088 }
1089
1090 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1091 {
1092         unsigned long flags;
1093
1094         spin_lock_irqsave(&port->lock, flags);
1095
1096         /* Wait until FIFO is empty */
1097         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1098                 cpu_relax();
1099
1100         /* Write a character */
1101         writel(c, port->membase + CDNS_UART_FIFO);
1102
1103         /* Wait until FIFO is empty */
1104         while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1105                 cpu_relax();
1106
1107         spin_unlock_irqrestore(&port->lock, flags);
1108 }
1109 #endif
1110
1111 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1112                    unsigned int oldstate)
1113 {
1114         switch (state) {
1115         case UART_PM_STATE_OFF:
1116                 pm_runtime_mark_last_busy(port->dev);
1117                 pm_runtime_put_autosuspend(port->dev);
1118                 break;
1119         default:
1120                 pm_runtime_get_sync(port->dev);
1121                 break;
1122         }
1123 }
1124
1125 static const struct uart_ops cdns_uart_ops = {
1126         .set_mctrl      = cdns_uart_set_mctrl,
1127         .get_mctrl      = cdns_uart_get_mctrl,
1128         .start_tx       = cdns_uart_start_tx,
1129         .stop_tx        = cdns_uart_stop_tx,
1130         .stop_rx        = cdns_uart_stop_rx,
1131         .tx_empty       = cdns_uart_tx_empty,
1132         .break_ctl      = cdns_uart_break_ctl,
1133         .set_termios    = cdns_uart_set_termios,
1134         .startup        = cdns_uart_startup,
1135         .shutdown       = cdns_uart_shutdown,
1136         .pm             = cdns_uart_pm,
1137         .type           = cdns_uart_type,
1138         .verify_port    = cdns_uart_verify_port,
1139         .request_port   = cdns_uart_request_port,
1140         .release_port   = cdns_uart_release_port,
1141         .config_port    = cdns_uart_config_port,
1142 #ifdef CONFIG_CONSOLE_POLL
1143         .poll_get_char  = cdns_uart_poll_get_char,
1144         .poll_put_char  = cdns_uart_poll_put_char,
1145 #endif
1146 };
1147
1148 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1149 /**
1150  * cdns_uart_console_putchar - write the character to the FIFO buffer
1151  * @port: Handle to the uart port structure
1152  * @ch: Character to be written
1153  */
1154 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1155 {
1156         while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1157                 cpu_relax();
1158         writel(ch, port->membase + CDNS_UART_FIFO);
1159 }
1160
1161 static void cdns_early_write(struct console *con, const char *s,
1162                                     unsigned n)
1163 {
1164         struct earlycon_device *dev = con->data;
1165
1166         uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1167 }
1168
1169 static int __init cdns_early_console_setup(struct earlycon_device *device,
1170                                            const char *opt)
1171 {
1172         struct uart_port *port = &device->port;
1173
1174         if (!port->membase)
1175                 return -ENODEV;
1176
1177         /* initialise control register */
1178         writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1179                port->membase + CDNS_UART_CR);
1180
1181         /* only set baud if specified on command line - otherwise
1182          * assume it has been initialized by a boot loader.
1183          */
1184         if (port->uartclk && device->baud) {
1185                 u32 cd = 0, bdiv = 0;
1186                 u32 mr;
1187                 int div8;
1188
1189                 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1190                                          &bdiv, &cd, &div8);
1191                 mr = CDNS_UART_MR_PARITY_NONE;
1192                 if (div8)
1193                         mr |= CDNS_UART_MR_CLKSEL;
1194
1195                 writel(mr,   port->membase + CDNS_UART_MR);
1196                 writel(cd,   port->membase + CDNS_UART_BAUDGEN);
1197                 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1198         }
1199
1200         device->con->write = cdns_early_write;
1201
1202         return 0;
1203 }
1204 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1205 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1206 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1207 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1208
1209
1210 /* Static pointer to console port */
1211 static struct uart_port *console_port;
1212
1213 /**
1214  * cdns_uart_console_write - perform write operation
1215  * @co: Console handle
1216  * @s: Pointer to character array
1217  * @count: No of characters
1218  */
1219 static void cdns_uart_console_write(struct console *co, const char *s,
1220                                 unsigned int count)
1221 {
1222         struct uart_port *port = console_port;
1223         unsigned long flags = 0;
1224         unsigned int imr, ctrl;
1225         int locked = 1;
1226
1227         if (port->sysrq)
1228                 locked = 0;
1229         else if (oops_in_progress)
1230                 locked = spin_trylock_irqsave(&port->lock, flags);
1231         else
1232                 spin_lock_irqsave(&port->lock, flags);
1233
1234         /* save and disable interrupt */
1235         imr = readl(port->membase + CDNS_UART_IMR);
1236         writel(imr, port->membase + CDNS_UART_IDR);
1237
1238         /*
1239          * Make sure that the tx part is enabled. Set the TX enable bit and
1240          * clear the TX disable bit to enable the transmitter.
1241          */
1242         ctrl = readl(port->membase + CDNS_UART_CR);
1243         ctrl &= ~CDNS_UART_CR_TX_DIS;
1244         ctrl |= CDNS_UART_CR_TX_EN;
1245         writel(ctrl, port->membase + CDNS_UART_CR);
1246
1247         uart_console_write(port, s, count, cdns_uart_console_putchar);
1248         while ((readl(port->membase + CDNS_UART_SR) &
1249                         (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1250                         CDNS_UART_SR_TXEMPTY)
1251                 cpu_relax();
1252
1253         /* restore interrupt state */
1254         writel(imr, port->membase + CDNS_UART_IER);
1255
1256         if (locked)
1257                 spin_unlock_irqrestore(&port->lock, flags);
1258 }
1259
1260 /**
1261  * cdns_uart_console_setup - Initialize the uart to default config
1262  * @co: Console handle
1263  * @options: Initial settings of uart
1264  *
1265  * Return: 0 on success, negative errno otherwise.
1266  */
1267 static int cdns_uart_console_setup(struct console *co, char *options)
1268 {
1269         struct uart_port *port = console_port;
1270
1271         int baud = 9600;
1272         int bits = 8;
1273         int parity = 'n';
1274         int flow = 'n';
1275
1276         if (!port->membase) {
1277                 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1278                          co->index);
1279                 return -ENODEV;
1280         }
1281
1282         if (options)
1283                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1284
1285         return uart_set_options(port, co, baud, parity, bits, flow);
1286 }
1287 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1288
1289 #ifdef CONFIG_PM_SLEEP
1290 /**
1291  * cdns_uart_suspend - suspend event
1292  * @device: Pointer to the device structure
1293  *
1294  * Return: 0
1295  */
1296 static int cdns_uart_suspend(struct device *device)
1297 {
1298         struct uart_port *port = dev_get_drvdata(device);
1299         struct cdns_uart *cdns_uart = port->private_data;
1300         int may_wake;
1301
1302         may_wake = device_may_wakeup(device);
1303
1304         if (console_suspend_enabled && uart_console(port) && may_wake) {
1305                 unsigned long flags = 0;
1306
1307                 spin_lock_irqsave(&port->lock, flags);
1308                 /* Empty the receive FIFO 1st before making changes */
1309                 while (!(readl(port->membase + CDNS_UART_SR) &
1310                                         CDNS_UART_SR_RXEMPTY))
1311                         readl(port->membase + CDNS_UART_FIFO);
1312                 /* set RX trigger level to 1 */
1313                 writel(1, port->membase + CDNS_UART_RXWM);
1314                 /* disable RX timeout interrups */
1315                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1316                 spin_unlock_irqrestore(&port->lock, flags);
1317         }
1318
1319         /*
1320          * Call the API provided in serial_core.c file which handles
1321          * the suspend.
1322          */
1323         return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1324 }
1325
1326 /**
1327  * cdns_uart_resume - Resume after a previous suspend
1328  * @device: Pointer to the device structure
1329  *
1330  * Return: 0
1331  */
1332 static int cdns_uart_resume(struct device *device)
1333 {
1334         struct uart_port *port = dev_get_drvdata(device);
1335         struct cdns_uart *cdns_uart = port->private_data;
1336         unsigned long flags = 0;
1337         u32 ctrl_reg;
1338         int may_wake;
1339
1340         may_wake = device_may_wakeup(device);
1341
1342         if (console_suspend_enabled && uart_console(port) && !may_wake) {
1343                 clk_enable(cdns_uart->pclk);
1344                 clk_enable(cdns_uart->uartclk);
1345
1346                 spin_lock_irqsave(&port->lock, flags);
1347
1348                 /* Set TX/RX Reset */
1349                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1350                 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1351                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1352                 while (readl(port->membase + CDNS_UART_CR) &
1353                                 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1354                         cpu_relax();
1355
1356                 /* restore rx timeout value */
1357                 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1358                 /* Enable Tx/Rx */
1359                 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1360                 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1361                 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1362                 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1363
1364                 clk_disable(cdns_uart->uartclk);
1365                 clk_disable(cdns_uart->pclk);
1366                 spin_unlock_irqrestore(&port->lock, flags);
1367         } else {
1368                 spin_lock_irqsave(&port->lock, flags);
1369                 /* restore original rx trigger level */
1370                 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1371                 /* enable RX timeout interrupt */
1372                 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1373                 spin_unlock_irqrestore(&port->lock, flags);
1374         }
1375
1376         return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1377 }
1378 #endif /* ! CONFIG_PM_SLEEP */
1379 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1380 {
1381         struct uart_port *port = dev_get_drvdata(dev);
1382         struct cdns_uart *cdns_uart = port->private_data;
1383
1384         clk_disable(cdns_uart->uartclk);
1385         clk_disable(cdns_uart->pclk);
1386         return 0;
1387 };
1388
1389 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1390 {
1391         struct uart_port *port = dev_get_drvdata(dev);
1392         struct cdns_uart *cdns_uart = port->private_data;
1393
1394         clk_enable(cdns_uart->pclk);
1395         clk_enable(cdns_uart->uartclk);
1396         return 0;
1397 };
1398
1399 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1400         SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1401         SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1402                            cdns_runtime_resume, NULL)
1403 };
1404
1405 static const struct cdns_platform_data zynqmp_uart_def = {
1406                                 .quirks = CDNS_UART_RXBS_SUPPORT, };
1407
1408 /* Match table for of_platform binding */
1409 static const struct of_device_id cdns_uart_of_match[] = {
1410         { .compatible = "xlnx,xuartps", },
1411         { .compatible = "cdns,uart-r1p8", },
1412         { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1413         { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1414         {}
1415 };
1416 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1417
1418 /*
1419  * Maximum number of instances without alias IDs but if there is alias
1420  * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1421  */
1422 #define MAX_UART_INSTANCES      32
1423
1424 /* Stores static aliases list */
1425 static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1426 static int alias_bitmap_initialized;
1427
1428 /* Stores actual bitmap of allocated IDs with alias IDs together */
1429 static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1430 /* Protect bitmap operations to have unique IDs */
1431 static DEFINE_MUTEX(bitmap_lock);
1432
1433 static int cdns_get_id(struct platform_device *pdev)
1434 {
1435         int id, ret;
1436
1437         mutex_lock(&bitmap_lock);
1438
1439         /* Alias list is stable that's why get alias bitmap only once */
1440         if (!alias_bitmap_initialized) {
1441                 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1442                                               alias_bitmap, MAX_UART_INSTANCES);
1443                 if (ret && ret != -EOVERFLOW) {
1444                         mutex_unlock(&bitmap_lock);
1445                         return ret;
1446                 }
1447
1448                 alias_bitmap_initialized++;
1449         }
1450
1451         /* Make sure that alias ID is not taken by instance without alias */
1452         bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1453
1454         dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1455                 MAX_UART_INSTANCES, bitmap);
1456
1457         /* Look for a serialN alias */
1458         id = of_alias_get_id(pdev->dev.of_node, "serial");
1459         if (id < 0) {
1460                 dev_warn(&pdev->dev,
1461                          "No serial alias passed. Using the first free id\n");
1462
1463                 /*
1464                  * Start with id 0 and check if there is no serial0 alias
1465                  * which points to device which is compatible with this driver.
1466                  * If alias exists then try next free position.
1467                  */
1468                 id = 0;
1469
1470                 for (;;) {
1471                         dev_info(&pdev->dev, "Checking id %d\n", id);
1472                         id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1473
1474                         /* No free empty instance */
1475                         if (id == MAX_UART_INSTANCES) {
1476                                 dev_err(&pdev->dev, "No free ID\n");
1477                                 mutex_unlock(&bitmap_lock);
1478                                 return -EINVAL;
1479                         }
1480
1481                         dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1482                         /* Check if ID is empty */
1483                         if (!test_and_set_bit(id, bitmap)) {
1484                                 /* Break the loop if bit is taken */
1485                                 dev_dbg(&pdev->dev,
1486                                         "Selected ID %d allocation passed\n",
1487                                         id);
1488                                 break;
1489                         }
1490                         dev_dbg(&pdev->dev,
1491                                 "Selected ID %d allocation failed\n", id);
1492                         /* if taking bit fails then try next one */
1493                         id++;
1494                 }
1495         }
1496
1497         mutex_unlock(&bitmap_lock);
1498
1499         return id;
1500 }
1501
1502 /**
1503  * cdns_uart_probe - Platform driver probe
1504  * @pdev: Pointer to the platform device structure
1505  *
1506  * Return: 0 on success, negative errno otherwise
1507  */
1508 static int cdns_uart_probe(struct platform_device *pdev)
1509 {
1510         int rc, irq;
1511         struct uart_port *port;
1512         struct resource *res;
1513         struct cdns_uart *cdns_uart_data;
1514         const struct of_device_id *match;
1515         struct uart_driver *cdns_uart_uart_driver;
1516         char *driver_name;
1517 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1518         struct console *cdns_uart_console;
1519 #endif
1520
1521         cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1522                         GFP_KERNEL);
1523         if (!cdns_uart_data)
1524                 return -ENOMEM;
1525         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1526         if (!port)
1527                 return -ENOMEM;
1528
1529         cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1530                                              sizeof(*cdns_uart_uart_driver),
1531                                              GFP_KERNEL);
1532         if (!cdns_uart_uart_driver)
1533                 return -ENOMEM;
1534
1535         cdns_uart_data->id = cdns_get_id(pdev);
1536         if (cdns_uart_data->id < 0)
1537                 return cdns_uart_data->id;
1538
1539         /* There is a need to use unique driver name */
1540         driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1541                                      CDNS_UART_NAME, cdns_uart_data->id);
1542         if (!driver_name) {
1543                 rc = -ENOMEM;
1544                 goto err_out_id;
1545         }
1546
1547         cdns_uart_uart_driver->owner = THIS_MODULE;
1548         cdns_uart_uart_driver->driver_name = driver_name;
1549         cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1550         cdns_uart_uart_driver->major = uartps_major;
1551         cdns_uart_uart_driver->minor = cdns_uart_data->id;
1552         cdns_uart_uart_driver->nr = 1;
1553
1554 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1555         cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1556                                          GFP_KERNEL);
1557         if (!cdns_uart_console) {
1558                 rc = -ENOMEM;
1559                 goto err_out_id;
1560         }
1561
1562         strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1563                 sizeof(cdns_uart_console->name));
1564         cdns_uart_console->index = cdns_uart_data->id;
1565         cdns_uart_console->write = cdns_uart_console_write;
1566         cdns_uart_console->device = uart_console_device;
1567         cdns_uart_console->setup = cdns_uart_console_setup;
1568         cdns_uart_console->flags = CON_PRINTBUFFER;
1569         cdns_uart_console->data = cdns_uart_uart_driver;
1570         cdns_uart_uart_driver->cons = cdns_uart_console;
1571 #endif
1572
1573         rc = uart_register_driver(cdns_uart_uart_driver);
1574         if (rc < 0) {
1575                 dev_err(&pdev->dev, "Failed to register driver\n");
1576                 goto err_out_id;
1577         }
1578
1579         cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1580
1581         /*
1582          * Setting up proper name_base needs to be done after uart
1583          * registration because tty_driver structure is not filled.
1584          * name_base is 0 by default.
1585          */
1586         cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1587
1588         match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1589         if (match && match->data) {
1590                 const struct cdns_platform_data *data = match->data;
1591
1592                 cdns_uart_data->quirks = data->quirks;
1593         }
1594
1595         cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1596         if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1597                 rc = PTR_ERR(cdns_uart_data->pclk);
1598                 goto err_out_unregister_driver;
1599         }
1600
1601         if (IS_ERR(cdns_uart_data->pclk)) {
1602                 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1603                 if (IS_ERR(cdns_uart_data->pclk)) {
1604                         rc = PTR_ERR(cdns_uart_data->pclk);
1605                         goto err_out_unregister_driver;
1606                 }
1607                 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1608         }
1609
1610         cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1611         if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1612                 rc = PTR_ERR(cdns_uart_data->uartclk);
1613                 goto err_out_unregister_driver;
1614         }
1615
1616         if (IS_ERR(cdns_uart_data->uartclk)) {
1617                 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1618                 if (IS_ERR(cdns_uart_data->uartclk)) {
1619                         rc = PTR_ERR(cdns_uart_data->uartclk);
1620                         goto err_out_unregister_driver;
1621                 }
1622                 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1623         }
1624
1625         rc = clk_prepare_enable(cdns_uart_data->pclk);
1626         if (rc) {
1627                 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1628                 goto err_out_unregister_driver;
1629         }
1630         rc = clk_prepare_enable(cdns_uart_data->uartclk);
1631         if (rc) {
1632                 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1633                 goto err_out_clk_dis_pclk;
1634         }
1635
1636         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1637         if (!res) {
1638                 rc = -ENODEV;
1639                 goto err_out_clk_disable;
1640         }
1641
1642         irq = platform_get_irq(pdev, 0);
1643         if (irq <= 0) {
1644                 rc = -ENXIO;
1645                 goto err_out_clk_disable;
1646         }
1647
1648 #ifdef CONFIG_COMMON_CLK
1649         cdns_uart_data->clk_rate_change_nb.notifier_call =
1650                         cdns_uart_clk_notifier_cb;
1651         if (clk_notifier_register(cdns_uart_data->uartclk,
1652                                 &cdns_uart_data->clk_rate_change_nb))
1653                 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1654 #endif
1655
1656         /* At this point, we've got an empty uart_port struct, initialize it */
1657         spin_lock_init(&port->lock);
1658         port->type      = PORT_UNKNOWN;
1659         port->iotype    = UPIO_MEM32;
1660         port->flags     = UPF_BOOT_AUTOCONF;
1661         port->ops       = &cdns_uart_ops;
1662         port->fifosize  = CDNS_UART_FIFO_SIZE;
1663         port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE);
1664
1665         /*
1666          * Register the port.
1667          * This function also registers this device with the tty layer
1668          * and triggers invocation of the config_port() entry point.
1669          */
1670         port->mapbase = res->start;
1671         port->irq = irq;
1672         port->dev = &pdev->dev;
1673         port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1674         port->private_data = cdns_uart_data;
1675         cdns_uart_data->port = port;
1676         platform_set_drvdata(pdev, port);
1677
1678         pm_runtime_use_autosuspend(&pdev->dev);
1679         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1680         pm_runtime_set_active(&pdev->dev);
1681         pm_runtime_enable(&pdev->dev);
1682         device_init_wakeup(port->dev, true);
1683
1684 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1685         /*
1686          * If console hasn't been found yet try to assign this port
1687          * because it is required to be assigned for console setup function.
1688          * If register_console() don't assign value, then console_port pointer
1689          * is cleanup.
1690          */
1691         if (!console_port)
1692                 console_port = port;
1693 #endif
1694
1695         rc = uart_add_one_port(cdns_uart_uart_driver, port);
1696         if (rc) {
1697                 dev_err(&pdev->dev,
1698                         "uart_add_one_port() failed; err=%i\n", rc);
1699                 goto err_out_pm_disable;
1700         }
1701
1702 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1703         /* This is not port which is used for console that's why clean it up */
1704         if (console_port == port &&
1705             !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1706                 console_port = NULL;
1707 #endif
1708
1709         uartps_major = cdns_uart_uart_driver->tty_driver->major;
1710         cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1711                                                              "cts-override");
1712         return 0;
1713
1714 err_out_pm_disable:
1715         pm_runtime_disable(&pdev->dev);
1716         pm_runtime_set_suspended(&pdev->dev);
1717         pm_runtime_dont_use_autosuspend(&pdev->dev);
1718 #ifdef CONFIG_COMMON_CLK
1719         clk_notifier_unregister(cdns_uart_data->uartclk,
1720                         &cdns_uart_data->clk_rate_change_nb);
1721 #endif
1722 err_out_clk_disable:
1723         clk_disable_unprepare(cdns_uart_data->uartclk);
1724 err_out_clk_dis_pclk:
1725         clk_disable_unprepare(cdns_uart_data->pclk);
1726 err_out_unregister_driver:
1727         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1728 err_out_id:
1729         mutex_lock(&bitmap_lock);
1730         if (cdns_uart_data->id < MAX_UART_INSTANCES)
1731                 clear_bit(cdns_uart_data->id, bitmap);
1732         mutex_unlock(&bitmap_lock);
1733         return rc;
1734 }
1735
1736 /**
1737  * cdns_uart_remove - called when the platform driver is unregistered
1738  * @pdev: Pointer to the platform device structure
1739  *
1740  * Return: 0 on success, negative errno otherwise
1741  */
1742 static int cdns_uart_remove(struct platform_device *pdev)
1743 {
1744         struct uart_port *port = platform_get_drvdata(pdev);
1745         struct cdns_uart *cdns_uart_data = port->private_data;
1746         int rc;
1747
1748         /* Remove the cdns_uart port from the serial core */
1749 #ifdef CONFIG_COMMON_CLK
1750         clk_notifier_unregister(cdns_uart_data->uartclk,
1751                         &cdns_uart_data->clk_rate_change_nb);
1752 #endif
1753         rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1754         port->mapbase = 0;
1755         mutex_lock(&bitmap_lock);
1756         if (cdns_uart_data->id < MAX_UART_INSTANCES)
1757                 clear_bit(cdns_uart_data->id, bitmap);
1758         mutex_unlock(&bitmap_lock);
1759         clk_disable_unprepare(cdns_uart_data->uartclk);
1760         clk_disable_unprepare(cdns_uart_data->pclk);
1761         pm_runtime_disable(&pdev->dev);
1762         pm_runtime_set_suspended(&pdev->dev);
1763         pm_runtime_dont_use_autosuspend(&pdev->dev);
1764         device_init_wakeup(&pdev->dev, false);
1765
1766 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1767         if (console_port == port)
1768                 console_port = NULL;
1769 #endif
1770
1771         /* If this is last instance major number should be initialized */
1772         mutex_lock(&bitmap_lock);
1773         if (bitmap_empty(bitmap, MAX_UART_INSTANCES))
1774                 uartps_major = 0;
1775         mutex_unlock(&bitmap_lock);
1776
1777         uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1778         return rc;
1779 }
1780
1781 static struct platform_driver cdns_uart_platform_driver = {
1782         .probe   = cdns_uart_probe,
1783         .remove  = cdns_uart_remove,
1784         .driver  = {
1785                 .name = CDNS_UART_NAME,
1786                 .of_match_table = cdns_uart_of_match,
1787                 .pm = &cdns_uart_dev_pm_ops,
1788                 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1789                 },
1790 };
1791
1792 static int __init cdns_uart_init(void)
1793 {
1794         /* Register the platform driver */
1795         return platform_driver_register(&cdns_uart_platform_driver);
1796 }
1797
1798 static void __exit cdns_uart_exit(void)
1799 {
1800         /* Unregister the platform driver */
1801         platform_driver_unregister(&cdns_uart_platform_driver);
1802 }
1803
1804 arch_initcall(cdns_uart_init);
1805 module_exit(cdns_uart_exit);
1806
1807 MODULE_DESCRIPTION("Driver for Cadence UART");
1808 MODULE_AUTHOR("Xilinx Inc.");
1809 MODULE_LICENSE("GPL");