1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * 2011 - 2014 (C) Xilinx Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
12 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
16 #include <linux/platform_device.h>
17 #include <linux/serial.h>
18 #include <linux/console.h>
19 #include <linux/serial_core.h>
20 #include <linux/slab.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
23 #include <linux/clk.h>
24 #include <linux/irq.h>
27 #include <linux/module.h>
28 #include <linux/pm_runtime.h>
30 #define CDNS_UART_TTY_NAME "ttyPS"
31 #define CDNS_UART_NAME "xuartps"
32 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
33 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
34 #define CDNS_UART_REGISTER_SPACE 0x1000
36 /* Rx Trigger level */
37 static int rx_trigger_level = 56;
38 module_param(rx_trigger_level, uint, S_IRUGO);
39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42 static int rx_timeout = 10;
43 module_param(rx_timeout, uint, S_IRUGO);
44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
46 /* Register offsets for the UART. */
47 #define CDNS_UART_CR 0x00 /* Control Register */
48 #define CDNS_UART_MR 0x04 /* Mode Register */
49 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
50 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
51 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
52 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
53 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
54 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
55 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
56 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
57 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
58 #define CDNS_UART_SR 0x2C /* Channel Status */
59 #define CDNS_UART_FIFO 0x30 /* FIFO */
60 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
61 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
62 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
63 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
64 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
65 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
67 /* Control Register Bit Definitions */
68 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
69 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
70 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
71 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
72 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
73 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
74 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
75 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
76 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
77 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
78 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
79 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
83 * The mode register (MR) defines the mode of transfer as well as the data
84 * format. If this register is modified during transmission or reception,
85 * data validity cannot be guaranteed.
87 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
88 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
89 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
90 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
92 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
93 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
96 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
97 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
98 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
99 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
102 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
103 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106 * Interrupt Registers:
107 * Interrupt control logic uses the interrupt enable register (IER) and the
108 * interrupt disable register (IDR) to set the value of the bits in the
109 * interrupt mask register (IMR). The IMR determines whether to pass an
110 * interrupt to the interrupt status register (ISR).
111 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
112 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
113 * Reading either IER or IDR returns 0x00.
114 * All four registers have the same bit definitions.
116 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
117 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
118 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
119 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
120 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
121 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
122 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
123 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
124 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
125 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
126 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
129 * Do not enable parity error interrupt for the following
130 * reason: When parity error interrupt is enabled, each Rx
131 * parity error always results in 2 events. The first one
132 * being parity error interrupt and the second one with a
133 * proper Rx interrupt with the incoming data. Disabling
134 * parity error interrupt ensures better handling of parity
135 * error events. With this change, for a parity error case, we
136 * get a Rx interrupt with parity error set in ISR register
137 * and we still handle parity errors in the desired way.
140 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
141 CDNS_UART_IXR_OVERRUN | \
142 CDNS_UART_IXR_RXTRIG | \
145 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
146 #define CDNS_UART_IXR_BRK 0x00002000
148 #define CDNS_UART_RXBS_SUPPORT BIT(1)
150 * Modem Control register:
151 * The read/write Modem Control register controls the interface with the modem
152 * or data set, or a peripheral device emulating a modem.
154 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
155 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
156 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159 * Channel Status Register:
160 * The channel status register (CSR) is provided to enable the control logic
161 * to monitor the status of bits in the channel interrupt status register,
162 * even if these are masked out by the interrupt mask register.
164 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
165 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
166 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
167 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
168 #define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
170 /* baud dividers min/max values */
171 #define CDNS_UART_BDIV_MIN 4
172 #define CDNS_UART_BDIV_MAX 255
173 #define CDNS_UART_CD_MAX 65535
174 #define UART_AUTOSUSPEND_TIMEOUT 3000
177 * struct cdns_uart - device data
178 * @port: Pointer to the UART port
179 * @uartclk: Reference clock
181 * @cdns_uart_driver: Pointer to UART driver
182 * @baud: Current baud rate
184 * @clk_rate_change_nb: Notifier block for clock changes
185 * @quirks: Flags for RXBS support.
188 struct uart_port *port;
191 struct uart_driver *cdns_uart_driver;
194 struct notifier_block clk_rate_change_nb;
197 struct cdns_platform_data {
200 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
204 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
205 * @dev_id: Id of the UART port
206 * @isrstatus: The interrupt status register value as read
209 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
211 struct uart_port *port = (struct uart_port *)dev_id;
212 struct cdns_uart *cdns_uart = port->private_data;
214 unsigned int rxbs_status = 0;
215 unsigned int status_mask;
216 unsigned int framerrprocessed = 0;
217 char status = TTY_NORMAL;
218 bool is_rxbs_support;
220 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
222 while ((readl(port->membase + CDNS_UART_SR) &
223 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
225 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
226 data = readl(port->membase + CDNS_UART_FIFO);
229 * There is no hardware break detection in Zynq, so we interpret
230 * framing error with all-zeros data as a break sequence.
231 * Most of the time, there's another non-zero byte at the
232 * end of the sequence.
234 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
236 port->read_status_mask |= CDNS_UART_IXR_BRK;
237 framerrprocessed = 1;
241 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
244 if (uart_handle_break(port))
248 isrstatus &= port->read_status_mask;
249 isrstatus &= ~port->ignore_status_mask;
250 status_mask = port->read_status_mask;
251 status_mask &= ~port->ignore_status_mask;
254 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
255 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
257 if (uart_handle_break(port))
261 if (uart_handle_sysrq_char(port, data))
264 if (is_rxbs_support) {
265 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
266 && (status_mask & CDNS_UART_IXR_PARITY)) {
267 port->icount.parity++;
270 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
271 && (status_mask & CDNS_UART_IXR_PARITY)) {
272 port->icount.frame++;
276 if (isrstatus & CDNS_UART_IXR_PARITY) {
277 port->icount.parity++;
280 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
282 port->icount.frame++;
286 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
287 port->icount.overrun++;
288 tty_insert_flip_char(&port->state->port, 0,
291 tty_insert_flip_char(&port->state->port, data, status);
294 spin_unlock(&port->lock);
295 tty_flip_buffer_push(&port->state->port);
296 spin_lock(&port->lock);
300 * cdns_uart_handle_tx - Handle the bytes to be Txed.
301 * @dev_id: Id of the UART port
304 static void cdns_uart_handle_tx(void *dev_id)
306 struct uart_port *port = (struct uart_port *)dev_id;
307 unsigned int numbytes;
309 if (uart_circ_empty(&port->state->xmit)) {
310 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
312 numbytes = port->fifosize;
313 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
314 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
316 * Get the data from the UART circular buffer
317 * and write it to the cdns_uart's TX_FIFO
321 port->state->xmit.buf[port->state->xmit.
322 tail], port->membase + CDNS_UART_FIFO);
327 * Adjust the tail of the UART buffer and wrap
328 * the buffer if it reaches limit.
330 port->state->xmit.tail =
331 (port->state->xmit.tail + 1) &
332 (UART_XMIT_SIZE - 1);
337 if (uart_circ_chars_pending(
338 &port->state->xmit) < WAKEUP_CHARS)
339 uart_write_wakeup(port);
344 * cdns_uart_isr - Interrupt handler
346 * @dev_id: Id of the port
350 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
352 struct uart_port *port = (struct uart_port *)dev_id;
353 unsigned int isrstatus;
355 spin_lock(&port->lock);
357 /* Read the interrupt status register to determine which
358 * interrupt(s) is/are active and clear them.
360 isrstatus = readl(port->membase + CDNS_UART_ISR);
361 writel(isrstatus, port->membase + CDNS_UART_ISR);
363 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
364 cdns_uart_handle_tx(dev_id);
365 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
367 if (isrstatus & CDNS_UART_IXR_RXMASK)
368 cdns_uart_handle_rx(dev_id, isrstatus);
370 spin_unlock(&port->lock);
375 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
376 * @clk: UART module input clock
377 * @baud: Desired baud rate
378 * @rbdiv: BDIV value (return value)
379 * @rcd: CD value (return value)
380 * @div8: Value for clk_sel bit in mod (return value)
381 * Return: baud rate, requested baud when possible, or actual baud when there
382 * was too much error, zero if no valid divisors are found.
384 * Formula to obtain baud rate is
385 * baud_tx/rx rate = clk/CD * (BDIV + 1)
386 * input_clk = (Uart User Defined Clock or Apb Clock)
387 * depends on UCLKEN in MR Reg
388 * clk = input_clk or input_clk/8;
389 * depends on CLKS in MR reg
390 * CD and BDIV depends on values in
391 * baud rate generate register
392 * baud rate clock divisor register
394 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
395 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
398 unsigned int calc_baud;
399 unsigned int bestbaud = 0;
400 unsigned int bauderror;
401 unsigned int besterror = ~0;
403 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
410 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
411 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
412 if (cd < 1 || cd > CDNS_UART_CD_MAX)
415 calc_baud = clk / (cd * (bdiv + 1));
417 if (baud > calc_baud)
418 bauderror = baud - calc_baud;
420 bauderror = calc_baud - baud;
422 if (besterror > bauderror) {
425 bestbaud = calc_baud;
426 besterror = bauderror;
429 /* use the values when percent error is acceptable */
430 if (((besterror * 100) / baud) < 3)
437 * cdns_uart_set_baud_rate - Calculate and set the baud rate
438 * @port: Handle to the uart port structure
439 * @baud: Baud rate to set
440 * Return: baud rate, requested baud when possible, or actual baud when there
441 * was too much error, zero if no valid divisors are found.
443 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
446 unsigned int calc_baud;
447 u32 cd = 0, bdiv = 0;
450 struct cdns_uart *cdns_uart = port->private_data;
452 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
455 /* Write new divisors to hardware */
456 mreg = readl(port->membase + CDNS_UART_MR);
458 mreg |= CDNS_UART_MR_CLKSEL;
460 mreg &= ~CDNS_UART_MR_CLKSEL;
461 writel(mreg, port->membase + CDNS_UART_MR);
462 writel(cd, port->membase + CDNS_UART_BAUDGEN);
463 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
464 cdns_uart->baud = baud;
469 #ifdef CONFIG_COMMON_CLK
471 * cdns_uart_clk_notitifer_cb - Clock notifier callback
472 * @nb: Notifier block
473 * @event: Notify event
474 * @data: Notifier data
475 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
477 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
478 unsigned long event, void *data)
481 struct uart_port *port;
483 struct clk_notifier_data *ndata = data;
484 unsigned long flags = 0;
485 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
487 port = cdns_uart->port;
492 case PRE_RATE_CHANGE:
498 * Find out if current baud-rate can be achieved with new clock
501 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
502 &bdiv, &cd, &div8)) {
503 dev_warn(port->dev, "clock rate change rejected\n");
507 spin_lock_irqsave(&cdns_uart->port->lock, flags);
509 /* Disable the TX and RX to set baud rate */
510 ctrl_reg = readl(port->membase + CDNS_UART_CR);
511 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
512 writel(ctrl_reg, port->membase + CDNS_UART_CR);
514 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
518 case POST_RATE_CHANGE:
520 * Set clk dividers to generate correct baud with new clock
524 spin_lock_irqsave(&cdns_uart->port->lock, flags);
527 port->uartclk = ndata->new_rate;
529 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
532 case ABORT_RATE_CHANGE:
534 spin_lock_irqsave(&cdns_uart->port->lock, flags);
536 /* Set TX/RX Reset */
537 ctrl_reg = readl(port->membase + CDNS_UART_CR);
538 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
539 writel(ctrl_reg, port->membase + CDNS_UART_CR);
541 while (readl(port->membase + CDNS_UART_CR) &
542 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
546 * Clear the RX disable and TX disable bits and then set the TX
547 * enable bit and RX enable bit to enable the transmitter and
550 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
551 ctrl_reg = readl(port->membase + CDNS_UART_CR);
552 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
553 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
554 writel(ctrl_reg, port->membase + CDNS_UART_CR);
556 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
566 * cdns_uart_start_tx - Start transmitting bytes
567 * @port: Handle to the uart port structure
569 static void cdns_uart_start_tx(struct uart_port *port)
573 if (uart_tx_stopped(port))
577 * Set the TX enable bit and clear the TX disable bit to enable the
580 status = readl(port->membase + CDNS_UART_CR);
581 status &= ~CDNS_UART_CR_TX_DIS;
582 status |= CDNS_UART_CR_TX_EN;
583 writel(status, port->membase + CDNS_UART_CR);
585 if (uart_circ_empty(&port->state->xmit))
588 cdns_uart_handle_tx(port);
590 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
591 /* Enable the TX Empty interrupt */
592 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
596 * cdns_uart_stop_tx - Stop TX
597 * @port: Handle to the uart port structure
599 static void cdns_uart_stop_tx(struct uart_port *port)
603 regval = readl(port->membase + CDNS_UART_CR);
604 regval |= CDNS_UART_CR_TX_DIS;
605 /* Disable the transmitter */
606 writel(regval, port->membase + CDNS_UART_CR);
610 * cdns_uart_stop_rx - Stop RX
611 * @port: Handle to the uart port structure
613 static void cdns_uart_stop_rx(struct uart_port *port)
617 /* Disable RX IRQs */
618 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
620 /* Disable the receiver */
621 regval = readl(port->membase + CDNS_UART_CR);
622 regval |= CDNS_UART_CR_RX_DIS;
623 writel(regval, port->membase + CDNS_UART_CR);
627 * cdns_uart_tx_empty - Check whether TX is empty
628 * @port: Handle to the uart port structure
630 * Return: TIOCSER_TEMT on success, 0 otherwise
632 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
636 status = readl(port->membase + CDNS_UART_SR) &
637 CDNS_UART_SR_TXEMPTY;
638 return status ? TIOCSER_TEMT : 0;
642 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
643 * transmitting char breaks
644 * @port: Handle to the uart port structure
645 * @ctl: Value based on which start or stop decision is taken
647 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
652 spin_lock_irqsave(&port->lock, flags);
654 status = readl(port->membase + CDNS_UART_CR);
657 writel(CDNS_UART_CR_STARTBRK | status,
658 port->membase + CDNS_UART_CR);
660 if ((status & CDNS_UART_CR_STOPBRK) == 0)
661 writel(CDNS_UART_CR_STOPBRK | status,
662 port->membase + CDNS_UART_CR);
664 spin_unlock_irqrestore(&port->lock, flags);
668 * cdns_uart_set_termios - termios operations, handling data length, parity,
669 * stop bits, flow control, baud rate
670 * @port: Handle to the uart port structure
671 * @termios: Handle to the input termios structure
672 * @old: Values of the previously saved termios structure
674 static void cdns_uart_set_termios(struct uart_port *port,
675 struct ktermios *termios, struct ktermios *old)
677 unsigned int cval = 0;
678 unsigned int baud, minbaud, maxbaud;
680 unsigned int ctrl_reg, mode_reg;
682 spin_lock_irqsave(&port->lock, flags);
684 /* Wait for the transmit FIFO to empty before making changes */
685 if (!(readl(port->membase + CDNS_UART_CR) &
686 CDNS_UART_CR_TX_DIS)) {
687 while (!(readl(port->membase + CDNS_UART_SR) &
688 CDNS_UART_SR_TXEMPTY)) {
693 /* Disable the TX and RX to set baud rate */
694 ctrl_reg = readl(port->membase + CDNS_UART_CR);
695 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
696 writel(ctrl_reg, port->membase + CDNS_UART_CR);
699 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
700 * min and max baud should be calculated here based on port->uartclk.
701 * this way we get a valid baud and can safely call set_baud()
703 minbaud = port->uartclk /
704 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
705 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
706 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
707 baud = cdns_uart_set_baud_rate(port, baud);
708 if (tty_termios_baud_rate(termios))
709 tty_termios_encode_baud_rate(termios, baud, baud);
711 /* Update the per-port timeout. */
712 uart_update_timeout(port, termios->c_cflag, baud);
714 /* Set TX/RX Reset */
715 ctrl_reg = readl(port->membase + CDNS_UART_CR);
716 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
717 writel(ctrl_reg, port->membase + CDNS_UART_CR);
719 while (readl(port->membase + CDNS_UART_CR) &
720 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
724 * Clear the RX disable and TX disable bits and then set the TX enable
725 * bit and RX enable bit to enable the transmitter and receiver.
727 ctrl_reg = readl(port->membase + CDNS_UART_CR);
728 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
729 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
730 writel(ctrl_reg, port->membase + CDNS_UART_CR);
732 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
734 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
735 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
736 port->ignore_status_mask = 0;
738 if (termios->c_iflag & INPCK)
739 port->read_status_mask |= CDNS_UART_IXR_PARITY |
740 CDNS_UART_IXR_FRAMING;
742 if (termios->c_iflag & IGNPAR)
743 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
744 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
746 /* ignore all characters if CREAD is not set */
747 if ((termios->c_cflag & CREAD) == 0)
748 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
749 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
750 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
752 mode_reg = readl(port->membase + CDNS_UART_MR);
754 /* Handling Data Size */
755 switch (termios->c_cflag & CSIZE) {
757 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
760 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
764 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
765 termios->c_cflag &= ~CSIZE;
766 termios->c_cflag |= CS8;
770 /* Handling Parity and Stop Bits length */
771 if (termios->c_cflag & CSTOPB)
772 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
774 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
776 if (termios->c_cflag & PARENB) {
777 /* Mark or Space parity */
778 if (termios->c_cflag & CMSPAR) {
779 if (termios->c_cflag & PARODD)
780 cval |= CDNS_UART_MR_PARITY_MARK;
782 cval |= CDNS_UART_MR_PARITY_SPACE;
784 if (termios->c_cflag & PARODD)
785 cval |= CDNS_UART_MR_PARITY_ODD;
787 cval |= CDNS_UART_MR_PARITY_EVEN;
790 cval |= CDNS_UART_MR_PARITY_NONE;
792 cval |= mode_reg & 1;
793 writel(cval, port->membase + CDNS_UART_MR);
795 spin_unlock_irqrestore(&port->lock, flags);
799 * cdns_uart_startup - Called when an application opens a cdns_uart port
800 * @port: Handle to the uart port structure
802 * Return: 0 on success, negative errno otherwise
804 static int cdns_uart_startup(struct uart_port *port)
806 struct cdns_uart *cdns_uart = port->private_data;
810 unsigned int status = 0;
812 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
814 spin_lock_irqsave(&port->lock, flags);
816 /* Disable the TX and RX */
817 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
818 port->membase + CDNS_UART_CR);
820 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
823 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
824 port->membase + CDNS_UART_CR);
826 while (readl(port->membase + CDNS_UART_CR) &
827 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
831 * Clear the RX disable bit and then set the RX enable bit to enable
834 status = readl(port->membase + CDNS_UART_CR);
835 status &= ~CDNS_UART_CR_RX_DIS;
836 status |= CDNS_UART_CR_RX_EN;
837 writel(status, port->membase + CDNS_UART_CR);
839 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
842 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
843 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
844 port->membase + CDNS_UART_MR);
847 * Set the RX FIFO Trigger level to use most of the FIFO, but it
848 * can be tuned with a module parameter
850 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
853 * Receive Timeout register is enabled but it
854 * can be tuned with a module parameter
856 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
858 /* Clear out any pending interrupts before enabling them */
859 writel(readl(port->membase + CDNS_UART_ISR),
860 port->membase + CDNS_UART_ISR);
862 spin_unlock_irqrestore(&port->lock, flags);
864 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
866 dev_err(port->dev, "request_irq '%d' failed with %d\n",
871 /* Set the Interrupt Registers with desired interrupts */
873 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
874 port->membase + CDNS_UART_IER);
876 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
882 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
883 * @port: Handle to the uart port structure
885 static void cdns_uart_shutdown(struct uart_port *port)
890 spin_lock_irqsave(&port->lock, flags);
892 /* Disable interrupts */
893 status = readl(port->membase + CDNS_UART_IMR);
894 writel(status, port->membase + CDNS_UART_IDR);
895 writel(0xffffffff, port->membase + CDNS_UART_ISR);
897 /* Disable the TX and RX */
898 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
899 port->membase + CDNS_UART_CR);
901 spin_unlock_irqrestore(&port->lock, flags);
903 free_irq(port->irq, port);
907 * cdns_uart_type - Set UART type to cdns_uart port
908 * @port: Handle to the uart port structure
910 * Return: string on success, NULL otherwise
912 static const char *cdns_uart_type(struct uart_port *port)
914 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
918 * cdns_uart_verify_port - Verify the port params
919 * @port: Handle to the uart port structure
920 * @ser: Handle to the structure whose members are compared
922 * Return: 0 on success, negative errno otherwise.
924 static int cdns_uart_verify_port(struct uart_port *port,
925 struct serial_struct *ser)
927 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
929 if (port->irq != ser->irq)
931 if (ser->io_type != UPIO_MEM)
933 if (port->iobase != ser->port)
941 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
942 * called when the driver adds a cdns_uart port via
943 * uart_add_one_port()
944 * @port: Handle to the uart port structure
946 * Return: 0 on success, negative errno otherwise.
948 static int cdns_uart_request_port(struct uart_port *port)
950 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
955 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
956 if (!port->membase) {
957 dev_err(port->dev, "Unable to map registers\n");
958 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
965 * cdns_uart_release_port - Release UART port
966 * @port: Handle to the uart port structure
968 * Release the memory region attached to a cdns_uart port. Called when the
969 * driver removes a cdns_uart port via uart_remove_one_port().
971 static void cdns_uart_release_port(struct uart_port *port)
973 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
974 iounmap(port->membase);
975 port->membase = NULL;
979 * cdns_uart_config_port - Configure UART port
980 * @port: Handle to the uart port structure
983 static void cdns_uart_config_port(struct uart_port *port, int flags)
985 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
986 port->type = PORT_XUARTPS;
990 * cdns_uart_get_mctrl - Get the modem control state
991 * @port: Handle to the uart port structure
993 * Return: the modem control state
995 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
997 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1000 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1005 val = readl(port->membase + CDNS_UART_MODEMCR);
1006 mode_reg = readl(port->membase + CDNS_UART_MR);
1008 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1009 CDNS_UART_MODEMCR_FCM);
1010 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1012 if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1013 val |= CDNS_UART_MODEMCR_FCM;
1014 if (mctrl & TIOCM_LOOP)
1015 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1017 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1019 writel(val, port->membase + CDNS_UART_MODEMCR);
1020 writel(mode_reg, port->membase + CDNS_UART_MR);
1023 #ifdef CONFIG_CONSOLE_POLL
1024 static int cdns_uart_poll_get_char(struct uart_port *port)
1027 unsigned long flags;
1029 spin_lock_irqsave(&port->lock, flags);
1031 /* Check if FIFO is empty */
1032 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1034 else /* Read a character */
1035 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1037 spin_unlock_irqrestore(&port->lock, flags);
1042 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1044 unsigned long flags;
1046 spin_lock_irqsave(&port->lock, flags);
1048 /* Wait until FIFO is empty */
1049 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1052 /* Write a character */
1053 writel(c, port->membase + CDNS_UART_FIFO);
1055 /* Wait until FIFO is empty */
1056 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1059 spin_unlock_irqrestore(&port->lock, flags);
1065 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1066 unsigned int oldstate)
1069 case UART_PM_STATE_OFF:
1070 pm_runtime_mark_last_busy(port->dev);
1071 pm_runtime_put_autosuspend(port->dev);
1074 pm_runtime_get_sync(port->dev);
1079 static const struct uart_ops cdns_uart_ops = {
1080 .set_mctrl = cdns_uart_set_mctrl,
1081 .get_mctrl = cdns_uart_get_mctrl,
1082 .start_tx = cdns_uart_start_tx,
1083 .stop_tx = cdns_uart_stop_tx,
1084 .stop_rx = cdns_uart_stop_rx,
1085 .tx_empty = cdns_uart_tx_empty,
1086 .break_ctl = cdns_uart_break_ctl,
1087 .set_termios = cdns_uart_set_termios,
1088 .startup = cdns_uart_startup,
1089 .shutdown = cdns_uart_shutdown,
1091 .type = cdns_uart_type,
1092 .verify_port = cdns_uart_verify_port,
1093 .request_port = cdns_uart_request_port,
1094 .release_port = cdns_uart_release_port,
1095 .config_port = cdns_uart_config_port,
1096 #ifdef CONFIG_CONSOLE_POLL
1097 .poll_get_char = cdns_uart_poll_get_char,
1098 .poll_put_char = cdns_uart_poll_put_char,
1102 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1104 * cdns_uart_console_putchar - write the character to the FIFO buffer
1105 * @port: Handle to the uart port structure
1106 * @ch: Character to be written
1108 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1110 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1112 writel(ch, port->membase + CDNS_UART_FIFO);
1115 static void cdns_early_write(struct console *con, const char *s,
1118 struct earlycon_device *dev = con->data;
1120 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1123 static int __init cdns_early_console_setup(struct earlycon_device *device,
1126 struct uart_port *port = &device->port;
1131 /* initialise control register */
1132 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1133 port->membase + CDNS_UART_CR);
1135 /* only set baud if specified on command line - otherwise
1136 * assume it has been initialized by a boot loader.
1138 if (port->uartclk && device->baud) {
1139 u32 cd = 0, bdiv = 0;
1143 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1145 mr = CDNS_UART_MR_PARITY_NONE;
1147 mr |= CDNS_UART_MR_CLKSEL;
1149 writel(mr, port->membase + CDNS_UART_MR);
1150 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1151 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1154 device->con->write = cdns_early_write;
1158 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1159 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1160 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1161 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1164 /* Static pointer to console port */
1165 static struct uart_port *console_port;
1168 * cdns_uart_console_write - perform write operation
1169 * @co: Console handle
1170 * @s: Pointer to character array
1171 * @count: No of characters
1173 static void cdns_uart_console_write(struct console *co, const char *s,
1176 struct uart_port *port = console_port;
1177 unsigned long flags;
1178 unsigned int imr, ctrl;
1183 else if (oops_in_progress)
1184 locked = spin_trylock_irqsave(&port->lock, flags);
1186 spin_lock_irqsave(&port->lock, flags);
1188 /* save and disable interrupt */
1189 imr = readl(port->membase + CDNS_UART_IMR);
1190 writel(imr, port->membase + CDNS_UART_IDR);
1193 * Make sure that the tx part is enabled. Set the TX enable bit and
1194 * clear the TX disable bit to enable the transmitter.
1196 ctrl = readl(port->membase + CDNS_UART_CR);
1197 ctrl &= ~CDNS_UART_CR_TX_DIS;
1198 ctrl |= CDNS_UART_CR_TX_EN;
1199 writel(ctrl, port->membase + CDNS_UART_CR);
1201 uart_console_write(port, s, count, cdns_uart_console_putchar);
1202 while ((readl(port->membase + CDNS_UART_SR) &
1203 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1204 CDNS_UART_SR_TXEMPTY)
1207 /* restore interrupt state */
1208 writel(imr, port->membase + CDNS_UART_IER);
1211 spin_unlock_irqrestore(&port->lock, flags);
1215 * cdns_uart_console_setup - Initialize the uart to default config
1216 * @co: Console handle
1217 * @options: Initial settings of uart
1219 * Return: 0 on success, negative errno otherwise.
1221 static int cdns_uart_console_setup(struct console *co, char *options)
1223 struct uart_port *port = console_port;
1230 if (!port->membase) {
1231 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1237 uart_parse_options(options, &baud, &parity, &bits, &flow);
1239 return uart_set_options(port, co, baud, parity, bits, flow);
1241 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1243 #ifdef CONFIG_PM_SLEEP
1245 * cdns_uart_suspend - suspend event
1246 * @device: Pointer to the device structure
1250 static int cdns_uart_suspend(struct device *device)
1252 struct uart_port *port = dev_get_drvdata(device);
1253 struct cdns_uart *cdns_uart = port->private_data;
1256 may_wake = device_may_wakeup(device);
1258 if (console_suspend_enabled && uart_console(port) && may_wake) {
1259 unsigned long flags = 0;
1261 spin_lock_irqsave(&port->lock, flags);
1262 /* Empty the receive FIFO 1st before making changes */
1263 while (!(readl(port->membase + CDNS_UART_SR) &
1264 CDNS_UART_SR_RXEMPTY))
1265 readl(port->membase + CDNS_UART_FIFO);
1266 /* set RX trigger level to 1 */
1267 writel(1, port->membase + CDNS_UART_RXWM);
1268 /* disable RX timeout interrups */
1269 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1270 spin_unlock_irqrestore(&port->lock, flags);
1274 * Call the API provided in serial_core.c file which handles
1277 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1281 * cdns_uart_resume - Resume after a previous suspend
1282 * @device: Pointer to the device structure
1286 static int cdns_uart_resume(struct device *device)
1288 struct uart_port *port = dev_get_drvdata(device);
1289 struct cdns_uart *cdns_uart = port->private_data;
1290 unsigned long flags = 0;
1294 may_wake = device_may_wakeup(device);
1296 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1297 clk_enable(cdns_uart->pclk);
1298 clk_enable(cdns_uart->uartclk);
1300 spin_lock_irqsave(&port->lock, flags);
1302 /* Set TX/RX Reset */
1303 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1304 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1305 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1306 while (readl(port->membase + CDNS_UART_CR) &
1307 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1310 /* restore rx timeout value */
1311 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1313 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1314 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1315 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1316 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1318 clk_disable(cdns_uart->uartclk);
1319 clk_disable(cdns_uart->pclk);
1320 spin_unlock_irqrestore(&port->lock, flags);
1322 spin_lock_irqsave(&port->lock, flags);
1323 /* restore original rx trigger level */
1324 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1325 /* enable RX timeout interrupt */
1326 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1327 spin_unlock_irqrestore(&port->lock, flags);
1330 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1332 #endif /* ! CONFIG_PM_SLEEP */
1333 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1335 struct uart_port *port = dev_get_drvdata(dev);
1336 struct cdns_uart *cdns_uart = port->private_data;
1338 clk_disable(cdns_uart->uartclk);
1339 clk_disable(cdns_uart->pclk);
1343 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1345 struct uart_port *port = dev_get_drvdata(dev);
1346 struct cdns_uart *cdns_uart = port->private_data;
1348 clk_enable(cdns_uart->pclk);
1349 clk_enable(cdns_uart->uartclk);
1353 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1354 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1355 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1356 cdns_runtime_resume, NULL)
1359 static const struct cdns_platform_data zynqmp_uart_def = {
1360 .quirks = CDNS_UART_RXBS_SUPPORT, };
1362 /* Match table for of_platform binding */
1363 static const struct of_device_id cdns_uart_of_match[] = {
1364 { .compatible = "xlnx,xuartps", },
1365 { .compatible = "cdns,uart-r1p8", },
1366 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1367 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1370 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1373 * Maximum number of instances without alias IDs but if there is alias
1374 * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1376 #define MAX_UART_INSTANCES 32
1378 /* Stores static aliases list */
1379 static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1380 static int alias_bitmap_initialized;
1382 /* Stores actual bitmap of allocated IDs with alias IDs together */
1383 static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1384 /* Protect bitmap operations to have unique IDs */
1385 static DEFINE_MUTEX(bitmap_lock);
1387 static int cdns_get_id(struct platform_device *pdev)
1391 mutex_lock(&bitmap_lock);
1393 /* Alias list is stable that's why get alias bitmap only once */
1394 if (!alias_bitmap_initialized) {
1395 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1396 alias_bitmap, MAX_UART_INSTANCES);
1397 if (ret && ret != -EOVERFLOW) {
1398 mutex_unlock(&bitmap_lock);
1402 alias_bitmap_initialized++;
1405 /* Make sure that alias ID is not taken by instance without alias */
1406 bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1408 dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1409 MAX_UART_INSTANCES, bitmap);
1411 /* Look for a serialN alias */
1412 id = of_alias_get_id(pdev->dev.of_node, "serial");
1414 dev_warn(&pdev->dev,
1415 "No serial alias passed. Using the first free id\n");
1418 * Start with id 0 and check if there is no serial0 alias
1419 * which points to device which is compatible with this driver.
1420 * If alias exists then try next free position.
1425 dev_info(&pdev->dev, "Checking id %d\n", id);
1426 id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1428 /* No free empty instance */
1429 if (id == MAX_UART_INSTANCES) {
1430 dev_err(&pdev->dev, "No free ID\n");
1431 mutex_unlock(&bitmap_lock);
1435 dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1436 /* Check if ID is empty */
1437 if (!test_and_set_bit(id, bitmap)) {
1438 /* Break the loop if bit is taken */
1440 "Selected ID %d allocation passed\n",
1445 "Selected ID %d allocation failed\n", id);
1446 /* if taking bit fails then try next one */
1451 mutex_unlock(&bitmap_lock);
1457 * cdns_uart_probe - Platform driver probe
1458 * @pdev: Pointer to the platform device structure
1460 * Return: 0 on success, negative errno otherwise
1462 static int cdns_uart_probe(struct platform_device *pdev)
1465 struct uart_port *port;
1466 struct resource *res;
1467 struct cdns_uart *cdns_uart_data;
1468 const struct of_device_id *match;
1469 struct uart_driver *cdns_uart_uart_driver;
1471 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1472 struct console *cdns_uart_console;
1475 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1477 if (!cdns_uart_data)
1479 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1483 cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1484 sizeof(*cdns_uart_uart_driver),
1486 if (!cdns_uart_uart_driver)
1489 cdns_uart_data->id = cdns_get_id(pdev);
1490 if (cdns_uart_data->id < 0)
1491 return cdns_uart_data->id;
1493 /* There is a need to use unique driver name */
1494 driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1495 CDNS_UART_NAME, cdns_uart_data->id);
1501 cdns_uart_uart_driver->owner = THIS_MODULE;
1502 cdns_uart_uart_driver->driver_name = driver_name;
1503 cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1504 cdns_uart_uart_driver->major = CDNS_UART_MAJOR;
1505 cdns_uart_uart_driver->minor = cdns_uart_data->id;
1506 cdns_uart_uart_driver->nr = 1;
1508 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1509 cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1511 if (!cdns_uart_console) {
1516 strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1517 sizeof(cdns_uart_console->name));
1518 cdns_uart_console->index = cdns_uart_data->id;
1519 cdns_uart_console->write = cdns_uart_console_write;
1520 cdns_uart_console->device = uart_console_device;
1521 cdns_uart_console->setup = cdns_uart_console_setup;
1522 cdns_uart_console->flags = CON_PRINTBUFFER;
1523 cdns_uart_console->data = cdns_uart_uart_driver;
1524 cdns_uart_uart_driver->cons = cdns_uart_console;
1527 rc = uart_register_driver(cdns_uart_uart_driver);
1529 dev_err(&pdev->dev, "Failed to register driver\n");
1533 cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1536 * Setting up proper name_base needs to be done after uart
1537 * registration because tty_driver structure is not filled.
1538 * name_base is 0 by default.
1540 cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1542 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1543 if (match && match->data) {
1544 const struct cdns_platform_data *data = match->data;
1546 cdns_uart_data->quirks = data->quirks;
1549 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1550 if (IS_ERR(cdns_uart_data->pclk)) {
1551 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1552 if (!IS_ERR(cdns_uart_data->pclk))
1553 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1555 if (IS_ERR(cdns_uart_data->pclk)) {
1556 dev_err(&pdev->dev, "pclk clock not found.\n");
1557 rc = PTR_ERR(cdns_uart_data->pclk);
1558 goto err_out_unregister_driver;
1561 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1562 if (IS_ERR(cdns_uart_data->uartclk)) {
1563 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1564 if (!IS_ERR(cdns_uart_data->uartclk))
1565 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1567 if (IS_ERR(cdns_uart_data->uartclk)) {
1568 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1569 rc = PTR_ERR(cdns_uart_data->uartclk);
1570 goto err_out_unregister_driver;
1573 rc = clk_prepare_enable(cdns_uart_data->pclk);
1575 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1576 goto err_out_unregister_driver;
1578 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1580 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1581 goto err_out_clk_dis_pclk;
1584 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1587 goto err_out_clk_disable;
1590 irq = platform_get_irq(pdev, 0);
1593 goto err_out_clk_disable;
1596 #ifdef CONFIG_COMMON_CLK
1597 cdns_uart_data->clk_rate_change_nb.notifier_call =
1598 cdns_uart_clk_notifier_cb;
1599 if (clk_notifier_register(cdns_uart_data->uartclk,
1600 &cdns_uart_data->clk_rate_change_nb))
1601 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1604 /* At this point, we've got an empty uart_port struct, initialize it */
1605 spin_lock_init(&port->lock);
1606 port->type = PORT_UNKNOWN;
1607 port->iotype = UPIO_MEM32;
1608 port->flags = UPF_BOOT_AUTOCONF;
1609 port->ops = &cdns_uart_ops;
1610 port->fifosize = CDNS_UART_FIFO_SIZE;
1613 * Register the port.
1614 * This function also registers this device with the tty layer
1615 * and triggers invocation of the config_port() entry point.
1617 port->mapbase = res->start;
1619 port->dev = &pdev->dev;
1620 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1621 port->private_data = cdns_uart_data;
1622 cdns_uart_data->port = port;
1623 platform_set_drvdata(pdev, port);
1625 pm_runtime_use_autosuspend(&pdev->dev);
1626 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1627 pm_runtime_set_active(&pdev->dev);
1628 pm_runtime_enable(&pdev->dev);
1629 device_init_wakeup(port->dev, true);
1631 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1633 * If console hasn't been found yet try to assign this port
1634 * because it is required to be assigned for console setup function.
1635 * If register_console() don't assign value, then console_port pointer
1639 console_port = port;
1642 rc = uart_add_one_port(cdns_uart_uart_driver, port);
1645 "uart_add_one_port() failed; err=%i\n", rc);
1646 goto err_out_pm_disable;
1649 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1650 /* This is not port which is used for console that's why clean it up */
1651 if (console_port == port &&
1652 !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1653 console_port = NULL;
1659 pm_runtime_disable(&pdev->dev);
1660 pm_runtime_set_suspended(&pdev->dev);
1661 pm_runtime_dont_use_autosuspend(&pdev->dev);
1662 #ifdef CONFIG_COMMON_CLK
1663 clk_notifier_unregister(cdns_uart_data->uartclk,
1664 &cdns_uart_data->clk_rate_change_nb);
1666 err_out_clk_disable:
1667 clk_disable_unprepare(cdns_uart_data->uartclk);
1668 err_out_clk_dis_pclk:
1669 clk_disable_unprepare(cdns_uart_data->pclk);
1670 err_out_unregister_driver:
1671 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1673 mutex_lock(&bitmap_lock);
1674 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1675 clear_bit(cdns_uart_data->id, bitmap);
1676 mutex_unlock(&bitmap_lock);
1681 * cdns_uart_remove - called when the platform driver is unregistered
1682 * @pdev: Pointer to the platform device structure
1684 * Return: 0 on success, negative errno otherwise
1686 static int cdns_uart_remove(struct platform_device *pdev)
1688 struct uart_port *port = platform_get_drvdata(pdev);
1689 struct cdns_uart *cdns_uart_data = port->private_data;
1692 /* Remove the cdns_uart port from the serial core */
1693 #ifdef CONFIG_COMMON_CLK
1694 clk_notifier_unregister(cdns_uart_data->uartclk,
1695 &cdns_uart_data->clk_rate_change_nb);
1697 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1699 mutex_lock(&bitmap_lock);
1700 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1701 clear_bit(cdns_uart_data->id, bitmap);
1702 mutex_unlock(&bitmap_lock);
1703 clk_disable_unprepare(cdns_uart_data->uartclk);
1704 clk_disable_unprepare(cdns_uart_data->pclk);
1705 pm_runtime_disable(&pdev->dev);
1706 pm_runtime_set_suspended(&pdev->dev);
1707 pm_runtime_dont_use_autosuspend(&pdev->dev);
1708 device_init_wakeup(&pdev->dev, false);
1710 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1711 if (console_port == port)
1712 console_port = NULL;
1715 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1719 static struct platform_driver cdns_uart_platform_driver = {
1720 .probe = cdns_uart_probe,
1721 .remove = cdns_uart_remove,
1723 .name = CDNS_UART_NAME,
1724 .of_match_table = cdns_uart_of_match,
1725 .pm = &cdns_uart_dev_pm_ops,
1726 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1730 static int __init cdns_uart_init(void)
1732 /* Register the platform driver */
1733 return platform_driver_register(&cdns_uart_platform_driver);
1736 static void __exit cdns_uart_exit(void)
1738 /* Unregister the platform driver */
1739 platform_driver_unregister(&cdns_uart_platform_driver);
1742 arch_initcall(cdns_uart_init);
1743 module_exit(cdns_uart_exit);
1745 MODULE_DESCRIPTION("Driver for Cadence UART");
1746 MODULE_AUTHOR("Xilinx Inc.");
1747 MODULE_LICENSE("GPL");