drivers/usb/dwc2/core_intr.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * core_intr.c - DesignWare HS OTG Controller common interrupt handling
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * This file contains the common interrupt handlers
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/spinlock.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  58 {
  59         switch (hsotg->op_state) {
  60         case OTG_STATE_A_HOST:
  61                 return "a_host";
  62         case OTG_STATE_A_SUSPEND:
  63                 return "a_suspend";
  64         case OTG_STATE_A_PERIPHERAL:
  65                 return "a_peripheral";
  66         case OTG_STATE_B_PERIPHERAL:
  67                 return "b_peripheral";
  68         case OTG_STATE_B_HOST:
  69                 return "b_host";
  70         default:
  71                 return "unknown";
  72         }
  73 }
  74
  75 /**
  76  * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  77  * When the PRTINT interrupt fires, there are certain status bits in the Host
  78  * Port that needs to get cleared.
  79  *
  80  * @hsotg: Programming view of DWC_otg controller
  81  */
  82 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  83 {
  84         u32 hprt0 = dwc2_readl(hsotg, HPRT0);
  85
  86         if (hprt0 & HPRT0_ENACHG) {
  87                 hprt0 &= ~HPRT0_ENA;
  88                 dwc2_writel(hsotg, hprt0, HPRT0);
  89         }
  90 }
  91
  92 /**
  93  * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  94  *
  95  * @hsotg: Programming view of DWC_otg controller
  96  */
  97 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  98 {
  99         /* Clear interrupt */
 100         dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
 101
 102         dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
 103                  dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 104 }
 105
 106 /**
 107  * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
 108  * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
 109  *
 110  * @hsotg: Programming view of DWC_otg controller
 111  */
 112 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
 113 {
 114         u32 gotgint;
 115         u32 gotgctl;
 116         u32 gintmsk;
 117
 118         gotgint = dwc2_readl(hsotg, GOTGINT);
 119         gotgctl = dwc2_readl(hsotg, GOTGCTL);
 120         dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
 121                 dwc2_op_state_str(hsotg));
 122
 123         if (gotgint & GOTGINT_SES_END_DET) {
 124                 dev_dbg(hsotg->dev,
 125                         " ++OTG Interrupt: Session End Detected++ (%s)\n",
 126                         dwc2_op_state_str(hsotg));
 127                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 128
 129                 if (dwc2_is_device_mode(hsotg))
 130                         dwc2_hsotg_disconnect(hsotg);
 131
 132                 if (hsotg->op_state == OTG_STATE_B_HOST) {
 133                         hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 134                 } else {
 135                         /*
 136                          * If not B_HOST and Device HNP still set, HNP did
 137                          * not succeed!
 138                          */
 139                         if (gotgctl & GOTGCTL_DEVHNPEN) {
 140                                 dev_dbg(hsotg->dev, "Session End Detected\n");
 141                                 dev_err(hsotg->dev,
 142                                         "Device Not Connected/Responding!\n");
 143                         }
 144
 145                         /*
 146                          * If Session End Detected the B-Cable has been
 147                          * disconnected
 148                          */
 149                         /* Reset to a clean state */
 150                         hsotg->lx_state = DWC2_L0;
 151                 }
 152
 153                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 154                 gotgctl &= ~GOTGCTL_DEVHNPEN;
 155                 dwc2_writel(hsotg, gotgctl, GOTGCTL);
 156         }
 157
 158         if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
 159                 dev_dbg(hsotg->dev,
 160                         " ++OTG Interrupt: Session Request Success Status Change++\n");
 161                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 162                 if (gotgctl & GOTGCTL_SESREQSCS) {
 163                         if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
 164                             hsotg->params.i2c_enable) {
 165                                 hsotg->srp_success = 1;
 166                         } else {
 167                                 /* Clear Session Request */
 168                                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 169                                 gotgctl &= ~GOTGCTL_SESREQ;
 170                                 dwc2_writel(hsotg, gotgctl, GOTGCTL);
 171                         }
 172                 }
 173         }
 174
 175         if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
 176                 /*
 177                  * Print statements during the HNP interrupt handling
 178                  * can cause it to fail
 179                  */
 180                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 181                 /*
 182                  * WA for 3.00a- HW is not setting cur_mode, even sometimes
 183                  * this does not help
 184                  */
 185                 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
 186                         udelay(100);
 187                 if (gotgctl & GOTGCTL_HSTNEGSCS) {
 188                         if (dwc2_is_host_mode(hsotg)) {
 189                                 hsotg->op_state = OTG_STATE_B_HOST;
 190                                 /*
 191                                  * Need to disable SOF interrupt immediately.
 192                                  * When switching from device to host, the PCD
 193                                  * interrupt handler won't handle the interrupt
 194                                  * if host mode is already set. The HCD
 195                                  * interrupt handler won't get called if the
 196                                  * HCD state is HALT. This means that the
 197                                  * interrupt does not get handled and Linux
 198                                  * complains loudly.
 199                                  */
 200                                 gintmsk = dwc2_readl(hsotg, GINTMSK);
 201                                 gintmsk &= ~GINTSTS_SOF;
 202                                 dwc2_writel(hsotg, gintmsk, GINTMSK);
 203
 204                                 /*
 205                                  * Call callback function with spin lock
 206                                  * released
 207                                  */
 208                                 spin_unlock(&hsotg->lock);
 209
 210                                 /* Initialize the Core for Host mode */
 211                                 dwc2_hcd_start(hsotg);
 212                                 spin_lock(&hsotg->lock);
 213                                 hsotg->op_state = OTG_STATE_B_HOST;
 214                         }
 215                 } else {
 216                         gotgctl = dwc2_readl(hsotg, GOTGCTL);
 217                         gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
 218                         dwc2_writel(hsotg, gotgctl, GOTGCTL);
 219                         dev_dbg(hsotg->dev, "HNP Failed\n");
 220                         dev_err(hsotg->dev,
 221                                 "Device Not Connected/Responding\n");
 222                 }
 223         }
 224
 225         if (gotgint & GOTGINT_HST_NEG_DET) {
 226                 /*
 227                  * The disconnect interrupt is set at the same time as
 228                  * Host Negotiation Detected. During the mode switch all
 229                  * interrupts are cleared so the disconnect interrupt
 230                  * handler will not get executed.
 231                  */
 232                 dev_dbg(hsotg->dev,
 233                         " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
 234                         (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
 235                 if (dwc2_is_device_mode(hsotg)) {
 236                         dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
 237                                 hsotg->op_state);
 238                         spin_unlock(&hsotg->lock);
 239                         dwc2_hcd_disconnect(hsotg, false);
 240                         spin_lock(&hsotg->lock);
 241                         hsotg->op_state = OTG_STATE_A_PERIPHERAL;
 242                 } else {
 243                         /* Need to disable SOF interrupt immediately */
 244                         gintmsk = dwc2_readl(hsotg, GINTMSK);
 245                         gintmsk &= ~GINTSTS_SOF;
 246                         dwc2_writel(hsotg, gintmsk, GINTMSK);
 247                         spin_unlock(&hsotg->lock);
 248                         dwc2_hcd_start(hsotg);
 249                         spin_lock(&hsotg->lock);
 250                         hsotg->op_state = OTG_STATE_A_HOST;
 251                 }
 252         }
 253
 254         if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
 255                 dev_dbg(hsotg->dev,
 256                         " ++OTG Interrupt: A-Device Timeout Change++\n");
 257         if (gotgint & GOTGINT_DBNCE_DONE)
 258                 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
 259
 260         /* Clear GOTGINT */
 261         dwc2_writel(hsotg, gotgint, GOTGINT);
 262 }
 263
 264 /**
 265  * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
 266  * Change Interrupt
 267  *
 268  * @hsotg: Programming view of DWC_otg controller
 269  *
 270  * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
 271  * Device to Host Mode transition or a Host to Device Mode transition. This only
 272  * occurs when the cable is connected/removed from the PHY connector.
 273  */
 274 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
 275 {
 276         u32 gintmsk;
 277
 278         /* Clear interrupt */
 279         dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
 280
 281         /* Need to disable SOF interrupt immediately */
 282         gintmsk = dwc2_readl(hsotg, GINTMSK);
 283         gintmsk &= ~GINTSTS_SOF;
 284         dwc2_writel(hsotg, gintmsk, GINTMSK);
 285
 286         dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++  (%s)\n",
 287                 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 288
 289         /*
 290          * Need to schedule a work, as there are possible DELAY function calls.
 291          */
 292         if (hsotg->wq_otg)
 293                 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
 294 }
 295
 296 /**
 297  * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
 298  * initiating the Session Request Protocol to request the host to turn on bus
 299  * power so a new session can begin
 300  *
 301  * @hsotg: Programming view of DWC_otg controller
 302  *
 303  * This handler responds by turning on bus power. If the DWC_otg controller is
 304  * in low power mode, this handler brings the controller out of low power mode
 305  * before turning on bus power.
 306  */
 307 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 308 {
 309         int ret;
 310
 311         /* Clear interrupt */
 312         dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
 313
 314         dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
 315                 hsotg->lx_state);
 316
 317         if (dwc2_is_device_mode(hsotg)) {
 318                 if (hsotg->lx_state == DWC2_L2) {
 319                         ret = dwc2_exit_partial_power_down(hsotg, true);
 320                         if (ret && (ret != -ENOTSUPP))
 321                                 dev_err(hsotg->dev,
 322                                         "exit power_down failed\n");
 323                 }
 324
 325                 /*
 326                  * Report disconnect if there is any previous session
 327                  * established
 328                  */
 329                 dwc2_hsotg_disconnect(hsotg);
 330         }
 331 }
 332
 333 /**
 334  * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
 335  *
 336  * @hsotg: Programming view of DWC_otg controller
 337  *
 338  */
 339 static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
 340 {
 341         u32 glpmcfg;
 342         u32 i = 0;
 343
 344         if (hsotg->lx_state != DWC2_L1) {
 345                 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
 346                 return;
 347         }
 348
 349         glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 350         if (dwc2_is_device_mode(hsotg)) {
 351                 dev_dbg(hsotg->dev, "Exit from L1 state\n");
 352                 glpmcfg &= ~GLPMCFG_ENBLSLPM;
 353                 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
 354                 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
 355
 356                 do {
 357                         glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 358
 359                         if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
 360                                          GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
 361                                 break;
 362
 363                         udelay(1);
 364                 } while (++i < 200);
 365
 366                 if (i == 200) {
 367                         dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
 368                         return;
 369                 }
 370                 dwc2_gadget_init_lpm(hsotg);
 371         } else {
 372                 /* TODO */
 373                 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
 374                 return;
 375         }
 376
 377         /* Change to L0 state */
 378         hsotg->lx_state = DWC2_L0;
 379
 380         /* Inform gadget to exit from L1 */
 381         call_gadget(hsotg, resume);
 382 }
 383
 384 /*
 385  * This interrupt indicates that the DWC_otg controller has detected a
 386  * resume or remote wakeup sequence. If the DWC_otg controller is in
 387  * low power mode, the handler must brings the controller out of low
 388  * power mode. The controller automatically begins resume signaling.
 389  * The handler schedules a time to stop resume signaling.
 390  */
 391 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 392 {
 393         int ret;
 394
 395         /* Clear interrupt */
 396         dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
 397
 398         dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
 399         dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
 400
 401         if (hsotg->lx_state == DWC2_L1) {
 402                 dwc2_wakeup_from_lpm_l1(hsotg);
 403                 return;
 404         }
 405
 406         if (dwc2_is_device_mode(hsotg)) {
 407                 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
 408                         dwc2_readl(hsotg, DSTS));
 409                 if (hsotg->lx_state == DWC2_L2) {
 410                         u32 dctl = dwc2_readl(hsotg, DCTL);
 411
 412                         /* Clear Remote Wakeup Signaling */
 413                         dctl &= ~DCTL_RMTWKUPSIG;
 414                         dwc2_writel(hsotg, dctl, DCTL);
 415                         ret = dwc2_exit_partial_power_down(hsotg, true);
 416                         if (ret && (ret != -ENOTSUPP))
 417                                 dev_err(hsotg->dev, "exit power_down failed\n");
 418
 419                         call_gadget(hsotg, resume);
 420                 }
 421                 /* Change to L0 state */
 422                 hsotg->lx_state = DWC2_L0;
 423         } else {
 424                 if (hsotg->params.power_down)
 425                         return;
 426
 427                 if (hsotg->lx_state != DWC2_L1) {
 428                         u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
 429
 430                         /* Restart the Phy Clock */
 431                         pcgcctl &= ~PCGCTL_STOPPCLK;
 432                         dwc2_writel(hsotg, pcgcctl, PCGCTL);
 433
 434                         /*
 435                          * If we've got this quirk then the PHY is stuck upon
 436                          * wakeup.  Assert reset.  This will propagate out and
 437                          * eventually we'll re-enumerate the device.  Not great
 438                          * but the best we can do.  We can't call phy_reset()
 439                          * at interrupt time but there's no hurry, so we'll
 440                          * schedule it for later.
 441                          */
 442                         if (hsotg->reset_phy_on_wake)
 443                                 dwc2_host_schedule_phy_reset(hsotg);
 444
 445                         mod_timer(&hsotg->wkp_timer,
 446                                   jiffies + msecs_to_jiffies(71));
 447                 } else {
 448                         /* Change to L0 state */
 449                         hsotg->lx_state = DWC2_L0;
 450                 }
 451         }
 452 }
 453
 454 /*
 455  * This interrupt indicates that a device has been disconnected from the
 456  * root port
 457  */
 458 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
 459 {
 460         dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
 461
 462         dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
 463                 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
 464                 dwc2_op_state_str(hsotg));
 465
 466         if (hsotg->op_state == OTG_STATE_A_HOST)
 467                 dwc2_hcd_disconnect(hsotg, false);
 468 }
 469
 470 /*
 471  * This interrupt indicates that SUSPEND state has been detected on the USB.
 472  *
 473  * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
 474  * to "a_host".
 475  *
 476  * When power management is enabled the core will be put in low power mode.
 477  */
 478 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
 479 {
 480         u32 dsts;
 481         int ret;
 482
 483         /* Clear interrupt */
 484         dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
 485
 486         dev_dbg(hsotg->dev, "USB SUSPEND\n");
 487
 488         if (dwc2_is_device_mode(hsotg)) {
 489                 /*
 490                  * Check the Device status register to determine if the Suspend
 491                  * state is active
 492                  */
 493                 dsts = dwc2_readl(hsotg, DSTS);
 494                 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
 495                 dev_dbg(hsotg->dev,
 496                         "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
 497                         !!(dsts & DSTS_SUSPSTS),
 498                         hsotg->hw_params.power_optimized,
 499                         hsotg->hw_params.hibernation);
 500
 501                 /* Ignore suspend request before enumeration */
 502                 if (!dwc2_is_device_connected(hsotg)) {
 503                         dev_dbg(hsotg->dev,
 504                                 "ignore suspend request before enumeration\n");
 505                         return;
 506                 }
 507                 if (dsts & DSTS_SUSPSTS) {
 508                         if (hsotg->hw_params.power_optimized) {
 509                                 ret = dwc2_enter_partial_power_down(hsotg);
 510                                 if (ret) {
 511                                         if (ret != -ENOTSUPP)
 512                                                 dev_err(hsotg->dev,
 513                                                         "%s: enter partial_power_down failed\n",
 514                                                         __func__);
 515                                         goto skip_power_saving;
 516                                 }
 517
 518                                 udelay(100);
 519
 520                                 /* Ask phy to be suspended */
 521                                 if (!IS_ERR_OR_NULL(hsotg->uphy))
 522                                         usb_phy_set_suspend(hsotg->uphy, true);
 523                         }
 524
 525                         if (hsotg->hw_params.hibernation) {
 526                                 ret = dwc2_enter_hibernation(hsotg, 0);
 527                                 if (ret && ret != -ENOTSUPP)
 528                                         dev_err(hsotg->dev,
 529                                                 "%s: enter hibernation failed\n",
 530                                                 __func__);
 531                         }
 532 skip_power_saving:
 533                         /*
 534                          * Change to L2 (suspend) state before releasing
 535                          * spinlock
 536                          */
 537                         hsotg->lx_state = DWC2_L2;
 538
 539                         /* Call gadget suspend callback */
 540                         call_gadget(hsotg, suspend);
 541                 }
 542         } else {
 543                 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
 544                         dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
 545
 546                         /* Change to L2 (suspend) state */
 547                         hsotg->lx_state = DWC2_L2;
 548                         /* Clear the a_peripheral flag, back to a_host */
 549                         spin_unlock(&hsotg->lock);
 550                         dwc2_hcd_start(hsotg);
 551                         spin_lock(&hsotg->lock);
 552                         hsotg->op_state = OTG_STATE_A_HOST;
 553                 }
 554         }
 555 }
 556
 557 /**
 558  * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
 559  *
 560  * @hsotg: Programming view of DWC_otg controller
 561  *
 562  */
 563 static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
 564 {
 565         u32 glpmcfg;
 566         u32 pcgcctl;
 567         u32 hird;
 568         u32 hird_thres;
 569         u32 hird_thres_en;
 570         u32 enslpm;
 571
 572         /* Clear interrupt */
 573         dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
 574
 575         glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 576
 577         if (!(glpmcfg & GLPMCFG_LPMCAP)) {
 578                 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
 579                 return;
 580         }
 581
 582         hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
 583         hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
 584                         ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
 585         hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
 586         enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
 587
 588         if (dwc2_is_device_mode(hsotg)) {
 589                 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
 590
 591                 if (hird_thres_en && hird >= hird_thres) {
 592                         dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
 593                 } else if (enslpm) {
 594                         dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
 595                 } else {
 596                         dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
 597
 598                         pcgcctl = dwc2_readl(hsotg, PCGCTL);
 599                         pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
 600                         dwc2_writel(hsotg, pcgcctl, PCGCTL);
 601                 }
 602                 /**
 603                  * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
 604                  */
 605                 udelay(10);
 606
 607                 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 608
 609                 if (glpmcfg & GLPMCFG_SLPSTS) {
 610                         /* Save the current state */
 611                         hsotg->lx_state = DWC2_L1;
 612                         dev_dbg(hsotg->dev,
 613                                 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
 614
 615                         /* Inform gadget that we are in L1 state */
 616                         call_gadget(hsotg, suspend);
 617                 }
 618         }
 619 }
 620
 621 #define GINTMSK_COMMON  (GINTSTS_WKUPINT | GINTSTS_SESSREQINT |         \
 622                          GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT |        \
 623                          GINTSTS_MODEMIS | GINTSTS_DISCONNINT |         \
 624                          GINTSTS_USBSUSP | GINTSTS_PRTINT |             \
 625                          GINTSTS_LPMTRANRCVD)
 626
 627 /*
 628  * This function returns the Core Interrupt register
 629  */
 630 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
 631 {
 632         u32 gintsts;
 633         u32 gintmsk;
 634         u32 gahbcfg;
 635         u32 gintmsk_common = GINTMSK_COMMON;
 636
 637         gintsts = dwc2_readl(hsotg, GINTSTS);
 638         gintmsk = dwc2_readl(hsotg, GINTMSK);
 639         gahbcfg = dwc2_readl(hsotg, GAHBCFG);
 640
 641         /* If any common interrupts set */
 642         if (gintsts & gintmsk_common)
 643                 dev_dbg(hsotg->dev, "gintsts=%08x  gintmsk=%08x\n",
 644                         gintsts, gintmsk);
 645
 646         if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
 647                 return gintsts & gintmsk & gintmsk_common;
 648         else
 649                 return 0;
 650 }
 651
 652 /*
 653  * GPWRDN interrupt handler.
 654  *
 655  * The GPWRDN interrupts are those that occur in both Host and
 656  * Device mode while core is in hibernated state.
 657  */
 658 static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
 659 {
 660         u32 gpwrdn;
 661         int linestate;
 662
 663         gpwrdn = dwc2_readl(hsotg, GPWRDN);
 664         /* clear all interrupt */
 665         dwc2_writel(hsotg, gpwrdn, GPWRDN);
 666         linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
 667         dev_dbg(hsotg->dev,
 668                 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
 669                 gpwrdn);
 670
 671         if ((gpwrdn & GPWRDN_DISCONN_DET) &&
 672             (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
 673                 u32 gpwrdn_tmp;
 674
 675                 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
 676
 677                 /* Switch-on voltage to the core */
 678                 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 679                 gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
 680                 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 681                 udelay(10);
 682
 683                 /* Reset core */
 684                 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 685                 gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
 686                 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 687                 udelay(10);
 688
 689                 /* Disable Power Down Clamp */
 690                 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 691                 gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
 692                 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 693                 udelay(10);
 694
 695                 /* Deassert reset core */
 696                 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 697                 gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
 698                 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 699                 udelay(10);
 700
 701                 /* Disable PMU interrupt */
 702                 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 703                 gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
 704                 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 705
 706                 /* De-assert Wakeup Logic */
 707                 gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 708                 gpwrdn_tmp &= ~GPWRDN_PMUACTV;
 709                 dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 710
 711                 hsotg->hibernated = 0;
 712
 713                 if (gpwrdn & GPWRDN_IDSTS) {
 714                         hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 715                         dwc2_core_init(hsotg, false);
 716                         dwc2_enable_global_interrupts(hsotg);
 717                         dwc2_hsotg_core_init_disconnected(hsotg, false);
 718                         dwc2_hsotg_core_connect(hsotg);
 719                 } else {
 720                         hsotg->op_state = OTG_STATE_A_HOST;
 721
 722                         /* Initialize the Core for Host mode */
 723                         dwc2_core_init(hsotg, false);
 724                         dwc2_enable_global_interrupts(hsotg);
 725                         dwc2_hcd_start(hsotg);
 726                 }
 727         }
 728
 729         if ((gpwrdn & GPWRDN_LNSTSCHG) &&
 730             (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
 731                 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
 732                 if (hsotg->hw_params.hibernation &&
 733                     hsotg->hibernated) {
 734                         if (gpwrdn & GPWRDN_IDSTS) {
 735                                 dwc2_exit_hibernation(hsotg, 0, 0, 0);
 736                                 call_gadget(hsotg, resume);
 737                         } else {
 738                                 dwc2_exit_hibernation(hsotg, 1, 0, 1);
 739                         }
 740                 }
 741         }
 742         if ((gpwrdn & GPWRDN_RST_DET) && (gpwrdn & GPWRDN_RST_DET_MSK)) {
 743                 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
 744                 if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
 745                         dwc2_exit_hibernation(hsotg, 0, 1, 0);
 746         }
 747         if ((gpwrdn & GPWRDN_STS_CHGINT) &&
 748             (gpwrdn & GPWRDN_STS_CHGINT_MSK) && linestate) {
 749                 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
 750                 if (hsotg->hw_params.hibernation &&
 751                     hsotg->hibernated) {
 752                         if (gpwrdn & GPWRDN_IDSTS) {
 753                                 dwc2_exit_hibernation(hsotg, 0, 0, 0);
 754                                 call_gadget(hsotg, resume);
 755                         } else {
 756                                 dwc2_exit_hibernation(hsotg, 1, 0, 1);
 757                         }
 758                 }
 759         }
 760 }
 761
 762 /*
 763  * Common interrupt handler
 764  *
 765  * The common interrupts are those that occur in both Host and Device mode.
 766  * This handler handles the following interrupts:
 767  * - Mode Mismatch Interrupt
 768  * - OTG Interrupt
 769  * - Connector ID Status Change Interrupt
 770  * - Disconnect Interrupt
 771  * - Session Request Interrupt
 772  * - Resume / Remote Wakeup Detected Interrupt
 773  * - Suspend Interrupt
 774  */
 775 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
 776 {
 777         struct dwc2_hsotg *hsotg = dev;
 778         u32 gintsts;
 779         irqreturn_t retval = IRQ_NONE;
 780
 781         spin_lock(&hsotg->lock);
 782
 783         if (!dwc2_is_controller_alive(hsotg)) {
 784                 dev_warn(hsotg->dev, "Controller is dead\n");
 785                 goto out;
 786         }
 787
 788         /* Reading current frame number value in device or host modes. */
 789         if (dwc2_is_device_mode(hsotg))
 790                 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
 791                                        & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
 792         else
 793                 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
 794                                        & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
 795
 796         gintsts = dwc2_read_common_intr(hsotg);
 797         if (gintsts & ~GINTSTS_PRTINT)
 798                 retval = IRQ_HANDLED;
 799
 800         /* In case of hibernated state gintsts must not work */
 801         if (hsotg->hibernated) {
 802                 dwc2_handle_gpwrdn_intr(hsotg);
 803                 retval = IRQ_HANDLED;
 804                 goto out;
 805         }
 806
 807         if (gintsts & GINTSTS_MODEMIS)
 808                 dwc2_handle_mode_mismatch_intr(hsotg);
 809         if (gintsts & GINTSTS_OTGINT)
 810                 dwc2_handle_otg_intr(hsotg);
 811         if (gintsts & GINTSTS_CONIDSTSCHNG)
 812                 dwc2_handle_conn_id_status_change_intr(hsotg);
 813         if (gintsts & GINTSTS_DISCONNINT)
 814                 dwc2_handle_disconnect_intr(hsotg);
 815         if (gintsts & GINTSTS_SESSREQINT)
 816                 dwc2_handle_session_req_intr(hsotg);
 817         if (gintsts & GINTSTS_WKUPINT)
 818                 dwc2_handle_wakeup_detected_intr(hsotg);
 819         if (gintsts & GINTSTS_USBSUSP)
 820                 dwc2_handle_usb_suspend_intr(hsotg);
 821         if (gintsts & GINTSTS_LPMTRANRCVD)
 822                 dwc2_handle_lpm_intr(hsotg);
 823
 824         if (gintsts & GINTSTS_PRTINT) {
 825                 /*
 826                  * The port interrupt occurs while in device mode with HPRT0
 827                  * Port Enable/Disable
 828                  */
 829                 if (dwc2_is_device_mode(hsotg)) {
 830                         dev_dbg(hsotg->dev,
 831                                 " --Port interrupt received in Device mode--\n");
 832                         dwc2_handle_usb_port_intr(hsotg);
 833                         retval = IRQ_HANDLED;
 834                 }
 835         }
 836
 837 out:
 838         spin_unlock(&hsotg->lock);
 839         return retval;
 840 }