drivers/usb/dwc2/hcd.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * hcd.c - DesignWare HS OTG Controller host-mode routines
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * This file contains the core HCD code, and implements the Linux hc_driver
  40  * API
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/spinlock.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/platform_device.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
  60
  61 /*
  62  * =========================================================================
  63  *  Host Core Layer Functions
  64  * =========================================================================
  65  */
  66
  67 /**
  68  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
  69  * used in both device and host modes
  70  *
  71  * @hsotg: Programming view of the DWC_otg controller
  72  */
  73 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
  74 {
  75         u32 intmsk;
  76
  77         /* Clear any pending OTG Interrupts */
  78         dwc2_writel(hsotg, 0xffffffff, GOTGINT);
  79
  80         /* Clear any pending interrupts */
  81         dwc2_writel(hsotg, 0xffffffff, GINTSTS);
  82
  83         /* Enable the interrupts in the GINTMSK */
  84         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
  85
  86         if (!hsotg->params.host_dma)
  87                 intmsk |= GINTSTS_RXFLVL;
  88         if (!hsotg->params.external_id_pin_ctl)
  89                 intmsk |= GINTSTS_CONIDSTSCHNG;
  90
  91         intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
  92                   GINTSTS_SESSREQINT;
  93
  94         if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
  95                 intmsk |= GINTSTS_LPMTRANRCVD;
  96
  97         dwc2_writel(hsotg, intmsk, GINTMSK);
  98 }
  99
 100 /*
 101  * Initializes the FSLSPClkSel field of the HCFG register depending on the
 102  * PHY type
 103  */
 104 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 105 {
 106         u32 hcfg, val;
 107
 108         if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 109              hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 110              hsotg->params.ulpi_fs_ls) ||
 111             hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 112                 /* Full speed PHY */
 113                 val = HCFG_FSLSPCLKSEL_48_MHZ;
 114         } else {
 115                 /* High speed PHY running at full speed or high speed */
 116                 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
 117         }
 118
 119         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
 120         hcfg = dwc2_readl(hsotg, HCFG);
 121         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 122         hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
 123         dwc2_writel(hsotg, hcfg, HCFG);
 124 }
 125
 126 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 127 {
 128         u32 usbcfg, ggpio, i2cctl;
 129         int retval = 0;
 130
 131         /*
 132          * core_init() is now called on every switch so only call the
 133          * following for the first time through
 134          */
 135         if (select_phy) {
 136                 dev_dbg(hsotg->dev, "FS PHY selected\n");
 137
 138                 usbcfg = dwc2_readl(hsotg, GUSBCFG);
 139                 if (!(usbcfg & GUSBCFG_PHYSEL)) {
 140                         usbcfg |= GUSBCFG_PHYSEL;
 141                         dwc2_writel(hsotg, usbcfg, GUSBCFG);
 142
 143                         /* Reset after a PHY select */
 144                         retval = dwc2_core_reset(hsotg, false);
 145
 146                         if (retval) {
 147                                 dev_err(hsotg->dev,
 148                                         "%s: Reset failed, aborting", __func__);
 149                                 return retval;
 150                         }
 151                 }
 152
 153                 if (hsotg->params.activate_stm_fs_transceiver) {
 154                         ggpio = dwc2_readl(hsotg, GGPIO);
 155                         if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
 156                                 dev_dbg(hsotg->dev, "Activating transceiver\n");
 157                                 /*
 158                                  * STM32F4x9 uses the GGPIO register as general
 159                                  * core configuration register.
 160                                  */
 161                                 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
 162                                 dwc2_writel(hsotg, ggpio, GGPIO);
 163                         }
 164                 }
 165         }
 166
 167         /*
 168          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
 169          * do this on HNP Dev/Host mode switches (done in dev_init and
 170          * host_init).
 171          */
 172         if (dwc2_is_host_mode(hsotg))
 173                 dwc2_init_fs_ls_pclk_sel(hsotg);
 174
 175         if (hsotg->params.i2c_enable) {
 176                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 177
 178                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 179                 usbcfg = dwc2_readl(hsotg, GUSBCFG);
 180                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 181                 dwc2_writel(hsotg, usbcfg, GUSBCFG);
 182
 183                 /* Program GI2CCTL.I2CEn */
 184                 i2cctl = dwc2_readl(hsotg, GI2CCTL);
 185                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 186                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 187                 i2cctl &= ~GI2CCTL_I2CEN;
 188                 dwc2_writel(hsotg, i2cctl, GI2CCTL);
 189                 i2cctl |= GI2CCTL_I2CEN;
 190                 dwc2_writel(hsotg, i2cctl, GI2CCTL);
 191         }
 192
 193         return retval;
 194 }
 195
 196 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 197 {
 198         u32 usbcfg, usbcfg_old;
 199         int retval = 0;
 200
 201         if (!select_phy)
 202                 return 0;
 203
 204         usbcfg = dwc2_readl(hsotg, GUSBCFG);
 205         usbcfg_old = usbcfg;
 206
 207         /*
 208          * HS PHY parameters. These parameters are preserved during soft reset
 209          * so only program the first time. Do a soft reset immediately after
 210          * setting phyif.
 211          */
 212         switch (hsotg->params.phy_type) {
 213         case DWC2_PHY_TYPE_PARAM_ULPI:
 214                 /* ULPI interface */
 215                 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
 216                 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 217                 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 218                 if (hsotg->params.phy_ulpi_ddr)
 219                         usbcfg |= GUSBCFG_DDRSEL;
 220
 221                 /* Set external VBUS indicator as needed. */
 222                 if (hsotg->params.oc_disable)
 223                         usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
 224                                    GUSBCFG_INDICATORPASSTHROUGH);
 225                 break;
 226         case DWC2_PHY_TYPE_PARAM_UTMI:
 227                 /* UTMI+ interface */
 228                 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
 229                 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 230                 if (hsotg->params.phy_utmi_width == 16)
 231                         usbcfg |= GUSBCFG_PHYIF16;
 232                 break;
 233         default:
 234                 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
 235                 break;
 236         }
 237
 238         if (usbcfg != usbcfg_old) {
 239                 dwc2_writel(hsotg, usbcfg, GUSBCFG);
 240
 241                 /* Reset after setting the PHY parameters */
 242                 retval = dwc2_core_reset(hsotg, false);
 243                 if (retval) {
 244                         dev_err(hsotg->dev,
 245                                 "%s: Reset failed, aborting", __func__);
 246                         return retval;
 247                 }
 248         }
 249
 250         return retval;
 251 }
 252
 253 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 254 {
 255         u32 usbcfg;
 256         int retval = 0;
 257
 258         if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
 259              hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
 260             hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 261                 /* If FS/LS mode with FS/LS PHY */
 262                 retval = dwc2_fs_phy_init(hsotg, select_phy);
 263                 if (retval)
 264                         return retval;
 265         } else {
 266                 /* High speed PHY */
 267                 retval = dwc2_hs_phy_init(hsotg, select_phy);
 268                 if (retval)
 269                         return retval;
 270         }
 271
 272         if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 273             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 274             hsotg->params.ulpi_fs_ls) {
 275                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 276                 usbcfg = dwc2_readl(hsotg, GUSBCFG);
 277                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 278                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 279                 dwc2_writel(hsotg, usbcfg, GUSBCFG);
 280         } else {
 281                 usbcfg = dwc2_readl(hsotg, GUSBCFG);
 282                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 283                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 284                 dwc2_writel(hsotg, usbcfg, GUSBCFG);
 285         }
 286
 287         return retval;
 288 }
 289
 290 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 291 {
 292         u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
 293
 294         switch (hsotg->hw_params.arch) {
 295         case GHWCFG2_EXT_DMA_ARCH:
 296                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 297                 return -EINVAL;
 298
 299         case GHWCFG2_INT_DMA_ARCH:
 300                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 301                 if (hsotg->params.ahbcfg != -1) {
 302                         ahbcfg &= GAHBCFG_CTRL_MASK;
 303                         ahbcfg |= hsotg->params.ahbcfg &
 304                                   ~GAHBCFG_CTRL_MASK;
 305                 }
 306                 break;
 307
 308         case GHWCFG2_SLAVE_ONLY_ARCH:
 309         default:
 310                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 311                 break;
 312         }
 313
 314         if (hsotg->params.host_dma)
 315                 ahbcfg |= GAHBCFG_DMA_EN;
 316         else
 317                 hsotg->params.dma_desc_enable = false;
 318
 319         dwc2_writel(hsotg, ahbcfg, GAHBCFG);
 320
 321         return 0;
 322 }
 323
 324 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 325 {
 326         u32 usbcfg;
 327
 328         usbcfg = dwc2_readl(hsotg, GUSBCFG);
 329         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 330
 331         switch (hsotg->hw_params.op_mode) {
 332         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 333                 if (hsotg->params.otg_cap ==
 334                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 335                         usbcfg |= GUSBCFG_HNPCAP;
 336                 if (hsotg->params.otg_cap !=
 337                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 338                         usbcfg |= GUSBCFG_SRPCAP;
 339                 break;
 340
 341         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 342         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 343         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 344                 if (hsotg->params.otg_cap !=
 345                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 346                         usbcfg |= GUSBCFG_SRPCAP;
 347                 break;
 348
 349         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 350         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 351         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 352         default:
 353                 break;
 354         }
 355
 356         dwc2_writel(hsotg, usbcfg, GUSBCFG);
 357 }
 358
 359 static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
 360 {
 361         if (hsotg->vbus_supply)
 362                 return regulator_enable(hsotg->vbus_supply);
 363
 364         return 0;
 365 }
 366
 367 static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
 368 {
 369         if (hsotg->vbus_supply)
 370                 return regulator_disable(hsotg->vbus_supply);
 371
 372         return 0;
 373 }
 374
 375 /**
 376  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 377  *
 378  * @hsotg: Programming view of DWC_otg controller
 379  */
 380 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 381 {
 382         u32 intmsk;
 383
 384         dev_dbg(hsotg->dev, "%s()\n", __func__);
 385
 386         /* Disable all interrupts */
 387         dwc2_writel(hsotg, 0, GINTMSK);
 388         dwc2_writel(hsotg, 0, HAINTMSK);
 389
 390         /* Enable the common interrupts */
 391         dwc2_enable_common_interrupts(hsotg);
 392
 393         /* Enable host mode interrupts without disturbing common interrupts */
 394         intmsk = dwc2_readl(hsotg, GINTMSK);
 395         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 396         dwc2_writel(hsotg, intmsk, GINTMSK);
 397 }
 398
 399 /**
 400  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 401  *
 402  * @hsotg: Programming view of DWC_otg controller
 403  */
 404 static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 405 {
 406         u32 intmsk = dwc2_readl(hsotg, GINTMSK);
 407
 408         /* Disable host mode interrupts without disturbing common interrupts */
 409         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 410                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
 411         dwc2_writel(hsotg, intmsk, GINTMSK);
 412 }
 413
 414 /*
 415  * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
 416  * For system that have a total fifo depth that is smaller than the default
 417  * RX + TX fifo size.
 418  *
 419  * @hsotg: Programming view of DWC_otg controller
 420  */
 421 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
 422 {
 423         struct dwc2_core_params *params = &hsotg->params;
 424         struct dwc2_hw_params *hw = &hsotg->hw_params;
 425         u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
 426
 427         total_fifo_size = hw->total_fifo_size;
 428         rxfsiz = params->host_rx_fifo_size;
 429         nptxfsiz = params->host_nperio_tx_fifo_size;
 430         ptxfsiz = params->host_perio_tx_fifo_size;
 431
 432         /*
 433          * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
 434          * allocation with support for high bandwidth endpoints. Synopsys
 435          * defines MPS(Max Packet size) for a periodic EP=1024, and for
 436          * non-periodic as 512.
 437          */
 438         if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
 439                 /*
 440                  * For Buffer DMA mode/Scatter Gather DMA mode
 441                  * 2 * ((Largest Packet size / 4) + 1 + 1) + n
 442                  * with n = number of host channel.
 443                  * 2 * ((1024/4) + 2) = 516
 444                  */
 445                 rxfsiz = 516 + hw->host_channels;
 446
 447                 /*
 448                  * min non-periodic tx fifo depth
 449                  * 2 * (largest non-periodic USB packet used / 4)
 450                  * 2 * (512/4) = 256
 451                  */
 452                 nptxfsiz = 256;
 453
 454                 /*
 455                  * min periodic tx fifo depth
 456                  * (largest packet size*MC)/4
 457                  * (1024 * 3)/4 = 768
 458                  */
 459                 ptxfsiz = 768;
 460
 461                 params->host_rx_fifo_size = rxfsiz;
 462                 params->host_nperio_tx_fifo_size = nptxfsiz;
 463                 params->host_perio_tx_fifo_size = ptxfsiz;
 464         }
 465
 466         /*
 467          * If the summation of RX, NPTX and PTX fifo sizes is still
 468          * bigger than the total_fifo_size, then we have a problem.
 469          *
 470          * We won't be able to allocate as many endpoints. Right now,
 471          * we're just printing an error message, but ideally this FIFO
 472          * allocation algorithm would be improved in the future.
 473          *
 474          * FIXME improve this FIFO allocation algorithm.
 475          */
 476         if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
 477                 dev_err(hsotg->dev, "invalid fifo sizes\n");
 478 }
 479
 480 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 481 {
 482         struct dwc2_core_params *params = &hsotg->params;
 483         u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
 484
 485         if (!params->enable_dynamic_fifo)
 486                 return;
 487
 488         dwc2_calculate_dynamic_fifo(hsotg);
 489
 490         /* Rx FIFO */
 491         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 492         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 493         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 494         grxfsiz |= params->host_rx_fifo_size <<
 495                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 496         dwc2_writel(hsotg, grxfsiz, GRXFSIZ);
 497         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
 498                 dwc2_readl(hsotg, GRXFSIZ));
 499
 500         /* Non-periodic Tx FIFO */
 501         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 502                 dwc2_readl(hsotg, GNPTXFSIZ));
 503         nptxfsiz = params->host_nperio_tx_fifo_size <<
 504                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 505         nptxfsiz |= params->host_rx_fifo_size <<
 506                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 507         dwc2_writel(hsotg, nptxfsiz, GNPTXFSIZ);
 508         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 509                 dwc2_readl(hsotg, GNPTXFSIZ));
 510
 511         /* Periodic Tx FIFO */
 512         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 513                 dwc2_readl(hsotg, HPTXFSIZ));
 514         hptxfsiz = params->host_perio_tx_fifo_size <<
 515                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 516         hptxfsiz |= (params->host_rx_fifo_size +
 517                      params->host_nperio_tx_fifo_size) <<
 518                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 519         dwc2_writel(hsotg, hptxfsiz, HPTXFSIZ);
 520         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
 521                 dwc2_readl(hsotg, HPTXFSIZ));
 522
 523         if (hsotg->params.en_multiple_tx_fifo &&
 524             hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
 525                 /*
 526                  * This feature was implemented in 2.91a version
 527                  * Global DFIFOCFG calculation for Host mode -
 528                  * include RxFIFO, NPTXFIFO and HPTXFIFO
 529                  */
 530                 dfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
 531                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
 532                 dfifocfg |= (params->host_rx_fifo_size +
 533                              params->host_nperio_tx_fifo_size +
 534                              params->host_perio_tx_fifo_size) <<
 535                             GDFIFOCFG_EPINFOBASE_SHIFT &
 536                             GDFIFOCFG_EPINFOBASE_MASK;
 537                 dwc2_writel(hsotg, dfifocfg, GDFIFOCFG);
 538         }
 539 }
 540
 541 /**
 542  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
 543  * the HFIR register according to PHY type and speed
 544  *
 545  * @hsotg: Programming view of DWC_otg controller
 546  *
 547  * NOTE: The caller can modify the value of the HFIR register only after the
 548  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
 549  * has been set
 550  */
 551 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
 552 {
 553         u32 usbcfg;
 554         u32 hprt0;
 555         int clock = 60; /* default value */
 556
 557         usbcfg = dwc2_readl(hsotg, GUSBCFG);
 558         hprt0 = dwc2_readl(hsotg, HPRT0);
 559
 560         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
 561             !(usbcfg & GUSBCFG_PHYIF16))
 562                 clock = 60;
 563         if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
 564             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
 565                 clock = 48;
 566         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 567             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 568                 clock = 30;
 569         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 570             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
 571                 clock = 60;
 572         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
 573             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
 574                 clock = 48;
 575         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
 576             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
 577                 clock = 48;
 578         if ((usbcfg & GUSBCFG_PHYSEL) &&
 579             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 580                 clock = 48;
 581
 582         if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
 583                 /* High speed case */
 584                 return 125 * clock - 1;
 585
 586         /* FS/LS case */
 587         return 1000 * clock - 1;
 588 }
 589
 590 /**
 591  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
 592  * buffer
 593  *
 594  * @hsotg: Programming view of DWC_otg controller
 595  * @dest:    Destination buffer for the packet
 596  * @bytes:   Number of bytes to copy to the destination
 597  */
 598 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
 599 {
 600         u32 *data_buf = (u32 *)dest;
 601         int word_count = (bytes + 3) / 4;
 602         int i;
 603
 604         /*
 605          * Todo: Account for the case where dest is not dword aligned. This
 606          * requires reading data from the FIFO into a u32 temp buffer, then
 607          * moving it into the data buffer.
 608          */
 609
 610         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
 611
 612         for (i = 0; i < word_count; i++, data_buf++)
 613                 *data_buf = dwc2_readl(hsotg, HCFIFO(0));
 614 }
 615
 616 /**
 617  * dwc2_dump_channel_info() - Prints the state of a host channel
 618  *
 619  * @hsotg: Programming view of DWC_otg controller
 620  * @chan:  Pointer to the channel to dump
 621  *
 622  * Must be called with interrupt disabled and spinlock held
 623  *
 624  * NOTE: This function will be removed once the peripheral controller code
 625  * is integrated and the driver is stable
 626  */
 627 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
 628                                    struct dwc2_host_chan *chan)
 629 {
 630 #ifdef VERBOSE_DEBUG
 631         int num_channels = hsotg->params.host_channels;
 632         struct dwc2_qh *qh;
 633         u32 hcchar;
 634         u32 hcsplt;
 635         u32 hctsiz;
 636         u32 hc_dma;
 637         int i;
 638
 639         if (!chan)
 640                 return;
 641
 642         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
 643         hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
 644         hctsiz = dwc2_readl(hsotg, HCTSIZ(chan->hc_num));
 645         hc_dma = dwc2_readl(hsotg, HCDMA(chan->hc_num));
 646
 647         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
 648         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
 649                 hcchar, hcsplt);
 650         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
 651                 hctsiz, hc_dma);
 652         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
 653                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
 654         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
 655         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
 656         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
 657         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
 658         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 659         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 660         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 661                 (unsigned long)chan->xfer_dma);
 662         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 663         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 664         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 665         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 666                             qh_list_entry)
 667                 dev_dbg(hsotg->dev, "    %p\n", qh);
 668         dev_dbg(hsotg->dev, "  NP waiting sched:\n");
 669         list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
 670                             qh_list_entry)
 671                 dev_dbg(hsotg->dev, "    %p\n", qh);
 672         dev_dbg(hsotg->dev, "  NP active sched:\n");
 673         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 674                             qh_list_entry)
 675                 dev_dbg(hsotg->dev, "    %p\n", qh);
 676         dev_dbg(hsotg->dev, "  Channels:\n");
 677         for (i = 0; i < num_channels; i++) {
 678                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 679
 680                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 681         }
 682 #endif /* VERBOSE_DEBUG */
 683 }
 684
 685 static int _dwc2_hcd_start(struct usb_hcd *hcd);
 686
 687 static void dwc2_host_start(struct dwc2_hsotg *hsotg)
 688 {
 689         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 690
 691         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
 692         _dwc2_hcd_start(hcd);
 693 }
 694
 695 static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
 696 {
 697         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
 698
 699         hcd->self.is_b_host = 0;
 700 }
 701
 702 static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
 703                                int *hub_addr, int *hub_port)
 704 {
 705         struct urb *urb = context;
 706
 707         if (urb->dev->tt)
 708                 *hub_addr = urb->dev->tt->hub->devnum;
 709         else
 710                 *hub_addr = 0;
 711         *hub_port = urb->dev->ttport;
 712 }
 713
 714 /*
 715  * =========================================================================
 716  *  Low Level Host Channel Access Functions
 717  * =========================================================================
 718  */
 719
 720 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
 721                                       struct dwc2_host_chan *chan)
 722 {
 723         u32 hcintmsk = HCINTMSK_CHHLTD;
 724
 725         switch (chan->ep_type) {
 726         case USB_ENDPOINT_XFER_CONTROL:
 727         case USB_ENDPOINT_XFER_BULK:
 728                 dev_vdbg(hsotg->dev, "control/bulk\n");
 729                 hcintmsk |= HCINTMSK_XFERCOMPL;
 730                 hcintmsk |= HCINTMSK_STALL;
 731                 hcintmsk |= HCINTMSK_XACTERR;
 732                 hcintmsk |= HCINTMSK_DATATGLERR;
 733                 if (chan->ep_is_in) {
 734                         hcintmsk |= HCINTMSK_BBLERR;
 735                 } else {
 736                         hcintmsk |= HCINTMSK_NAK;
 737                         hcintmsk |= HCINTMSK_NYET;
 738                         if (chan->do_ping)
 739                                 hcintmsk |= HCINTMSK_ACK;
 740                 }
 741
 742                 if (chan->do_split) {
 743                         hcintmsk |= HCINTMSK_NAK;
 744                         if (chan->complete_split)
 745                                 hcintmsk |= HCINTMSK_NYET;
 746                         else
 747                                 hcintmsk |= HCINTMSK_ACK;
 748                 }
 749
 750                 if (chan->error_state)
 751                         hcintmsk |= HCINTMSK_ACK;
 752                 break;
 753
 754         case USB_ENDPOINT_XFER_INT:
 755                 if (dbg_perio())
 756                         dev_vdbg(hsotg->dev, "intr\n");
 757                 hcintmsk |= HCINTMSK_XFERCOMPL;
 758                 hcintmsk |= HCINTMSK_NAK;
 759                 hcintmsk |= HCINTMSK_STALL;
 760                 hcintmsk |= HCINTMSK_XACTERR;
 761                 hcintmsk |= HCINTMSK_DATATGLERR;
 762                 hcintmsk |= HCINTMSK_FRMOVRUN;
 763
 764                 if (chan->ep_is_in)
 765                         hcintmsk |= HCINTMSK_BBLERR;
 766                 if (chan->error_state)
 767                         hcintmsk |= HCINTMSK_ACK;
 768                 if (chan->do_split) {
 769                         if (chan->complete_split)
 770                                 hcintmsk |= HCINTMSK_NYET;
 771                         else
 772                                 hcintmsk |= HCINTMSK_ACK;
 773                 }
 774                 break;
 775
 776         case USB_ENDPOINT_XFER_ISOC:
 777                 if (dbg_perio())
 778                         dev_vdbg(hsotg->dev, "isoc\n");
 779                 hcintmsk |= HCINTMSK_XFERCOMPL;
 780                 hcintmsk |= HCINTMSK_FRMOVRUN;
 781                 hcintmsk |= HCINTMSK_ACK;
 782
 783                 if (chan->ep_is_in) {
 784                         hcintmsk |= HCINTMSK_XACTERR;
 785                         hcintmsk |= HCINTMSK_BBLERR;
 786                 }
 787                 break;
 788         default:
 789                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
 790                 break;
 791         }
 792
 793         dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
 794         if (dbg_hc(chan))
 795                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 796 }
 797
 798 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
 799                                     struct dwc2_host_chan *chan)
 800 {
 801         u32 hcintmsk = HCINTMSK_CHHLTD;
 802
 803         /*
 804          * For Descriptor DMA mode core halts the channel on AHB error.
 805          * Interrupt is not required.
 806          */
 807         if (!hsotg->params.dma_desc_enable) {
 808                 if (dbg_hc(chan))
 809                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
 810                 hcintmsk |= HCINTMSK_AHBERR;
 811         } else {
 812                 if (dbg_hc(chan))
 813                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
 814                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 815                         hcintmsk |= HCINTMSK_XFERCOMPL;
 816         }
 817
 818         if (chan->error_state && !chan->do_split &&
 819             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
 820                 if (dbg_hc(chan))
 821                         dev_vdbg(hsotg->dev, "setting ACK\n");
 822                 hcintmsk |= HCINTMSK_ACK;
 823                 if (chan->ep_is_in) {
 824                         hcintmsk |= HCINTMSK_DATATGLERR;
 825                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
 826                                 hcintmsk |= HCINTMSK_NAK;
 827                 }
 828         }
 829
 830         dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
 831         if (dbg_hc(chan))
 832                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
 833 }
 834
 835 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
 836                                 struct dwc2_host_chan *chan)
 837 {
 838         u32 intmsk;
 839
 840         if (hsotg->params.host_dma) {
 841                 if (dbg_hc(chan))
 842                         dev_vdbg(hsotg->dev, "DMA enabled\n");
 843                 dwc2_hc_enable_dma_ints(hsotg, chan);
 844         } else {
 845                 if (dbg_hc(chan))
 846                         dev_vdbg(hsotg->dev, "DMA disabled\n");
 847                 dwc2_hc_enable_slave_ints(hsotg, chan);
 848         }
 849
 850         /* Enable the top level host channel interrupt */
 851         intmsk = dwc2_readl(hsotg, HAINTMSK);
 852         intmsk |= 1 << chan->hc_num;
 853         dwc2_writel(hsotg, intmsk, HAINTMSK);
 854         if (dbg_hc(chan))
 855                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
 856
 857         /* Make sure host channel interrupts are enabled */
 858         intmsk = dwc2_readl(hsotg, GINTMSK);
 859         intmsk |= GINTSTS_HCHINT;
 860         dwc2_writel(hsotg, intmsk, GINTMSK);
 861         if (dbg_hc(chan))
 862                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
 863 }
 864
 865 /**
 866  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
 867  * a specific endpoint
 868  *
 869  * @hsotg: Programming view of DWC_otg controller
 870  * @chan:  Information needed to initialize the host channel
 871  *
 872  * The HCCHARn register is set up with the characteristics specified in chan.
 873  * Host channel interrupts that may need to be serviced while this transfer is
 874  * in progress are enabled.
 875  */
 876 static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
 877 {
 878         u8 hc_num = chan->hc_num;
 879         u32 hcintmsk;
 880         u32 hcchar;
 881         u32 hcsplt = 0;
 882
 883         if (dbg_hc(chan))
 884                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 885
 886         /* Clear old interrupt conditions for this host channel */
 887         hcintmsk = 0xffffffff;
 888         hcintmsk &= ~HCINTMSK_RESERVED14_31;
 889         dwc2_writel(hsotg, hcintmsk, HCINT(hc_num));
 890
 891         /* Enable channel interrupts required for this transfer */
 892         dwc2_hc_enable_ints(hsotg, chan);
 893
 894         /*
 895          * Program the HCCHARn register with the endpoint characteristics for
 896          * the current transfer
 897          */
 898         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
 899         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
 900         if (chan->ep_is_in)
 901                 hcchar |= HCCHAR_EPDIR;
 902         if (chan->speed == USB_SPEED_LOW)
 903                 hcchar |= HCCHAR_LSPDDEV;
 904         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
 905         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
 906         dwc2_writel(hsotg, hcchar, HCCHAR(hc_num));
 907         if (dbg_hc(chan)) {
 908                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
 909                          hc_num, hcchar);
 910
 911                 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
 912                          __func__, hc_num);
 913                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
 914                          chan->dev_addr);
 915                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
 916                          chan->ep_num);
 917                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
 918                          chan->ep_is_in);
 919                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
 920                          chan->speed == USB_SPEED_LOW);
 921                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
 922                          chan->ep_type);
 923                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
 924                          chan->max_packet);
 925         }
 926
 927         /* Program the HCSPLT register for SPLITs */
 928         if (chan->do_split) {
 929                 if (dbg_hc(chan))
 930                         dev_vdbg(hsotg->dev,
 931                                  "Programming HC %d with split --> %s\n",
 932                                  hc_num,
 933                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
 934                 if (chan->complete_split)
 935                         hcsplt |= HCSPLT_COMPSPLT;
 936                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
 937                           HCSPLT_XACTPOS_MASK;
 938                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
 939                           HCSPLT_HUBADDR_MASK;
 940                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
 941                           HCSPLT_PRTADDR_MASK;
 942                 if (dbg_hc(chan)) {
 943                         dev_vdbg(hsotg->dev, "    comp split %d\n",
 944                                  chan->complete_split);
 945                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
 946                                  chan->xact_pos);
 947                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
 948                                  chan->hub_addr);
 949                         dev_vdbg(hsotg->dev, "    hub port %d\n",
 950                                  chan->hub_port);
 951                         dev_vdbg(hsotg->dev, "    is_in %d\n",
 952                                  chan->ep_is_in);
 953                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
 954                                  chan->max_packet);
 955                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
 956                                  chan->xfer_len);
 957                 }
 958         }
 959
 960         dwc2_writel(hsotg, hcsplt, HCSPLT(hc_num));
 961 }
 962
 963 /**
 964  * dwc2_hc_halt() - Attempts to halt a host channel
 965  *
 966  * @hsotg:       Controller register interface
 967  * @chan:        Host channel to halt
 968  * @halt_status: Reason for halting the channel
 969  *
 970  * This function should only be called in Slave mode or to abort a transfer in
 971  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
 972  * controller halts the channel when the transfer is complete or a condition
 973  * occurs that requires application intervention.
 974  *
 975  * In slave mode, checks for a free request queue entry, then sets the Channel
 976  * Enable and Channel Disable bits of the Host Channel Characteristics
 977  * register of the specified channel to intiate the halt. If there is no free
 978  * request queue entry, sets only the Channel Disable bit of the HCCHARn
 979  * register to flush requests for this channel. In the latter case, sets a
 980  * flag to indicate that the host channel needs to be halted when a request
 981  * queue slot is open.
 982  *
 983  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
 984  * HCCHARn register. The controller ensures there is space in the request
 985  * queue before submitting the halt request.
 986  *
 987  * Some time may elapse before the core flushes any posted requests for this
 988  * host channel and halts. The Channel Halted interrupt handler completes the
 989  * deactivation of the host channel.
 990  */
 991 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
 992                   enum dwc2_halt_status halt_status)
 993 {
 994         u32 nptxsts, hptxsts, hcchar;
 995
 996         if (dbg_hc(chan))
 997                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
 998
 999         /*
1000          * In buffer DMA or external DMA mode channel can't be halted
1001          * for non-split periodic channels. At the end of the next
1002          * uframe/frame (in the worst case), the core generates a channel
1003          * halted and disables the channel automatically.
1004          */
1005         if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
1006             hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
1007                 if (!chan->do_split &&
1008                     (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
1009                      chan->ep_type == USB_ENDPOINT_XFER_INT)) {
1010                         dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1011                                 __func__);
1012                         return;
1013                 }
1014         }
1015
1016         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1017                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1018
1019         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1020             halt_status == DWC2_HC_XFER_AHB_ERR) {
1021                 /*
1022                  * Disable all channel interrupts except Ch Halted. The QTD
1023                  * and QH state associated with this transfer has been cleared
1024                  * (in the case of URB_DEQUEUE), so the channel needs to be
1025                  * shut down carefully to prevent crashes.
1026                  */
1027                 u32 hcintmsk = HCINTMSK_CHHLTD;
1028
1029                 dev_vdbg(hsotg->dev, "dequeue/error\n");
1030                 dwc2_writel(hsotg, hcintmsk, HCINTMSK(chan->hc_num));
1031
1032                 /*
1033                  * Make sure no other interrupts besides halt are currently
1034                  * pending. Handling another interrupt could cause a crash due
1035                  * to the QTD and QH state.
1036                  */
1037                 dwc2_writel(hsotg, ~hcintmsk, HCINT(chan->hc_num));
1038
1039                 /*
1040                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1041                  * even if the channel was already halted for some other
1042                  * reason
1043                  */
1044                 chan->halt_status = halt_status;
1045
1046                 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1047                 if (!(hcchar & HCCHAR_CHENA)) {
1048                         /*
1049                          * The channel is either already halted or it hasn't
1050                          * started yet. In DMA mode, the transfer may halt if
1051                          * it finishes normally or a condition occurs that
1052                          * requires driver intervention. Don't want to halt
1053                          * the channel again. In either Slave or DMA mode,
1054                          * it's possible that the transfer has been assigned
1055                          * to a channel, but not started yet when an URB is
1056                          * dequeued. Don't want to halt a channel that hasn't
1057                          * started yet.
1058                          */
1059                         return;
1060                 }
1061         }
1062         if (chan->halt_pending) {
1063                 /*
1064                  * A halt has already been issued for this channel. This might
1065                  * happen when a transfer is aborted by a higher level in
1066                  * the stack.
1067                  */
1068                 dev_vdbg(hsotg->dev,
1069                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
1070                          __func__, chan->hc_num);
1071                 return;
1072         }
1073
1074         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1075
1076         /* No need to set the bit in DDMA for disabling the channel */
1077         /* TODO check it everywhere channel is disabled */
1078         if (!hsotg->params.dma_desc_enable) {
1079                 if (dbg_hc(chan))
1080                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1081                 hcchar |= HCCHAR_CHENA;
1082         } else {
1083                 if (dbg_hc(chan))
1084                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
1085         }
1086         hcchar |= HCCHAR_CHDIS;
1087
1088         if (!hsotg->params.host_dma) {
1089                 if (dbg_hc(chan))
1090                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
1091                 hcchar |= HCCHAR_CHENA;
1092
1093                 /* Check for space in the request queue to issue the halt */
1094                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1095                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1096                         dev_vdbg(hsotg->dev, "control/bulk\n");
1097                         nptxsts = dwc2_readl(hsotg, GNPTXSTS);
1098                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1099                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
1100                                 hcchar &= ~HCCHAR_CHENA;
1101                         }
1102                 } else {
1103                         if (dbg_perio())
1104                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
1105                         hptxsts = dwc2_readl(hsotg, HPTXSTS);
1106                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1107                             hsotg->queuing_high_bandwidth) {
1108                                 if (dbg_perio())
1109                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
1110                                 hcchar &= ~HCCHAR_CHENA;
1111                         }
1112                 }
1113         } else {
1114                 if (dbg_hc(chan))
1115                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1116         }
1117
1118         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1119         chan->halt_status = halt_status;
1120
1121         if (hcchar & HCCHAR_CHENA) {
1122                 if (dbg_hc(chan))
1123                         dev_vdbg(hsotg->dev, "Channel enabled\n");
1124                 chan->halt_pending = 1;
1125                 chan->halt_on_queue = 0;
1126         } else {
1127                 if (dbg_hc(chan))
1128                         dev_vdbg(hsotg->dev, "Channel disabled\n");
1129                 chan->halt_on_queue = 1;
1130         }
1131
1132         if (dbg_hc(chan)) {
1133                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1134                          chan->hc_num);
1135                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
1136                          hcchar);
1137                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
1138                          chan->halt_pending);
1139                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
1140                          chan->halt_on_queue);
1141                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
1142                          chan->halt_status);
1143         }
1144 }
1145
1146 /**
1147  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1148  *
1149  * @hsotg: Programming view of DWC_otg controller
1150  * @chan:  Identifies the host channel to clean up
1151  *
1152  * This function is normally called after a transfer is done and the host
1153  * channel is being released
1154  */
1155 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1156 {
1157         u32 hcintmsk;
1158
1159         chan->xfer_started = 0;
1160
1161         list_del_init(&chan->split_order_list_entry);
1162
1163         /*
1164          * Clear channel interrupt enables and any unhandled channel interrupt
1165          * conditions
1166          */
1167         dwc2_writel(hsotg, 0, HCINTMSK(chan->hc_num));
1168         hcintmsk = 0xffffffff;
1169         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1170         dwc2_writel(hsotg, hcintmsk, HCINT(chan->hc_num));
1171 }
1172
1173 /**
1174  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1175  * which frame a periodic transfer should occur
1176  *
1177  * @hsotg:  Programming view of DWC_otg controller
1178  * @chan:   Identifies the host channel to set up and its properties
1179  * @hcchar: Current value of the HCCHAR register for the specified host channel
1180  *
1181  * This function has no effect on non-periodic transfers
1182  */
1183 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1184                                        struct dwc2_host_chan *chan, u32 *hcchar)
1185 {
1186         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1187             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1188                 int host_speed;
1189                 int xfer_ns;
1190                 int xfer_us;
1191                 int bytes_in_fifo;
1192                 u16 fifo_space;
1193                 u16 frame_number;
1194                 u16 wire_frame;
1195
1196                 /*
1197                  * Try to figure out if we're an even or odd frame. If we set
1198                  * even and the current frame number is even the the transfer
1199                  * will happen immediately.  Similar if both are odd. If one is
1200                  * even and the other is odd then the transfer will happen when
1201                  * the frame number ticks.
1202                  *
1203                  * There's a bit of a balancing act to get this right.
1204                  * Sometimes we may want to send data in the current frame (AK
1205                  * right away).  We might want to do this if the frame number
1206                  * _just_ ticked, but we might also want to do this in order
1207                  * to continue a split transaction that happened late in a
1208                  * microframe (so we didn't know to queue the next transfer
1209                  * until the frame number had ticked).  The problem is that we
1210                  * need a lot of knowledge to know if there's actually still
1211                  * time to send things or if it would be better to wait until
1212                  * the next frame.
1213                  *
1214                  * We can look at how much time is left in the current frame
1215                  * and make a guess about whether we'll have time to transfer.
1216                  * We'll do that.
1217                  */
1218
1219                 /* Get speed host is running at */
1220                 host_speed = (chan->speed != USB_SPEED_HIGH &&
1221                               !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1222
1223                 /* See how many bytes are in the periodic FIFO right now */
1224                 fifo_space = (dwc2_readl(hsotg, HPTXSTS) &
1225                               TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1226                 bytes_in_fifo = sizeof(u32) *
1227                                 (hsotg->params.host_perio_tx_fifo_size -
1228                                  fifo_space);
1229
1230                 /*
1231                  * Roughly estimate bus time for everything in the periodic
1232                  * queue + our new transfer.  This is "rough" because we're
1233                  * using a function that makes takes into account IN/OUT
1234                  * and INT/ISO and we're just slamming in one value for all
1235                  * transfers.  This should be an over-estimate and that should
1236                  * be OK, but we can probably tighten it.
1237                  */
1238                 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1239                                             chan->xfer_len + bytes_in_fifo);
1240                 xfer_us = NS_TO_US(xfer_ns);
1241
1242                 /* See what frame number we'll be at by the time we finish */
1243                 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1244
1245                 /* This is when we were scheduled to be on the wire */
1246                 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1247
1248                 /*
1249                  * If we'd finish _after_ the frame we're scheduled in then
1250                  * it's hopeless.  Just schedule right away and hope for the
1251                  * best.  Note that it _might_ be wise to call back into the
1252                  * scheduler to pick a better frame, but this is better than
1253                  * nothing.
1254                  */
1255                 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1256                         dwc2_sch_vdbg(hsotg,
1257                                       "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1258                                       chan->qh, wire_frame, frame_number,
1259                                       dwc2_frame_num_dec(frame_number,
1260                                                          wire_frame));
1261                         wire_frame = frame_number;
1262
1263                         /*
1264                          * We picked a different frame number; communicate this
1265                          * back to the scheduler so it doesn't try to schedule
1266                          * another in the same frame.
1267                          *
1268                          * Remember that next_active_frame is 1 before the wire
1269                          * frame.
1270                          */
1271                         chan->qh->next_active_frame =
1272                                 dwc2_frame_num_dec(frame_number, 1);
1273                 }
1274
1275                 if (wire_frame & 1)
1276                         *hcchar |= HCCHAR_ODDFRM;
1277                 else
1278                         *hcchar &= ~HCCHAR_ODDFRM;
1279         }
1280 }
1281
1282 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1283 {
1284         /* Set up the initial PID for the transfer */
1285         if (chan->speed == USB_SPEED_HIGH) {
1286                 if (chan->ep_is_in) {
1287                         if (chan->multi_count == 1)
1288                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1289                         else if (chan->multi_count == 2)
1290                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1291                         else
1292                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1293                 } else {
1294                         if (chan->multi_count == 1)
1295                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1296                         else
1297                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1298                 }
1299         } else {
1300                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1301         }
1302 }
1303
1304 /**
1305  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1306  * the Host Channel
1307  *
1308  * @hsotg: Programming view of DWC_otg controller
1309  * @chan:  Information needed to initialize the host channel
1310  *
1311  * This function should only be called in Slave mode. For a channel associated
1312  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1313  * associated with a periodic EP, the periodic Tx FIFO is written.
1314  *
1315  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1316  * the number of bytes written to the Tx FIFO.
1317  */
1318 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1319                                  struct dwc2_host_chan *chan)
1320 {
1321         u32 i;
1322         u32 remaining_count;
1323         u32 byte_count;
1324         u32 dword_count;
1325         u32 *data_buf = (u32 *)chan->xfer_buf;
1326
1327         if (dbg_hc(chan))
1328                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1329
1330         remaining_count = chan->xfer_len - chan->xfer_count;
1331         if (remaining_count > chan->max_packet)
1332                 byte_count = chan->max_packet;
1333         else
1334                 byte_count = remaining_count;
1335
1336         dword_count = (byte_count + 3) / 4;
1337
1338         if (((unsigned long)data_buf & 0x3) == 0) {
1339                 /* xfer_buf is DWORD aligned */
1340                 for (i = 0; i < dword_count; i++, data_buf++)
1341                         dwc2_writel(hsotg, *data_buf, HCFIFO(chan->hc_num));
1342         } else {
1343                 /* xfer_buf is not DWORD aligned */
1344                 for (i = 0; i < dword_count; i++, data_buf++) {
1345                         u32 data = data_buf[0] | data_buf[1] << 8 |
1346                                    data_buf[2] << 16 | data_buf[3] << 24;
1347                         dwc2_writel(hsotg, data, HCFIFO(chan->hc_num));
1348                 }
1349         }
1350
1351         chan->xfer_count += byte_count;
1352         chan->xfer_buf += byte_count;
1353 }
1354
1355 /**
1356  * dwc2_hc_do_ping() - Starts a PING transfer
1357  *
1358  * @hsotg: Programming view of DWC_otg controller
1359  * @chan:  Information needed to initialize the host channel
1360  *
1361  * This function should only be called in Slave mode. The Do Ping bit is set in
1362  * the HCTSIZ register, then the channel is enabled.
1363  */
1364 static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1365                             struct dwc2_host_chan *chan)
1366 {
1367         u32 hcchar;
1368         u32 hctsiz;
1369
1370         if (dbg_hc(chan))
1371                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1372                          chan->hc_num);
1373
1374         hctsiz = TSIZ_DOPNG;
1375         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1376         dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1377
1378         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1379         hcchar |= HCCHAR_CHENA;
1380         hcchar &= ~HCCHAR_CHDIS;
1381         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1382 }
1383
1384 /**
1385  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1386  * channel and starts the transfer
1387  *
1388  * @hsotg: Programming view of DWC_otg controller
1389  * @chan:  Information needed to initialize the host channel. The xfer_len value
1390  *         may be reduced to accommodate the max widths of the XferSize and
1391  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1392  *         changed to reflect the final xfer_len value.
1393  *
1394  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1395  * the caller must ensure that there is sufficient space in the request queue
1396  * and Tx Data FIFO.
1397  *
1398  * For an OUT transfer in Slave mode, it loads a data packet into the
1399  * appropriate FIFO. If necessary, additional data packets are loaded in the
1400  * Host ISR.
1401  *
1402  * For an IN transfer in Slave mode, a data packet is requested. The data
1403  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1404  * additional data packets are requested in the Host ISR.
1405  *
1406  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1407  * register along with a packet count of 1 and the channel is enabled. This
1408  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1409  * simply set to 0 since no data transfer occurs in this case.
1410  *
1411  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1412  * all the information required to perform the subsequent data transfer. In
1413  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1414  * controller performs the entire PING protocol, then starts the data
1415  * transfer.
1416  */
1417 static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1418                                    struct dwc2_host_chan *chan)
1419 {
1420         u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1421         u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1422         u32 hcchar;
1423         u32 hctsiz = 0;
1424         u16 num_packets;
1425         u32 ec_mc;
1426
1427         if (dbg_hc(chan))
1428                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1429
1430         if (chan->do_ping) {
1431                 if (!hsotg->params.host_dma) {
1432                         if (dbg_hc(chan))
1433                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1434                         dwc2_hc_do_ping(hsotg, chan);
1435                         chan->xfer_started = 1;
1436                         return;
1437                 }
1438
1439                 if (dbg_hc(chan))
1440                         dev_vdbg(hsotg->dev, "ping, DMA\n");
1441
1442                 hctsiz |= TSIZ_DOPNG;
1443         }
1444
1445         if (chan->do_split) {
1446                 if (dbg_hc(chan))
1447                         dev_vdbg(hsotg->dev, "split\n");
1448                 num_packets = 1;
1449
1450                 if (chan->complete_split && !chan->ep_is_in)
1451                         /*
1452                          * For CSPLIT OUT Transfer, set the size to 0 so the
1453                          * core doesn't expect any data written to the FIFO
1454                          */
1455                         chan->xfer_len = 0;
1456                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1457                         chan->xfer_len = chan->max_packet;
1458                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1459                         chan->xfer_len = 188;
1460
1461                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1462                           TSIZ_XFERSIZE_MASK;
1463
1464                 /* For split set ec_mc for immediate retries */
1465                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1466                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1467                         ec_mc = 3;
1468                 else
1469                         ec_mc = 1;
1470         } else {
1471                 if (dbg_hc(chan))
1472                         dev_vdbg(hsotg->dev, "no split\n");
1473                 /*
1474                  * Ensure that the transfer length and packet count will fit
1475                  * in the widths allocated for them in the HCTSIZn register
1476                  */
1477                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1478                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1479                         /*
1480                          * Make sure the transfer size is no larger than one
1481                          * (micro)frame's worth of data. (A check was done
1482                          * when the periodic transfer was accepted to ensure
1483                          * that a (micro)frame's worth of data can be
1484                          * programmed into a channel.)
1485                          */
1486                         u32 max_periodic_len =
1487                                 chan->multi_count * chan->max_packet;
1488
1489                         if (chan->xfer_len > max_periodic_len)
1490                                 chan->xfer_len = max_periodic_len;
1491                 } else if (chan->xfer_len > max_hc_xfer_size) {
1492                         /*
1493                          * Make sure that xfer_len is a multiple of max packet
1494                          * size
1495                          */
1496                         chan->xfer_len =
1497                                 max_hc_xfer_size - chan->max_packet + 1;
1498                 }
1499
1500                 if (chan->xfer_len > 0) {
1501                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1502                                         chan->max_packet;
1503                         if (num_packets > max_hc_pkt_count) {
1504                                 num_packets = max_hc_pkt_count;
1505                                 chan->xfer_len = num_packets * chan->max_packet;
1506                         }
1507                 } else {
1508                         /* Need 1 packet for transfer length of 0 */
1509                         num_packets = 1;
1510                 }
1511
1512                 if (chan->ep_is_in)
1513                         /*
1514                          * Always program an integral # of max packets for IN
1515                          * transfers
1516                          */
1517                         chan->xfer_len = num_packets * chan->max_packet;
1518
1519                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1520                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1521                         /*
1522                          * Make sure that the multi_count field matches the
1523                          * actual transfer length
1524                          */
1525                         chan->multi_count = num_packets;
1526
1527                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1528                         dwc2_set_pid_isoc(chan);
1529
1530                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1531                           TSIZ_XFERSIZE_MASK;
1532
1533                 /* The ec_mc gets the multi_count for non-split */
1534                 ec_mc = chan->multi_count;
1535         }
1536
1537         chan->start_pkt_count = num_packets;
1538         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1539         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1540                   TSIZ_SC_MC_PID_MASK;
1541         dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1542         if (dbg_hc(chan)) {
1543                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1544                          hctsiz, chan->hc_num);
1545
1546                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1547                          chan->hc_num);
1548                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1549                          (hctsiz & TSIZ_XFERSIZE_MASK) >>
1550                          TSIZ_XFERSIZE_SHIFT);
1551                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1552                          (hctsiz & TSIZ_PKTCNT_MASK) >>
1553                          TSIZ_PKTCNT_SHIFT);
1554                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1555                          (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1556                          TSIZ_SC_MC_PID_SHIFT);
1557         }
1558
1559         if (hsotg->params.host_dma) {
1560                 dma_addr_t dma_addr;
1561
1562                 if (chan->align_buf) {
1563                         if (dbg_hc(chan))
1564                                 dev_vdbg(hsotg->dev, "align_buf\n");
1565                         dma_addr = chan->align_buf;
1566                 } else {
1567                         dma_addr = chan->xfer_dma;
1568                 }
1569                 dwc2_writel(hsotg, (u32)dma_addr, HCDMA(chan->hc_num));
1570
1571                 if (dbg_hc(chan))
1572                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1573                                  (unsigned long)dma_addr, chan->hc_num);
1574         }
1575
1576         /* Start the split */
1577         if (chan->do_split) {
1578                 u32 hcsplt = dwc2_readl(hsotg, HCSPLT(chan->hc_num));
1579
1580                 hcsplt |= HCSPLT_SPLTENA;
1581                 dwc2_writel(hsotg, hcsplt, HCSPLT(chan->hc_num));
1582         }
1583
1584         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1585         hcchar &= ~HCCHAR_MULTICNT_MASK;
1586         hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1587         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1588
1589         if (hcchar & HCCHAR_CHDIS)
1590                 dev_warn(hsotg->dev,
1591                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1592                          __func__, chan->hc_num, hcchar);
1593
1594         /* Set host channel enable after all other setup is complete */
1595         hcchar |= HCCHAR_CHENA;
1596         hcchar &= ~HCCHAR_CHDIS;
1597
1598         if (dbg_hc(chan))
1599                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1600                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1601                          HCCHAR_MULTICNT_SHIFT);
1602
1603         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1604         if (dbg_hc(chan))
1605                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1606                          chan->hc_num);
1607
1608         chan->xfer_started = 1;
1609         chan->requests++;
1610
1611         if (!hsotg->params.host_dma &&
1612             !chan->ep_is_in && chan->xfer_len > 0)
1613                 /* Load OUT packet into the appropriate Tx FIFO */
1614                 dwc2_hc_write_packet(hsotg, chan);
1615 }
1616
1617 /**
1618  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1619  * host channel and starts the transfer in Descriptor DMA mode
1620  *
1621  * @hsotg: Programming view of DWC_otg controller
1622  * @chan:  Information needed to initialize the host channel
1623  *
1624  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1625  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1626  * with micro-frame bitmap.
1627  *
1628  * Initializes HCDMA register with descriptor list address and CTD value then
1629  * starts the transfer via enabling the channel.
1630  */
1631 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1632                                  struct dwc2_host_chan *chan)
1633 {
1634         u32 hcchar;
1635         u32 hctsiz = 0;
1636
1637         if (chan->do_ping)
1638                 hctsiz |= TSIZ_DOPNG;
1639
1640         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1641                 dwc2_set_pid_isoc(chan);
1642
1643         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1644         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1645                   TSIZ_SC_MC_PID_MASK;
1646
1647         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1648         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1649
1650         /* Non-zero only for high-speed interrupt endpoints */
1651         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1652
1653         if (dbg_hc(chan)) {
1654                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1655                          chan->hc_num);
1656                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1657                          chan->data_pid_start);
1658                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1659         }
1660
1661         dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
1662
1663         dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1664                                    chan->desc_list_sz, DMA_TO_DEVICE);
1665
1666         dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
1667
1668         if (dbg_hc(chan))
1669                 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1670                          &chan->desc_list_addr, chan->hc_num);
1671
1672         hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1673         hcchar &= ~HCCHAR_MULTICNT_MASK;
1674         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1675                   HCCHAR_MULTICNT_MASK;
1676
1677         if (hcchar & HCCHAR_CHDIS)
1678                 dev_warn(hsotg->dev,
1679                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1680                          __func__, chan->hc_num, hcchar);
1681
1682         /* Set host channel enable after all other setup is complete */
1683         hcchar |= HCCHAR_CHENA;
1684         hcchar &= ~HCCHAR_CHDIS;
1685
1686         if (dbg_hc(chan))
1687                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1688                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1689                          HCCHAR_MULTICNT_SHIFT);
1690
1691         dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1692         if (dbg_hc(chan))
1693                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1694                          chan->hc_num);
1695
1696         chan->xfer_started = 1;
1697         chan->requests++;
1698 }
1699
1700 /**
1701  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1702  * a previous call to dwc2_hc_start_transfer()
1703  *
1704  * @hsotg: Programming view of DWC_otg controller
1705  * @chan:  Information needed to initialize the host channel
1706  *
1707  * The caller must ensure there is sufficient space in the request queue and Tx
1708  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1709  * the controller acts autonomously to complete transfers programmed to a host
1710  * channel.
1711  *
1712  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1713  * if there is any data remaining to be queued. For an IN transfer, another
1714  * data packet is always requested. For the SETUP phase of a control transfer,
1715  * this function does nothing.
1716  *
1717  * Return: 1 if a new request is queued, 0 if no more requests are required
1718  * for this transfer
1719  */
1720 static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1721                                      struct dwc2_host_chan *chan)
1722 {
1723         if (dbg_hc(chan))
1724                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1725                          chan->hc_num);
1726
1727         if (chan->do_split)
1728                 /* SPLITs always queue just once per channel */
1729                 return 0;
1730
1731         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1732                 /* SETUPs are queued only once since they can't be NAK'd */
1733                 return 0;
1734
1735         if (chan->ep_is_in) {
1736                 /*
1737                  * Always queue another request for other IN transfers. If
1738                  * back-to-back INs are issued and NAKs are received for both,
1739                  * the driver may still be processing the first NAK when the
1740                  * second NAK is received. When the interrupt handler clears
1741                  * the NAK interrupt for the first NAK, the second NAK will
1742                  * not be seen. So we can't depend on the NAK interrupt
1743                  * handler to requeue a NAK'd request. Instead, IN requests
1744                  * are issued each time this function is called. When the
1745                  * transfer completes, the extra requests for the channel will
1746                  * be flushed.
1747                  */
1748                 u32 hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
1749
1750                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1751                 hcchar |= HCCHAR_CHENA;
1752                 hcchar &= ~HCCHAR_CHDIS;
1753                 if (dbg_hc(chan))
1754                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
1755                                  hcchar);
1756                 dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
1757                 chan->requests++;
1758                 return 1;
1759         }
1760
1761         /* OUT transfers */
1762
1763         if (chan->xfer_count < chan->xfer_len) {
1764                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1765                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1766                         u32 hcchar = dwc2_readl(hsotg,
1767                                                 HCCHAR(chan->hc_num));
1768
1769                         dwc2_hc_set_even_odd_frame(hsotg, chan,
1770                                                    &hcchar);
1771                 }
1772
1773                 /* Load OUT packet into the appropriate Tx FIFO */
1774                 dwc2_hc_write_packet(hsotg, chan);
1775                 chan->requests++;
1776                 return 1;
1777         }
1778
1779         return 0;
1780 }
1781
1782 /*
1783  * =========================================================================
1784  *  HCD
1785  * =========================================================================
1786  */
1787
1788 /*
1789  * Processes all the URBs in a single list of QHs. Completes them with
1790  * -ETIMEDOUT and frees the QTD.
1791  *
1792  * Must be called with interrupt disabled and spinlock held
1793  */
1794 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1795                                       struct list_head *qh_list)
1796 {
1797         struct dwc2_qh *qh, *qh_tmp;
1798         struct dwc2_qtd *qtd, *qtd_tmp;
1799
1800         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1801                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1802                                          qtd_list_entry) {
1803                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1804                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1805                 }
1806         }
1807 }
1808
1809 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1810                               struct list_head *qh_list)
1811 {
1812         struct dwc2_qtd *qtd, *qtd_tmp;
1813         struct dwc2_qh *qh, *qh_tmp;
1814         unsigned long flags;
1815
1816         if (!qh_list->next)
1817                 /* The list hasn't been initialized yet */
1818                 return;
1819
1820         spin_lock_irqsave(&hsotg->lock, flags);
1821
1822         /* Ensure there are no QTDs or URBs left */
1823         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1824
1825         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1826                 dwc2_hcd_qh_unlink(hsotg, qh);
1827
1828                 /* Free each QTD in the QH's QTD list */
1829                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1830                                          qtd_list_entry)
1831                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1832
1833                 if (qh->channel && qh->channel->qh == qh)
1834                         qh->channel->qh = NULL;
1835
1836                 spin_unlock_irqrestore(&hsotg->lock, flags);
1837                 dwc2_hcd_qh_free(hsotg, qh);
1838                 spin_lock_irqsave(&hsotg->lock, flags);
1839         }
1840
1841         spin_unlock_irqrestore(&hsotg->lock, flags);
1842 }
1843
1844 /*
1845  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1846  * and periodic schedules. The QTD associated with each URB is removed from
1847  * the schedule and freed. This function may be called when a disconnect is
1848  * detected or when the HCD is being stopped.
1849  *
1850  * Must be called with interrupt disabled and spinlock held
1851  */
1852 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1853 {
1854         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1855         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1856         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1857         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1858         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1859         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1860         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1861 }
1862
1863 /**
1864  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1865  *
1866  * @hsotg: Pointer to struct dwc2_hsotg
1867  */
1868 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1869 {
1870         u32 hprt0;
1871
1872         if (hsotg->op_state == OTG_STATE_B_HOST) {
1873                 /*
1874                  * Reset the port. During a HNP mode switch the reset
1875                  * needs to occur within 1ms and have a duration of at
1876                  * least 50ms.
1877                  */
1878                 hprt0 = dwc2_read_hprt0(hsotg);
1879                 hprt0 |= HPRT0_RST;
1880                 dwc2_writel(hsotg, hprt0, HPRT0);
1881         }
1882
1883         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1884                            msecs_to_jiffies(50));
1885 }
1886
1887 /* Must be called with interrupt disabled and spinlock held */
1888 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1889 {
1890         int num_channels = hsotg->params.host_channels;
1891         struct dwc2_host_chan *channel;
1892         u32 hcchar;
1893         int i;
1894
1895         if (!hsotg->params.host_dma) {
1896                 /* Flush out any channel requests in slave mode */
1897                 for (i = 0; i < num_channels; i++) {
1898                         channel = hsotg->hc_ptr_array[i];
1899                         if (!list_empty(&channel->hc_list_entry))
1900                                 continue;
1901                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
1902                         if (hcchar & HCCHAR_CHENA) {
1903                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1904                                 hcchar |= HCCHAR_CHDIS;
1905                                 dwc2_writel(hsotg, hcchar, HCCHAR(i));
1906                         }
1907                 }
1908         }
1909
1910         for (i = 0; i < num_channels; i++) {
1911                 channel = hsotg->hc_ptr_array[i];
1912                 if (!list_empty(&channel->hc_list_entry))
1913                         continue;
1914                 hcchar = dwc2_readl(hsotg, HCCHAR(i));
1915                 if (hcchar & HCCHAR_CHENA) {
1916                         /* Halt the channel */
1917                         hcchar |= HCCHAR_CHDIS;
1918                         dwc2_writel(hsotg, hcchar, HCCHAR(i));
1919                 }
1920
1921                 dwc2_hc_cleanup(hsotg, channel);
1922                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1923                 /*
1924                  * Added for Descriptor DMA to prevent channel double cleanup in
1925                  * release_channel_ddma(), which is called from ep_disable when
1926                  * device disconnects
1927                  */
1928                 channel->qh = NULL;
1929         }
1930         /* All channels have been freed, mark them available */
1931         if (hsotg->params.uframe_sched) {
1932                 hsotg->available_host_channels =
1933                         hsotg->params.host_channels;
1934         } else {
1935                 hsotg->non_periodic_channels = 0;
1936                 hsotg->periodic_channels = 0;
1937         }
1938 }
1939
1940 /**
1941  * dwc2_hcd_connect() - Handles connect of the HCD
1942  *
1943  * @hsotg: Pointer to struct dwc2_hsotg
1944  *
1945  * Must be called with interrupt disabled and spinlock held
1946  */
1947 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1948 {
1949         if (hsotg->lx_state != DWC2_L0)
1950                 usb_hcd_resume_root_hub(hsotg->priv);
1951
1952         hsotg->flags.b.port_connect_status_change = 1;
1953         hsotg->flags.b.port_connect_status = 1;
1954 }
1955
1956 /**
1957  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1958  *
1959  * @hsotg: Pointer to struct dwc2_hsotg
1960  * @force: If true, we won't try to reconnect even if we see device connected.
1961  *
1962  * Must be called with interrupt disabled and spinlock held
1963  */
1964 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1965 {
1966         u32 intr;
1967         u32 hprt0;
1968
1969         /* Set status flags for the hub driver */
1970         hsotg->flags.b.port_connect_status_change = 1;
1971         hsotg->flags.b.port_connect_status = 0;
1972
1973         /*
1974          * Shutdown any transfers in process by clearing the Tx FIFO Empty
1975          * interrupt mask and status bits and disabling subsequent host
1976          * channel interrupts.
1977          */
1978         intr = dwc2_readl(hsotg, GINTMSK);
1979         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1980         dwc2_writel(hsotg, intr, GINTMSK);
1981         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1982         dwc2_writel(hsotg, intr, GINTSTS);
1983
1984         /*
1985          * Turn off the vbus power only if the core has transitioned to device
1986          * mode. If still in host mode, need to keep power on to detect a
1987          * reconnection.
1988          */
1989         if (dwc2_is_device_mode(hsotg)) {
1990                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1991                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1992                         dwc2_writel(hsotg, 0, HPRT0);
1993                 }
1994
1995                 dwc2_disable_host_interrupts(hsotg);
1996         }
1997
1998         /* Respond with an error status to all URBs in the schedule */
1999         dwc2_kill_all_urbs(hsotg);
2000
2001         if (dwc2_is_host_mode(hsotg))
2002                 /* Clean up any host channels that were in use */
2003                 dwc2_hcd_cleanup_channels(hsotg);
2004
2005         dwc2_host_disconnect(hsotg);
2006
2007         /*
2008          * Add an extra check here to see if we're actually connected but
2009          * we don't have a detection interrupt pending.  This can happen if:
2010          *   1. hardware sees connect
2011          *   2. hardware sees disconnect
2012          *   3. hardware sees connect
2013          *   4. dwc2_port_intr() - clears connect interrupt
2014          *   5. dwc2_handle_common_intr() - calls here
2015          *
2016          * Without the extra check here we will end calling disconnect
2017          * and won't get any future interrupts to handle the connect.
2018          */
2019         if (!force) {
2020                 hprt0 = dwc2_readl(hsotg, HPRT0);
2021                 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2022                         dwc2_hcd_connect(hsotg);
2023         }
2024 }
2025
2026 /**
2027  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2028  *
2029  * @hsotg: Pointer to struct dwc2_hsotg
2030  */
2031 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2032 {
2033         if (hsotg->bus_suspended) {
2034                 hsotg->flags.b.port_suspend_change = 1;
2035                 usb_hcd_resume_root_hub(hsotg->priv);
2036         }
2037
2038         if (hsotg->lx_state == DWC2_L1)
2039                 hsotg->flags.b.port_l1_change = 1;
2040 }
2041
2042 /**
2043  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2044  *
2045  * @hsotg: Pointer to struct dwc2_hsotg
2046  *
2047  * Must be called with interrupt disabled and spinlock held
2048  */
2049 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2050 {
2051         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2052
2053         /*
2054          * The root hub should be disconnected before this function is called.
2055          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2056          * and the QH lists (via ..._hcd_endpoint_disable).
2057          */
2058
2059         /* Turn off all host-specific interrupts */
2060         dwc2_disable_host_interrupts(hsotg);
2061
2062         /* Turn off the vbus power */
2063         dev_dbg(hsotg->dev, "PortPower off\n");
2064         dwc2_writel(hsotg, 0, HPRT0);
2065 }
2066
2067 /* Caller must hold driver lock */
2068 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2069                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2070                                 struct dwc2_qtd *qtd)
2071 {
2072         u32 intr_mask;
2073         int retval;
2074         int dev_speed;
2075
2076         if (!hsotg->flags.b.port_connect_status) {
2077                 /* No longer connected */
2078                 dev_err(hsotg->dev, "Not connected\n");
2079                 return -ENODEV;
2080         }
2081
2082         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2083
2084         /* Some configurations cannot support LS traffic on a FS root port */
2085         if ((dev_speed == USB_SPEED_LOW) &&
2086             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2087             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2088                 u32 hprt0 = dwc2_readl(hsotg, HPRT0);
2089                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2090
2091                 if (prtspd == HPRT0_SPD_FULL_SPEED)
2092                         return -ENODEV;
2093         }
2094
2095         if (!qtd)
2096                 return -EINVAL;
2097
2098         dwc2_hcd_qtd_init(qtd, urb);
2099         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2100         if (retval) {
2101                 dev_err(hsotg->dev,
2102                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2103                         retval);
2104                 return retval;
2105         }
2106
2107         intr_mask = dwc2_readl(hsotg, GINTMSK);
2108         if (!(intr_mask & GINTSTS_SOF)) {
2109                 enum dwc2_transaction_type tr_type;
2110
2111                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2112                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2113                         /*
2114                          * Do not schedule SG transactions until qtd has
2115                          * URB_GIVEBACK_ASAP set
2116                          */
2117                         return 0;
2118
2119                 tr_type = dwc2_hcd_select_transactions(hsotg);
2120                 if (tr_type != DWC2_TRANSACTION_NONE)
2121                         dwc2_hcd_queue_transactions(hsotg, tr_type);
2122         }
2123
2124         return 0;
2125 }
2126
2127 /* Must be called with interrupt disabled and spinlock held */
2128 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2129                                 struct dwc2_hcd_urb *urb)
2130 {
2131         struct dwc2_qh *qh;
2132         struct dwc2_qtd *urb_qtd;
2133
2134         urb_qtd = urb->qtd;
2135         if (!urb_qtd) {
2136                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2137                 return -EINVAL;
2138         }
2139
2140         qh = urb_qtd->qh;
2141         if (!qh) {
2142                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2143                 return -EINVAL;
2144         }
2145
2146         urb->priv = NULL;
2147
2148         if (urb_qtd->in_process && qh->channel) {
2149                 dwc2_dump_channel_info(hsotg, qh->channel);
2150
2151                 /* The QTD is in process (it has been assigned to a channel) */
2152                 if (hsotg->flags.b.port_connect_status)
2153                         /*
2154                          * If still connected (i.e. in host mode), halt the
2155                          * channel so it can be used for other transfers. If
2156                          * no longer connected, the host registers can't be
2157                          * written to halt the channel since the core is in
2158                          * device mode.
2159                          */
2160                         dwc2_hc_halt(hsotg, qh->channel,
2161                                      DWC2_HC_XFER_URB_DEQUEUE);
2162         }
2163
2164         /*
2165          * Free the QTD and clean up the associated QH. Leave the QH in the
2166          * schedule if it has any remaining QTDs.
2167          */
2168         if (!hsotg->params.dma_desc_enable) {
2169                 u8 in_process = urb_qtd->in_process;
2170
2171                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2172                 if (in_process) {
2173                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2174                         qh->channel = NULL;
2175                 } else if (list_empty(&qh->qtd_list)) {
2176                         dwc2_hcd_qh_unlink(hsotg, qh);
2177                 }
2178         } else {
2179                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2180         }
2181
2182         return 0;
2183 }
2184
2185 /* Must NOT be called with interrupt disabled or spinlock held */
2186 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2187                                      struct usb_host_endpoint *ep, int retry)
2188 {
2189         struct dwc2_qtd *qtd, *qtd_tmp;
2190         struct dwc2_qh *qh;
2191         unsigned long flags;
2192         int rc;
2193
2194         spin_lock_irqsave(&hsotg->lock, flags);
2195
2196         qh = ep->hcpriv;
2197         if (!qh) {
2198                 rc = -EINVAL;
2199                 goto err;
2200         }
2201
2202         while (!list_empty(&qh->qtd_list) && retry--) {
2203                 if (retry == 0) {
2204                         dev_err(hsotg->dev,
2205                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2206                         rc = -EBUSY;
2207                         goto err;
2208                 }
2209
2210                 spin_unlock_irqrestore(&hsotg->lock, flags);
2211                 msleep(20);
2212                 spin_lock_irqsave(&hsotg->lock, flags);
2213                 qh = ep->hcpriv;
2214                 if (!qh) {
2215                         rc = -EINVAL;
2216                         goto err;
2217                 }
2218         }
2219
2220         dwc2_hcd_qh_unlink(hsotg, qh);
2221
2222         /* Free each QTD in the QH's QTD list */
2223         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2224                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2225
2226         ep->hcpriv = NULL;
2227
2228         if (qh->channel && qh->channel->qh == qh)
2229                 qh->channel->qh = NULL;
2230
2231         spin_unlock_irqrestore(&hsotg->lock, flags);
2232
2233         dwc2_hcd_qh_free(hsotg, qh);
2234
2235         return 0;
2236
2237 err:
2238         ep->hcpriv = NULL;
2239         spin_unlock_irqrestore(&hsotg->lock, flags);
2240
2241         return rc;
2242 }
2243
2244 /* Must be called with interrupt disabled and spinlock held */
2245 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2246                                    struct usb_host_endpoint *ep)
2247 {
2248         struct dwc2_qh *qh = ep->hcpriv;
2249
2250         if (!qh)
2251                 return -EINVAL;
2252
2253         qh->data_toggle = DWC2_HC_PID_DATA0;
2254
2255         return 0;
2256 }
2257
2258 /**
2259  * dwc2_core_init() - Initializes the DWC_otg controller registers and
2260  * prepares the core for device mode or host mode operation
2261  *
2262  * @hsotg:         Programming view of the DWC_otg controller
2263  * @initial_setup: If true then this is the first init for this instance.
2264  */
2265 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2266 {
2267         u32 usbcfg, otgctl;
2268         int retval;
2269
2270         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2271
2272         usbcfg = dwc2_readl(hsotg, GUSBCFG);
2273
2274         /* Set ULPI External VBUS bit if needed */
2275         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2276         if (hsotg->params.phy_ulpi_ext_vbus)
2277                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2278
2279         /* Set external TS Dline pulsing bit if needed */
2280         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2281         if (hsotg->params.ts_dline)
2282                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2283
2284         dwc2_writel(hsotg, usbcfg, GUSBCFG);
2285
2286         /*
2287          * Reset the Controller
2288          *
2289          * We only need to reset the controller if this is a re-init.
2290          * For the first init we know for sure that earlier code reset us (it
2291          * needed to in order to properly detect various parameters).
2292          */
2293         if (!initial_setup) {
2294                 retval = dwc2_core_reset(hsotg, false);
2295                 if (retval) {
2296                         dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2297                                 __func__);
2298                         return retval;
2299                 }
2300         }
2301
2302         /*
2303          * This needs to happen in FS mode before any other programming occurs
2304          */
2305         retval = dwc2_phy_init(hsotg, initial_setup);
2306         if (retval)
2307                 return retval;
2308
2309         /* Program the GAHBCFG Register */
2310         retval = dwc2_gahbcfg_init(hsotg);
2311         if (retval)
2312                 return retval;
2313
2314         /* Program the GUSBCFG register */
2315         dwc2_gusbcfg_init(hsotg);
2316
2317         /* Program the GOTGCTL register */
2318         otgctl = dwc2_readl(hsotg, GOTGCTL);
2319         otgctl &= ~GOTGCTL_OTGVER;
2320         dwc2_writel(hsotg, otgctl, GOTGCTL);
2321
2322         /* Clear the SRP success bit for FS-I2c */
2323         hsotg->srp_success = 0;
2324
2325         /* Enable common interrupts */
2326         dwc2_enable_common_interrupts(hsotg);
2327
2328         /*
2329          * Do device or host initialization based on mode during PCD and
2330          * HCD initialization
2331          */
2332         if (dwc2_is_host_mode(hsotg)) {
2333                 dev_dbg(hsotg->dev, "Host Mode\n");
2334                 hsotg->op_state = OTG_STATE_A_HOST;
2335         } else {
2336                 dev_dbg(hsotg->dev, "Device Mode\n");
2337                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2338         }
2339
2340         return 0;
2341 }
2342
2343 /**
2344  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2345  * Host mode
2346  *
2347  * @hsotg: Programming view of DWC_otg controller
2348  *
2349  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2350  * request queues. Host channels are reset to ensure that they are ready for
2351  * performing transfers.
2352  */
2353 static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2354 {
2355         u32 hcfg, hfir, otgctl, usbcfg;
2356
2357         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2358
2359         /* Set HS/FS Timeout Calibration to 7 (max available value).
2360          * The number of PHY clocks that the application programs in
2361          * this field is added to the high/full speed interpacket timeout
2362          * duration in the core to account for any additional delays
2363          * introduced by the PHY. This can be required, because the delay
2364          * introduced by the PHY in generating the linestate condition
2365          * can vary from one PHY to another.
2366          */
2367         usbcfg = dwc2_readl(hsotg, GUSBCFG);
2368         usbcfg |= GUSBCFG_TOUTCAL(7);
2369         dwc2_writel(hsotg, usbcfg, GUSBCFG);
2370
2371         /* Restart the Phy Clock */
2372         dwc2_writel(hsotg, 0, PCGCTL);
2373
2374         /* Initialize Host Configuration Register */
2375         dwc2_init_fs_ls_pclk_sel(hsotg);
2376         if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2377             hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2378                 hcfg = dwc2_readl(hsotg, HCFG);
2379                 hcfg |= HCFG_FSLSSUPP;
2380                 dwc2_writel(hsotg, hcfg, HCFG);
2381         }
2382
2383         /*
2384          * This bit allows dynamic reloading of the HFIR register during
2385          * runtime. This bit needs to be programmed during initial configuration
2386          * and its value must not be changed during runtime.
2387          */
2388         if (hsotg->params.reload_ctl) {
2389                 hfir = dwc2_readl(hsotg, HFIR);
2390                 hfir |= HFIR_RLDCTRL;
2391                 dwc2_writel(hsotg, hfir, HFIR);
2392         }
2393
2394         if (hsotg->params.dma_desc_enable) {
2395                 u32 op_mode = hsotg->hw_params.op_mode;
2396
2397                 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2398                     !hsotg->hw_params.dma_desc_enable ||
2399                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2400                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2401                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2402                         dev_err(hsotg->dev,
2403                                 "Hardware does not support descriptor DMA mode -\n");
2404                         dev_err(hsotg->dev,
2405                                 "falling back to buffer DMA mode.\n");
2406                         hsotg->params.dma_desc_enable = false;
2407                 } else {
2408                         hcfg = dwc2_readl(hsotg, HCFG);
2409                         hcfg |= HCFG_DESCDMA;
2410                         dwc2_writel(hsotg, hcfg, HCFG);
2411                 }
2412         }
2413
2414         /* Configure data FIFO sizes */
2415         dwc2_config_fifos(hsotg);
2416
2417         /* TODO - check this */
2418         /* Clear Host Set HNP Enable in the OTG Control Register */
2419         otgctl = dwc2_readl(hsotg, GOTGCTL);
2420         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2421         dwc2_writel(hsotg, otgctl, GOTGCTL);
2422
2423         /* Make sure the FIFOs are flushed */
2424         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2425         dwc2_flush_rx_fifo(hsotg);
2426
2427         /* Clear Host Set HNP Enable in the OTG Control Register */
2428         otgctl = dwc2_readl(hsotg, GOTGCTL);
2429         otgctl &= ~GOTGCTL_HSTSETHNPEN;
2430         dwc2_writel(hsotg, otgctl, GOTGCTL);
2431
2432         if (!hsotg->params.dma_desc_enable) {
2433                 int num_channels, i;
2434                 u32 hcchar;
2435
2436                 /* Flush out any leftover queued requests */
2437                 num_channels = hsotg->params.host_channels;
2438                 for (i = 0; i < num_channels; i++) {
2439                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
2440                         hcchar &= ~HCCHAR_CHENA;
2441                         hcchar |= HCCHAR_CHDIS;
2442                         hcchar &= ~HCCHAR_EPDIR;
2443                         dwc2_writel(hsotg, hcchar, HCCHAR(i));
2444                 }
2445
2446                 /* Halt all channels to put them into a known state */
2447                 for (i = 0; i < num_channels; i++) {
2448                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
2449                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2450                         hcchar &= ~HCCHAR_EPDIR;
2451                         dwc2_writel(hsotg, hcchar, HCCHAR(i));
2452                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2453                                 __func__, i);
2454
2455                         if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2456                                                       HCCHAR_CHENA, 1000)) {
2457                                 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2458                                          i);
2459                         }
2460                 }
2461         }
2462
2463         /* Enable ACG feature in host mode, if supported */
2464         dwc2_enable_acg(hsotg);
2465
2466         /* Turn on the vbus power */
2467         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2468         if (hsotg->op_state == OTG_STATE_A_HOST) {
2469                 u32 hprt0 = dwc2_read_hprt0(hsotg);
2470
2471                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2472                         !!(hprt0 & HPRT0_PWR));
2473                 if (!(hprt0 & HPRT0_PWR)) {
2474                         hprt0 |= HPRT0_PWR;
2475                         dwc2_writel(hsotg, hprt0, HPRT0);
2476                 }
2477         }
2478
2479         dwc2_enable_host_interrupts(hsotg);
2480 }
2481
2482 /*
2483  * Initializes dynamic portions of the DWC_otg HCD state
2484  *
2485  * Must be called with interrupt disabled and spinlock held
2486  */
2487 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2488 {
2489         struct dwc2_host_chan *chan, *chan_tmp;
2490         int num_channels;
2491         int i;
2492
2493         hsotg->flags.d32 = 0;
2494         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2495
2496         if (hsotg->params.uframe_sched) {
2497                 hsotg->available_host_channels =
2498                         hsotg->params.host_channels;
2499         } else {
2500                 hsotg->non_periodic_channels = 0;
2501                 hsotg->periodic_channels = 0;
2502         }
2503
2504         /*
2505          * Put all channels in the free channel list and clean up channel
2506          * states
2507          */
2508         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2509                                  hc_list_entry)
2510                 list_del_init(&chan->hc_list_entry);
2511
2512         num_channels = hsotg->params.host_channels;
2513         for (i = 0; i < num_channels; i++) {
2514                 chan = hsotg->hc_ptr_array[i];
2515                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2516                 dwc2_hc_cleanup(hsotg, chan);
2517         }
2518
2519         /* Initialize the DWC core for host mode operation */
2520         dwc2_core_host_init(hsotg);
2521 }
2522
2523 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2524                                struct dwc2_host_chan *chan,
2525                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2526 {
2527         int hub_addr, hub_port;
2528
2529         chan->do_split = 1;
2530         chan->xact_pos = qtd->isoc_split_pos;
2531         chan->complete_split = qtd->complete_split;
2532         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2533         chan->hub_addr = (u8)hub_addr;
2534         chan->hub_port = (u8)hub_port;
2535 }
2536
2537 static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2538                               struct dwc2_host_chan *chan,
2539                               struct dwc2_qtd *qtd)
2540 {
2541         struct dwc2_hcd_urb *urb = qtd->urb;
2542         struct dwc2_hcd_iso_packet_desc *frame_desc;
2543
2544         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2545         case USB_ENDPOINT_XFER_CONTROL:
2546                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2547
2548                 switch (qtd->control_phase) {
2549                 case DWC2_CONTROL_SETUP:
2550                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
2551                         chan->do_ping = 0;
2552                         chan->ep_is_in = 0;
2553                         chan->data_pid_start = DWC2_HC_PID_SETUP;
2554                         if (hsotg->params.host_dma)
2555                                 chan->xfer_dma = urb->setup_dma;
2556                         else
2557                                 chan->xfer_buf = urb->setup_packet;
2558                         chan->xfer_len = 8;
2559                         break;
2560
2561                 case DWC2_CONTROL_DATA:
2562                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
2563                         chan->data_pid_start = qtd->data_toggle;
2564                         break;
2565
2566                 case DWC2_CONTROL_STATUS:
2567                         /*
2568                          * Direction is opposite of data direction or IN if no
2569                          * data
2570                          */
2571                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
2572                         if (urb->length == 0)
2573                                 chan->ep_is_in = 1;
2574                         else
2575                                 chan->ep_is_in =
2576                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
2577                         if (chan->ep_is_in)
2578                                 chan->do_ping = 0;
2579                         chan->data_pid_start = DWC2_HC_PID_DATA1;
2580                         chan->xfer_len = 0;
2581                         if (hsotg->params.host_dma)
2582                                 chan->xfer_dma = hsotg->status_buf_dma;
2583                         else
2584                                 chan->xfer_buf = hsotg->status_buf;
2585                         break;
2586                 }
2587                 break;
2588
2589         case USB_ENDPOINT_XFER_BULK:
2590                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2591                 break;
2592
2593         case USB_ENDPOINT_XFER_INT:
2594                 chan->ep_type = USB_ENDPOINT_XFER_INT;
2595                 break;
2596
2597         case USB_ENDPOINT_XFER_ISOC:
2598                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2599                 if (hsotg->params.dma_desc_enable)
2600                         break;
2601
2602                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2603                 frame_desc->status = 0;
2604
2605                 if (hsotg->params.host_dma) {
2606                         chan->xfer_dma = urb->dma;
2607                         chan->xfer_dma += frame_desc->offset +
2608                                         qtd->isoc_split_offset;
2609                 } else {
2610                         chan->xfer_buf = urb->buf;
2611                         chan->xfer_buf += frame_desc->offset +
2612                                         qtd->isoc_split_offset;
2613                 }
2614
2615                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2616
2617                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2618                         if (chan->xfer_len <= 188)
2619                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2620                         else
2621                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2622                 }
2623                 break;
2624         }
2625 }
2626
2627 static int dwc2_alloc_split_dma_aligned_buf(struct dwc2_hsotg *hsotg,
2628                                             struct dwc2_qh *qh,
2629                                             struct dwc2_host_chan *chan)
2630 {
2631         if (!hsotg->unaligned_cache ||
2632             chan->max_packet > DWC2_KMEM_UNALIGNED_BUF_SIZE)
2633                 return -ENOMEM;
2634
2635         if (!qh->dw_align_buf) {
2636                 qh->dw_align_buf = kmem_cache_alloc(hsotg->unaligned_cache,
2637                                                     GFP_ATOMIC | GFP_DMA);
2638                 if (!qh->dw_align_buf)
2639                         return -ENOMEM;
2640         }
2641
2642         qh->dw_align_buf_dma = dma_map_single(hsotg->dev, qh->dw_align_buf,
2643                                               DWC2_KMEM_UNALIGNED_BUF_SIZE,
2644                                               DMA_FROM_DEVICE);
2645
2646         if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
2647                 dev_err(hsotg->dev, "can't map align_buf\n");
2648                 chan->align_buf = 0;
2649                 return -EINVAL;
2650         }
2651
2652         chan->align_buf = qh->dw_align_buf_dma;
2653         return 0;
2654 }
2655
2656 #define DWC2_USB_DMA_ALIGN 4
2657
2658 static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2659 {
2660         void *stored_xfer_buffer;
2661         size_t length;
2662
2663         if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2664                 return;
2665
2666         /* Restore urb->transfer_buffer from the end of the allocated area */
2667         memcpy(&stored_xfer_buffer, urb->transfer_buffer +
2668                urb->transfer_buffer_length, sizeof(urb->transfer_buffer));
2669
2670         if (usb_urb_dir_in(urb)) {
2671                 if (usb_pipeisoc(urb->pipe))
2672                         length = urb->transfer_buffer_length;
2673                 else
2674                         length = urb->actual_length;
2675
2676                 memcpy(stored_xfer_buffer, urb->transfer_buffer, length);
2677         }
2678         kfree(urb->transfer_buffer);
2679         urb->transfer_buffer = stored_xfer_buffer;
2680
2681         urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2682 }
2683
2684 static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2685 {
2686         void *kmalloc_ptr;
2687         size_t kmalloc_size;
2688
2689         if (urb->num_sgs || urb->sg ||
2690             urb->transfer_buffer_length == 0 ||
2691             !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2692                 return 0;
2693
2694         /*
2695          * Allocate a buffer with enough padding for original transfer_buffer
2696          * pointer. This allocation is guaranteed to be aligned properly for
2697          * DMA
2698          */
2699         kmalloc_size = urb->transfer_buffer_length +
2700                 sizeof(urb->transfer_buffer);
2701
2702         kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2703         if (!kmalloc_ptr)
2704                 return -ENOMEM;
2705
2706         /*
2707          * Position value of original urb->transfer_buffer pointer to the end
2708          * of allocation for later referencing
2709          */
2710         memcpy(kmalloc_ptr + urb->transfer_buffer_length,
2711                &urb->transfer_buffer, sizeof(urb->transfer_buffer));
2712
2713         if (usb_urb_dir_out(urb))
2714                 memcpy(kmalloc_ptr, urb->transfer_buffer,
2715                        urb->transfer_buffer_length);
2716         urb->transfer_buffer = kmalloc_ptr;
2717
2718         urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2719
2720         return 0;
2721 }
2722
2723 static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2724                                 gfp_t mem_flags)
2725 {
2726         int ret;
2727
2728         /* We assume setup_dma is always aligned; warn if not */
2729         WARN_ON_ONCE(urb->setup_dma &&
2730                      (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2731
2732         ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2733         if (ret)
2734                 return ret;
2735
2736         ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2737         if (ret)
2738                 dwc2_free_dma_aligned_buffer(urb);
2739
2740         return ret;
2741 }
2742
2743 static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2744 {
2745         usb_hcd_unmap_urb_for_dma(hcd, urb);
2746         dwc2_free_dma_aligned_buffer(urb);
2747 }
2748
2749 /**
2750  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2751  * channel and initializes the host channel to perform the transactions. The
2752  * host channel is removed from the free list.
2753  *
2754  * @hsotg: The HCD state structure
2755  * @qh:    Transactions from the first QTD for this QH are selected and assigned
2756  *         to a free host channel
2757  */
2758 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2759 {
2760         struct dwc2_host_chan *chan;
2761         struct dwc2_hcd_urb *urb;
2762         struct dwc2_qtd *qtd;
2763
2764         if (dbg_qh(qh))
2765                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2766
2767         if (list_empty(&qh->qtd_list)) {
2768                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2769                 return -ENOMEM;
2770         }
2771
2772         if (list_empty(&hsotg->free_hc_list)) {
2773                 dev_dbg(hsotg->dev, "No free channel to assign\n");
2774                 return -ENOMEM;
2775         }
2776
2777         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2778                                 hc_list_entry);
2779
2780         /* Remove host channel from free list */
2781         list_del_init(&chan->hc_list_entry);
2782
2783         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2784         urb = qtd->urb;
2785         qh->channel = chan;
2786         qtd->in_process = 1;
2787
2788         /*
2789          * Use usb_pipedevice to determine device address. This address is
2790          * 0 before the SET_ADDRESS command and the correct address afterward.
2791          */
2792         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2793         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2794         chan->speed = qh->dev_speed;
2795         chan->max_packet = dwc2_max_packet(qh->maxp);
2796
2797         chan->xfer_started = 0;
2798         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2799         chan->error_state = (qtd->error_count > 0);
2800         chan->halt_on_queue = 0;
2801         chan->halt_pending = 0;
2802         chan->requests = 0;
2803
2804         /*
2805          * The following values may be modified in the transfer type section
2806          * below. The xfer_len value may be reduced when the transfer is
2807          * started to accommodate the max widths of the XferSize and PktCnt
2808          * fields in the HCTSIZn register.
2809          */
2810
2811         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2812         if (chan->ep_is_in)
2813                 chan->do_ping = 0;
2814         else
2815                 chan->do_ping = qh->ping_state;
2816
2817         chan->data_pid_start = qh->data_toggle;
2818         chan->multi_count = 1;
2819
2820         if (urb->actual_length > urb->length &&
2821             !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2822                 urb->actual_length = urb->length;
2823
2824         if (hsotg->params.host_dma)
2825                 chan->xfer_dma = urb->dma + urb->actual_length;
2826         else
2827                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2828
2829         chan->xfer_len = urb->length - urb->actual_length;
2830         chan->xfer_count = 0;
2831
2832         /* Set the split attributes if required */
2833         if (qh->do_split)
2834                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2835         else
2836                 chan->do_split = 0;
2837
2838         /* Set the transfer attributes */
2839         dwc2_hc_init_xfer(hsotg, chan, qtd);
2840
2841         /* For non-dword aligned buffers */
2842         if (hsotg->params.host_dma && qh->do_split &&
2843             chan->ep_is_in && (chan->xfer_dma & 0x3)) {
2844                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
2845                 if (dwc2_alloc_split_dma_aligned_buf(hsotg, qh, chan)) {
2846                         dev_err(hsotg->dev,
2847                                 "Failed to allocate memory to handle non-aligned buffer\n");
2848                         /* Add channel back to free list */
2849                         chan->align_buf = 0;
2850                         chan->multi_count = 0;
2851                         list_add_tail(&chan->hc_list_entry,
2852                                       &hsotg->free_hc_list);
2853                         qtd->in_process = 0;
2854                         qh->channel = NULL;
2855                         return -ENOMEM;
2856                 }
2857         } else {
2858                 /*
2859                  * We assume that DMA is always aligned in non-split
2860                  * case or split out case. Warn if not.
2861                  */
2862                 WARN_ON_ONCE(hsotg->params.host_dma &&
2863                              (chan->xfer_dma & 0x3));
2864                 chan->align_buf = 0;
2865         }
2866
2867         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2868             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2869                 /*
2870                  * This value may be modified when the transfer is started
2871                  * to reflect the actual transfer length
2872                  */
2873                 chan->multi_count = dwc2_hb_mult(qh->maxp);
2874
2875         if (hsotg->params.dma_desc_enable) {
2876                 chan->desc_list_addr = qh->desc_list_dma;
2877                 chan->desc_list_sz = qh->desc_list_sz;
2878         }
2879
2880         dwc2_hc_init(hsotg, chan);
2881         chan->qh = qh;
2882
2883         return 0;
2884 }
2885
2886 /**
2887  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2888  * schedule and assigns them to available host channels. Called from the HCD
2889  * interrupt handler functions.
2890  *
2891  * @hsotg: The HCD state structure
2892  *
2893  * Return: The types of new transactions that were assigned to host channels
2894  */
2895 enum dwc2_transaction_type dwc2_hcd_select_transactions(
2896                 struct dwc2_hsotg *hsotg)
2897 {
2898         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2899         struct list_head *qh_ptr;
2900         struct dwc2_qh *qh;
2901         int num_channels;
2902
2903 #ifdef DWC2_DEBUG_SOF
2904         dev_vdbg(hsotg->dev, "  Select Transactions\n");
2905 #endif
2906
2907         /* Process entries in the periodic ready list */
2908         qh_ptr = hsotg->periodic_sched_ready.next;
2909         while (qh_ptr != &hsotg->periodic_sched_ready) {
2910                 if (list_empty(&hsotg->free_hc_list))
2911                         break;
2912                 if (hsotg->params.uframe_sched) {
2913                         if (hsotg->available_host_channels <= 1)
2914                                 break;
2915                         hsotg->available_host_channels--;
2916                 }
2917                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2918                 if (dwc2_assign_and_init_hc(hsotg, qh))
2919                         break;
2920
2921                 /*
2922                  * Move the QH from the periodic ready schedule to the
2923                  * periodic assigned schedule
2924                  */
2925                 qh_ptr = qh_ptr->next;
2926                 list_move_tail(&qh->qh_list_entry,
2927                                &hsotg->periodic_sched_assigned);
2928                 ret_val = DWC2_TRANSACTION_PERIODIC;
2929         }
2930
2931         /*
2932          * Process entries in the inactive portion of the non-periodic
2933          * schedule. Some free host channels may not be used if they are
2934          * reserved for periodic transfers.
2935          */
2936         num_channels = hsotg->params.host_channels;
2937         qh_ptr = hsotg->non_periodic_sched_inactive.next;
2938         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2939                 if (!hsotg->params.uframe_sched &&
2940                     hsotg->non_periodic_channels >= num_channels -
2941                                                 hsotg->periodic_channels)
2942                         break;
2943                 if (list_empty(&hsotg->free_hc_list))
2944                         break;
2945                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2946                 if (hsotg->params.uframe_sched) {
2947                         if (hsotg->available_host_channels < 1)
2948                                 break;
2949                         hsotg->available_host_channels--;
2950                 }
2951
2952                 if (dwc2_assign_and_init_hc(hsotg, qh))
2953                         break;
2954
2955                 /*
2956                  * Move the QH from the non-periodic inactive schedule to the
2957                  * non-periodic active schedule
2958                  */
2959                 qh_ptr = qh_ptr->next;
2960                 list_move_tail(&qh->qh_list_entry,
2961                                &hsotg->non_periodic_sched_active);
2962
2963                 if (ret_val == DWC2_TRANSACTION_NONE)
2964                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2965                 else
2966                         ret_val = DWC2_TRANSACTION_ALL;
2967
2968                 if (!hsotg->params.uframe_sched)
2969                         hsotg->non_periodic_channels++;
2970         }
2971
2972         return ret_val;
2973 }
2974
2975 /**
2976  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2977  * a host channel associated with either a periodic or non-periodic transfer
2978  *
2979  * @hsotg: The HCD state structure
2980  * @chan:  Host channel descriptor associated with either a periodic or
2981  *         non-periodic transfer
2982  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2983  *                     for periodic transfers or the non-periodic Tx FIFO
2984  *                     for non-periodic transfers
2985  *
2986  * Return: 1 if a request is queued and more requests may be needed to
2987  * complete the transfer, 0 if no more requests are required for this
2988  * transfer, -1 if there is insufficient space in the Tx FIFO
2989  *
2990  * This function assumes that there is space available in the appropriate
2991  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2992  * it checks whether space is available in the appropriate Tx FIFO.
2993  *
2994  * Must be called with interrupt disabled and spinlock held
2995  */
2996 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2997                                   struct dwc2_host_chan *chan,
2998                                   u16 fifo_dwords_avail)
2999 {
3000         int retval = 0;
3001
3002         if (chan->do_split)
3003                 /* Put ourselves on the list to keep order straight */
3004                 list_move_tail(&chan->split_order_list_entry,
3005                                &hsotg->split_order);
3006
3007         if (hsotg->params.host_dma) {
3008                 if (hsotg->params.dma_desc_enable) {
3009                         if (!chan->xfer_started ||
3010                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
3011                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
3012                                 chan->qh->ping_state = 0;
3013                         }
3014                 } else if (!chan->xfer_started) {
3015                         dwc2_hc_start_transfer(hsotg, chan);
3016                         chan->qh->ping_state = 0;
3017                 }
3018         } else if (chan->halt_pending) {
3019                 /* Don't queue a request if the channel has been halted */
3020         } else if (chan->halt_on_queue) {
3021                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
3022         } else if (chan->do_ping) {
3023                 if (!chan->xfer_started)
3024                         dwc2_hc_start_transfer(hsotg, chan);
3025         } else if (!chan->ep_is_in ||
3026                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
3027                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
3028                         if (!chan->xfer_started) {
3029                                 dwc2_hc_start_transfer(hsotg, chan);
3030                                 retval = 1;
3031                         } else {
3032                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
3033                         }
3034                 } else {
3035                         retval = -1;
3036                 }
3037         } else {
3038                 if (!chan->xfer_started) {
3039                         dwc2_hc_start_transfer(hsotg, chan);
3040                         retval = 1;
3041                 } else {
3042                         retval = dwc2_hc_continue_transfer(hsotg, chan);
3043                 }
3044         }
3045
3046         return retval;
3047 }
3048
3049 /*
3050  * Processes periodic channels for the next frame and queues transactions for
3051  * these channels to the DWC_otg controller. After queueing transactions, the
3052  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3053  * to queue as Periodic Tx FIFO or request queue space becomes available.
3054  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3055  *
3056  * Must be called with interrupt disabled and spinlock held
3057  */
3058 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
3059 {
3060         struct list_head *qh_ptr;
3061         struct dwc2_qh *qh;
3062         u32 tx_status;
3063         u32 fspcavail;
3064         u32 gintmsk;
3065         int status;
3066         bool no_queue_space = false;
3067         bool no_fifo_space = false;
3068         u32 qspcavail;
3069
3070         /* If empty list then just adjust interrupt enables */
3071         if (list_empty(&hsotg->periodic_sched_assigned))
3072                 goto exit;
3073
3074         if (dbg_perio())
3075                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3076
3077         tx_status = dwc2_readl(hsotg, HPTXSTS);
3078         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3079                     TXSTS_QSPCAVAIL_SHIFT;
3080         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3081                     TXSTS_FSPCAVAIL_SHIFT;
3082
3083         if (dbg_perio()) {
3084                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
3085                          qspcavail);
3086                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
3087                          fspcavail);
3088         }
3089
3090         qh_ptr = hsotg->periodic_sched_assigned.next;
3091         while (qh_ptr != &hsotg->periodic_sched_assigned) {
3092                 tx_status = dwc2_readl(hsotg, HPTXSTS);
3093                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3094                             TXSTS_QSPCAVAIL_SHIFT;
3095                 if (qspcavail == 0) {
3096                         no_queue_space = true;
3097                         break;
3098                 }
3099
3100                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3101                 if (!qh->channel) {
3102                         qh_ptr = qh_ptr->next;
3103                         continue;
3104                 }
3105
3106                 /* Make sure EP's TT buffer is clean before queueing qtds */
3107                 if (qh->tt_buffer_dirty) {
3108                         qh_ptr = qh_ptr->next;
3109                         continue;
3110                 }
3111
3112                 /*
3113                  * Set a flag if we're queuing high-bandwidth in slave mode.
3114                  * The flag prevents any halts to get into the request queue in
3115                  * the middle of multiple high-bandwidth packets getting queued.
3116                  */
3117                 if (!hsotg->params.host_dma &&
3118                     qh->channel->multi_count > 1)
3119                         hsotg->queuing_high_bandwidth = 1;
3120
3121                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3122                             TXSTS_FSPCAVAIL_SHIFT;
3123                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3124                 if (status < 0) {
3125                         no_fifo_space = true;
3126                         break;
3127                 }
3128
3129                 /*
3130                  * In Slave mode, stay on the current transfer until there is
3131                  * nothing more to do or the high-bandwidth request count is
3132                  * reached. In DMA mode, only need to queue one request. The
3133                  * controller automatically handles multiple packets for
3134                  * high-bandwidth transfers.
3135                  */
3136                 if (hsotg->params.host_dma || status == 0 ||
3137                     qh->channel->requests == qh->channel->multi_count) {
3138                         qh_ptr = qh_ptr->next;
3139                         /*
3140                          * Move the QH from the periodic assigned schedule to
3141                          * the periodic queued schedule
3142                          */
3143                         list_move_tail(&qh->qh_list_entry,
3144                                        &hsotg->periodic_sched_queued);
3145
3146                         /* done queuing high bandwidth */
3147                         hsotg->queuing_high_bandwidth = 0;
3148                 }
3149         }
3150
3151 exit:
3152         if (no_queue_space || no_fifo_space ||
3153             (!hsotg->params.host_dma &&
3154              !list_empty(&hsotg->periodic_sched_assigned))) {
3155                 /*
3156                  * May need to queue more transactions as the request
3157                  * queue or Tx FIFO empties. Enable the periodic Tx
3158                  * FIFO empty interrupt. (Always use the half-empty
3159                  * level to ensure that new requests are loaded as
3160                  * soon as possible.)
3161                  */
3162                 gintmsk = dwc2_readl(hsotg, GINTMSK);
3163                 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3164                         gintmsk |= GINTSTS_PTXFEMP;
3165                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3166                 }
3167         } else {
3168                 /*
3169                  * Disable the Tx FIFO empty interrupt since there are
3170                  * no more transactions that need to be queued right
3171                  * now. This function is called from interrupt
3172                  * handlers to queue more transactions as transfer
3173                  * states change.
3174                  */
3175                 gintmsk = dwc2_readl(hsotg, GINTMSK);
3176                 if (gintmsk & GINTSTS_PTXFEMP) {
3177                         gintmsk &= ~GINTSTS_PTXFEMP;
3178                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3179                 }
3180         }
3181 }
3182
3183 /*
3184  * Processes active non-periodic channels and queues transactions for these
3185  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3186  * FIFO Empty interrupt is enabled if there are more transactions to queue as
3187  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3188  * FIFO Empty interrupt is disabled.
3189  *
3190  * Must be called with interrupt disabled and spinlock held
3191  */
3192 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3193 {
3194         struct list_head *orig_qh_ptr;
3195         struct dwc2_qh *qh;
3196         u32 tx_status;
3197         u32 qspcavail;
3198         u32 fspcavail;
3199         u32 gintmsk;
3200         int status;
3201         int no_queue_space = 0;
3202         int no_fifo_space = 0;
3203         int more_to_do = 0;
3204
3205         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3206
3207         tx_status = dwc2_readl(hsotg, GNPTXSTS);
3208         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3209                     TXSTS_QSPCAVAIL_SHIFT;
3210         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3211                     TXSTS_FSPCAVAIL_SHIFT;
3212         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3213                  qspcavail);
3214         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
3215                  fspcavail);
3216
3217         /*
3218          * Keep track of the starting point. Skip over the start-of-list
3219          * entry.
3220          */
3221         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3222                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3223         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3224
3225         /*
3226          * Process once through the active list or until no more space is
3227          * available in the request queue or the Tx FIFO
3228          */
3229         do {
3230                 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3231                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3232                             TXSTS_QSPCAVAIL_SHIFT;
3233                 if (!hsotg->params.host_dma && qspcavail == 0) {
3234                         no_queue_space = 1;
3235                         break;
3236                 }
3237
3238                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3239                                 qh_list_entry);
3240                 if (!qh->channel)
3241                         goto next;
3242
3243                 /* Make sure EP's TT buffer is clean before queueing qtds */
3244                 if (qh->tt_buffer_dirty)
3245                         goto next;
3246
3247                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3248                             TXSTS_FSPCAVAIL_SHIFT;
3249                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3250
3251                 if (status > 0) {
3252                         more_to_do = 1;
3253                 } else if (status < 0) {
3254                         no_fifo_space = 1;
3255                         break;
3256                 }
3257 next:
3258                 /* Advance to next QH, skipping start-of-list entry */
3259                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3260                 if (hsotg->non_periodic_qh_ptr ==
3261                                 &hsotg->non_periodic_sched_active)
3262                         hsotg->non_periodic_qh_ptr =
3263                                         hsotg->non_periodic_qh_ptr->next;
3264         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3265
3266         if (!hsotg->params.host_dma) {
3267                 tx_status = dwc2_readl(hsotg, GNPTXSTS);
3268                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3269                             TXSTS_QSPCAVAIL_SHIFT;
3270                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3271                             TXSTS_FSPCAVAIL_SHIFT;
3272                 dev_vdbg(hsotg->dev,
3273                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
3274                          qspcavail);
3275                 dev_vdbg(hsotg->dev,
3276                          "  NP Tx FIFO Space Avail (after queue): %d\n",
3277                          fspcavail);
3278
3279                 if (more_to_do || no_queue_space || no_fifo_space) {
3280                         /*
3281                          * May need to queue more transactions as the request
3282                          * queue or Tx FIFO empties. Enable the non-periodic
3283                          * Tx FIFO empty interrupt. (Always use the half-empty
3284                          * level to ensure that new requests are loaded as
3285                          * soon as possible.)
3286                          */
3287                         gintmsk = dwc2_readl(hsotg, GINTMSK);
3288                         gintmsk |= GINTSTS_NPTXFEMP;
3289                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3290                 } else {
3291                         /*
3292                          * Disable the Tx FIFO empty interrupt since there are
3293                          * no more transactions that need to be queued right
3294                          * now. This function is called from interrupt
3295                          * handlers to queue more transactions as transfer
3296                          * states change.
3297                          */
3298                         gintmsk = dwc2_readl(hsotg, GINTMSK);
3299                         gintmsk &= ~GINTSTS_NPTXFEMP;
3300                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3301                 }
3302         }
3303 }
3304
3305 /**
3306  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3307  * and queues transactions for these channels to the DWC_otg controller. Called
3308  * from the HCD interrupt handler functions.
3309  *
3310  * @hsotg:   The HCD state structure
3311  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3312  *           or both)
3313  *
3314  * Must be called with interrupt disabled and spinlock held
3315  */
3316 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3317                                  enum dwc2_transaction_type tr_type)
3318 {
3319 #ifdef DWC2_DEBUG_SOF
3320         dev_vdbg(hsotg->dev, "Queue Transactions\n");
3321 #endif
3322         /* Process host channels associated with periodic transfers */
3323         if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3324             tr_type == DWC2_TRANSACTION_ALL)
3325                 dwc2_process_periodic_channels(hsotg);
3326
3327         /* Process host channels associated with non-periodic transfers */
3328         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3329             tr_type == DWC2_TRANSACTION_ALL) {
3330                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3331                         dwc2_process_non_periodic_channels(hsotg);
3332                 } else {
3333                         /*
3334                          * Ensure NP Tx FIFO empty interrupt is disabled when
3335                          * there are no non-periodic transfers to process
3336                          */
3337                         u32 gintmsk = dwc2_readl(hsotg, GINTMSK);
3338
3339                         gintmsk &= ~GINTSTS_NPTXFEMP;
3340                         dwc2_writel(hsotg, gintmsk, GINTMSK);
3341                 }
3342         }
3343 }
3344
3345 static void dwc2_conn_id_status_change(struct work_struct *work)
3346 {
3347         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3348                                                 wf_otg);
3349         u32 count = 0;
3350         u32 gotgctl;
3351         unsigned long flags;
3352
3353         dev_dbg(hsotg->dev, "%s()\n", __func__);
3354
3355         gotgctl = dwc2_readl(hsotg, GOTGCTL);
3356         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3357         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3358                 !!(gotgctl & GOTGCTL_CONID_B));
3359
3360         /* B-Device connector (Device Mode) */
3361         if (gotgctl & GOTGCTL_CONID_B) {
3362                 dwc2_vbus_supply_exit(hsotg);
3363                 /* Wait for switch to device mode */
3364                 dev_dbg(hsotg->dev, "connId B\n");
3365                 if (hsotg->bus_suspended) {
3366                         dev_info(hsotg->dev,
3367                                  "Do port resume before switching to device mode\n");
3368                         dwc2_port_resume(hsotg);
3369                 }
3370                 while (!dwc2_is_device_mode(hsotg)) {
3371                         dev_info(hsotg->dev,
3372                                  "Waiting for Peripheral Mode, Mode=%s\n",
3373                                  dwc2_is_host_mode(hsotg) ? "Host" :
3374                                  "Peripheral");
3375                         msleep(20);
3376                         /*
3377                          * Sometimes the initial GOTGCTRL read is wrong, so
3378                          * check it again and jump to host mode if that was
3379                          * the case.
3380                          */
3381                         gotgctl = dwc2_readl(hsotg, GOTGCTL);
3382                         if (!(gotgctl & GOTGCTL_CONID_B))
3383                                 goto host;
3384                         if (++count > 250)
3385                                 break;
3386                 }
3387                 if (count > 250)
3388                         dev_err(hsotg->dev,
3389                                 "Connection id status change timed out\n");
3390                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3391                 dwc2_core_init(hsotg, false);
3392                 dwc2_enable_global_interrupts(hsotg);
3393                 spin_lock_irqsave(&hsotg->lock, flags);
3394                 dwc2_hsotg_core_init_disconnected(hsotg, false);
3395                 spin_unlock_irqrestore(&hsotg->lock, flags);
3396                 /* Enable ACG feature in device mode,if supported */
3397                 dwc2_enable_acg(hsotg);
3398                 dwc2_hsotg_core_connect(hsotg);
3399         } else {
3400 host:
3401                 /* A-Device connector (Host Mode) */
3402                 dev_dbg(hsotg->dev, "connId A\n");
3403                 while (!dwc2_is_host_mode(hsotg)) {
3404                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3405                                  dwc2_is_host_mode(hsotg) ?
3406                                  "Host" : "Peripheral");
3407                         msleep(20);
3408                         if (++count > 250)
3409                                 break;
3410                 }
3411                 if (count > 250)
3412                         dev_err(hsotg->dev,
3413                                 "Connection id status change timed out\n");
3414
3415                 spin_lock_irqsave(&hsotg->lock, flags);
3416                 dwc2_hsotg_disconnect(hsotg);
3417                 spin_unlock_irqrestore(&hsotg->lock, flags);
3418
3419                 hsotg->op_state = OTG_STATE_A_HOST;
3420                 /* Initialize the Core for Host mode */
3421                 dwc2_core_init(hsotg, false);
3422                 dwc2_enable_global_interrupts(hsotg);
3423                 dwc2_hcd_start(hsotg);
3424         }
3425 }
3426
3427 static void dwc2_wakeup_detected(struct timer_list *t)
3428 {
3429         struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3430         u32 hprt0;
3431
3432         dev_dbg(hsotg->dev, "%s()\n", __func__);
3433
3434         /*
3435          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3436          * so that OPT tests pass with all PHYs.)
3437          */
3438         hprt0 = dwc2_read_hprt0(hsotg);
3439         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3440         hprt0 &= ~HPRT0_RES;
3441         dwc2_writel(hsotg, hprt0, HPRT0);
3442         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3443                 dwc2_readl(hsotg, HPRT0));
3444
3445         dwc2_hcd_rem_wakeup(hsotg);
3446         hsotg->bus_suspended = false;
3447
3448         /* Change to L0 state */
3449         hsotg->lx_state = DWC2_L0;
3450 }
3451
3452 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3453 {
3454         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3455
3456         return hcd->self.b_hnp_enable;
3457 }
3458
3459 /* Must NOT be called with interrupt disabled or spinlock held */
3460 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3461 {
3462         unsigned long flags;
3463         u32 hprt0;
3464         u32 pcgctl;
3465         u32 gotgctl;
3466
3467         dev_dbg(hsotg->dev, "%s()\n", __func__);
3468
3469         spin_lock_irqsave(&hsotg->lock, flags);
3470
3471         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3472                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
3473                 gotgctl |= GOTGCTL_HSTSETHNPEN;
3474                 dwc2_writel(hsotg, gotgctl, GOTGCTL);
3475                 hsotg->op_state = OTG_STATE_A_SUSPEND;
3476         }
3477
3478         hprt0 = dwc2_read_hprt0(hsotg);
3479         hprt0 |= HPRT0_SUSP;
3480         dwc2_writel(hsotg, hprt0, HPRT0);
3481
3482         hsotg->bus_suspended = true;
3483
3484         /*
3485          * If power_down is supported, Phy clock will be suspended
3486          * after registers are backuped.
3487          */
3488         if (!hsotg->params.power_down) {
3489                 /* Suspend the Phy Clock */
3490                 pcgctl = dwc2_readl(hsotg, PCGCTL);
3491                 pcgctl |= PCGCTL_STOPPCLK;
3492                 dwc2_writel(hsotg, pcgctl, PCGCTL);
3493                 udelay(10);
3494         }
3495
3496         /* For HNP the bus must be suspended for at least 200ms */
3497         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3498                 pcgctl = dwc2_readl(hsotg, PCGCTL);
3499                 pcgctl &= ~PCGCTL_STOPPCLK;
3500                 dwc2_writel(hsotg, pcgctl, PCGCTL);
3501
3502                 spin_unlock_irqrestore(&hsotg->lock, flags);
3503
3504                 msleep(200);
3505         } else {
3506                 spin_unlock_irqrestore(&hsotg->lock, flags);
3507         }
3508 }
3509
3510 /* Must NOT be called with interrupt disabled or spinlock held */
3511 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3512 {
3513         unsigned long flags;
3514         u32 hprt0;
3515         u32 pcgctl;
3516
3517         spin_lock_irqsave(&hsotg->lock, flags);
3518
3519         /*
3520          * If power_down is supported, Phy clock is already resumed
3521          * after registers restore.
3522          */
3523         if (!hsotg->params.power_down) {
3524                 pcgctl = dwc2_readl(hsotg, PCGCTL);
3525                 pcgctl &= ~PCGCTL_STOPPCLK;
3526                 dwc2_writel(hsotg, pcgctl, PCGCTL);
3527                 spin_unlock_irqrestore(&hsotg->lock, flags);
3528                 msleep(20);
3529                 spin_lock_irqsave(&hsotg->lock, flags);
3530         }
3531
3532         hprt0 = dwc2_read_hprt0(hsotg);
3533         hprt0 |= HPRT0_RES;
3534         hprt0 &= ~HPRT0_SUSP;
3535         dwc2_writel(hsotg, hprt0, HPRT0);
3536         spin_unlock_irqrestore(&hsotg->lock, flags);
3537
3538         msleep(USB_RESUME_TIMEOUT);
3539
3540         spin_lock_irqsave(&hsotg->lock, flags);
3541         hprt0 = dwc2_read_hprt0(hsotg);
3542         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3543         dwc2_writel(hsotg, hprt0, HPRT0);
3544         hsotg->bus_suspended = false;
3545         spin_unlock_irqrestore(&hsotg->lock, flags);
3546 }
3547
3548 /* Handles hub class-specific requests */
3549 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3550                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
3551 {
3552         struct usb_hub_descriptor *hub_desc;
3553         int retval = 0;
3554         u32 hprt0;
3555         u32 port_status;
3556         u32 speed;
3557         u32 pcgctl;
3558         u32 pwr;
3559
3560         switch (typereq) {
3561         case ClearHubFeature:
3562                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3563
3564                 switch (wvalue) {
3565                 case C_HUB_LOCAL_POWER:
3566                 case C_HUB_OVER_CURRENT:
3567                         /* Nothing required here */
3568                         break;
3569
3570                 default:
3571                         retval = -EINVAL;
3572                         dev_err(hsotg->dev,
3573                                 "ClearHubFeature request %1xh unknown\n",
3574                                 wvalue);
3575                 }
3576                 break;
3577
3578         case ClearPortFeature:
3579                 if (wvalue != USB_PORT_FEAT_L1)
3580                         if (!windex || windex > 1)
3581                                 goto error;
3582                 switch (wvalue) {
3583                 case USB_PORT_FEAT_ENABLE:
3584                         dev_dbg(hsotg->dev,
3585                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3586                         hprt0 = dwc2_read_hprt0(hsotg);
3587                         hprt0 |= HPRT0_ENA;
3588                         dwc2_writel(hsotg, hprt0, HPRT0);
3589                         break;
3590
3591                 case USB_PORT_FEAT_SUSPEND:
3592                         dev_dbg(hsotg->dev,
3593                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3594
3595                         if (hsotg->bus_suspended) {
3596                                 if (hsotg->hibernated)
3597                                         dwc2_exit_hibernation(hsotg, 0, 0, 1);
3598                                 else
3599                                         dwc2_port_resume(hsotg);
3600                         }
3601                         break;
3602
3603                 case USB_PORT_FEAT_POWER:
3604                         dev_dbg(hsotg->dev,
3605                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3606                         hprt0 = dwc2_read_hprt0(hsotg);
3607                         pwr = hprt0 & HPRT0_PWR;
3608                         hprt0 &= ~HPRT0_PWR;
3609                         dwc2_writel(hsotg, hprt0, HPRT0);
3610                         if (pwr)
3611                                 dwc2_vbus_supply_exit(hsotg);
3612                         break;
3613
3614                 case USB_PORT_FEAT_INDICATOR:
3615                         dev_dbg(hsotg->dev,
3616                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3617                         /* Port indicator not supported */
3618                         break;
3619
3620                 case USB_PORT_FEAT_C_CONNECTION:
3621                         /*
3622                          * Clears driver's internal Connect Status Change flag
3623                          */
3624                         dev_dbg(hsotg->dev,
3625                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3626                         hsotg->flags.b.port_connect_status_change = 0;
3627                         break;
3628
3629                 case USB_PORT_FEAT_C_RESET:
3630                         /* Clears driver's internal Port Reset Change flag */
3631                         dev_dbg(hsotg->dev,
3632                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3633                         hsotg->flags.b.port_reset_change = 0;
3634                         break;
3635
3636                 case USB_PORT_FEAT_C_ENABLE:
3637                         /*
3638                          * Clears the driver's internal Port Enable/Disable
3639                          * Change flag
3640                          */
3641                         dev_dbg(hsotg->dev,
3642                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3643                         hsotg->flags.b.port_enable_change = 0;
3644                         break;
3645
3646                 case USB_PORT_FEAT_C_SUSPEND:
3647                         /*
3648                          * Clears the driver's internal Port Suspend Change
3649                          * flag, which is set when resume signaling on the host
3650                          * port is complete
3651                          */
3652                         dev_dbg(hsotg->dev,
3653                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3654                         hsotg->flags.b.port_suspend_change = 0;
3655                         break;
3656
3657                 case USB_PORT_FEAT_C_PORT_L1:
3658                         dev_dbg(hsotg->dev,
3659                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3660                         hsotg->flags.b.port_l1_change = 0;
3661                         break;
3662
3663                 case USB_PORT_FEAT_C_OVER_CURRENT:
3664                         dev_dbg(hsotg->dev,
3665                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3666                         hsotg->flags.b.port_over_current_change = 0;
3667                         break;
3668
3669                 default:
3670                         retval = -EINVAL;
3671                         dev_err(hsotg->dev,
3672                                 "ClearPortFeature request %1xh unknown or unsupported\n",
3673                                 wvalue);
3674                 }
3675                 break;
3676
3677         case GetHubDescriptor:
3678                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3679                 hub_desc = (struct usb_hub_descriptor *)buf;
3680                 hub_desc->bDescLength = 9;
3681                 hub_desc->bDescriptorType = USB_DT_HUB;
3682                 hub_desc->bNbrPorts = 1;
3683                 hub_desc->wHubCharacteristics =
3684                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3685                                     HUB_CHAR_INDV_PORT_OCPM);
3686                 hub_desc->bPwrOn2PwrGood = 1;
3687                 hub_desc->bHubContrCurrent = 0;
3688                 hub_desc->u.hs.DeviceRemovable[0] = 0;
3689                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3690                 break;
3691
3692         case GetHubStatus:
3693                 dev_dbg(hsotg->dev, "GetHubStatus\n");
3694                 memset(buf, 0, 4);
3695                 break;
3696
3697         case GetPortStatus:
3698                 dev_vdbg(hsotg->dev,
3699                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3700                          hsotg->flags.d32);
3701                 if (!windex || windex > 1)
3702                         goto error;
3703
3704                 port_status = 0;
3705                 if (hsotg->flags.b.port_connect_status_change)
3706                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3707                 if (hsotg->flags.b.port_enable_change)
3708                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
3709                 if (hsotg->flags.b.port_suspend_change)
3710                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3711                 if (hsotg->flags.b.port_l1_change)
3712                         port_status |= USB_PORT_STAT_C_L1 << 16;
3713                 if (hsotg->flags.b.port_reset_change)
3714                         port_status |= USB_PORT_STAT_C_RESET << 16;
3715                 if (hsotg->flags.b.port_over_current_change) {
3716                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
3717                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3718                 }
3719
3720                 if (!hsotg->flags.b.port_connect_status) {
3721                         /*
3722                          * The port is disconnected, which means the core is
3723                          * either in device mode or it soon will be. Just
3724                          * return 0's for the remainder of the port status
3725                          * since the port register can't be read if the core
3726                          * is in device mode.
3727                          */
3728                         *(__le32 *)buf = cpu_to_le32(port_status);
3729                         break;
3730                 }
3731
3732                 hprt0 = dwc2_readl(hsotg, HPRT0);
3733                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
3734
3735                 if (hprt0 & HPRT0_CONNSTS)
3736                         port_status |= USB_PORT_STAT_CONNECTION;
3737                 if (hprt0 & HPRT0_ENA)
3738                         port_status |= USB_PORT_STAT_ENABLE;
3739                 if (hprt0 & HPRT0_SUSP)
3740                         port_status |= USB_PORT_STAT_SUSPEND;
3741                 if (hprt0 & HPRT0_OVRCURRACT)
3742                         port_status |= USB_PORT_STAT_OVERCURRENT;
3743                 if (hprt0 & HPRT0_RST)
3744                         port_status |= USB_PORT_STAT_RESET;
3745                 if (hprt0 & HPRT0_PWR)
3746                         port_status |= USB_PORT_STAT_POWER;
3747
3748                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3749                 if (speed == HPRT0_SPD_HIGH_SPEED)
3750                         port_status |= USB_PORT_STAT_HIGH_SPEED;
3751                 else if (speed == HPRT0_SPD_LOW_SPEED)
3752                         port_status |= USB_PORT_STAT_LOW_SPEED;
3753
3754                 if (hprt0 & HPRT0_TSTCTL_MASK)
3755                         port_status |= USB_PORT_STAT_TEST;
3756                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3757
3758                 if (hsotg->params.dma_desc_fs_enable) {
3759                         /*
3760                          * Enable descriptor DMA only if a full speed
3761                          * device is connected.
3762                          */
3763                         if (hsotg->new_connection &&
3764                             ((port_status &
3765                               (USB_PORT_STAT_CONNECTION |
3766                                USB_PORT_STAT_HIGH_SPEED |
3767                                USB_PORT_STAT_LOW_SPEED)) ==
3768                                USB_PORT_STAT_CONNECTION)) {
3769                                 u32 hcfg;
3770
3771                                 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3772                                 hsotg->params.dma_desc_enable = true;
3773                                 hcfg = dwc2_readl(hsotg, HCFG);
3774                                 hcfg |= HCFG_DESCDMA;
3775                                 dwc2_writel(hsotg, hcfg, HCFG);
3776                                 hsotg->new_connection = false;
3777                         }
3778                 }
3779
3780                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3781                 *(__le32 *)buf = cpu_to_le32(port_status);
3782                 break;
3783
3784         case SetHubFeature:
3785                 dev_dbg(hsotg->dev, "SetHubFeature\n");
3786                 /* No HUB features supported */
3787                 break;
3788
3789         case SetPortFeature:
3790                 dev_dbg(hsotg->dev, "SetPortFeature\n");
3791                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3792                         goto error;
3793
3794                 if (!hsotg->flags.b.port_connect_status) {
3795                         /*
3796                          * The port is disconnected, which means the core is
3797                          * either in device mode or it soon will be. Just
3798                          * return without doing anything since the port
3799                          * register can't be written if the core is in device
3800                          * mode.
3801                          */
3802                         break;
3803                 }
3804
3805                 switch (wvalue) {
3806                 case USB_PORT_FEAT_SUSPEND:
3807                         dev_dbg(hsotg->dev,
3808                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3809                         if (windex != hsotg->otg_port)
3810                                 goto error;
3811                         if (hsotg->params.power_down == 2)
3812                                 dwc2_enter_hibernation(hsotg, 1);
3813                         else
3814                                 dwc2_port_suspend(hsotg, windex);
3815                         break;
3816
3817                 case USB_PORT_FEAT_POWER:
3818                         dev_dbg(hsotg->dev,
3819                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3820                         hprt0 = dwc2_read_hprt0(hsotg);
3821                         pwr = hprt0 & HPRT0_PWR;
3822                         hprt0 |= HPRT0_PWR;
3823                         dwc2_writel(hsotg, hprt0, HPRT0);
3824                         if (!pwr)
3825                                 dwc2_vbus_supply_init(hsotg);
3826                         break;
3827
3828                 case USB_PORT_FEAT_RESET:
3829                         if (hsotg->params.power_down == 2 &&
3830                             hsotg->hibernated)
3831                                 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3832                         hprt0 = dwc2_read_hprt0(hsotg);
3833                         dev_dbg(hsotg->dev,
3834                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3835                         pcgctl = dwc2_readl(hsotg, PCGCTL);
3836                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3837                         dwc2_writel(hsotg, pcgctl, PCGCTL);
3838                         /* ??? Original driver does this */
3839                         dwc2_writel(hsotg, 0, PCGCTL);
3840
3841                         hprt0 = dwc2_read_hprt0(hsotg);
3842                         pwr = hprt0 & HPRT0_PWR;
3843                         /* Clear suspend bit if resetting from suspend state */
3844                         hprt0 &= ~HPRT0_SUSP;
3845
3846                         /*
3847                          * When B-Host the Port reset bit is set in the Start
3848                          * HCD Callback function, so that the reset is started
3849                          * within 1ms of the HNP success interrupt
3850                          */
3851                         if (!dwc2_hcd_is_b_host(hsotg)) {
3852                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
3853                                 dev_dbg(hsotg->dev,
3854                                         "In host mode, hprt0=%08x\n", hprt0);
3855                                 dwc2_writel(hsotg, hprt0, HPRT0);
3856                                 if (!pwr)
3857                                         dwc2_vbus_supply_init(hsotg);
3858                         }
3859
3860                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3861                         msleep(50);
3862                         hprt0 &= ~HPRT0_RST;
3863                         dwc2_writel(hsotg, hprt0, HPRT0);
3864                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
3865                         break;
3866
3867                 case USB_PORT_FEAT_INDICATOR:
3868                         dev_dbg(hsotg->dev,
3869                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3870                         /* Not supported */
3871                         break;
3872
3873                 case USB_PORT_FEAT_TEST:
3874                         hprt0 = dwc2_read_hprt0(hsotg);
3875                         dev_dbg(hsotg->dev,
3876                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3877                         hprt0 &= ~HPRT0_TSTCTL_MASK;
3878                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3879                         dwc2_writel(hsotg, hprt0, HPRT0);
3880                         break;
3881
3882                 default:
3883                         retval = -EINVAL;
3884                         dev_err(hsotg->dev,
3885                                 "SetPortFeature %1xh unknown or unsupported\n",
3886                                 wvalue);
3887                         break;
3888                 }
3889                 break;
3890
3891         default:
3892 error:
3893                 retval = -EINVAL;
3894                 dev_dbg(hsotg->dev,
3895                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3896                         typereq, windex, wvalue);
3897                 break;
3898         }
3899
3900         return retval;
3901 }
3902
3903 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3904 {
3905         int retval;
3906
3907         if (port != 1)
3908                 return -EINVAL;
3909
3910         retval = (hsotg->flags.b.port_connect_status_change ||
3911                   hsotg->flags.b.port_reset_change ||
3912                   hsotg->flags.b.port_enable_change ||
3913                   hsotg->flags.b.port_suspend_change ||
3914                   hsotg->flags.b.port_over_current_change);
3915
3916         if (retval) {
3917                 dev_dbg(hsotg->dev,
3918                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3919                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
3920                         hsotg->flags.b.port_connect_status_change);
3921                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
3922                         hsotg->flags.b.port_reset_change);
3923                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
3924                         hsotg->flags.b.port_enable_change);
3925                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
3926                         hsotg->flags.b.port_suspend_change);
3927                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
3928                         hsotg->flags.b.port_over_current_change);
3929         }
3930
3931         return retval;
3932 }
3933
3934 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3935 {
3936         u32 hfnum = dwc2_readl(hsotg, HFNUM);
3937
3938 #ifdef DWC2_DEBUG_SOF
3939         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3940                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3941 #endif
3942         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3943 }
3944
3945 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3946 {
3947         u32 hprt = dwc2_readl(hsotg, HPRT0);
3948         u32 hfir = dwc2_readl(hsotg, HFIR);
3949         u32 hfnum = dwc2_readl(hsotg, HFNUM);
3950         unsigned int us_per_frame;
3951         unsigned int frame_number;
3952         unsigned int remaining;
3953         unsigned int interval;
3954         unsigned int phy_clks;
3955
3956         /* High speed has 125 us per (micro) frame; others are 1 ms per */
3957         us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3958
3959         /* Extract fields */
3960         frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3961         remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3962         interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3963
3964         /*
3965          * Number of phy clocks since the last tick of the frame number after
3966          * "us" has passed.
3967          */
3968         phy_clks = (interval - remaining) +
3969                    DIV_ROUND_UP(interval * us, us_per_frame);
3970
3971         return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3972 }
3973
3974 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3975 {
3976         return hsotg->op_state == OTG_STATE_B_HOST;
3977 }
3978
3979 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3980                                                int iso_desc_count,
3981                                                gfp_t mem_flags)
3982 {
3983         struct dwc2_hcd_urb *urb;
3984         u32 size = sizeof(*urb) + iso_desc_count *
3985                    sizeof(struct dwc2_hcd_iso_packet_desc);
3986
3987         urb = kzalloc(size, mem_flags);
3988         if (urb)
3989                 urb->packet_count = iso_desc_count;
3990         return urb;
3991 }
3992
3993 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3994                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
3995                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3996 {
3997         if (dbg_perio() ||
3998             ep_type == USB_ENDPOINT_XFER_BULK ||
3999             ep_type == USB_ENDPOINT_XFER_CONTROL)
4000                 dev_vdbg(hsotg->dev,
4001                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
4002                          dev_addr, ep_num, ep_dir, ep_type, mps);
4003         urb->pipe_info.dev_addr = dev_addr;
4004         urb->pipe_info.ep_num = ep_num;
4005         urb->pipe_info.pipe_type = ep_type;
4006         urb->pipe_info.pipe_dir = ep_dir;
4007         urb->pipe_info.mps = mps;
4008 }
4009
4010 /*
4011  * NOTE: This function will be removed once the peripheral controller code
4012  * is integrated and the driver is stable
4013  */
4014 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
4015 {
4016 #ifdef DEBUG
4017         struct dwc2_host_chan *chan;
4018         struct dwc2_hcd_urb *urb;
4019         struct dwc2_qtd *qtd;
4020         int num_channels;
4021         u32 np_tx_status;
4022         u32 p_tx_status;
4023         int i;
4024
4025         num_channels = hsotg->params.host_channels;
4026         dev_dbg(hsotg->dev, "\n");
4027         dev_dbg(hsotg->dev,
4028                 "************************************************************\n");
4029         dev_dbg(hsotg->dev, "HCD State:\n");
4030         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
4031
4032         for (i = 0; i < num_channels; i++) {
4033                 chan = hsotg->hc_ptr_array[i];
4034                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
4035                 dev_dbg(hsotg->dev,
4036                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
4037                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
4038                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
4039                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
4040                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
4041                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
4042                         chan->data_pid_start);
4043                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
4044                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
4045                         chan->xfer_started);
4046                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
4047                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
4048                         (unsigned long)chan->xfer_dma);
4049                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
4050                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
4051                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
4052                         chan->halt_on_queue);
4053                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
4054                         chan->halt_pending);
4055                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
4056                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
4057                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
4058                         chan->complete_split);
4059                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
4060                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
4061                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
4062                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
4063                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
4064
4065                 if (chan->xfer_started) {
4066                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
4067
4068                         hfnum = dwc2_readl(hsotg, HFNUM);
4069                         hcchar = dwc2_readl(hsotg, HCCHAR(i));
4070                         hctsiz = dwc2_readl(hsotg, HCTSIZ(i));
4071                         hcint = dwc2_readl(hsotg, HCINT(i));
4072                         hcintmsk = dwc2_readl(hsotg, HCINTMSK(i));
4073                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
4074                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
4075                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
4076                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
4077                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
4078                 }
4079
4080                 if (!(chan->xfer_started && chan->qh))
4081                         continue;
4082
4083                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4084                         if (!qtd->in_process)
4085                                 break;
4086                         urb = qtd->urb;
4087                         dev_dbg(hsotg->dev, "    URB Info:\n");
4088                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
4089                                 qtd, urb);
4090                         if (urb) {
4091                                 dev_dbg(hsotg->dev,
4092                                         "      Dev: %d, EP: %d %s\n",
4093                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
4094                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
4095                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4096                                         "IN" : "OUT");
4097                                 dev_dbg(hsotg->dev,
4098                                         "      Max packet size: %d\n",
4099                                         dwc2_hcd_get_mps(&urb->pipe_info));
4100                                 dev_dbg(hsotg->dev,
4101                                         "      transfer_buffer: %p\n",
4102                                         urb->buf);
4103                                 dev_dbg(hsotg->dev,
4104                                         "      transfer_dma: %08lx\n",
4105                                         (unsigned long)urb->dma);
4106                                 dev_dbg(hsotg->dev,
4107                                         "      transfer_buffer_length: %d\n",
4108                                         urb->length);
4109                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
4110                                         urb->actual_length);
4111                         }
4112                 }
4113         }
4114
4115         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
4116                 hsotg->non_periodic_channels);
4117         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
4118                 hsotg->periodic_channels);
4119         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
4120         np_tx_status = dwc2_readl(hsotg, GNPTXSTS);
4121         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
4122                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4123         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
4124                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4125         p_tx_status = dwc2_readl(hsotg, HPTXSTS);
4126         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
4127                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4128         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
4129                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4130         dwc2_dump_global_registers(hsotg);
4131         dwc2_dump_host_registers(hsotg);
4132         dev_dbg(hsotg->dev,
4133                 "************************************************************\n");
4134         dev_dbg(hsotg->dev, "\n");
4135 #endif
4136 }
4137
4138 struct wrapper_priv_data {
4139         struct dwc2_hsotg *hsotg;
4140 };
4141
4142 /* Gets the dwc2_hsotg from a usb_hcd */
4143 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4144 {
4145         struct wrapper_priv_data *p;
4146
4147         p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4148         return p->hsotg;
4149 }
4150
4151 /**
4152  * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4153  *
4154  * This will get the dwc2_tt structure (and ttport) associated with the given
4155  * context (which is really just a struct urb pointer).
4156  *
4157  * The first time this is called for a given TT we allocate memory for our
4158  * structure.  When everyone is done and has called dwc2_host_put_tt_info()
4159  * then the refcount for the structure will go to 0 and we'll free it.
4160  *
4161  * @hsotg:     The HCD state structure for the DWC OTG controller.
4162  * @context:   The priv pointer from a struct dwc2_hcd_urb.
4163  * @mem_flags: Flags for allocating memory.
4164  * @ttport:    We'll return this device's port number here.  That's used to
4165  *             reference into the bitmap if we're on a multi_tt hub.
4166  *
4167  * Return: a pointer to a struct dwc2_tt.  Don't forget to call
4168  *         dwc2_host_put_tt_info()!  Returns NULL upon memory alloc failure.
4169  */
4170
4171 struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4172                                       gfp_t mem_flags, int *ttport)
4173 {
4174         struct urb *urb = context;
4175         struct dwc2_tt *dwc_tt = NULL;
4176
4177         if (urb->dev->tt) {
4178                 *ttport = urb->dev->ttport;
4179
4180                 dwc_tt = urb->dev->tt->hcpriv;
4181                 if (!dwc_tt) {
4182                         size_t bitmap_size;
4183
4184                         /*
4185                          * For single_tt we need one schedule.  For multi_tt
4186                          * we need one per port.
4187                          */
4188                         bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4189                                       sizeof(dwc_tt->periodic_bitmaps[0]);
4190                         if (urb->dev->tt->multi)
4191                                 bitmap_size *= urb->dev->tt->hub->maxchild;
4192
4193                         dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4194                                          mem_flags);
4195                         if (!dwc_tt)
4196                                 return NULL;
4197
4198                         dwc_tt->usb_tt = urb->dev->tt;
4199                         dwc_tt->usb_tt->hcpriv = dwc_tt;
4200                 }
4201
4202                 dwc_tt->refcount++;
4203         }
4204
4205         return dwc_tt;
4206 }
4207
4208 /**
4209  * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4210  *
4211  * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4212  * of the structure are done.
4213  *
4214  * It's OK to call this with NULL.
4215  *
4216  * @hsotg:     The HCD state structure for the DWC OTG controller.
4217  * @dwc_tt:    The pointer returned by dwc2_host_get_tt_info.
4218  */
4219 void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4220 {
4221         /* Model kfree and make put of NULL a no-op */
4222         if (!dwc_tt)
4223                 return;
4224
4225         WARN_ON(dwc_tt->refcount < 1);
4226
4227         dwc_tt->refcount--;
4228         if (!dwc_tt->refcount) {
4229                 dwc_tt->usb_tt->hcpriv = NULL;
4230                 kfree(dwc_tt);
4231         }
4232 }
4233
4234 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4235 {
4236         struct urb *urb = context;
4237
4238         return urb->dev->speed;
4239 }
4240
4241 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4242                                         struct urb *urb)
4243 {
4244         struct usb_bus *bus = hcd_to_bus(hcd);
4245
4246         if (urb->interval)
4247                 bus->bandwidth_allocated += bw / urb->interval;
4248         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4249                 bus->bandwidth_isoc_reqs++;
4250         else
4251                 bus->bandwidth_int_reqs++;
4252 }
4253
4254 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4255                                     struct urb *urb)
4256 {
4257         struct usb_bus *bus = hcd_to_bus(hcd);
4258
4259         if (urb->interval)
4260                 bus->bandwidth_allocated -= bw / urb->interval;
4261         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4262                 bus->bandwidth_isoc_reqs--;
4263         else
4264                 bus->bandwidth_int_reqs--;
4265 }
4266
4267 /*
4268  * Sets the final status of an URB and returns it to the upper layer. Any
4269  * required cleanup of the URB is performed.
4270  *
4271  * Must be called with interrupt disabled and spinlock held
4272  */
4273 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4274                         int status)
4275 {
4276         struct urb *urb;
4277         int i;
4278
4279         if (!qtd) {
4280                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4281                 return;
4282         }
4283
4284         if (!qtd->urb) {
4285                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4286                 return;
4287         }
4288
4289         urb = qtd->urb->priv;
4290         if (!urb) {
4291                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4292                 return;
4293         }
4294
4295         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4296
4297         if (dbg_urb(urb))
4298                 dev_vdbg(hsotg->dev,
4299                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4300                          __func__, urb, usb_pipedevice(urb->pipe),
4301                          usb_pipeendpoint(urb->pipe),
4302                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4303                          urb->actual_length);
4304
4305         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4306                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4307                 for (i = 0; i < urb->number_of_packets; ++i) {
4308                         urb->iso_frame_desc[i].actual_length =
4309                                 dwc2_hcd_urb_get_iso_desc_actual_length(
4310                                                 qtd->urb, i);
4311                         urb->iso_frame_desc[i].status =
4312                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4313                 }
4314         }
4315
4316         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4317                 for (i = 0; i < urb->number_of_packets; i++)
4318                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4319                                  i, urb->iso_frame_desc[i].status);
4320         }
4321
4322         urb->status = status;
4323         if (!status) {
4324                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4325                     urb->actual_length < urb->transfer_buffer_length)
4326                         urb->status = -EREMOTEIO;
4327         }
4328
4329         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4330             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4331                 struct usb_host_endpoint *ep = urb->ep;
4332
4333                 if (ep)
4334                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4335                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4336                                         urb);
4337         }
4338
4339         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4340         urb->hcpriv = NULL;
4341         kfree(qtd->urb);
4342         qtd->urb = NULL;
4343
4344         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4345 }
4346
4347 /*
4348  * Work queue function for starting the HCD when A-Cable is connected
4349  */
4350 static void dwc2_hcd_start_func(struct work_struct *work)
4351 {
4352         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4353                                                 start_work.work);
4354
4355         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4356         dwc2_host_start(hsotg);
4357 }
4358
4359 /*
4360  * Reset work queue function
4361  */
4362 static void dwc2_hcd_reset_func(struct work_struct *work)
4363 {
4364         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4365                                                 reset_work.work);
4366         unsigned long flags;
4367         u32 hprt0;
4368
4369         dev_dbg(hsotg->dev, "USB RESET function called\n");
4370
4371         spin_lock_irqsave(&hsotg->lock, flags);
4372
4373         hprt0 = dwc2_read_hprt0(hsotg);
4374         hprt0 &= ~HPRT0_RST;
4375         dwc2_writel(hsotg, hprt0, HPRT0);
4376         hsotg->flags.b.port_reset_change = 1;
4377
4378         spin_unlock_irqrestore(&hsotg->lock, flags);
4379 }
4380
4381 /*
4382  * =========================================================================
4383  *  Linux HC Driver Functions
4384  * =========================================================================
4385  */
4386
4387 /*
4388  * Initializes the DWC_otg controller and its root hub and prepares it for host
4389  * mode operation. Activates the root port. Returns 0 on success and a negative
4390  * error code on failure.
4391  */
4392 static int _dwc2_hcd_start(struct usb_hcd *hcd)
4393 {
4394         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4395         struct usb_bus *bus = hcd_to_bus(hcd);
4396         unsigned long flags;
4397         u32 hprt0;
4398         int ret;
4399
4400         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4401
4402         spin_lock_irqsave(&hsotg->lock, flags);
4403         hsotg->lx_state = DWC2_L0;
4404         hcd->state = HC_STATE_RUNNING;
4405         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4406
4407         if (dwc2_is_device_mode(hsotg)) {
4408                 spin_unlock_irqrestore(&hsotg->lock, flags);
4409                 return 0;       /* why 0 ?? */
4410         }
4411
4412         dwc2_hcd_reinit(hsotg);
4413
4414         hprt0 = dwc2_read_hprt0(hsotg);
4415         /* Has vbus power been turned on in dwc2_core_host_init ? */
4416         if (hprt0 & HPRT0_PWR) {
4417                 /* Enable external vbus supply before resuming root hub */
4418                 spin_unlock_irqrestore(&hsotg->lock, flags);
4419                 ret = dwc2_vbus_supply_init(hsotg);
4420                 if (ret)
4421                         return ret;
4422                 spin_lock_irqsave(&hsotg->lock, flags);
4423         }
4424
4425         /* Initialize and connect root hub if one is not already attached */
4426         if (bus->root_hub) {
4427                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4428                 /* Inform the HUB driver to resume */
4429                 usb_hcd_resume_root_hub(hcd);
4430         }
4431
4432         spin_unlock_irqrestore(&hsotg->lock, flags);
4433
4434         return 0;
4435 }
4436
4437 /*
4438  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4439  * stopped.
4440  */
4441 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4442 {
4443         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4444         unsigned long flags;
4445         u32 hprt0;
4446
4447         /* Turn off all host-specific interrupts */
4448         dwc2_disable_host_interrupts(hsotg);
4449
4450         /* Wait for interrupt processing to finish */
4451         synchronize_irq(hcd->irq);
4452
4453         spin_lock_irqsave(&hsotg->lock, flags);
4454         hprt0 = dwc2_read_hprt0(hsotg);
4455         /* Ensure hcd is disconnected */
4456         dwc2_hcd_disconnect(hsotg, true);
4457         dwc2_hcd_stop(hsotg);
4458         hsotg->lx_state = DWC2_L3;
4459         hcd->state = HC_STATE_HALT;
4460         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4461         spin_unlock_irqrestore(&hsotg->lock, flags);
4462
4463         /* keep balanced supply init/exit by checking HPRT0_PWR */
4464         if (hprt0 & HPRT0_PWR)
4465                 dwc2_vbus_supply_exit(hsotg);
4466
4467         usleep_range(1000, 3000);
4468 }
4469
4470 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4471 {
4472         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4473         unsigned long flags;
4474         int ret = 0;
4475         u32 hprt0;
4476
4477         spin_lock_irqsave(&hsotg->lock, flags);
4478
4479         if (dwc2_is_device_mode(hsotg))
4480                 goto unlock;
4481
4482         if (hsotg->lx_state != DWC2_L0)
4483                 goto unlock;
4484
4485         if (!HCD_HW_ACCESSIBLE(hcd))
4486                 goto unlock;
4487
4488         if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4489                 goto unlock;
4490
4491         if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
4492                 goto skip_power_saving;
4493
4494         /*
4495          * Drive USB suspend and disable port Power
4496          * if usb bus is not suspended.
4497          */
4498         if (!hsotg->bus_suspended) {
4499                 hprt0 = dwc2_read_hprt0(hsotg);
4500                 hprt0 |= HPRT0_SUSP;
4501                 hprt0 &= ~HPRT0_PWR;
4502                 dwc2_writel(hsotg, hprt0, HPRT0);
4503                 spin_unlock_irqrestore(&hsotg->lock, flags);
4504                 dwc2_vbus_supply_exit(hsotg);
4505                 spin_lock_irqsave(&hsotg->lock, flags);
4506         }
4507
4508         /* Enter partial_power_down */
4509         ret = dwc2_enter_partial_power_down(hsotg);
4510         if (ret) {
4511                 if (ret != -ENOTSUPP)
4512                         dev_err(hsotg->dev,
4513                                 "enter partial_power_down failed\n");
4514                 goto skip_power_saving;
4515         }
4516
4517         /* Ask phy to be suspended */
4518         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4519                 spin_unlock_irqrestore(&hsotg->lock, flags);
4520                 usb_phy_set_suspend(hsotg->uphy, true);
4521                 spin_lock_irqsave(&hsotg->lock, flags);
4522         }
4523
4524         /* After entering partial_power_down, hardware is no more accessible */
4525         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4526
4527 skip_power_saving:
4528         hsotg->lx_state = DWC2_L2;
4529 unlock:
4530         spin_unlock_irqrestore(&hsotg->lock, flags);
4531
4532         return ret;
4533 }
4534
4535 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4536 {
4537         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4538         unsigned long flags;
4539         int ret = 0;
4540
4541         spin_lock_irqsave(&hsotg->lock, flags);
4542
4543         if (dwc2_is_device_mode(hsotg))
4544                 goto unlock;
4545
4546         if (hsotg->lx_state != DWC2_L2)
4547                 goto unlock;
4548
4549         if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
4550                 hsotg->lx_state = DWC2_L0;
4551                 goto unlock;
4552         }
4553
4554         /*
4555          * Set HW accessible bit before powering on the controller
4556          * since an interrupt may rise.
4557          */
4558         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4559
4560         /*
4561          * Enable power if not already done.
4562          * This must not be spinlocked since duration
4563          * of this call is unknown.
4564          */
4565         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4566                 spin_unlock_irqrestore(&hsotg->lock, flags);
4567                 usb_phy_set_suspend(hsotg->uphy, false);
4568                 spin_lock_irqsave(&hsotg->lock, flags);
4569         }
4570
4571         /* Exit partial_power_down */
4572         ret = dwc2_exit_partial_power_down(hsotg, true);
4573         if (ret && (ret != -ENOTSUPP))
4574                 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4575
4576         hsotg->lx_state = DWC2_L0;
4577
4578         spin_unlock_irqrestore(&hsotg->lock, flags);
4579
4580         if (hsotg->bus_suspended) {
4581                 spin_lock_irqsave(&hsotg->lock, flags);
4582                 hsotg->flags.b.port_suspend_change = 1;
4583                 spin_unlock_irqrestore(&hsotg->lock, flags);
4584                 dwc2_port_resume(hsotg);
4585         } else {
4586                 dwc2_vbus_supply_init(hsotg);
4587
4588                 /* Wait for controller to correctly update D+/D- level */
4589                 usleep_range(3000, 5000);
4590
4591                 /*
4592                  * Clear Port Enable and Port Status changes.
4593                  * Enable Port Power.
4594                  */
4595                 dwc2_writel(hsotg, HPRT0_PWR | HPRT0_CONNDET |
4596                                 HPRT0_ENACHG, HPRT0);
4597                 /* Wait for controller to detect Port Connect */
4598                 usleep_range(5000, 7000);
4599         }
4600
4601         return ret;
4602 unlock:
4603         spin_unlock_irqrestore(&hsotg->lock, flags);
4604
4605         return ret;
4606 }
4607
4608 /* Returns the current frame number */
4609 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4610 {
4611         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4612
4613         return dwc2_hcd_get_frame_number(hsotg);
4614 }
4615
4616 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4617                                char *fn_name)
4618 {
4619 #ifdef VERBOSE_DEBUG
4620         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4621         char *pipetype = NULL;
4622         char *speed = NULL;
4623
4624         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4625         dev_vdbg(hsotg->dev, "  Device address: %d\n",
4626                  usb_pipedevice(urb->pipe));
4627         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
4628                  usb_pipeendpoint(urb->pipe),
4629                  usb_pipein(urb->pipe) ? "IN" : "OUT");
4630
4631         switch (usb_pipetype(urb->pipe)) {
4632         case PIPE_CONTROL:
4633                 pipetype = "CONTROL";
4634                 break;
4635         case PIPE_BULK:
4636                 pipetype = "BULK";
4637                 break;
4638         case PIPE_INTERRUPT:
4639                 pipetype = "INTERRUPT";
4640                 break;
4641         case PIPE_ISOCHRONOUS:
4642                 pipetype = "ISOCHRONOUS";
4643                 break;
4644         }
4645
4646         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
4647                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4648                  "IN" : "OUT");
4649
4650         switch (urb->dev->speed) {
4651         case USB_SPEED_HIGH:
4652                 speed = "HIGH";
4653                 break;
4654         case USB_SPEED_FULL:
4655                 speed = "FULL";
4656                 break;
4657         case USB_SPEED_LOW:
4658                 speed = "LOW";
4659                 break;
4660         default:
4661                 speed = "UNKNOWN";
4662                 break;
4663         }
4664
4665         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
4666         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
4667                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4668         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
4669                  urb->transfer_buffer_length);
4670         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
4671                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4672         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
4673                  urb->setup_packet, (unsigned long)urb->setup_dma);
4674         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
4675
4676         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4677                 int i;
4678
4679                 for (i = 0; i < urb->number_of_packets; i++) {
4680                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
4681                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
4682                                  urb->iso_frame_desc[i].offset,
4683                                  urb->iso_frame_desc[i].length);
4684                 }
4685         }
4686 #endif
4687 }
4688
4689 /*
4690  * Starts processing a USB transfer request specified by a USB Request Block
4691  * (URB). mem_flags indicates the type of memory allocation to use while
4692  * processing this URB.
4693  */
4694 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4695                                  gfp_t mem_flags)
4696 {
4697         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4698         struct usb_host_endpoint *ep = urb->ep;
4699         struct dwc2_hcd_urb *dwc2_urb;
4700         int i;
4701         int retval;
4702         int alloc_bandwidth = 0;
4703         u8 ep_type = 0;
4704         u32 tflags = 0;
4705         void *buf;
4706         unsigned long flags;
4707         struct dwc2_qh *qh;
4708         bool qh_allocated = false;
4709         struct dwc2_qtd *qtd;
4710
4711         if (dbg_urb(urb)) {
4712                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4713                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4714         }
4715
4716         if (!ep)
4717                 return -EINVAL;
4718
4719         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4720             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4721                 spin_lock_irqsave(&hsotg->lock, flags);
4722                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4723                         alloc_bandwidth = 1;
4724                 spin_unlock_irqrestore(&hsotg->lock, flags);
4725         }
4726
4727         switch (usb_pipetype(urb->pipe)) {
4728         case PIPE_CONTROL:
4729                 ep_type = USB_ENDPOINT_XFER_CONTROL;
4730                 break;
4731         case PIPE_ISOCHRONOUS:
4732                 ep_type = USB_ENDPOINT_XFER_ISOC;
4733                 break;
4734         case PIPE_BULK:
4735                 ep_type = USB_ENDPOINT_XFER_BULK;
4736                 break;
4737         case PIPE_INTERRUPT:
4738                 ep_type = USB_ENDPOINT_XFER_INT;
4739                 break;
4740         }
4741
4742         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4743                                       mem_flags);
4744         if (!dwc2_urb)
4745                 return -ENOMEM;
4746
4747         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4748                                   usb_pipeendpoint(urb->pipe), ep_type,
4749                                   usb_pipein(urb->pipe),
4750                                   usb_maxpacket(urb->dev, urb->pipe,
4751                                                 !(usb_pipein(urb->pipe))));
4752
4753         buf = urb->transfer_buffer;
4754
4755         if (hcd->self.uses_dma) {
4756                 if (!buf && (urb->transfer_dma & 3)) {
4757                         dev_err(hsotg->dev,
4758                                 "%s: unaligned transfer with no transfer_buffer",
4759                                 __func__);
4760                         retval = -EINVAL;
4761                         goto fail0;
4762                 }
4763         }
4764
4765         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4766                 tflags |= URB_GIVEBACK_ASAP;
4767         if (urb->transfer_flags & URB_ZERO_PACKET)
4768                 tflags |= URB_SEND_ZERO_PACKET;
4769
4770         dwc2_urb->priv = urb;
4771         dwc2_urb->buf = buf;
4772         dwc2_urb->dma = urb->transfer_dma;
4773         dwc2_urb->length = urb->transfer_buffer_length;
4774         dwc2_urb->setup_packet = urb->setup_packet;
4775         dwc2_urb->setup_dma = urb->setup_dma;
4776         dwc2_urb->flags = tflags;
4777         dwc2_urb->interval = urb->interval;
4778         dwc2_urb->status = -EINPROGRESS;
4779
4780         for (i = 0; i < urb->number_of_packets; ++i)
4781                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4782                                                  urb->iso_frame_desc[i].offset,
4783                                                  urb->iso_frame_desc[i].length);
4784
4785         urb->hcpriv = dwc2_urb;
4786         qh = (struct dwc2_qh *)ep->hcpriv;
4787         /* Create QH for the endpoint if it doesn't exist */
4788         if (!qh) {
4789                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4790                 if (!qh) {
4791                         retval = -ENOMEM;
4792                         goto fail0;
4793                 }
4794                 ep->hcpriv = qh;
4795                 qh_allocated = true;
4796         }
4797
4798         qtd = kzalloc(sizeof(*qtd), mem_flags);
4799         if (!qtd) {
4800                 retval = -ENOMEM;
4801                 goto fail1;
4802         }
4803
4804         spin_lock_irqsave(&hsotg->lock, flags);
4805         retval = usb_hcd_link_urb_to_ep(hcd, urb);
4806         if (retval)
4807                 goto fail2;
4808
4809         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4810         if (retval)
4811                 goto fail3;
4812
4813         if (alloc_bandwidth) {
4814                 dwc2_allocate_bus_bandwidth(hcd,
4815                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4816                                 urb);
4817         }
4818
4819         spin_unlock_irqrestore(&hsotg->lock, flags);
4820
4821         return 0;
4822
4823 fail3:
4824         dwc2_urb->priv = NULL;
4825         usb_hcd_unlink_urb_from_ep(hcd, urb);
4826         if (qh_allocated && qh->channel && qh->channel->qh == qh)
4827                 qh->channel->qh = NULL;
4828 fail2:
4829         spin_unlock_irqrestore(&hsotg->lock, flags);
4830         urb->hcpriv = NULL;
4831         kfree(qtd);
4832         qtd = NULL;
4833 fail1:
4834         if (qh_allocated) {
4835                 struct dwc2_qtd *qtd2, *qtd2_tmp;
4836
4837                 ep->hcpriv = NULL;
4838                 dwc2_hcd_qh_unlink(hsotg, qh);
4839                 /* Free each QTD in the QH's QTD list */
4840                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4841                                          qtd_list_entry)
4842                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4843                 dwc2_hcd_qh_free(hsotg, qh);
4844         }
4845 fail0:
4846         kfree(dwc2_urb);
4847
4848         return retval;
4849 }
4850
4851 /*
4852  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4853  */
4854 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4855                                  int status)
4856 {
4857         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4858         int rc;
4859         unsigned long flags;
4860
4861         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4862         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4863
4864         spin_lock_irqsave(&hsotg->lock, flags);
4865
4866         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4867         if (rc)
4868                 goto out;
4869
4870         if (!urb->hcpriv) {
4871                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4872                 goto out;
4873         }
4874
4875         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4876
4877         usb_hcd_unlink_urb_from_ep(hcd, urb);
4878
4879         kfree(urb->hcpriv);
4880         urb->hcpriv = NULL;
4881
4882         /* Higher layer software sets URB status */
4883         spin_unlock(&hsotg->lock);
4884         usb_hcd_giveback_urb(hcd, urb, status);
4885         spin_lock(&hsotg->lock);
4886
4887         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4888         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
4889 out:
4890         spin_unlock_irqrestore(&hsotg->lock, flags);
4891
4892         return rc;
4893 }
4894
4895 /*
4896  * Frees resources in the DWC_otg controller related to a given endpoint. Also
4897  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4898  * must already be dequeued.
4899  */
4900 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4901                                        struct usb_host_endpoint *ep)
4902 {
4903         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4904
4905         dev_dbg(hsotg->dev,
4906                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4907                 ep->desc.bEndpointAddress, ep->hcpriv);
4908         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4909 }
4910
4911 /*
4912  * Resets endpoint specific parameter values, in current version used to reset
4913  * the data toggle (as a WA). This function can be called from usb_clear_halt
4914  * routine.
4915  */
4916 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4917                                      struct usb_host_endpoint *ep)
4918 {
4919         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4920         unsigned long flags;
4921
4922         dev_dbg(hsotg->dev,
4923                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4924                 ep->desc.bEndpointAddress);
4925
4926         spin_lock_irqsave(&hsotg->lock, flags);
4927         dwc2_hcd_endpoint_reset(hsotg, ep);
4928         spin_unlock_irqrestore(&hsotg->lock, flags);
4929 }
4930
4931 /*
4932  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4933  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4934  * interrupt.
4935  *
4936  * This function is called by the USB core when an interrupt occurs
4937  */
4938 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4939 {
4940         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4941
4942         return dwc2_handle_hcd_intr(hsotg);
4943 }
4944
4945 /*
4946  * Creates Status Change bitmap for the root hub and root port. The bitmap is
4947  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4948  * is the status change indicator for the single root port. Returns 1 if either
4949  * change indicator is 1, otherwise returns 0.
4950  */
4951 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4952 {
4953         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4954
4955         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4956         return buf[0] != 0;
4957 }
4958
4959 /* Handles hub class-specific requests */
4960 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4961                                  u16 windex, char *buf, u16 wlength)
4962 {
4963         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4964                                           wvalue, windex, buf, wlength);
4965         return retval;
4966 }
4967
4968 /* Handles hub TT buffer clear completions */
4969 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4970                                                struct usb_host_endpoint *ep)
4971 {
4972         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4973         struct dwc2_qh *qh;
4974         unsigned long flags;
4975
4976         qh = ep->hcpriv;
4977         if (!qh)
4978                 return;
4979
4980         spin_lock_irqsave(&hsotg->lock, flags);
4981         qh->tt_buffer_dirty = 0;
4982
4983         if (hsotg->flags.b.port_connect_status)
4984                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4985
4986         spin_unlock_irqrestore(&hsotg->lock, flags);
4987 }
4988
4989 /*
4990  * HPRT0_SPD_HIGH_SPEED: high speed
4991  * HPRT0_SPD_FULL_SPEED: full speed
4992  */
4993 static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4994 {
4995         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4996
4997         if (hsotg->params.speed == speed)
4998                 return;
4999
5000         hsotg->params.speed = speed;
5001         queue_work(hsotg->wq_otg, &hsotg->wf_otg);
5002 }
5003
5004 static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
5005 {
5006         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5007
5008         if (!hsotg->params.change_speed_quirk)
5009                 return;
5010
5011         /*
5012          * On removal, set speed to default high-speed.
5013          */
5014         if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
5015             udev->parent->speed < USB_SPEED_HIGH) {
5016                 dev_info(hsotg->dev, "Set speed to default high-speed\n");
5017                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5018         }
5019 }
5020
5021 static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
5022 {
5023         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
5024
5025         if (!hsotg->params.change_speed_quirk)
5026                 return 0;
5027
5028         if (udev->speed == USB_SPEED_HIGH) {
5029                 dev_info(hsotg->dev, "Set speed to high-speed\n");
5030                 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
5031         } else if ((udev->speed == USB_SPEED_FULL ||
5032                                 udev->speed == USB_SPEED_LOW)) {
5033                 /*
5034                  * Change speed setting to full-speed if there's
5035                  * a full-speed or low-speed device plugged in.
5036                  */
5037                 dev_info(hsotg->dev, "Set speed to full-speed\n");
5038                 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
5039         }
5040
5041         return 0;
5042 }
5043
5044 static struct hc_driver dwc2_hc_driver = {
5045         .description = "dwc2_hsotg",
5046         .product_desc = "DWC OTG Controller",
5047         .hcd_priv_size = sizeof(struct wrapper_priv_data),
5048
5049         .irq = _dwc2_hcd_irq,
5050         .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
5051
5052         .start = _dwc2_hcd_start,
5053         .stop = _dwc2_hcd_stop,
5054         .urb_enqueue = _dwc2_hcd_urb_enqueue,
5055         .urb_dequeue = _dwc2_hcd_urb_dequeue,
5056         .endpoint_disable = _dwc2_hcd_endpoint_disable,
5057         .endpoint_reset = _dwc2_hcd_endpoint_reset,
5058         .get_frame_number = _dwc2_hcd_get_frame_number,
5059
5060         .hub_status_data = _dwc2_hcd_hub_status_data,
5061         .hub_control = _dwc2_hcd_hub_control,
5062         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
5063
5064         .bus_suspend = _dwc2_hcd_suspend,
5065         .bus_resume = _dwc2_hcd_resume,
5066
5067         .map_urb_for_dma        = dwc2_map_urb_for_dma,
5068         .unmap_urb_for_dma      = dwc2_unmap_urb_for_dma,
5069 };
5070
5071 /*
5072  * Frees secondary storage associated with the dwc2_hsotg structure contained
5073  * in the struct usb_hcd field
5074  */
5075 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
5076 {
5077         u32 ahbcfg;
5078         u32 dctl;
5079         int i;
5080
5081         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
5082
5083         /* Free memory for QH/QTD lists */
5084         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
5085         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
5086         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
5087         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
5088         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
5089         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5090         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5091
5092         /* Free memory for the host channels */
5093         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5094                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5095
5096                 if (chan) {
5097                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5098                                 i, chan);
5099                         hsotg->hc_ptr_array[i] = NULL;
5100                         kfree(chan);
5101                 }
5102         }
5103
5104         if (hsotg->params.host_dma) {
5105                 if (hsotg->status_buf) {
5106                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5107                                           hsotg->status_buf,
5108                                           hsotg->status_buf_dma);
5109                         hsotg->status_buf = NULL;
5110                 }
5111         } else {
5112                 kfree(hsotg->status_buf);
5113                 hsotg->status_buf = NULL;
5114         }
5115
5116         ahbcfg = dwc2_readl(hsotg, GAHBCFG);
5117
5118         /* Disable all interrupts */
5119         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5120         dwc2_writel(hsotg, ahbcfg, GAHBCFG);
5121         dwc2_writel(hsotg, 0, GINTMSK);
5122
5123         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5124                 dctl = dwc2_readl(hsotg, DCTL);
5125                 dctl |= DCTL_SFTDISCON;
5126                 dwc2_writel(hsotg, dctl, DCTL);
5127         }
5128
5129         if (hsotg->wq_otg) {
5130                 if (!cancel_work_sync(&hsotg->wf_otg))
5131                         flush_workqueue(hsotg->wq_otg);
5132                 destroy_workqueue(hsotg->wq_otg);
5133         }
5134
5135         del_timer(&hsotg->wkp_timer);
5136 }
5137
5138 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5139 {
5140         /* Turn off all host-specific interrupts */
5141         dwc2_disable_host_interrupts(hsotg);
5142
5143         dwc2_hcd_free(hsotg);
5144 }
5145
5146 /*
5147  * Initializes the HCD. This function allocates memory for and initializes the
5148  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5149  * USB bus with the core and calls the hc_driver->start() function. It returns
5150  * a negative error on failure.
5151  */
5152 int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5153 {
5154         struct platform_device *pdev = to_platform_device(hsotg->dev);
5155         struct resource *res;
5156         struct usb_hcd *hcd;
5157         struct dwc2_host_chan *channel;
5158         u32 hcfg;
5159         int i, num_channels;
5160         int retval;
5161
5162         if (usb_disabled())
5163                 return -ENODEV;
5164
5165         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5166
5167         retval = -ENOMEM;
5168
5169         hcfg = dwc2_readl(hsotg, HCFG);
5170         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5171
5172 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5173         hsotg->frame_num_array = kcalloc(FRAME_NUM_ARRAY_SIZE,
5174                                          sizeof(*hsotg->frame_num_array),
5175                                          GFP_KERNEL);
5176         if (!hsotg->frame_num_array)
5177                 goto error1;
5178         hsotg->last_frame_num_array =
5179                 kcalloc(FRAME_NUM_ARRAY_SIZE,
5180                         sizeof(*hsotg->last_frame_num_array), GFP_KERNEL);
5181         if (!hsotg->last_frame_num_array)
5182                 goto error1;
5183 #endif
5184         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5185
5186         /* Check if the bus driver or platform code has setup a dma_mask */
5187         if (hsotg->params.host_dma &&
5188             !hsotg->dev->dma_mask) {
5189                 dev_warn(hsotg->dev,
5190                          "dma_mask not set, disabling DMA\n");
5191                 hsotg->params.host_dma = false;
5192                 hsotg->params.dma_desc_enable = false;
5193         }
5194
5195         /* Set device flags indicating whether the HCD supports DMA */
5196         if (hsotg->params.host_dma) {
5197                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5198                         dev_warn(hsotg->dev, "can't set DMA mask\n");
5199                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5200                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5201         }
5202
5203         if (hsotg->params.change_speed_quirk) {
5204                 dwc2_hc_driver.free_dev = dwc2_free_dev;
5205                 dwc2_hc_driver.reset_device = dwc2_reset_device;
5206         }
5207
5208         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5209         if (!hcd)
5210                 goto error1;
5211
5212         if (!hsotg->params.host_dma)
5213                 hcd->self.uses_dma = 0;
5214
5215         hcd->has_tt = 1;
5216
5217         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5218         hcd->rsrc_start = res->start;
5219         hcd->rsrc_len = resource_size(res);
5220
5221         ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5222         hsotg->priv = hcd;
5223
5224         /*
5225          * Disable the global interrupt until all the interrupt handlers are
5226          * installed
5227          */
5228         dwc2_disable_global_interrupts(hsotg);
5229
5230         /* Initialize the DWC_otg core, and select the Phy type */
5231         retval = dwc2_core_init(hsotg, true);
5232         if (retval)
5233                 goto error2;
5234
5235         /* Create new workqueue and init work */
5236         retval = -ENOMEM;
5237         hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5238         if (!hsotg->wq_otg) {
5239                 dev_err(hsotg->dev, "Failed to create workqueue\n");
5240                 goto error2;
5241         }
5242         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5243
5244         timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5245
5246         /* Initialize the non-periodic schedule */
5247         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5248         INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5249         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5250
5251         /* Initialize the periodic schedule */
5252         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5253         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5254         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5255         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5256
5257         INIT_LIST_HEAD(&hsotg->split_order);
5258
5259         /*
5260          * Create a host channel descriptor for each host channel implemented
5261          * in the controller. Initialize the channel descriptor array.
5262          */
5263         INIT_LIST_HEAD(&hsotg->free_hc_list);
5264         num_channels = hsotg->params.host_channels;
5265         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5266
5267         for (i = 0; i < num_channels; i++) {
5268                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5269                 if (!channel)
5270                         goto error3;
5271                 channel->hc_num = i;
5272                 INIT_LIST_HEAD(&channel->split_order_list_entry);
5273                 hsotg->hc_ptr_array[i] = channel;
5274         }
5275
5276         /* Initialize hsotg start work */
5277         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5278
5279         /* Initialize port reset work */
5280         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5281
5282         /*
5283          * Allocate space for storing data on status transactions. Normally no
5284          * data is sent, but this space acts as a bit bucket. This must be
5285          * done after usb_add_hcd since that function allocates the DMA buffer
5286          * pool.
5287          */
5288         if (hsotg->params.host_dma)
5289                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5290                                         DWC2_HCD_STATUS_BUF_SIZE,
5291                                         &hsotg->status_buf_dma, GFP_KERNEL);
5292         else
5293                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5294                                           GFP_KERNEL);
5295
5296         if (!hsotg->status_buf)
5297                 goto error3;
5298
5299         /*
5300          * Create kmem caches to handle descriptor buffers in descriptor
5301          * DMA mode.
5302          * Alignment must be set to 512 bytes.
5303          */
5304         if (hsotg->params.dma_desc_enable ||
5305             hsotg->params.dma_desc_fs_enable) {
5306                 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5307                                 sizeof(struct dwc2_dma_desc) *
5308                                 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5309                                 NULL);
5310                 if (!hsotg->desc_gen_cache) {
5311                         dev_err(hsotg->dev,
5312                                 "unable to create dwc2 generic desc cache\n");
5313
5314                         /*
5315                          * Disable descriptor dma mode since it will not be
5316                          * usable.
5317                          */
5318                         hsotg->params.dma_desc_enable = false;
5319                         hsotg->params.dma_desc_fs_enable = false;
5320                 }
5321
5322                 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5323                                 sizeof(struct dwc2_dma_desc) *
5324                                 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5325                 if (!hsotg->desc_hsisoc_cache) {
5326                         dev_err(hsotg->dev,
5327                                 "unable to create dwc2 hs isoc desc cache\n");
5328
5329                         kmem_cache_destroy(hsotg->desc_gen_cache);
5330
5331                         /*
5332                          * Disable descriptor dma mode since it will not be
5333                          * usable.
5334                          */
5335                         hsotg->params.dma_desc_enable = false;
5336                         hsotg->params.dma_desc_fs_enable = false;
5337                 }
5338         }
5339
5340         if (hsotg->params.host_dma) {
5341                 /*
5342                  * Create kmem caches to handle non-aligned buffer
5343                  * in Buffer DMA mode.
5344                  */
5345                 hsotg->unaligned_cache = kmem_cache_create("dwc2-unaligned-dma",
5346                                                 DWC2_KMEM_UNALIGNED_BUF_SIZE, 4,
5347                                                 SLAB_CACHE_DMA, NULL);
5348                 if (!hsotg->unaligned_cache)
5349                         dev_err(hsotg->dev,
5350                                 "unable to create dwc2 unaligned cache\n");
5351         }
5352
5353         hsotg->otg_port = 1;
5354         hsotg->frame_list = NULL;
5355         hsotg->frame_list_dma = 0;
5356         hsotg->periodic_qh_count = 0;
5357
5358         /* Initiate lx_state to L3 disconnected state */
5359         hsotg->lx_state = DWC2_L3;
5360
5361         hcd->self.otg_port = hsotg->otg_port;
5362
5363         /* Don't support SG list at this point */
5364         hcd->self.sg_tablesize = 0;
5365
5366         if (!IS_ERR_OR_NULL(hsotg->uphy))
5367                 otg_set_host(hsotg->uphy->otg, &hcd->self);
5368
5369         /*
5370          * Finish generic HCD initialization and start the HCD. This function
5371          * allocates the DMA buffer pool, registers the USB bus, requests the
5372          * IRQ line, and calls hcd_start method.
5373          */
5374         retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5375         if (retval < 0)
5376                 goto error4;
5377
5378         device_wakeup_enable(hcd->self.controller);
5379
5380         dwc2_hcd_dump_state(hsotg);
5381
5382         dwc2_enable_global_interrupts(hsotg);
5383
5384         return 0;
5385
5386 error4:
5387         kmem_cache_destroy(hsotg->unaligned_cache);
5388         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5389         kmem_cache_destroy(hsotg->desc_gen_cache);
5390 error3:
5391         dwc2_hcd_release(hsotg);
5392 error2:
5393         usb_put_hcd(hcd);
5394 error1:
5395
5396 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5397         kfree(hsotg->last_frame_num_array);
5398         kfree(hsotg->frame_num_array);
5399 #endif
5400
5401         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5402         return retval;
5403 }
5404
5405 /*
5406  * Removes the HCD.
5407  * Frees memory and resources associated with the HCD and deregisters the bus.
5408  */
5409 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5410 {
5411         struct usb_hcd *hcd;
5412
5413         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5414
5415         hcd = dwc2_hsotg_to_hcd(hsotg);
5416         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5417
5418         if (!hcd) {
5419                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5420                         __func__);
5421                 return;
5422         }
5423
5424         if (!IS_ERR_OR_NULL(hsotg->uphy))
5425                 otg_set_host(hsotg->uphy->otg, NULL);
5426
5427         usb_remove_hcd(hcd);
5428         hsotg->priv = NULL;
5429
5430         kmem_cache_destroy(hsotg->unaligned_cache);
5431         kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5432         kmem_cache_destroy(hsotg->desc_gen_cache);
5433
5434         dwc2_hcd_release(hsotg);
5435         usb_put_hcd(hcd);
5436
5437 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5438         kfree(hsotg->last_frame_num_array);
5439         kfree(hsotg->frame_num_array);
5440 #endif
5441 }
5442
5443 /**
5444  * dwc2_backup_host_registers() - Backup controller host registers.
5445  * When suspending usb bus, registers needs to be backuped
5446  * if controller power is disabled once suspended.
5447  *
5448  * @hsotg: Programming view of the DWC_otg controller
5449  */
5450 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5451 {
5452         struct dwc2_hregs_backup *hr;
5453         int i;
5454
5455         dev_dbg(hsotg->dev, "%s\n", __func__);
5456
5457         /* Backup Host regs */
5458         hr = &hsotg->hr_backup;
5459         hr->hcfg = dwc2_readl(hsotg, HCFG);
5460         hr->haintmsk = dwc2_readl(hsotg, HAINTMSK);
5461         for (i = 0; i < hsotg->params.host_channels; ++i)
5462                 hr->hcintmsk[i] = dwc2_readl(hsotg, HCINTMSK(i));
5463
5464         hr->hprt0 = dwc2_read_hprt0(hsotg);
5465         hr->hfir = dwc2_readl(hsotg, HFIR);
5466         hr->hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
5467         hr->valid = true;
5468
5469         return 0;
5470 }
5471
5472 /**
5473  * dwc2_restore_host_registers() - Restore controller host registers.
5474  * When resuming usb bus, device registers needs to be restored
5475  * if controller power were disabled.
5476  *
5477  * @hsotg: Programming view of the DWC_otg controller
5478  */
5479 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5480 {
5481         struct dwc2_hregs_backup *hr;
5482         int i;
5483
5484         dev_dbg(hsotg->dev, "%s\n", __func__);
5485
5486         /* Restore host regs */
5487         hr = &hsotg->hr_backup;
5488         if (!hr->valid) {
5489                 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5490                         __func__);
5491                 return -EINVAL;
5492         }
5493         hr->valid = false;
5494
5495         dwc2_writel(hsotg, hr->hcfg, HCFG);
5496         dwc2_writel(hsotg, hr->haintmsk, HAINTMSK);
5497
5498         for (i = 0; i < hsotg->params.host_channels; ++i)
5499                 dwc2_writel(hsotg, hr->hcintmsk[i], HCINTMSK(i));
5500
5501         dwc2_writel(hsotg, hr->hprt0, HPRT0);
5502         dwc2_writel(hsotg, hr->hfir, HFIR);
5503         dwc2_writel(hsotg, hr->hptxfsiz, HPTXFSIZ);
5504         hsotg->frame_number = 0;
5505
5506         return 0;
5507 }
5508
5509 /**
5510  * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5511  *
5512  * @hsotg: Programming view of the DWC_otg controller
5513  */
5514 int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5515 {
5516         unsigned long flags;
5517         int ret = 0;
5518         u32 hprt0;
5519         u32 pcgcctl;
5520         u32 gusbcfg;
5521         u32 gpwrdn;
5522
5523         dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5524         ret = dwc2_backup_global_registers(hsotg);
5525         if (ret) {
5526                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5527                         __func__);
5528                 return ret;
5529         }
5530         ret = dwc2_backup_host_registers(hsotg);
5531         if (ret) {
5532                 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5533                         __func__);
5534                 return ret;
5535         }
5536
5537         /* Enter USB Suspend Mode */
5538         hprt0 = dwc2_readl(hsotg, HPRT0);
5539         hprt0 |= HPRT0_SUSP;
5540         hprt0 &= ~HPRT0_ENA;
5541         dwc2_writel(hsotg, hprt0, HPRT0);
5542
5543         /* Wait for the HPRT0.PrtSusp register field to be set */
5544         if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 3000))
5545                 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5546
5547         /*
5548          * We need to disable interrupts to prevent servicing of any IRQ
5549          * during going to hibernation
5550          */
5551         spin_lock_irqsave(&hsotg->lock, flags);
5552         hsotg->lx_state = DWC2_L2;
5553
5554         gusbcfg = dwc2_readl(hsotg, GUSBCFG);
5555         if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5556                 /* ULPI interface */
5557                 /* Suspend the Phy Clock */
5558                 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5559                 pcgcctl |= PCGCTL_STOPPCLK;
5560                 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5561                 udelay(10);
5562
5563                 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5564                 gpwrdn |= GPWRDN_PMUACTV;
5565                 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5566                 udelay(10);
5567         } else {
5568                 /* UTMI+ Interface */
5569                 gpwrdn = dwc2_readl(hsotg, GPWRDN);
5570                 gpwrdn |= GPWRDN_PMUACTV;
5571                 dwc2_writel(hsotg, gpwrdn, GPWRDN);
5572                 udelay(10);
5573
5574                 pcgcctl = dwc2_readl(hsotg, PCGCTL);
5575                 pcgcctl |= PCGCTL_STOPPCLK;
5576                 dwc2_writel(hsotg, pcgcctl, PCGCTL);
5577                 udelay(10);
5578         }
5579
5580         /* Enable interrupts from wake up logic */
5581         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5582         gpwrdn |= GPWRDN_PMUINTSEL;
5583         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5584         udelay(10);
5585
5586         /* Unmask host mode interrupts in GPWRDN */
5587         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5588         gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5589         gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5590         gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5591         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5592         udelay(10);
5593
5594         /* Enable Power Down Clamp */
5595         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5596         gpwrdn |= GPWRDN_PWRDNCLMP;
5597         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5598         udelay(10);
5599
5600         /* Switch off VDD */
5601         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5602         gpwrdn |= GPWRDN_PWRDNSWTCH;
5603         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5604
5605         hsotg->hibernated = 1;
5606         hsotg->bus_suspended = 1;
5607         dev_dbg(hsotg->dev, "Host hibernation completed\n");
5608         spin_unlock_irqrestore(&hsotg->lock, flags);
5609         return ret;
5610 }
5611
5612 /*
5613  * dwc2_host_exit_hibernation()
5614  *
5615  * @hsotg: Programming view of the DWC_otg controller
5616  * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5617  * @param reset: indicates whether resume is initiated by Reset.
5618  *
5619  * Return: non-zero if failed to enter to hibernation.
5620  *
5621  * This function is for exiting from Host mode hibernation by
5622  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5623  */
5624 int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5625                                int reset)
5626 {
5627         u32 gpwrdn;
5628         u32 hprt0;
5629         int ret = 0;
5630         struct dwc2_gregs_backup *gr;
5631         struct dwc2_hregs_backup *hr;
5632
5633         gr = &hsotg->gr_backup;
5634         hr = &hsotg->hr_backup;
5635
5636         dev_dbg(hsotg->dev,
5637                 "%s: called with rem_wakeup = %d reset = %d\n",
5638                 __func__, rem_wakeup, reset);
5639
5640         dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5641         hsotg->hibernated = 0;
5642
5643         /*
5644          * This step is not described in functional spec but if not wait for
5645          * this delay, mismatch interrupts occurred because just after restore
5646          * core is in Device mode(gintsts.curmode == 0)
5647          */
5648         mdelay(100);
5649
5650         /* Clear all pending interupts */
5651         dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5652
5653         /* De-assert Restore */
5654         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5655         gpwrdn &= ~GPWRDN_RESTORE;
5656         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5657         udelay(10);
5658
5659         /* Restore GUSBCFG, HCFG */
5660         dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
5661         dwc2_writel(hsotg, hr->hcfg, HCFG);
5662
5663         /* De-assert Wakeup Logic */
5664         gpwrdn = dwc2_readl(hsotg, GPWRDN);
5665         gpwrdn &= ~GPWRDN_PMUACTV;
5666         dwc2_writel(hsotg, gpwrdn, GPWRDN);
5667         udelay(10);
5668
5669         hprt0 = hr->hprt0;
5670         hprt0 |= HPRT0_PWR;
5671         hprt0 &= ~HPRT0_ENA;
5672         hprt0 &= ~HPRT0_SUSP;
5673         dwc2_writel(hsotg, hprt0, HPRT0);
5674
5675         hprt0 = hr->hprt0;
5676         hprt0 |= HPRT0_PWR;
5677         hprt0 &= ~HPRT0_ENA;
5678         hprt0 &= ~HPRT0_SUSP;
5679
5680         if (reset) {
5681                 hprt0 |= HPRT0_RST;
5682                 dwc2_writel(hsotg, hprt0, HPRT0);
5683
5684                 /* Wait for Resume time and then program HPRT again */
5685                 mdelay(60);
5686                 hprt0 &= ~HPRT0_RST;
5687                 dwc2_writel(hsotg, hprt0, HPRT0);
5688         } else {
5689                 hprt0 |= HPRT0_RES;
5690                 dwc2_writel(hsotg, hprt0, HPRT0);
5691
5692                 /* Wait for Resume time and then program HPRT again */
5693                 mdelay(100);
5694                 hprt0 &= ~HPRT0_RES;
5695                 dwc2_writel(hsotg, hprt0, HPRT0);
5696         }
5697         /* Clear all interrupt status */
5698         hprt0 = dwc2_readl(hsotg, HPRT0);
5699         hprt0 |= HPRT0_CONNDET;
5700         hprt0 |= HPRT0_ENACHG;
5701         hprt0 &= ~HPRT0_ENA;
5702         dwc2_writel(hsotg, hprt0, HPRT0);
5703
5704         hprt0 = dwc2_readl(hsotg, HPRT0);
5705
5706         /* Clear all pending interupts */
5707         dwc2_writel(hsotg, 0xffffffff, GINTSTS);
5708
5709         /* Restore global registers */
5710         ret = dwc2_restore_global_registers(hsotg);
5711         if (ret) {
5712                 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5713                         __func__);
5714                 return ret;
5715         }
5716
5717         /* Restore host registers */
5718         ret = dwc2_restore_host_registers(hsotg);
5719         if (ret) {
5720                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5721                         __func__);
5722                 return ret;
5723         }
5724
5725         dwc2_hcd_rem_wakeup(hsotg);
5726
5727         hsotg->hibernated = 0;
5728         hsotg->bus_suspended = 0;
5729         hsotg->lx_state = DWC2_L0;
5730         dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5731         return ret;
5732 }