drivers/usb/dwc2/params.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * Copyright (C) 2004-2016 Synopsys, Inc.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions, and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. The names of the above-listed copyright holders may not be used
  15  *    to endorse or promote products derived from this software without
  16  *    specific prior written permission.
  17  *
  18  * ALTERNATIVELY, this software may be distributed under the terms of the
  19  * GNU General Public License ("GPL") as published by the Free Software
  20  * Foundation; either version 2 of the License, or (at your option) any
  21  * later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  24  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  25  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  26  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  27  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  28  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  29  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  30  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  31  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  32  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  33  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34  */
  35
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/of_device.h>
  39
  40 #include "core.h"
  41
  42 static void dwc2_set_bcm_params(struct dwc2_hsotg *hsotg)
  43 {
  44         struct dwc2_core_params *p = &hsotg->params;
  45
  46         p->host_rx_fifo_size = 774;
  47         p->max_transfer_size = 65535;
  48         p->max_packet_count = 511;
  49         p->ahbcfg = 0x10;
  50 }
  51
  52 static void dwc2_set_his_params(struct dwc2_hsotg *hsotg)
  53 {
  54         struct dwc2_core_params *p = &hsotg->params;
  55
  56         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  57         p->speed = DWC2_SPEED_PARAM_HIGH;
  58         p->host_rx_fifo_size = 512;
  59         p->host_nperio_tx_fifo_size = 512;
  60         p->host_perio_tx_fifo_size = 512;
  61         p->max_transfer_size = 65535;
  62         p->max_packet_count = 511;
  63         p->host_channels = 16;
  64         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
  65         p->phy_utmi_width = 8;
  66         p->i2c_enable = false;
  67         p->reload_ctl = false;
  68         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  69                 GAHBCFG_HBSTLEN_SHIFT;
  70         p->change_speed_quirk = true;
  71         p->power_down = false;
  72 }
  73
  74 static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
  75 {
  76         struct dwc2_core_params *p = &hsotg->params;
  77
  78         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
  79         p->host_rx_fifo_size = 525;
  80         p->host_nperio_tx_fifo_size = 128;
  81         p->host_perio_tx_fifo_size = 256;
  82         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  83                 GAHBCFG_HBSTLEN_SHIFT;
  84         p->power_down = 0;
  85 }
  86
  87 static void dwc2_set_ltq_params(struct dwc2_hsotg *hsotg)
  88 {
  89         struct dwc2_core_params *p = &hsotg->params;
  90
  91         p->otg_cap = 2;
  92         p->host_rx_fifo_size = 288;
  93         p->host_nperio_tx_fifo_size = 128;
  94         p->host_perio_tx_fifo_size = 96;
  95         p->max_transfer_size = 65535;
  96         p->max_packet_count = 511;
  97         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 <<
  98                 GAHBCFG_HBSTLEN_SHIFT;
  99 }
 100
 101 static void dwc2_set_amlogic_params(struct dwc2_hsotg *hsotg)
 102 {
 103         struct dwc2_core_params *p = &hsotg->params;
 104
 105         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 106         p->speed = DWC2_SPEED_PARAM_HIGH;
 107         p->host_rx_fifo_size = 512;
 108         p->host_nperio_tx_fifo_size = 500;
 109         p->host_perio_tx_fifo_size = 500;
 110         p->host_channels = 16;
 111         p->phy_type = DWC2_PHY_TYPE_PARAM_UTMI;
 112         p->ahbcfg = GAHBCFG_HBSTLEN_INCR8 <<
 113                 GAHBCFG_HBSTLEN_SHIFT;
 114 }
 115
 116 static void dwc2_set_amcc_params(struct dwc2_hsotg *hsotg)
 117 {
 118         struct dwc2_core_params *p = &hsotg->params;
 119
 120         p->ahbcfg = GAHBCFG_HBSTLEN_INCR16 << GAHBCFG_HBSTLEN_SHIFT;
 121 }
 122
 123 static void dwc2_set_stm32f4x9_fsotg_params(struct dwc2_hsotg *hsotg)
 124 {
 125         struct dwc2_core_params *p = &hsotg->params;
 126
 127         p->otg_cap = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 128         p->speed = DWC2_SPEED_PARAM_FULL;
 129         p->host_rx_fifo_size = 128;
 130         p->host_nperio_tx_fifo_size = 96;
 131         p->host_perio_tx_fifo_size = 96;
 132         p->max_packet_count = 256;
 133         p->phy_type = DWC2_PHY_TYPE_PARAM_FS;
 134         p->i2c_enable = false;
 135         p->activate_stm_fs_transceiver = true;
 136 }
 137
 138 static void dwc2_set_stm32f7_hsotg_params(struct dwc2_hsotg *hsotg)
 139 {
 140         struct dwc2_core_params *p = &hsotg->params;
 141
 142         p->host_rx_fifo_size = 622;
 143         p->host_nperio_tx_fifo_size = 128;
 144         p->host_perio_tx_fifo_size = 256;
 145 }
 146
 147 const struct of_device_id dwc2_of_match_table[] = {
 148         { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
 149         { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
 150         { .compatible = "rockchip,rk3066-usb", .data = dwc2_set_rk_params },
 151         { .compatible = "lantiq,arx100-usb", .data = dwc2_set_ltq_params },
 152         { .compatible = "lantiq,xrx200-usb", .data = dwc2_set_ltq_params },
 153         { .compatible = "snps,dwc2" },
 154         { .compatible = "samsung,s3c6400-hsotg" },
 155         { .compatible = "amlogic,meson8-usb",
 156           .data = dwc2_set_amlogic_params },
 157         { .compatible = "amlogic,meson8b-usb",
 158           .data = dwc2_set_amlogic_params },
 159         { .compatible = "amlogic,meson-gxbb-usb",
 160           .data = dwc2_set_amlogic_params },
 161         { .compatible = "amcc,dwc-otg", .data = dwc2_set_amcc_params },
 162         { .compatible = "st,stm32f4x9-fsotg",
 163           .data = dwc2_set_stm32f4x9_fsotg_params },
 164         { .compatible = "st,stm32f4x9-hsotg" },
 165         { .compatible = "st,stm32f7-hsotg",
 166           .data = dwc2_set_stm32f7_hsotg_params },
 167         {},
 168 };
 169 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 170
 171 static void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg)
 172 {
 173         u8 val;
 174
 175         switch (hsotg->hw_params.op_mode) {
 176         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 177                 val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
 178                 break;
 179         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 180         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 181         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 182                 val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
 183                 break;
 184         default:
 185                 val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
 186                 break;
 187         }
 188
 189         hsotg->params.otg_cap = val;
 190 }
 191
 192 static void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg)
 193 {
 194         int val;
 195         u32 hs_phy_type = hsotg->hw_params.hs_phy_type;
 196
 197         val = DWC2_PHY_TYPE_PARAM_FS;
 198         if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
 199                 if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
 200                     hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
 201                         val = DWC2_PHY_TYPE_PARAM_UTMI;
 202                 else
 203                         val = DWC2_PHY_TYPE_PARAM_ULPI;
 204         }
 205
 206         if (dwc2_is_fs_iot(hsotg))
 207                 hsotg->params.phy_type = DWC2_PHY_TYPE_PARAM_FS;
 208
 209         hsotg->params.phy_type = val;
 210 }
 211
 212 static void dwc2_set_param_speed(struct dwc2_hsotg *hsotg)
 213 {
 214         int val;
 215
 216         val = hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS ?
 217                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
 218
 219         if (dwc2_is_fs_iot(hsotg))
 220                 val = DWC2_SPEED_PARAM_FULL;
 221
 222         if (dwc2_is_hs_iot(hsotg))
 223                 val = DWC2_SPEED_PARAM_HIGH;
 224
 225         hsotg->params.speed = val;
 226 }
 227
 228 static void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 229 {
 230         int val;
 231
 232         val = (hsotg->hw_params.utmi_phy_data_width ==
 233                GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
 234
 235         hsotg->params.phy_utmi_width = val;
 236 }
 237
 238 static void dwc2_set_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 239 {
 240         struct dwc2_core_params *p = &hsotg->params;
 241         int depth_average;
 242         int fifo_count;
 243         int i;
 244
 245         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 246
 247         memset(p->g_tx_fifo_size, 0, sizeof(p->g_tx_fifo_size));
 248         depth_average = dwc2_hsotg_tx_fifo_average_depth(hsotg);
 249         for (i = 1; i <= fifo_count; i++)
 250                 p->g_tx_fifo_size[i] = depth_average;
 251 }
 252
 253 static void dwc2_set_param_power_down(struct dwc2_hsotg *hsotg)
 254 {
 255         int val;
 256
 257         if (hsotg->hw_params.hibernation)
 258                 val = 2;
 259         else if (hsotg->hw_params.power_optimized)
 260                 val = 1;
 261         else
 262                 val = 0;
 263
 264         hsotg->params.power_down = val;
 265 }
 266
 267 /**
 268  * dwc2_set_default_params() - Set all core parameters to their
 269  * auto-detected default values.
 270  *
 271  * @hsotg: Programming view of the DWC_otg controller
 272  *
 273  */
 274 static void dwc2_set_default_params(struct dwc2_hsotg *hsotg)
 275 {
 276         struct dwc2_hw_params *hw = &hsotg->hw_params;
 277         struct dwc2_core_params *p = &hsotg->params;
 278         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 279
 280         dwc2_set_param_otg_cap(hsotg);
 281         dwc2_set_param_phy_type(hsotg);
 282         dwc2_set_param_speed(hsotg);
 283         dwc2_set_param_phy_utmi_width(hsotg);
 284         dwc2_set_param_power_down(hsotg);
 285         p->phy_ulpi_ddr = false;
 286         p->phy_ulpi_ext_vbus = false;
 287
 288         p->enable_dynamic_fifo = hw->enable_dynamic_fifo;
 289         p->en_multiple_tx_fifo = hw->en_multiple_tx_fifo;
 290         p->i2c_enable = hw->i2c_enable;
 291         p->acg_enable = hw->acg_enable;
 292         p->ulpi_fs_ls = false;
 293         p->ts_dline = false;
 294         p->reload_ctl = (hw->snpsid >= DWC2_CORE_REV_2_92a);
 295         p->uframe_sched = true;
 296         p->external_id_pin_ctl = false;
 297         p->lpm = true;
 298         p->lpm_clock_gating = true;
 299         p->besl = true;
 300         p->hird_threshold_en = true;
 301         p->hird_threshold = 4;
 302         p->ipg_isoc_en = false;
 303         p->service_interval = false;
 304         p->max_packet_count = hw->max_packet_count;
 305         p->max_transfer_size = hw->max_transfer_size;
 306         p->ahbcfg = GAHBCFG_HBSTLEN_INCR << GAHBCFG_HBSTLEN_SHIFT;
 307         p->ref_clk_per = 33333;
 308         p->sof_cnt_wkup_alert = 100;
 309
 310         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 311             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 312                 p->host_dma = dma_capable;
 313                 p->dma_desc_enable = false;
 314                 p->dma_desc_fs_enable = false;
 315                 p->host_support_fs_ls_low_power = false;
 316                 p->host_ls_low_power_phy_clk = false;
 317                 p->host_channels = hw->host_channels;
 318                 p->host_rx_fifo_size = hw->rx_fifo_size;
 319                 p->host_nperio_tx_fifo_size = hw->host_nperio_tx_fifo_size;
 320                 p->host_perio_tx_fifo_size = hw->host_perio_tx_fifo_size;
 321         }
 322
 323         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 324             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 325                 p->g_dma = dma_capable;
 326                 p->g_dma_desc = hw->dma_desc_enable;
 327
 328                 /*
 329                  * The values for g_rx_fifo_size (2048) and
 330                  * g_np_tx_fifo_size (1024) come from the legacy s3c
 331                  * gadget driver. These defaults have been hard-coded
 332                  * for some time so many platforms depend on these
 333                  * values. Leave them as defaults for now and only
 334                  * auto-detect if the hardware does not support the
 335                  * default.
 336                  */
 337                 p->g_rx_fifo_size = 2048;
 338                 p->g_np_tx_fifo_size = 1024;
 339                 dwc2_set_param_tx_fifo_sizes(hsotg);
 340         }
 341 }
 342
 343 /**
 344  * dwc2_get_device_properties() - Read in device properties.
 345  *
 346  * @hsotg: Programming view of the DWC_otg controller
 347  *
 348  * Read in the device properties and adjust core parameters if needed.
 349  */
 350 static void dwc2_get_device_properties(struct dwc2_hsotg *hsotg)
 351 {
 352         struct dwc2_core_params *p = &hsotg->params;
 353         int num;
 354
 355         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 356             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 357                 device_property_read_u32(hsotg->dev, "g-rx-fifo-size",
 358                                          &p->g_rx_fifo_size);
 359
 360                 device_property_read_u32(hsotg->dev, "g-np-tx-fifo-size",
 361                                          &p->g_np_tx_fifo_size);
 362
 363                 num = device_property_read_u32_array(hsotg->dev,
 364                                                      "g-tx-fifo-size",
 365                                                      NULL, 0);
 366
 367                 if (num > 0) {
 368                         num = min(num, 15);
 369                         memset(p->g_tx_fifo_size, 0,
 370                                sizeof(p->g_tx_fifo_size));
 371                         device_property_read_u32_array(hsotg->dev,
 372                                                        "g-tx-fifo-size",
 373                                                        &p->g_tx_fifo_size[1],
 374                                                        num);
 375                 }
 376         }
 377
 378         if (of_find_property(hsotg->dev->of_node, "disable-over-current", NULL))
 379                 p->oc_disable = true;
 380 }
 381
 382 static void dwc2_check_param_otg_cap(struct dwc2_hsotg *hsotg)
 383 {
 384         int valid = 1;
 385
 386         switch (hsotg->params.otg_cap) {
 387         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
 388                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
 389                         valid = 0;
 390                 break;
 391         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
 392                 switch (hsotg->hw_params.op_mode) {
 393                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 394                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 395                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 396                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 397                         break;
 398                 default:
 399                         valid = 0;
 400                         break;
 401                 }
 402                 break;
 403         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 404                 /* always valid */
 405                 break;
 406         default:
 407                 valid = 0;
 408                 break;
 409         }
 410
 411         if (!valid)
 412                 dwc2_set_param_otg_cap(hsotg);
 413 }
 414
 415 static void dwc2_check_param_phy_type(struct dwc2_hsotg *hsotg)
 416 {
 417         int valid = 0;
 418         u32 hs_phy_type;
 419         u32 fs_phy_type;
 420
 421         hs_phy_type = hsotg->hw_params.hs_phy_type;
 422         fs_phy_type = hsotg->hw_params.fs_phy_type;
 423
 424         switch (hsotg->params.phy_type) {
 425         case DWC2_PHY_TYPE_PARAM_FS:
 426                 if (fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
 427                         valid = 1;
 428                 break;
 429         case DWC2_PHY_TYPE_PARAM_UTMI:
 430                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 431                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 432                         valid = 1;
 433                 break;
 434         case DWC2_PHY_TYPE_PARAM_ULPI:
 435                 if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI) ||
 436                     (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
 437                         valid = 1;
 438                 break;
 439         default:
 440                 break;
 441         }
 442
 443         if (!valid)
 444                 dwc2_set_param_phy_type(hsotg);
 445 }
 446
 447 static void dwc2_check_param_speed(struct dwc2_hsotg *hsotg)
 448 {
 449         int valid = 1;
 450         int phy_type = hsotg->params.phy_type;
 451         int speed = hsotg->params.speed;
 452
 453         switch (speed) {
 454         case DWC2_SPEED_PARAM_HIGH:
 455                 if ((hsotg->params.speed == DWC2_SPEED_PARAM_HIGH) &&
 456                     (phy_type == DWC2_PHY_TYPE_PARAM_FS))
 457                         valid = 0;
 458                 break;
 459         case DWC2_SPEED_PARAM_FULL:
 460         case DWC2_SPEED_PARAM_LOW:
 461                 break;
 462         default:
 463                 valid = 0;
 464                 break;
 465         }
 466
 467         if (!valid)
 468                 dwc2_set_param_speed(hsotg);
 469 }
 470
 471 static void dwc2_check_param_phy_utmi_width(struct dwc2_hsotg *hsotg)
 472 {
 473         int valid = 0;
 474         int param = hsotg->params.phy_utmi_width;
 475         int width = hsotg->hw_params.utmi_phy_data_width;
 476
 477         switch (width) {
 478         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
 479                 valid = (param == 8);
 480                 break;
 481         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
 482                 valid = (param == 16);
 483                 break;
 484         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
 485                 valid = (param == 8 || param == 16);
 486                 break;
 487         }
 488
 489         if (!valid)
 490                 dwc2_set_param_phy_utmi_width(hsotg);
 491 }
 492
 493 static void dwc2_check_param_power_down(struct dwc2_hsotg *hsotg)
 494 {
 495         int param = hsotg->params.power_down;
 496
 497         switch (param) {
 498         case DWC2_POWER_DOWN_PARAM_NONE:
 499                 break;
 500         case DWC2_POWER_DOWN_PARAM_PARTIAL:
 501                 if (hsotg->hw_params.power_optimized)
 502                         break;
 503                 dev_dbg(hsotg->dev,
 504                         "Partial power down isn't supported by HW\n");
 505                 param = DWC2_POWER_DOWN_PARAM_NONE;
 506                 break;
 507         case DWC2_POWER_DOWN_PARAM_HIBERNATION:
 508                 if (hsotg->hw_params.hibernation)
 509                         break;
 510                 dev_dbg(hsotg->dev,
 511                         "Hibernation isn't supported by HW\n");
 512                 param = DWC2_POWER_DOWN_PARAM_NONE;
 513                 break;
 514         default:
 515                 dev_err(hsotg->dev,
 516                         "%s: Invalid parameter power_down=%d\n",
 517                         __func__, param);
 518                 param = DWC2_POWER_DOWN_PARAM_NONE;
 519                 break;
 520         }
 521
 522         hsotg->params.power_down = param;
 523 }
 524
 525 static void dwc2_check_param_tx_fifo_sizes(struct dwc2_hsotg *hsotg)
 526 {
 527         int fifo_count;
 528         int fifo;
 529         int min;
 530         u32 total = 0;
 531         u32 dptxfszn;
 532
 533         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 534         min = hsotg->hw_params.en_multiple_tx_fifo ? 16 : 4;
 535
 536         for (fifo = 1; fifo <= fifo_count; fifo++)
 537                 total += hsotg->params.g_tx_fifo_size[fifo];
 538
 539         if (total > dwc2_hsotg_tx_fifo_total_depth(hsotg) || !total) {
 540                 dev_warn(hsotg->dev, "%s: Invalid parameter g-tx-fifo-size, setting to default average\n",
 541                          __func__);
 542                 dwc2_set_param_tx_fifo_sizes(hsotg);
 543         }
 544
 545         for (fifo = 1; fifo <= fifo_count; fifo++) {
 546                 dptxfszn = hsotg->hw_params.g_tx_fifo_size[fifo];
 547
 548                 if (hsotg->params.g_tx_fifo_size[fifo] < min ||
 549                     hsotg->params.g_tx_fifo_size[fifo] >  dptxfszn) {
 550                         dev_warn(hsotg->dev, "%s: Invalid parameter g_tx_fifo_size[%d]=%d\n",
 551                                  __func__, fifo,
 552                                  hsotg->params.g_tx_fifo_size[fifo]);
 553                         hsotg->params.g_tx_fifo_size[fifo] = dptxfszn;
 554                 }
 555         }
 556 }
 557
 558 #define CHECK_RANGE(_param, _min, _max, _def) do {                      \
 559                 if ((int)(hsotg->params._param) < (_min) ||             \
 560                     (hsotg->params._param) > (_max)) {                  \
 561                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 562                                  __func__, #_param, hsotg->params._param); \
 563                         hsotg->params._param = (_def);                  \
 564                 }                                                       \
 565         } while (0)
 566
 567 #define CHECK_BOOL(_param, _check) do {                                 \
 568                 if (hsotg->params._param && !(_check)) {                \
 569                         dev_warn(hsotg->dev, "%s: Invalid parameter %s=%d\n", \
 570                                  __func__, #_param, hsotg->params._param); \
 571                         hsotg->params._param = false;                   \
 572                 }                                                       \
 573         } while (0)
 574
 575 static void dwc2_check_params(struct dwc2_hsotg *hsotg)
 576 {
 577         struct dwc2_hw_params *hw = &hsotg->hw_params;
 578         struct dwc2_core_params *p = &hsotg->params;
 579         bool dma_capable = !(hw->arch == GHWCFG2_SLAVE_ONLY_ARCH);
 580
 581         dwc2_check_param_otg_cap(hsotg);
 582         dwc2_check_param_phy_type(hsotg);
 583         dwc2_check_param_speed(hsotg);
 584         dwc2_check_param_phy_utmi_width(hsotg);
 585         dwc2_check_param_power_down(hsotg);
 586         CHECK_BOOL(enable_dynamic_fifo, hw->enable_dynamic_fifo);
 587         CHECK_BOOL(en_multiple_tx_fifo, hw->en_multiple_tx_fifo);
 588         CHECK_BOOL(i2c_enable, hw->i2c_enable);
 589         CHECK_BOOL(ipg_isoc_en, hw->ipg_isoc_en);
 590         CHECK_BOOL(acg_enable, hw->acg_enable);
 591         CHECK_BOOL(reload_ctl, (hsotg->hw_params.snpsid > DWC2_CORE_REV_2_92a));
 592         CHECK_BOOL(lpm, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_80a));
 593         CHECK_BOOL(lpm, hw->lpm_mode);
 594         CHECK_BOOL(lpm_clock_gating, hsotg->params.lpm);
 595         CHECK_BOOL(besl, hsotg->params.lpm);
 596         CHECK_BOOL(besl, (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a));
 597         CHECK_BOOL(hird_threshold_en, hsotg->params.lpm);
 598         CHECK_RANGE(hird_threshold, 0, hsotg->params.besl ? 12 : 7, 0);
 599         CHECK_BOOL(service_interval, hw->service_interval_mode);
 600         CHECK_RANGE(max_packet_count,
 601                     15, hw->max_packet_count,
 602                     hw->max_packet_count);
 603         CHECK_RANGE(max_transfer_size,
 604                     2047, hw->max_transfer_size,
 605                     hw->max_transfer_size);
 606
 607         if ((hsotg->dr_mode == USB_DR_MODE_HOST) ||
 608             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 609                 CHECK_BOOL(host_dma, dma_capable);
 610                 CHECK_BOOL(dma_desc_enable, p->host_dma);
 611                 CHECK_BOOL(dma_desc_fs_enable, p->dma_desc_enable);
 612                 CHECK_BOOL(host_ls_low_power_phy_clk,
 613                            p->phy_type == DWC2_PHY_TYPE_PARAM_FS);
 614                 CHECK_RANGE(host_channels,
 615                             1, hw->host_channels,
 616                             hw->host_channels);
 617                 CHECK_RANGE(host_rx_fifo_size,
 618                             16, hw->rx_fifo_size,
 619                             hw->rx_fifo_size);
 620                 CHECK_RANGE(host_nperio_tx_fifo_size,
 621                             16, hw->host_nperio_tx_fifo_size,
 622                             hw->host_nperio_tx_fifo_size);
 623                 CHECK_RANGE(host_perio_tx_fifo_size,
 624                             16, hw->host_perio_tx_fifo_size,
 625                             hw->host_perio_tx_fifo_size);
 626         }
 627
 628         if ((hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) ||
 629             (hsotg->dr_mode == USB_DR_MODE_OTG)) {
 630                 CHECK_BOOL(g_dma, dma_capable);
 631                 CHECK_BOOL(g_dma_desc, (p->g_dma && hw->dma_desc_enable));
 632                 CHECK_RANGE(g_rx_fifo_size,
 633                             16, hw->rx_fifo_size,
 634                             hw->rx_fifo_size);
 635                 CHECK_RANGE(g_np_tx_fifo_size,
 636                             16, hw->dev_nperio_tx_fifo_size,
 637                             hw->dev_nperio_tx_fifo_size);
 638                 dwc2_check_param_tx_fifo_sizes(hsotg);
 639         }
 640 }
 641
 642 /*
 643  * Gets host hardware parameters. Forces host mode if not currently in
 644  * host mode. Should be called immediately after a core soft reset in
 645  * order to get the reset values.
 646  */
 647 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg)
 648 {
 649         struct dwc2_hw_params *hw = &hsotg->hw_params;
 650         u32 gnptxfsiz;
 651         u32 hptxfsiz;
 652
 653         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 654                 return;
 655
 656         dwc2_force_mode(hsotg, true);
 657
 658         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 659         hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
 660
 661         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 662                                        FIFOSIZE_DEPTH_SHIFT;
 663         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 664                                       FIFOSIZE_DEPTH_SHIFT;
 665 }
 666
 667 /*
 668  * Gets device hardware parameters. Forces device mode if not
 669  * currently in device mode. Should be called immediately after a core
 670  * soft reset in order to get the reset values.
 671  */
 672 static void dwc2_get_dev_hwparams(struct dwc2_hsotg *hsotg)
 673 {
 674         struct dwc2_hw_params *hw = &hsotg->hw_params;
 675         u32 gnptxfsiz;
 676         int fifo, fifo_count;
 677
 678         if (hsotg->dr_mode == USB_DR_MODE_HOST)
 679                 return;
 680
 681         dwc2_force_mode(hsotg, false);
 682
 683         gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
 684
 685         fifo_count = dwc2_hsotg_tx_fifo_count(hsotg);
 686
 687         for (fifo = 1; fifo <= fifo_count; fifo++) {
 688                 hw->g_tx_fifo_size[fifo] =
 689                         (dwc2_readl(hsotg, DPTXFSIZN(fifo)) &
 690                          FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 691         }
 692
 693         hw->dev_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
 694                                        FIFOSIZE_DEPTH_SHIFT;
 695 }
 696
 697 /**
 698  * During device initialization, read various hardware configuration
 699  * registers and interpret the contents.
 700  *
 701  * @hsotg: Programming view of the DWC_otg controller
 702  *
 703  */
 704 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
 705 {
 706         struct dwc2_hw_params *hw = &hsotg->hw_params;
 707         unsigned int width;
 708         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
 709         u32 grxfsiz;
 710
 711         /*
 712          * Attempt to ensure this device is really a DWC_otg Controller.
 713          * Read and verify the GSNPSID register contents. The value should be
 714          * 0x45f4xxxx, 0x5531xxxx or 0x5532xxxx
 715          */
 716
 717         hw->snpsid = dwc2_readl(hsotg, GSNPSID);
 718         if ((hw->snpsid & GSNPSID_ID_MASK) != DWC2_OTG_ID &&
 719             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_FS_IOT_ID &&
 720             (hw->snpsid & GSNPSID_ID_MASK) != DWC2_HS_IOT_ID) {
 721                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
 722                         hw->snpsid);
 723                 return -ENODEV;
 724         }
 725
 726         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
 727                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
 728                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
 729
 730         hwcfg1 = dwc2_readl(hsotg, GHWCFG1);
 731         hwcfg2 = dwc2_readl(hsotg, GHWCFG2);
 732         hwcfg3 = dwc2_readl(hsotg, GHWCFG3);
 733         hwcfg4 = dwc2_readl(hsotg, GHWCFG4);
 734         grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
 735
 736         /* hwcfg1 */
 737         hw->dev_ep_dirs = hwcfg1;
 738
 739         /* hwcfg2 */
 740         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
 741                       GHWCFG2_OP_MODE_SHIFT;
 742         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
 743                    GHWCFG2_ARCHITECTURE_SHIFT;
 744         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
 745         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
 746                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
 747         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
 748                           GHWCFG2_HS_PHY_TYPE_SHIFT;
 749         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
 750                           GHWCFG2_FS_PHY_TYPE_SHIFT;
 751         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
 752                          GHWCFG2_NUM_DEV_EP_SHIFT;
 753         hw->nperio_tx_q_depth =
 754                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
 755                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
 756         hw->host_perio_tx_q_depth =
 757                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
 758                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
 759         hw->dev_token_q_depth =
 760                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
 761                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
 762
 763         /* hwcfg3 */
 764         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
 765                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
 766         hw->max_transfer_size = (1 << (width + 11)) - 1;
 767         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
 768                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 769         hw->max_packet_count = (1 << (width + 4)) - 1;
 770         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
 771         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
 772                               GHWCFG3_DFIFO_DEPTH_SHIFT;
 773         hw->lpm_mode = !!(hwcfg3 & GHWCFG3_OTG_LPM_EN);
 774
 775         /* hwcfg4 */
 776         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
 777         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
 778                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
 779         hw->num_dev_in_eps = (hwcfg4 & GHWCFG4_NUM_IN_EPS_MASK) >>
 780                              GHWCFG4_NUM_IN_EPS_SHIFT;
 781         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
 782         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
 783         hw->hibernation = !!(hwcfg4 & GHWCFG4_HIBER);
 784         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
 785                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
 786         hw->acg_enable = !!(hwcfg4 & GHWCFG4_ACG_SUPPORTED);
 787         hw->ipg_isoc_en = !!(hwcfg4 & GHWCFG4_IPG_ISOC_SUPPORTED);
 788         hw->service_interval_mode = !!(hwcfg4 &
 789                                        GHWCFG4_SERVICE_INTERVAL_SUPPORTED);
 790
 791         /* fifo sizes */
 792         hw->rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
 793                                 GRXFSIZ_DEPTH_SHIFT;
 794         /*
 795          * Host specific hardware parameters. Reading these parameters
 796          * requires the controller to be in host mode. The mode will
 797          * be forced, if necessary, to read these values.
 798          */
 799         dwc2_get_host_hwparams(hsotg);
 800         dwc2_get_dev_hwparams(hsotg);
 801
 802         return 0;
 803 }
 804
 805 int dwc2_init_params(struct dwc2_hsotg *hsotg)
 806 {
 807         const struct of_device_id *match;
 808         void (*set_params)(void *data);
 809
 810         dwc2_set_default_params(hsotg);
 811         dwc2_get_device_properties(hsotg);
 812
 813         match = of_match_device(dwc2_of_match_table, hsotg->dev);
 814         if (match && match->data) {
 815                 set_params = match->data;
 816                 set_params(hsotg);
 817         }
 818
 819         dwc2_check_params(hsotg);
 820
 821         return 0;
 822 }