drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81         }
  82
  83         if (mode != dwc->dr_mode) {
  84                 dev_warn(dev,
  85                          "Configuration mismatch. dr_mode forced to %s\n",
  86                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  87
  88                 dwc->dr_mode = mode;
  89         }
  90
  91         return 0;
  92 }
  93
  94 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
  95 {
  96         u32 reg;
  97
  98         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  99         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 100         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 101         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 102
 103         dwc->current_dr_role = mode;
 104 }
 105
 106 static void __dwc3_set_mode(struct work_struct *work)
 107 {
 108         struct dwc3 *dwc = work_to_dwc(work);
 109         unsigned long flags;
 110         int ret;
 111
 112         if (dwc->dr_mode != USB_DR_MODE_OTG)
 113                 return;
 114
 115         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 116                 dwc3_otg_update(dwc, 0);
 117
 118         if (!dwc->desired_dr_role)
 119                 return;
 120
 121         if (dwc->desired_dr_role == dwc->current_dr_role)
 122                 return;
 123
 124         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 125                 return;
 126
 127         switch (dwc->current_dr_role) {
 128         case DWC3_GCTL_PRTCAP_HOST:
 129                 dwc3_host_exit(dwc);
 130                 break;
 131         case DWC3_GCTL_PRTCAP_DEVICE:
 132                 dwc3_gadget_exit(dwc);
 133                 dwc3_event_buffers_cleanup(dwc);
 134                 break;
 135         case DWC3_GCTL_PRTCAP_OTG:
 136                 dwc3_otg_exit(dwc);
 137                 spin_lock_irqsave(&dwc->lock, flags);
 138                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 139                 spin_unlock_irqrestore(&dwc->lock, flags);
 140                 dwc3_otg_update(dwc, 1);
 141                 break;
 142         default:
 143                 break;
 144         }
 145
 146         spin_lock_irqsave(&dwc->lock, flags);
 147
 148         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 149
 150         spin_unlock_irqrestore(&dwc->lock, flags);
 151
 152         switch (dwc->desired_dr_role) {
 153         case DWC3_GCTL_PRTCAP_HOST:
 154                 ret = dwc3_host_init(dwc);
 155                 if (ret) {
 156                         dev_err(dwc->dev, "failed to initialize host\n");
 157                 } else {
 158                         if (dwc->usb2_phy)
 159                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 160                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 161                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 162                         phy_calibrate(dwc->usb2_generic_phy);
 163                 }
 164                 break;
 165         case DWC3_GCTL_PRTCAP_DEVICE:
 166                 dwc3_event_buffers_setup(dwc);
 167
 168                 if (dwc->usb2_phy)
 169                         otg_set_vbus(dwc->usb2_phy->otg, false);
 170                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 171                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 172
 173                 ret = dwc3_gadget_init(dwc);
 174                 if (ret)
 175                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 176                 break;
 177         case DWC3_GCTL_PRTCAP_OTG:
 178                 dwc3_otg_init(dwc);
 179                 dwc3_otg_update(dwc, 0);
 180                 break;
 181         default:
 182                 break;
 183         }
 184
 185 }
 186
 187 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 188 {
 189         unsigned long flags;
 190
 191         spin_lock_irqsave(&dwc->lock, flags);
 192         dwc->desired_dr_role = mode;
 193         spin_unlock_irqrestore(&dwc->lock, flags);
 194
 195         queue_work(system_freezable_wq, &dwc->drd_work);
 196 }
 197
 198 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 199 {
 200         struct dwc3             *dwc = dep->dwc;
 201         u32                     reg;
 202
 203         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 204                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 205                         DWC3_GDBGFIFOSPACE_TYPE(type));
 206
 207         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 208
 209         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 210 }
 211
 212 /**
 213  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 214  * @dwc: pointer to our context structure
 215  */
 216 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 217 {
 218         u32             reg;
 219         int             retries = 1000;
 220         int             ret;
 221
 222         usb_phy_init(dwc->usb2_phy);
 223         usb_phy_init(dwc->usb3_phy);
 224         ret = phy_init(dwc->usb2_generic_phy);
 225         if (ret < 0)
 226                 return ret;
 227
 228         ret = phy_init(dwc->usb3_generic_phy);
 229         if (ret < 0) {
 230                 phy_exit(dwc->usb2_generic_phy);
 231                 return ret;
 232         }
 233
 234         /*
 235          * We're resetting only the device side because, if we're in host mode,
 236          * XHCI driver will reset the host block. If dwc3 was configured for
 237          * host-only mode, then we can return early.
 238          */
 239         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 240                 return 0;
 241
 242         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 243         reg |= DWC3_DCTL_CSFTRST;
 244         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 245
 246         do {
 247                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 248                 if (!(reg & DWC3_DCTL_CSFTRST))
 249                         goto done;
 250
 251                 udelay(1);
 252         } while (--retries);
 253
 254         phy_exit(dwc->usb3_generic_phy);
 255         phy_exit(dwc->usb2_generic_phy);
 256
 257         return -ETIMEDOUT;
 258
 259 done:
 260         /*
 261          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 262          * we must wait at least 50ms before accessing the PHY domain
 263          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 264          */
 265         if (dwc3_is_usb31(dwc))
 266                 msleep(50);
 267
 268         return 0;
 269 }
 270
 271 static const struct clk_bulk_data dwc3_core_clks[] = {
 272         { .id = "ref" },
 273         { .id = "bus_early" },
 274         { .id = "suspend" },
 275 };
 276
 277 /*
 278  * dwc3_frame_length_adjustment - Adjusts frame length if required
 279  * @dwc3: Pointer to our controller context structure
 280  */
 281 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 282 {
 283         u32 reg;
 284         u32 dft;
 285
 286         if (dwc->revision < DWC3_REVISION_250A)
 287                 return;
 288
 289         if (dwc->fladj == 0)
 290                 return;
 291
 292         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 293         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 294         if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
 295             "request value same as default, ignoring\n")) {
 296                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 297                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 298                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 299         }
 300 }
 301
 302 /**
 303  * dwc3_free_one_event_buffer - Frees one event buffer
 304  * @dwc: Pointer to our controller context structure
 305  * @evt: Pointer to event buffer to be freed
 306  */
 307 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 308                 struct dwc3_event_buffer *evt)
 309 {
 310         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 311 }
 312
 313 /**
 314  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 315  * @dwc: Pointer to our controller context structure
 316  * @length: size of the event buffer
 317  *
 318  * Returns a pointer to the allocated event buffer structure on success
 319  * otherwise ERR_PTR(errno).
 320  */
 321 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 322                 unsigned length)
 323 {
 324         struct dwc3_event_buffer        *evt;
 325
 326         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 327         if (!evt)
 328                 return ERR_PTR(-ENOMEM);
 329
 330         evt->dwc        = dwc;
 331         evt->length     = length;
 332         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 333         if (!evt->cache)
 334                 return ERR_PTR(-ENOMEM);
 335
 336         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 337                         &evt->dma, GFP_KERNEL);
 338         if (!evt->buf)
 339                 return ERR_PTR(-ENOMEM);
 340
 341         return evt;
 342 }
 343
 344 /**
 345  * dwc3_free_event_buffers - frees all allocated event buffers
 346  * @dwc: Pointer to our controller context structure
 347  */
 348 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 349 {
 350         struct dwc3_event_buffer        *evt;
 351
 352         evt = dwc->ev_buf;
 353         if (evt)
 354                 dwc3_free_one_event_buffer(dwc, evt);
 355 }
 356
 357 /**
 358  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 359  * @dwc: pointer to our controller context structure
 360  * @length: size of event buffer
 361  *
 362  * Returns 0 on success otherwise negative errno. In the error case, dwc
 363  * may contain some buffers allocated but not all which were requested.
 364  */
 365 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 366 {
 367         struct dwc3_event_buffer *evt;
 368
 369         evt = dwc3_alloc_one_event_buffer(dwc, length);
 370         if (IS_ERR(evt)) {
 371                 dev_err(dwc->dev, "can't allocate event buffer\n");
 372                 return PTR_ERR(evt);
 373         }
 374         dwc->ev_buf = evt;
 375
 376         return 0;
 377 }
 378
 379 /**
 380  * dwc3_event_buffers_setup - setup our allocated event buffers
 381  * @dwc: pointer to our controller context structure
 382  *
 383  * Returns 0 on success otherwise negative errno.
 384  */
 385 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 386 {
 387         struct dwc3_event_buffer        *evt;
 388
 389         evt = dwc->ev_buf;
 390         evt->lpos = 0;
 391         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 392                         lower_32_bits(evt->dma));
 393         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 394                         upper_32_bits(evt->dma));
 395         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 396                         DWC3_GEVNTSIZ_SIZE(evt->length));
 397         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 398
 399         return 0;
 400 }
 401
 402 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 403 {
 404         struct dwc3_event_buffer        *evt;
 405
 406         evt = dwc->ev_buf;
 407
 408         evt->lpos = 0;
 409
 410         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 411         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 412         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 413                         | DWC3_GEVNTSIZ_SIZE(0));
 414         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 415 }
 416
 417 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 418 {
 419         if (!dwc->has_hibernation)
 420                 return 0;
 421
 422         if (!dwc->nr_scratch)
 423                 return 0;
 424
 425         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 426                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 427         if (!dwc->scratchbuf)
 428                 return -ENOMEM;
 429
 430         return 0;
 431 }
 432
 433 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 434 {
 435         dma_addr_t scratch_addr;
 436         u32 param;
 437         int ret;
 438
 439         if (!dwc->has_hibernation)
 440                 return 0;
 441
 442         if (!dwc->nr_scratch)
 443                 return 0;
 444
 445          /* should never fall here */
 446         if (!WARN_ON(dwc->scratchbuf))
 447                 return 0;
 448
 449         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 450                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 451                         DMA_BIDIRECTIONAL);
 452         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 453                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 454                 ret = -EFAULT;
 455                 goto err0;
 456         }
 457
 458         dwc->scratch_addr = scratch_addr;
 459
 460         param = lower_32_bits(scratch_addr);
 461
 462         ret = dwc3_send_gadget_generic_command(dwc,
 463                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 464         if (ret < 0)
 465                 goto err1;
 466
 467         param = upper_32_bits(scratch_addr);
 468
 469         ret = dwc3_send_gadget_generic_command(dwc,
 470                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 471         if (ret < 0)
 472                 goto err1;
 473
 474         return 0;
 475
 476 err1:
 477         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 478                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 479
 480 err0:
 481         return ret;
 482 }
 483
 484 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 485 {
 486         if (!dwc->has_hibernation)
 487                 return;
 488
 489         if (!dwc->nr_scratch)
 490                 return;
 491
 492          /* should never fall here */
 493         if (!WARN_ON(dwc->scratchbuf))
 494                 return;
 495
 496         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 497                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 498         kfree(dwc->scratchbuf);
 499 }
 500
 501 static void dwc3_core_num_eps(struct dwc3 *dwc)
 502 {
 503         struct dwc3_hwparams    *parms = &dwc->hwparams;
 504
 505         dwc->num_eps = DWC3_NUM_EPS(parms);
 506 }
 507
 508 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 509 {
 510         struct dwc3_hwparams    *parms = &dwc->hwparams;
 511
 512         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 513         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 514         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 515         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 516         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 517         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 518         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 519         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 520         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 521 }
 522
 523 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 524 {
 525         int intf;
 526         int ret = 0;
 527
 528         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 529
 530         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 531             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 532              dwc->hsphy_interface &&
 533              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 534                 ret = dwc3_ulpi_init(dwc);
 535
 536         return ret;
 537 }
 538
 539 /**
 540  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 541  * @dwc: Pointer to our controller context structure
 542  *
 543  * Returns 0 on success. The USB PHY interfaces are configured but not
 544  * initialized. The PHY interfaces and the PHYs get initialized together with
 545  * the core in dwc3_core_init.
 546  */
 547 static int dwc3_phy_setup(struct dwc3 *dwc)
 548 {
 549         u32 reg;
 550
 551         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 552
 553         /*
 554          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 555          * PHYs. Also, this bit is not supposed to be used in normal operation.
 556          */
 557         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 558
 559         /*
 560          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 561          * to '0' during coreConsultant configuration. So default value
 562          * will be '0' when the core is reset. Application needs to set it
 563          * to '1' after the core initialization is completed.
 564          */
 565         if (dwc->revision > DWC3_REVISION_194A)
 566                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 567
 568         if (dwc->u2ss_inp3_quirk)
 569                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 570
 571         if (dwc->dis_rxdet_inp3_quirk)
 572                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 573
 574         if (dwc->req_p1p2p3_quirk)
 575                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 576
 577         if (dwc->del_p1p2p3_quirk)
 578                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 579
 580         if (dwc->del_phy_power_chg_quirk)
 581                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 582
 583         if (dwc->lfps_filter_quirk)
 584                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 585
 586         if (dwc->rx_detect_poll_quirk)
 587                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 588
 589         if (dwc->tx_de_emphasis_quirk)
 590                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 591
 592         if (dwc->dis_u3_susphy_quirk)
 593                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 594
 595         if (dwc->dis_del_phy_power_chg_quirk)
 596                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 597
 598         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 599
 600         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 601
 602         /* Select the HS PHY interface */
 603         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 604         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 605                 if (dwc->hsphy_interface &&
 606                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 607                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 608                         break;
 609                 } else if (dwc->hsphy_interface &&
 610                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 611                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 612                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 613                 } else {
 614                         /* Relying on default value. */
 615                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 616                                 break;
 617                 }
 618                 /* FALLTHROUGH */
 619         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 620                 /* FALLTHROUGH */
 621         default:
 622                 break;
 623         }
 624
 625         switch (dwc->hsphy_mode) {
 626         case USBPHY_INTERFACE_MODE_UTMI:
 627                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 628                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 629                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 630                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 631                 break;
 632         case USBPHY_INTERFACE_MODE_UTMIW:
 633                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 634                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 635                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 636                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 637                 break;
 638         default:
 639                 break;
 640         }
 641
 642         /*
 643          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 644          * '0' during coreConsultant configuration. So default value will
 645          * be '0' when the core is reset. Application needs to set it to
 646          * '1' after the core initialization is completed.
 647          */
 648         if (dwc->revision > DWC3_REVISION_194A)
 649                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 650
 651         if (dwc->dis_u2_susphy_quirk)
 652                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 653
 654         if (dwc->dis_enblslpm_quirk)
 655                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 656
 657         if (dwc->dis_u2_freeclk_exists_quirk)
 658                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 659
 660         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 661
 662         return 0;
 663 }
 664
 665 static void dwc3_core_exit(struct dwc3 *dwc)
 666 {
 667         dwc3_event_buffers_cleanup(dwc);
 668
 669         usb_phy_shutdown(dwc->usb2_phy);
 670         usb_phy_shutdown(dwc->usb3_phy);
 671         phy_exit(dwc->usb2_generic_phy);
 672         phy_exit(dwc->usb3_generic_phy);
 673
 674         usb_phy_set_suspend(dwc->usb2_phy, 1);
 675         usb_phy_set_suspend(dwc->usb3_phy, 1);
 676         phy_power_off(dwc->usb2_generic_phy);
 677         phy_power_off(dwc->usb3_generic_phy);
 678         clk_bulk_disable(dwc->num_clks, dwc->clks);
 679         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
 680         reset_control_assert(dwc->reset);
 681 }
 682
 683 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 684 {
 685         u32 reg;
 686
 687         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 688
 689         /* This should read as U3 followed by revision number */
 690         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 691                 /* Detected DWC_usb3 IP */
 692                 dwc->revision = reg;
 693         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 694                 /* Detected DWC_usb31 IP */
 695                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 696                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 697         } else {
 698                 return false;
 699         }
 700
 701         return true;
 702 }
 703
 704 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 705 {
 706         u32 hwparams4 = dwc->hwparams.hwparams4;
 707         u32 reg;
 708
 709         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 710         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 711
 712         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 713         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 714                 /**
 715                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 716                  * issue which would cause xHCI compliance tests to fail.
 717                  *
 718                  * Because of that we cannot enable clock gating on such
 719                  * configurations.
 720                  *
 721                  * Refers to:
 722                  *
 723                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 724                  * SOF/ITP Mode Used
 725                  */
 726                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 727                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 728                                 (dwc->revision >= DWC3_REVISION_210A &&
 729                                 dwc->revision <= DWC3_REVISION_250A))
 730                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 731                 else
 732                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 733                 break;
 734         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 735                 /* enable hibernation here */
 736                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 737
 738                 /*
 739                  * REVISIT Enabling this bit so that host-mode hibernation
 740                  * will work. Device-mode hibernation is not yet implemented.
 741                  */
 742                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 743                 break;
 744         default:
 745                 /* nothing */
 746                 break;
 747         }
 748
 749         /* check if current dwc3 is on simulation board */
 750         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 751                 dev_info(dwc->dev, "Running with FPGA optmizations\n");
 752                 dwc->is_fpga = true;
 753         }
 754
 755         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 756                         "disable_scramble cannot be used on non-FPGA builds\n");
 757
 758         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 759                 reg |= DWC3_GCTL_DISSCRAMBLE;
 760         else
 761                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 762
 763         if (dwc->u2exit_lfps_quirk)
 764                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 765
 766         /*
 767          * WORKAROUND: DWC3 revisions <1.90a have a bug
 768          * where the device can fail to connect at SuperSpeed
 769          * and falls back to high-speed mode which causes
 770          * the device to enter a Connect/Disconnect loop
 771          */
 772         if (dwc->revision < DWC3_REVISION_190A)
 773                 reg |= DWC3_GCTL_U2RSTECN;
 774
 775         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 776 }
 777
 778 static int dwc3_core_get_phy(struct dwc3 *dwc);
 779 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 780
 781 /**
 782  * dwc3_core_init - Low-level initialization of DWC3 Core
 783  * @dwc: Pointer to our controller context structure
 784  *
 785  * Returns 0 on success otherwise negative errno.
 786  */
 787 static int dwc3_core_init(struct dwc3 *dwc)
 788 {
 789         u32                     reg;
 790         int                     ret;
 791
 792         if (!dwc3_core_is_valid(dwc)) {
 793                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 794                 ret = -ENODEV;
 795                 goto err0;
 796         }
 797
 798         /*
 799          * Write Linux Version Code to our GUID register so it's easy to figure
 800          * out which kernel version a bug was found.
 801          */
 802         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 803
 804         /* Handle USB2.0-only core configuration */
 805         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 806                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 807                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 808                         dwc->maximum_speed = USB_SPEED_HIGH;
 809         }
 810
 811         ret = dwc3_phy_setup(dwc);
 812         if (ret)
 813                 goto err0;
 814
 815         if (!dwc->ulpi_ready) {
 816                 ret = dwc3_core_ulpi_init(dwc);
 817                 if (ret)
 818                         goto err0;
 819                 dwc->ulpi_ready = true;
 820         }
 821
 822         if (!dwc->phys_ready) {
 823                 ret = dwc3_core_get_phy(dwc);
 824                 if (ret)
 825                         goto err0a;
 826                 dwc->phys_ready = true;
 827         }
 828
 829         ret = dwc3_core_soft_reset(dwc);
 830         if (ret)
 831                 goto err0a;
 832
 833         dwc3_core_setup_global_control(dwc);
 834         dwc3_core_num_eps(dwc);
 835
 836         ret = dwc3_setup_scratch_buffers(dwc);
 837         if (ret)
 838                 goto err1;
 839
 840         /* Adjust Frame Length */
 841         dwc3_frame_length_adjustment(dwc);
 842
 843         usb_phy_set_suspend(dwc->usb2_phy, 0);
 844         usb_phy_set_suspend(dwc->usb3_phy, 0);
 845         ret = phy_power_on(dwc->usb2_generic_phy);
 846         if (ret < 0)
 847                 goto err2;
 848
 849         ret = phy_power_on(dwc->usb3_generic_phy);
 850         if (ret < 0)
 851                 goto err3;
 852
 853         ret = dwc3_event_buffers_setup(dwc);
 854         if (ret) {
 855                 dev_err(dwc->dev, "failed to setup event buffers\n");
 856                 goto err4;
 857         }
 858
 859         /*
 860          * ENDXFER polling is available on version 3.10a and later of
 861          * the DWC_usb3 controller. It is NOT available in the
 862          * DWC_usb31 controller.
 863          */
 864         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 865                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 866                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 867                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 868         }
 869
 870         if (dwc->revision >= DWC3_REVISION_250A) {
 871                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 872
 873                 /*
 874                  * Enable hardware control of sending remote wakeup
 875                  * in HS when the device is in the L1 state.
 876                  */
 877                 if (dwc->revision >= DWC3_REVISION_290A)
 878                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 879
 880                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 881                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 882
 883                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 884         }
 885
 886         /*
 887          * Must config both number of packets and max burst settings to enable
 888          * RX and/or TX threshold.
 889          */
 890         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
 891                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
 892                 u8 rx_maxburst = dwc->rx_max_burst_prd;
 893                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
 894                 u8 tx_maxburst = dwc->tx_max_burst_prd;
 895
 896                 if (rx_thr_num && rx_maxburst) {
 897                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
 898                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
 899
 900                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
 901                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
 902
 903                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
 904                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
 905
 906                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
 907                 }
 908
 909                 if (tx_thr_num && tx_maxburst) {
 910                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
 911                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
 912
 913                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
 914                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
 915
 916                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
 917                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
 918
 919                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
 920                 }
 921         }
 922
 923         return 0;
 924
 925 err4:
 926         phy_power_off(dwc->usb3_generic_phy);
 927
 928 err3:
 929         phy_power_off(dwc->usb2_generic_phy);
 930
 931 err2:
 932         usb_phy_set_suspend(dwc->usb2_phy, 1);
 933         usb_phy_set_suspend(dwc->usb3_phy, 1);
 934
 935 err1:
 936         usb_phy_shutdown(dwc->usb2_phy);
 937         usb_phy_shutdown(dwc->usb3_phy);
 938         phy_exit(dwc->usb2_generic_phy);
 939         phy_exit(dwc->usb3_generic_phy);
 940
 941 err0a:
 942         dwc3_ulpi_exit(dwc);
 943
 944 err0:
 945         return ret;
 946 }
 947
 948 static int dwc3_core_get_phy(struct dwc3 *dwc)
 949 {
 950         struct device           *dev = dwc->dev;
 951         struct device_node      *node = dev->of_node;
 952         int ret;
 953
 954         if (node) {
 955                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 956                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 957         } else {
 958                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 959                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 960         }
 961
 962         if (IS_ERR(dwc->usb2_phy)) {
 963                 ret = PTR_ERR(dwc->usb2_phy);
 964                 if (ret == -ENXIO || ret == -ENODEV) {
 965                         dwc->usb2_phy = NULL;
 966                 } else if (ret == -EPROBE_DEFER) {
 967                         return ret;
 968                 } else {
 969                         dev_err(dev, "no usb2 phy configured\n");
 970                         return ret;
 971                 }
 972         }
 973
 974         if (IS_ERR(dwc->usb3_phy)) {
 975                 ret = PTR_ERR(dwc->usb3_phy);
 976                 if (ret == -ENXIO || ret == -ENODEV) {
 977                         dwc->usb3_phy = NULL;
 978                 } else if (ret == -EPROBE_DEFER) {
 979                         return ret;
 980                 } else {
 981                         dev_err(dev, "no usb3 phy configured\n");
 982                         return ret;
 983                 }
 984         }
 985
 986         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 987         if (IS_ERR(dwc->usb2_generic_phy)) {
 988                 ret = PTR_ERR(dwc->usb2_generic_phy);
 989                 if (ret == -ENOSYS || ret == -ENODEV) {
 990                         dwc->usb2_generic_phy = NULL;
 991                 } else if (ret == -EPROBE_DEFER) {
 992                         return ret;
 993                 } else {
 994                         dev_err(dev, "no usb2 phy configured\n");
 995                         return ret;
 996                 }
 997         }
 998
 999         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1000         if (IS_ERR(dwc->usb3_generic_phy)) {
1001                 ret = PTR_ERR(dwc->usb3_generic_phy);
1002                 if (ret == -ENOSYS || ret == -ENODEV) {
1003                         dwc->usb3_generic_phy = NULL;
1004                 } else if (ret == -EPROBE_DEFER) {
1005                         return ret;
1006                 } else {
1007                         dev_err(dev, "no usb3 phy configured\n");
1008                         return ret;
1009                 }
1010         }
1011
1012         return 0;
1013 }
1014
1015 static int dwc3_core_init_mode(struct dwc3 *dwc)
1016 {
1017         struct device *dev = dwc->dev;
1018         int ret;
1019
1020         switch (dwc->dr_mode) {
1021         case USB_DR_MODE_PERIPHERAL:
1022                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1023
1024                 if (dwc->usb2_phy)
1025                         otg_set_vbus(dwc->usb2_phy->otg, false);
1026                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1027                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1028
1029                 ret = dwc3_gadget_init(dwc);
1030                 if (ret) {
1031                         if (ret != -EPROBE_DEFER)
1032                                 dev_err(dev, "failed to initialize gadget\n");
1033                         return ret;
1034                 }
1035                 break;
1036         case USB_DR_MODE_HOST:
1037                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1038
1039                 if (dwc->usb2_phy)
1040                         otg_set_vbus(dwc->usb2_phy->otg, true);
1041                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1042                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1043
1044                 ret = dwc3_host_init(dwc);
1045                 if (ret) {
1046                         if (ret != -EPROBE_DEFER)
1047                                 dev_err(dev, "failed to initialize host\n");
1048                         return ret;
1049                 }
1050                 phy_calibrate(dwc->usb2_generic_phy);
1051                 break;
1052         case USB_DR_MODE_OTG:
1053                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1054                 ret = dwc3_drd_init(dwc);
1055                 if (ret) {
1056                         if (ret != -EPROBE_DEFER)
1057                                 dev_err(dev, "failed to initialize dual-role\n");
1058                         return ret;
1059                 }
1060                 break;
1061         default:
1062                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1063                 return -EINVAL;
1064         }
1065
1066         return 0;
1067 }
1068
1069 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1070 {
1071         switch (dwc->dr_mode) {
1072         case USB_DR_MODE_PERIPHERAL:
1073                 dwc3_gadget_exit(dwc);
1074                 break;
1075         case USB_DR_MODE_HOST:
1076                 dwc3_host_exit(dwc);
1077                 break;
1078         case USB_DR_MODE_OTG:
1079                 dwc3_drd_exit(dwc);
1080                 break;
1081         default:
1082                 /* do nothing */
1083                 break;
1084         }
1085 }
1086
1087 static void dwc3_get_properties(struct dwc3 *dwc)
1088 {
1089         struct device           *dev = dwc->dev;
1090         u8                      lpm_nyet_threshold;
1091         u8                      tx_de_emphasis;
1092         u8                      hird_threshold;
1093         u8                      rx_thr_num_pkt_prd;
1094         u8                      rx_max_burst_prd;
1095         u8                      tx_thr_num_pkt_prd;
1096         u8                      tx_max_burst_prd;
1097
1098         /* default to highest possible threshold */
1099         lpm_nyet_threshold = 0xff;
1100
1101         /* default to -3.5dB de-emphasis */
1102         tx_de_emphasis = 1;
1103
1104         /*
1105          * default to assert utmi_sleep_n and use maximum allowed HIRD
1106          * threshold value of 0b1100
1107          */
1108         hird_threshold = 12;
1109
1110         dwc->maximum_speed = usb_get_maximum_speed(dev);
1111         dwc->dr_mode = usb_get_dr_mode(dev);
1112         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1113
1114         dwc->sysdev_is_parent = device_property_read_bool(dev,
1115                                 "linux,sysdev_is_parent");
1116         if (dwc->sysdev_is_parent)
1117                 dwc->sysdev = dwc->dev->parent;
1118         else
1119                 dwc->sysdev = dwc->dev;
1120
1121         dwc->has_lpm_erratum = device_property_read_bool(dev,
1122                                 "snps,has-lpm-erratum");
1123         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1124                                 &lpm_nyet_threshold);
1125         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1126                                 "snps,is-utmi-l1-suspend");
1127         device_property_read_u8(dev, "snps,hird-threshold",
1128                                 &hird_threshold);
1129         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1130                                 "snps,usb3_lpm_capable");
1131         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1132                                 &rx_thr_num_pkt_prd);
1133         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1134                                 &rx_max_burst_prd);
1135         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1136                                 &tx_thr_num_pkt_prd);
1137         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1138                                 &tx_max_burst_prd);
1139
1140         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1141                                 "snps,disable_scramble_quirk");
1142         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1143                                 "snps,u2exit_lfps_quirk");
1144         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1145                                 "snps,u2ss_inp3_quirk");
1146         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1147                                 "snps,req_p1p2p3_quirk");
1148         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1149                                 "snps,del_p1p2p3_quirk");
1150         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1151                                 "snps,del_phy_power_chg_quirk");
1152         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1153                                 "snps,lfps_filter_quirk");
1154         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1155                                 "snps,rx_detect_poll_quirk");
1156         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1157                                 "snps,dis_u3_susphy_quirk");
1158         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1159                                 "snps,dis_u2_susphy_quirk");
1160         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1161                                 "snps,dis_enblslpm_quirk");
1162         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1163                                 "snps,dis_rxdet_inp3_quirk");
1164         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1165                                 "snps,dis-u2-freeclk-exists-quirk");
1166         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1167                                 "snps,dis-del-phy-power-chg-quirk");
1168         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1169                                 "snps,dis-tx-ipgap-linecheck-quirk");
1170
1171         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1172                                 "snps,tx_de_emphasis_quirk");
1173         device_property_read_u8(dev, "snps,tx_de_emphasis",
1174                                 &tx_de_emphasis);
1175         device_property_read_string(dev, "snps,hsphy_interface",
1176                                     &dwc->hsphy_interface);
1177         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1178                                  &dwc->fladj);
1179
1180         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1181                                 "snps,dis_metastability_quirk");
1182
1183         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1184         dwc->tx_de_emphasis = tx_de_emphasis;
1185
1186         dwc->hird_threshold = hird_threshold
1187                 | (dwc->is_utmi_l1_suspend << 4);
1188
1189         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1190         dwc->rx_max_burst_prd = rx_max_burst_prd;
1191
1192         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1193         dwc->tx_max_burst_prd = tx_max_burst_prd;
1194
1195         dwc->imod_interval = 0;
1196 }
1197
1198 /* check whether the core supports IMOD */
1199 bool dwc3_has_imod(struct dwc3 *dwc)
1200 {
1201         return ((dwc3_is_usb3(dwc) &&
1202                  dwc->revision >= DWC3_REVISION_300A) ||
1203                 (dwc3_is_usb31(dwc) &&
1204                  dwc->revision >= DWC3_USB31_REVISION_120A));
1205 }
1206
1207 static void dwc3_check_params(struct dwc3 *dwc)
1208 {
1209         struct device *dev = dwc->dev;
1210
1211         /* Check for proper value of imod_interval */
1212         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1213                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1214                 dwc->imod_interval = 0;
1215         }
1216
1217         /*
1218          * Workaround for STAR 9000961433 which affects only version
1219          * 3.00a of the DWC_usb3 core. This prevents the controller
1220          * interrupt from being masked while handling events. IMOD
1221          * allows us to work around this issue. Enable it for the
1222          * affected version.
1223          */
1224         if (!dwc->imod_interval &&
1225             (dwc->revision == DWC3_REVISION_300A))
1226                 dwc->imod_interval = 1;
1227
1228         /* Check the maximum_speed parameter */
1229         switch (dwc->maximum_speed) {
1230         case USB_SPEED_LOW:
1231         case USB_SPEED_FULL:
1232         case USB_SPEED_HIGH:
1233         case USB_SPEED_SUPER:
1234         case USB_SPEED_SUPER_PLUS:
1235                 break;
1236         default:
1237                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1238                         dwc->maximum_speed);
1239                 /* fall through */
1240         case USB_SPEED_UNKNOWN:
1241                 /* default to superspeed */
1242                 dwc->maximum_speed = USB_SPEED_SUPER;
1243
1244                 /*
1245                  * default to superspeed plus if we are capable.
1246                  */
1247                 if (dwc3_is_usb31(dwc) &&
1248                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1249                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1250                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1251
1252                 break;
1253         }
1254 }
1255
1256 static int dwc3_probe(struct platform_device *pdev)
1257 {
1258         struct device           *dev = &pdev->dev;
1259         struct resource         *res, dwc_res;
1260         struct dwc3             *dwc;
1261
1262         int                     ret;
1263
1264         void __iomem            *regs;
1265
1266         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1267         if (!dwc)
1268                 return -ENOMEM;
1269
1270         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1271                                  GFP_KERNEL);
1272         if (!dwc->clks)
1273                 return -ENOMEM;
1274
1275         dwc->dev = dev;
1276
1277         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1278         if (!res) {
1279                 dev_err(dev, "missing memory resource\n");
1280                 return -ENODEV;
1281         }
1282
1283         dwc->xhci_resources[0].start = res->start;
1284         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1285                                         DWC3_XHCI_REGS_END;
1286         dwc->xhci_resources[0].flags = res->flags;
1287         dwc->xhci_resources[0].name = res->name;
1288
1289         /*
1290          * Request memory region but exclude xHCI regs,
1291          * since it will be requested by the xhci-plat driver.
1292          */
1293         dwc_res = *res;
1294         dwc_res.start += DWC3_GLOBALS_REGS_START;
1295
1296         regs = devm_ioremap_resource(dev, &dwc_res);
1297         if (IS_ERR(regs))
1298                 return PTR_ERR(regs);
1299
1300         dwc->regs       = regs;
1301         dwc->regs_size  = resource_size(&dwc_res);
1302
1303         dwc3_get_properties(dwc);
1304
1305         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1306         if (IS_ERR(dwc->reset))
1307                 return PTR_ERR(dwc->reset);
1308
1309         if (dev->of_node) {
1310                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1311
1312                 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1313                 if (ret == -EPROBE_DEFER)
1314                         return ret;
1315                 /*
1316                  * Clocks are optional, but new DT platforms should support all
1317                  * clocks as required by the DT-binding.
1318                  */
1319                 if (ret)
1320                         dwc->num_clks = 0;
1321         }
1322
1323         ret = reset_control_deassert(dwc->reset);
1324         if (ret)
1325                 goto put_clks;
1326
1327         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1328         if (ret)
1329                 goto assert_reset;
1330
1331         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1332         if (ret)
1333                 goto unprepare_clks;
1334
1335         platform_set_drvdata(pdev, dwc);
1336         dwc3_cache_hwparams(dwc);
1337
1338         spin_lock_init(&dwc->lock);
1339
1340         pm_runtime_set_active(dev);
1341         pm_runtime_use_autosuspend(dev);
1342         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1343         pm_runtime_enable(dev);
1344         ret = pm_runtime_get_sync(dev);
1345         if (ret < 0)
1346                 goto err1;
1347
1348         pm_runtime_forbid(dev);
1349
1350         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1351         if (ret) {
1352                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1353                 ret = -ENOMEM;
1354                 goto err2;
1355         }
1356
1357         ret = dwc3_get_dr_mode(dwc);
1358         if (ret)
1359                 goto err3;
1360
1361         ret = dwc3_alloc_scratch_buffers(dwc);
1362         if (ret)
1363                 goto err3;
1364
1365         ret = dwc3_core_init(dwc);
1366         if (ret) {
1367                 dev_err(dev, "failed to initialize core\n");
1368                 goto err4;
1369         }
1370
1371         dwc3_check_params(dwc);
1372
1373         ret = dwc3_core_init_mode(dwc);
1374         if (ret)
1375                 goto err5;
1376
1377         dwc3_debugfs_init(dwc);
1378         pm_runtime_put(dev);
1379
1380         return 0;
1381
1382 err5:
1383         dwc3_event_buffers_cleanup(dwc);
1384
1385 err4:
1386         dwc3_free_scratch_buffers(dwc);
1387
1388 err3:
1389         dwc3_free_event_buffers(dwc);
1390
1391 err2:
1392         pm_runtime_allow(&pdev->dev);
1393
1394 err1:
1395         pm_runtime_put_sync(&pdev->dev);
1396         pm_runtime_disable(&pdev->dev);
1397
1398         clk_bulk_disable(dwc->num_clks, dwc->clks);
1399 unprepare_clks:
1400         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1401 assert_reset:
1402         reset_control_assert(dwc->reset);
1403 put_clks:
1404         clk_bulk_put(dwc->num_clks, dwc->clks);
1405
1406         return ret;
1407 }
1408
1409 static int dwc3_remove(struct platform_device *pdev)
1410 {
1411         struct dwc3     *dwc = platform_get_drvdata(pdev);
1412
1413         pm_runtime_get_sync(&pdev->dev);
1414
1415         dwc3_debugfs_exit(dwc);
1416         dwc3_core_exit_mode(dwc);
1417
1418         dwc3_core_exit(dwc);
1419         dwc3_ulpi_exit(dwc);
1420
1421         pm_runtime_put_sync(&pdev->dev);
1422         pm_runtime_allow(&pdev->dev);
1423         pm_runtime_disable(&pdev->dev);
1424
1425         dwc3_free_event_buffers(dwc);
1426         dwc3_free_scratch_buffers(dwc);
1427         clk_bulk_put(dwc->num_clks, dwc->clks);
1428
1429         return 0;
1430 }
1431
1432 #ifdef CONFIG_PM
1433 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1434 {
1435         int ret;
1436
1437         ret = reset_control_deassert(dwc->reset);
1438         if (ret)
1439                 return ret;
1440
1441         ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1442         if (ret)
1443                 goto assert_reset;
1444
1445         ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1446         if (ret)
1447                 goto unprepare_clks;
1448
1449         ret = dwc3_core_init(dwc);
1450         if (ret)
1451                 goto disable_clks;
1452
1453         return 0;
1454
1455 disable_clks:
1456         clk_bulk_disable(dwc->num_clks, dwc->clks);
1457 unprepare_clks:
1458         clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1459 assert_reset:
1460         reset_control_assert(dwc->reset);
1461
1462         return ret;
1463 }
1464
1465 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1466 {
1467         unsigned long   flags;
1468         u32 reg;
1469
1470         switch (dwc->current_dr_role) {
1471         case DWC3_GCTL_PRTCAP_DEVICE:
1472                 spin_lock_irqsave(&dwc->lock, flags);
1473                 dwc3_gadget_suspend(dwc);
1474                 spin_unlock_irqrestore(&dwc->lock, flags);
1475                 dwc3_core_exit(dwc);
1476                 break;
1477         case DWC3_GCTL_PRTCAP_HOST:
1478                 if (!PMSG_IS_AUTO(msg)) {
1479                         dwc3_core_exit(dwc);
1480                         break;
1481                 }
1482
1483                 /* Let controller to suspend HSPHY before PHY driver suspends */
1484                 if (dwc->dis_u2_susphy_quirk ||
1485                     dwc->dis_enblslpm_quirk) {
1486                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1487                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1488                                 DWC3_GUSB2PHYCFG_SUSPHY;
1489                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1490
1491                         /* Give some time for USB2 PHY to suspend */
1492                         usleep_range(5000, 6000);
1493                 }
1494
1495                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1496                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1497                 break;
1498         case DWC3_GCTL_PRTCAP_OTG:
1499                 /* do nothing during runtime_suspend */
1500                 if (PMSG_IS_AUTO(msg))
1501                         break;
1502
1503                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1504                         spin_lock_irqsave(&dwc->lock, flags);
1505                         dwc3_gadget_suspend(dwc);
1506                         spin_unlock_irqrestore(&dwc->lock, flags);
1507                 }
1508
1509                 dwc3_otg_exit(dwc);
1510                 dwc3_core_exit(dwc);
1511                 break;
1512         default:
1513                 /* do nothing */
1514                 break;
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1521 {
1522         unsigned long   flags;
1523         int             ret;
1524         u32             reg;
1525
1526         switch (dwc->current_dr_role) {
1527         case DWC3_GCTL_PRTCAP_DEVICE:
1528                 ret = dwc3_core_init_for_resume(dwc);
1529                 if (ret)
1530                         return ret;
1531
1532                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1533                 spin_lock_irqsave(&dwc->lock, flags);
1534                 dwc3_gadget_resume(dwc);
1535                 spin_unlock_irqrestore(&dwc->lock, flags);
1536                 break;
1537         case DWC3_GCTL_PRTCAP_HOST:
1538                 if (!PMSG_IS_AUTO(msg)) {
1539                         ret = dwc3_core_init_for_resume(dwc);
1540                         if (ret)
1541                                 return ret;
1542                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1543                         break;
1544                 }
1545                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1546                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1547                 if (dwc->dis_u2_susphy_quirk)
1548                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1549
1550                 if (dwc->dis_enblslpm_quirk)
1551                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1552
1553                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1554
1555                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1556                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1557                 break;
1558         case DWC3_GCTL_PRTCAP_OTG:
1559                 /* nothing to do on runtime_resume */
1560                 if (PMSG_IS_AUTO(msg))
1561                         break;
1562
1563                 ret = dwc3_core_init(dwc);
1564                 if (ret)
1565                         return ret;
1566
1567                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1568
1569                 dwc3_otg_init(dwc);
1570                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1571                         dwc3_otg_host_init(dwc);
1572                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1573                         spin_lock_irqsave(&dwc->lock, flags);
1574                         dwc3_gadget_resume(dwc);
1575                         spin_unlock_irqrestore(&dwc->lock, flags);
1576                 }
1577
1578                 break;
1579         default:
1580                 /* do nothing */
1581                 break;
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int dwc3_runtime_checks(struct dwc3 *dwc)
1588 {
1589         switch (dwc->current_dr_role) {
1590         case DWC3_GCTL_PRTCAP_DEVICE:
1591                 if (dwc->connected)
1592                         return -EBUSY;
1593                 break;
1594         case DWC3_GCTL_PRTCAP_HOST:
1595         default:
1596                 /* do nothing */
1597                 break;
1598         }
1599
1600         return 0;
1601 }
1602
1603 static int dwc3_runtime_suspend(struct device *dev)
1604 {
1605         struct dwc3     *dwc = dev_get_drvdata(dev);
1606         int             ret;
1607
1608         if (dwc3_runtime_checks(dwc))
1609                 return -EBUSY;
1610
1611         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1612         if (ret)
1613                 return ret;
1614
1615         device_init_wakeup(dev, true);
1616
1617         return 0;
1618 }
1619
1620 static int dwc3_runtime_resume(struct device *dev)
1621 {
1622         struct dwc3     *dwc = dev_get_drvdata(dev);
1623         int             ret;
1624
1625         device_init_wakeup(dev, false);
1626
1627         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1628         if (ret)
1629                 return ret;
1630
1631         switch (dwc->current_dr_role) {
1632         case DWC3_GCTL_PRTCAP_DEVICE:
1633                 dwc3_gadget_process_pending_events(dwc);
1634                 break;
1635         case DWC3_GCTL_PRTCAP_HOST:
1636         default:
1637                 /* do nothing */
1638                 break;
1639         }
1640
1641         pm_runtime_mark_last_busy(dev);
1642
1643         return 0;
1644 }
1645
1646 static int dwc3_runtime_idle(struct device *dev)
1647 {
1648         struct dwc3     *dwc = dev_get_drvdata(dev);
1649
1650         switch (dwc->current_dr_role) {
1651         case DWC3_GCTL_PRTCAP_DEVICE:
1652                 if (dwc3_runtime_checks(dwc))
1653                         return -EBUSY;
1654                 break;
1655         case DWC3_GCTL_PRTCAP_HOST:
1656         default:
1657                 /* do nothing */
1658                 break;
1659         }
1660
1661         pm_runtime_mark_last_busy(dev);
1662         pm_runtime_autosuspend(dev);
1663
1664         return 0;
1665 }
1666 #endif /* CONFIG_PM */
1667
1668 #ifdef CONFIG_PM_SLEEP
1669 static int dwc3_suspend(struct device *dev)
1670 {
1671         struct dwc3     *dwc = dev_get_drvdata(dev);
1672         int             ret;
1673
1674         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1675         if (ret)
1676                 return ret;
1677
1678         pinctrl_pm_select_sleep_state(dev);
1679
1680         return 0;
1681 }
1682
1683 static int dwc3_resume(struct device *dev)
1684 {
1685         struct dwc3     *dwc = dev_get_drvdata(dev);
1686         int             ret;
1687
1688         pinctrl_pm_select_default_state(dev);
1689
1690         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1691         if (ret)
1692                 return ret;
1693
1694         pm_runtime_disable(dev);
1695         pm_runtime_set_active(dev);
1696         pm_runtime_enable(dev);
1697
1698         return 0;
1699 }
1700 #endif /* CONFIG_PM_SLEEP */
1701
1702 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1703         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1704         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1705                         dwc3_runtime_idle)
1706 };
1707
1708 #ifdef CONFIG_OF
1709 static const struct of_device_id of_dwc3_match[] = {
1710         {
1711                 .compatible = "snps,dwc3"
1712         },
1713         {
1714                 .compatible = "synopsys,dwc3"
1715         },
1716         { },
1717 };
1718 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1719 #endif
1720
1721 #ifdef CONFIG_ACPI
1722
1723 #define ACPI_ID_INTEL_BSW       "808622B7"
1724
1725 static const struct acpi_device_id dwc3_acpi_match[] = {
1726         { ACPI_ID_INTEL_BSW, 0 },
1727         { },
1728 };
1729 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1730 #endif
1731
1732 static struct platform_driver dwc3_driver = {
1733         .probe          = dwc3_probe,
1734         .remove         = dwc3_remove,
1735         .driver         = {
1736                 .name   = "dwc3",
1737                 .of_match_table = of_match_ptr(of_dwc3_match),
1738                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1739                 .pm     = &dwc3_dev_pm_ops,
1740         },
1741 };
1742
1743 module_platform_driver(dwc3_driver);
1744
1745 MODULE_ALIAS("platform:dwc3");
1746 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1747 MODULE_LICENSE("GPL v2");
1748 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");