2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - enables usb2 test modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will return 0 on
44 * success or -EINVAL if wrong Test Selector is passed.
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
71 * dwc3_gadget_get_link_state - gets current state of usb link
72 * @dwc: pointer to our context structure
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83 return DWC3_DSTS_USBLNKST(reg);
87 * dwc3_gadget_set_link_state - sets usb link to a particular state
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
100 * Wait until device controller is ready. Only applies to 1.94a and
103 if (dwc->revision >= DWC3_REVISION_194A) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
127 if (dwc->revision >= DWC3_REVISION_194A)
130 /* wait for a change in DSTS */
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135 if (DWC3_DSTS_USBLNKST(reg) == state)
145 * dwc3_ep_inc_trb - increment a trb index.
146 * @index: Pointer to the TRB index to increment.
148 * The index should never point to the link TRB. After incrementing,
149 * if it is point to the link TRB, wrap around to the beginning. The
150 * link TRB is always at the last TRB entry.
152 static void dwc3_ep_inc_trb(u8 *index)
155 if (*index == (DWC3_TRB_NUM - 1))
160 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
161 * @dep: The endpoint whose enqueue pointer we're incrementing
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
169 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
170 * @dep: The endpoint whose enqueue pointer we're incrementing
172 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
174 dwc3_ep_inc_trb(&dep->trb_dequeue);
178 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
179 * @dep: The endpoint to whom the request belongs to
180 * @req: The request we're giving back
181 * @status: completion code for the request
183 * Must be called with controller's lock held and interrupts disabled. This
184 * function will unmap @req and call its ->complete() callback to notify upper
185 * layers that it has completed.
187 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
190 struct dwc3 *dwc = dep->dwc;
192 req->started = false;
193 list_del(&req->list);
196 if (req->request.status == -EINPROGRESS)
197 req->request.status = status;
200 usb_gadget_unmap_request_by_dev(dwc->sysdev,
201 &req->request, req->direction);
205 trace_dwc3_gadget_giveback(req);
207 spin_unlock(&dwc->lock);
208 usb_gadget_giveback_request(&dep->endpoint, &req->request);
209 spin_lock(&dwc->lock);
212 pm_runtime_put(dwc->dev);
216 * dwc3_send_gadget_generic_command - issue a generic command for the controller
217 * @dwc: pointer to the controller context
218 * @cmd: the command to be issued
219 * @param: command parameter
221 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
222 * and wait for its completion.
224 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
231 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
232 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
235 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
236 if (!(reg & DWC3_DGCMD_CMDACT)) {
237 status = DWC3_DGCMD_STATUS(reg);
249 trace_dwc3_gadget_generic_cmd(cmd, param, status);
254 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
257 * dwc3_send_gadget_ep_cmd - issue an endpoint command
258 * @dep: the endpoint to which the command is going to be issued
259 * @cmd: the command to be issued
260 * @params: parameters to the command
262 * Caller should handle locking. This function will issue @cmd with given
263 * @params to @dep and wait for its completion.
265 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
266 struct dwc3_gadget_ep_cmd_params *params)
268 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
269 struct dwc3 *dwc = dep->dwc;
278 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
279 * we're issuing an endpoint command, we must check if
280 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
282 * We will also set SUSPHY bit to what it was before returning as stated
283 * by the same section on Synopsys databook.
285 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
286 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
287 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
289 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
290 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
294 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
297 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
298 dwc->link_state == DWC3_LINK_STATE_U2 ||
299 dwc->link_state == DWC3_LINK_STATE_U3);
301 if (unlikely(needs_wakeup)) {
302 ret = __dwc3_gadget_wakeup(dwc);
303 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
308 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
309 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
310 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
313 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
314 * not relying on XferNotReady, we can make use of a special "No
315 * Response Update Transfer" command where we should clear both CmdAct
318 * With this, we don't need to wait for command completion and can
319 * straight away issue further commands to the endpoint.
321 * NOTICE: We're making an assumption that control endpoints will never
322 * make use of Update Transfer command. This is a safe assumption
323 * because we can never have more than one request at a time with
324 * Control Endpoints. If anybody changes that assumption, this chunk
325 * needs to be updated accordingly.
327 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
328 !usb_endpoint_xfer_isoc(desc))
329 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
331 cmd |= DWC3_DEPCMD_CMDACT;
333 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
335 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
336 if (!(reg & DWC3_DEPCMD_CMDACT)) {
337 cmd_status = DWC3_DEPCMD_STATUS(reg);
339 switch (cmd_status) {
343 case DEPEVT_TRANSFER_NO_RESOURCE:
346 case DEPEVT_TRANSFER_BUS_EXPIRY:
348 * SW issues START TRANSFER command to
349 * isochronous ep with future frame interval. If
350 * future interval time has already passed when
351 * core receives the command, it will respond
352 * with an error status of 'Bus Expiry'.
354 * Instead of always returning -EINVAL, let's
355 * give a hint to the gadget driver that this is
356 * the case by returning -EAGAIN.
361 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
370 cmd_status = -ETIMEDOUT;
373 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
376 switch (DWC3_DEPCMD_CMD(cmd)) {
377 case DWC3_DEPCMD_STARTTRANSFER:
378 dep->flags |= DWC3_EP_TRANSFER_STARTED;
380 case DWC3_DEPCMD_ENDTRANSFER:
381 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
389 if (unlikely(susphy)) {
390 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
391 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
392 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
398 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
400 struct dwc3 *dwc = dep->dwc;
401 struct dwc3_gadget_ep_cmd_params params;
402 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
405 * As of core revision 2.60a the recommended programming model
406 * is to set the ClearPendIN bit when issuing a Clear Stall EP
407 * command for IN endpoints. This is to prevent an issue where
408 * some (non-compliant) hosts may not send ACK TPs for pending
409 * IN transfers due to a mishandled error condition. Synopsys
412 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
413 (dwc->gadget.speed >= USB_SPEED_SUPER))
414 cmd |= DWC3_DEPCMD_CLEARPENDIN;
416 memset(¶ms, 0, sizeof(params));
418 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
421 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
422 struct dwc3_trb *trb)
424 u32 offset = (char *) trb - (char *) dep->trb_pool;
426 return dep->trb_pool_dma + offset;
429 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
431 struct dwc3 *dwc = dep->dwc;
436 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
437 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
438 &dep->trb_pool_dma, GFP_KERNEL);
439 if (!dep->trb_pool) {
440 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
448 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
450 struct dwc3 *dwc = dep->dwc;
452 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
453 dep->trb_pool, dep->trb_pool_dma);
455 dep->trb_pool = NULL;
456 dep->trb_pool_dma = 0;
459 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
462 * dwc3_gadget_start_config - configure ep resources
463 * @dwc: pointer to our controller context structure
464 * @dep: endpoint that is being enabled
466 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
467 * completion, it will set Transfer Resource for all available endpoints.
469 * The assignment of transfer resources cannot perfectly follow the data book
470 * due to the fact that the controller driver does not have all knowledge of the
471 * configuration in advance. It is given this information piecemeal by the
472 * composite gadget framework after every SET_CONFIGURATION and
473 * SET_INTERFACE. Trying to follow the databook programming model in this
474 * scenario can cause errors. For two reasons:
476 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
477 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
478 * incorrect in the scenario of multiple interfaces.
480 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
481 * endpoint on alt setting (8.1.6).
483 * The following simplified method is used instead:
485 * All hardware endpoints can be assigned a transfer resource and this setting
486 * will stay persistent until either a core reset or hibernation. So whenever we
487 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
488 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
489 * guaranteed that there are as many transfer resources as endpoints.
491 * This function is called for each endpoint when it is being enabled but is
492 * triggered only when called for EP0-out, which always happens first, and which
493 * should only happen in one of the above conditions.
495 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
497 struct dwc3_gadget_ep_cmd_params params;
505 memset(¶ms, 0x00, sizeof(params));
506 cmd = DWC3_DEPCMD_DEPSTARTCFG;
508 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
512 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
513 struct dwc3_ep *dep = dwc->eps[i];
518 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
526 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
527 bool modify, bool restore)
529 const struct usb_ss_ep_comp_descriptor *comp_desc;
530 const struct usb_endpoint_descriptor *desc;
531 struct dwc3_gadget_ep_cmd_params params;
533 if (dev_WARN_ONCE(dwc->dev, modify && restore,
534 "Can't modify and restore\n"))
537 comp_desc = dep->endpoint.comp_desc;
538 desc = dep->endpoint.desc;
540 memset(¶ms, 0x00, sizeof(params));
542 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
543 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
545 /* Burst size is only needed in SuperSpeed mode */
546 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
547 u32 burst = dep->endpoint.maxburst;
548 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
552 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
553 } else if (restore) {
554 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
555 params.param2 |= dep->saved_state;
557 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
560 if (usb_endpoint_xfer_control(desc))
561 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
563 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
564 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
566 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
567 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
568 | DWC3_DEPCFG_STREAM_EVENT_EN;
569 dep->stream_capable = true;
572 if (!usb_endpoint_xfer_control(desc))
573 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
576 * We are doing 1:1 mapping for endpoints, meaning
577 * Physical Endpoints 2 maps to Logical Endpoint 2 and
578 * so on. We consider the direction bit as part of the physical
579 * endpoint number. So USB endpoint 0x81 is 0x03.
581 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
584 * We must use the lower 16 TX FIFOs even though
588 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
590 if (desc->bInterval) {
591 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
592 dep->interval = 1 << (desc->bInterval - 1);
595 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
598 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
600 struct dwc3_gadget_ep_cmd_params params;
602 memset(¶ms, 0x00, sizeof(params));
604 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
606 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
611 * __dwc3_gadget_ep_enable - initializes a hw endpoint
612 * @dep: endpoint to be initialized
613 * @modify: if true, modify existing endpoint configuration
614 * @restore: if true, restore endpoint configuration from scratch buffer
616 * Caller should take care of locking. Execute all necessary commands to
617 * initialize a HW endpoint so it can be used by a gadget driver.
619 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
620 bool modify, bool restore)
622 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
623 struct dwc3 *dwc = dep->dwc;
628 if (!(dep->flags & DWC3_EP_ENABLED)) {
629 ret = dwc3_gadget_start_config(dwc, dep);
634 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
638 if (!(dep->flags & DWC3_EP_ENABLED)) {
639 struct dwc3_trb *trb_st_hw;
640 struct dwc3_trb *trb_link;
642 dep->type = usb_endpoint_type(desc);
643 dep->flags |= DWC3_EP_ENABLED;
644 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
646 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
647 reg |= DWC3_DALEPENA_EP(dep->number);
648 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
650 init_waitqueue_head(&dep->wait_end_transfer);
652 if (usb_endpoint_xfer_control(desc))
655 /* Initialize the TRB ring */
656 dep->trb_dequeue = 0;
657 dep->trb_enqueue = 0;
658 memset(dep->trb_pool, 0,
659 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
661 /* Link TRB. The HWO bit is never reset */
662 trb_st_hw = &dep->trb_pool[0];
664 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
665 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
666 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
667 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
668 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
672 * Issue StartTransfer here with no-op TRB so we can always rely on No
673 * Response Update Transfer command.
675 if (usb_endpoint_xfer_bulk(desc)) {
676 struct dwc3_gadget_ep_cmd_params params;
677 struct dwc3_trb *trb;
681 memset(¶ms, 0, sizeof(params));
682 trb = &dep->trb_pool[0];
683 trb_dma = dwc3_trb_dma_offset(dep, trb);
685 params.param0 = upper_32_bits(trb_dma);
686 params.param1 = lower_32_bits(trb_dma);
688 cmd = DWC3_DEPCMD_STARTTRANSFER;
690 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
694 dep->flags |= DWC3_EP_BUSY;
696 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
697 WARN_ON_ONCE(!dep->resource_index);
702 trace_dwc3_gadget_ep_enable(dep);
707 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
708 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
710 struct dwc3_request *req;
712 dwc3_stop_active_transfer(dwc, dep->number, true);
714 /* - giveback all requests to gadget driver */
715 while (!list_empty(&dep->started_list)) {
716 req = next_request(&dep->started_list);
718 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
721 while (!list_empty(&dep->pending_list)) {
722 req = next_request(&dep->pending_list);
724 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
729 * __dwc3_gadget_ep_disable - disables a hw endpoint
730 * @dep: the endpoint to disable
732 * This function undoes what __dwc3_gadget_ep_enable did and also removes
733 * requests which are currently being processed by the hardware and those which
734 * are not yet scheduled.
736 * Caller should take care of locking.
738 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
740 struct dwc3 *dwc = dep->dwc;
743 trace_dwc3_gadget_ep_disable(dep);
745 dwc3_remove_requests(dwc, dep);
747 /* make sure HW endpoint isn't stalled */
748 if (dep->flags & DWC3_EP_STALL)
749 __dwc3_gadget_ep_set_halt(dep, 0, false);
751 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
752 reg &= ~DWC3_DALEPENA_EP(dep->number);
753 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
755 dep->stream_capable = false;
757 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
759 /* Clear out the ep descriptors for non-ep0 */
760 if (dep->number > 1) {
761 dep->endpoint.comp_desc = NULL;
762 dep->endpoint.desc = NULL;
768 /* -------------------------------------------------------------------------- */
770 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
771 const struct usb_endpoint_descriptor *desc)
776 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
781 /* -------------------------------------------------------------------------- */
783 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
784 const struct usb_endpoint_descriptor *desc)
791 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
792 pr_debug("dwc3: invalid parameters\n");
796 if (!desc->wMaxPacketSize) {
797 pr_debug("dwc3: missing wMaxPacketSize\n");
801 dep = to_dwc3_ep(ep);
804 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
805 "%s is already enabled\n",
809 spin_lock_irqsave(&dwc->lock, flags);
810 ret = __dwc3_gadget_ep_enable(dep, false, false);
811 spin_unlock_irqrestore(&dwc->lock, flags);
816 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
824 pr_debug("dwc3: invalid parameters\n");
828 dep = to_dwc3_ep(ep);
831 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
832 "%s is already disabled\n",
836 spin_lock_irqsave(&dwc->lock, flags);
837 ret = __dwc3_gadget_ep_disable(dep);
838 spin_unlock_irqrestore(&dwc->lock, flags);
843 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
846 struct dwc3_request *req;
847 struct dwc3_ep *dep = to_dwc3_ep(ep);
849 req = kzalloc(sizeof(*req), gfp_flags);
853 req->epnum = dep->number;
856 dep->allocated_requests++;
858 trace_dwc3_alloc_request(req);
860 return &req->request;
863 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
864 struct usb_request *request)
866 struct dwc3_request *req = to_dwc3_request(request);
867 struct dwc3_ep *dep = to_dwc3_ep(ep);
869 dep->allocated_requests--;
870 trace_dwc3_free_request(req);
874 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
876 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
877 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
878 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
880 struct dwc3 *dwc = dep->dwc;
881 struct usb_gadget *gadget = &dwc->gadget;
882 enum usb_device_speed speed = gadget->speed;
884 dwc3_ep_inc_enq(dep);
886 trb->size = DWC3_TRB_SIZE_LENGTH(length);
887 trb->bpl = lower_32_bits(dma);
888 trb->bph = upper_32_bits(dma);
890 switch (usb_endpoint_type(dep->endpoint.desc)) {
891 case USB_ENDPOINT_XFER_CONTROL:
892 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
895 case USB_ENDPOINT_XFER_ISOC:
897 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
899 if (speed == USB_SPEED_HIGH) {
900 struct usb_ep *ep = &dep->endpoint;
901 trb->size |= DWC3_TRB_SIZE_PCM1(ep->mult - 1);
904 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
907 /* always enable Interrupt on Missed ISOC */
908 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
911 case USB_ENDPOINT_XFER_BULK:
912 case USB_ENDPOINT_XFER_INT:
913 trb->ctrl = DWC3_TRBCTL_NORMAL;
917 * This is only possible with faulty memory because we
918 * checked it already :)
920 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
921 usb_endpoint_type(dep->endpoint.desc));
924 /* always enable Continue on Short Packet */
925 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
926 trb->ctrl |= DWC3_TRB_CTRL_CSP;
929 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
932 if ((!no_interrupt && !chain) ||
933 (dwc3_calc_trbs_left(dep) == 0))
934 trb->ctrl |= DWC3_TRB_CTRL_IOC;
937 trb->ctrl |= DWC3_TRB_CTRL_CHN;
939 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
940 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
942 trb->ctrl |= DWC3_TRB_CTRL_HWO;
944 trace_dwc3_prepare_trb(dep, trb);
948 * dwc3_prepare_one_trb - setup one TRB from one request
949 * @dep: endpoint for which this request is prepared
950 * @req: dwc3_request pointer
951 * @chain: should this TRB be chained to the next?
952 * @node: only for isochronous endpoints. First TRB needs different type.
954 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
955 struct dwc3_request *req, unsigned chain, unsigned node)
957 struct dwc3_trb *trb;
958 unsigned length = req->request.length;
959 unsigned stream_id = req->request.stream_id;
960 unsigned short_not_ok = req->request.short_not_ok;
961 unsigned no_interrupt = req->request.no_interrupt;
962 dma_addr_t dma = req->request.dma;
964 trb = &dep->trb_pool[dep->trb_enqueue];
967 dwc3_gadget_move_started_request(req);
969 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
970 dep->queued_requests++;
973 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
974 stream_id, short_not_ok, no_interrupt);
978 * dwc3_ep_prev_trb - returns the previous TRB in the ring
979 * @dep: The endpoint with the TRB ring
980 * @index: The index of the current TRB in the ring
982 * Returns the TRB prior to the one pointed to by the index. If the
983 * index is 0, we will wrap backwards, skip the link TRB, and return
984 * the one just before that.
986 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
991 tmp = DWC3_TRB_NUM - 1;
993 return &dep->trb_pool[tmp - 1];
996 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
998 struct dwc3_trb *tmp;
1002 * If enqueue & dequeue are equal than it is either full or empty.
1004 * One way to know for sure is if the TRB right before us has HWO bit
1005 * set or not. If it has, then we're definitely full and can't fit any
1006 * more transfers in our ring.
1008 if (dep->trb_enqueue == dep->trb_dequeue) {
1009 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1010 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
1013 return DWC3_TRB_NUM - 1;
1016 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1017 trbs_left &= (DWC3_TRB_NUM - 1);
1019 if (dep->trb_dequeue < dep->trb_enqueue)
1025 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1026 struct dwc3_request *req)
1028 struct scatterlist *sg = req->sg;
1029 struct scatterlist *s;
1032 for_each_sg(sg, s, req->num_pending_sgs, i) {
1033 unsigned int length = req->request.length;
1034 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1035 unsigned int rem = length % maxp;
1036 unsigned chain = true;
1041 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1042 struct dwc3 *dwc = dep->dwc;
1043 struct dwc3_trb *trb;
1045 req->unaligned = true;
1047 /* prepare normal TRB */
1048 dwc3_prepare_one_trb(dep, req, true, i);
1050 /* Now prepare one extra TRB to align transfer size */
1051 trb = &dep->trb_pool[dep->trb_enqueue];
1052 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1053 maxp - rem, false, 0,
1054 req->request.stream_id,
1055 req->request.short_not_ok,
1056 req->request.no_interrupt);
1058 dwc3_prepare_one_trb(dep, req, chain, i);
1061 if (!dwc3_calc_trbs_left(dep))
1066 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1067 struct dwc3_request *req)
1069 unsigned int length = req->request.length;
1070 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1071 unsigned int rem = length % maxp;
1073 if (rem && usb_endpoint_dir_out(dep->endpoint.desc)) {
1074 struct dwc3 *dwc = dep->dwc;
1075 struct dwc3_trb *trb;
1077 req->unaligned = true;
1079 /* prepare normal TRB */
1080 dwc3_prepare_one_trb(dep, req, true, 0);
1082 /* Now prepare one extra TRB to align transfer size */
1083 trb = &dep->trb_pool[dep->trb_enqueue];
1084 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1085 false, 0, req->request.stream_id,
1086 req->request.short_not_ok,
1087 req->request.no_interrupt);
1088 } else if (req->request.zero && req->request.length &&
1089 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1090 struct dwc3 *dwc = dep->dwc;
1091 struct dwc3_trb *trb;
1095 /* prepare normal TRB */
1096 dwc3_prepare_one_trb(dep, req, true, 0);
1098 /* Now prepare one extra TRB to handle ZLP */
1099 trb = &dep->trb_pool[dep->trb_enqueue];
1100 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1101 false, 0, req->request.stream_id,
1102 req->request.short_not_ok,
1103 req->request.no_interrupt);
1105 dwc3_prepare_one_trb(dep, req, false, 0);
1110 * dwc3_prepare_trbs - setup TRBs from requests
1111 * @dep: endpoint for which requests are being prepared
1113 * The function goes through the requests list and sets up TRBs for the
1114 * transfers. The function returns once there are no more TRBs available or
1115 * it runs out of requests.
1117 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1119 struct dwc3_request *req, *n;
1121 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1123 if (!dwc3_calc_trbs_left(dep))
1127 * We can get in a situation where there's a request in the started list
1128 * but there weren't enough TRBs to fully kick it in the first time
1129 * around, so it has been waiting for more TRBs to be freed up.
1131 * In that case, we should check if we have a request with pending_sgs
1132 * in the started list and prepare TRBs for that request first,
1133 * otherwise we will prepare TRBs completely out of order and that will
1136 list_for_each_entry(req, &dep->started_list, list) {
1137 if (req->num_pending_sgs > 0)
1138 dwc3_prepare_one_trb_sg(dep, req);
1140 if (!dwc3_calc_trbs_left(dep))
1144 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1145 struct dwc3 *dwc = dep->dwc;
1148 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1153 req->sg = req->request.sg;
1154 req->num_pending_sgs = req->request.num_mapped_sgs;
1156 if (req->num_pending_sgs > 0)
1157 dwc3_prepare_one_trb_sg(dep, req);
1159 dwc3_prepare_one_trb_linear(dep, req);
1161 if (!dwc3_calc_trbs_left(dep))
1166 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1168 struct dwc3_gadget_ep_cmd_params params;
1169 struct dwc3_request *req;
1174 starting = !(dep->flags & DWC3_EP_BUSY);
1176 dwc3_prepare_trbs(dep);
1177 req = next_request(&dep->started_list);
1179 dep->flags |= DWC3_EP_PENDING_REQUEST;
1183 memset(¶ms, 0, sizeof(params));
1186 params.param0 = upper_32_bits(req->trb_dma);
1187 params.param1 = lower_32_bits(req->trb_dma);
1188 cmd = DWC3_DEPCMD_STARTTRANSFER |
1189 DWC3_DEPCMD_PARAM(cmd_param);
1191 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1192 DWC3_DEPCMD_PARAM(dep->resource_index);
1195 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1198 * FIXME we need to iterate over the list of requests
1199 * here and stop, unmap, free and del each of the linked
1200 * requests instead of what we do now.
1203 memset(req->trb, 0, sizeof(struct dwc3_trb));
1204 dep->queued_requests--;
1205 dwc3_gadget_giveback(dep, req, ret);
1209 dep->flags |= DWC3_EP_BUSY;
1212 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1213 WARN_ON_ONCE(!dep->resource_index);
1219 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1223 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1224 return DWC3_DSTS_SOFFN(reg);
1227 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1228 struct dwc3_ep *dep, u32 cur_uf)
1232 if (list_empty(&dep->pending_list)) {
1233 dev_info(dwc->dev, "%s: ran out of requests\n",
1235 dep->flags |= DWC3_EP_PENDING_REQUEST;
1240 * Schedule the first trb for one interval in the future or at
1241 * least 4 microframes.
1243 uf = cur_uf + max_t(u32, 4, dep->interval);
1245 __dwc3_gadget_kick_transfer(dep, uf);
1248 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1249 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1253 mask = ~(dep->interval - 1);
1254 cur_uf = event->parameters & mask;
1256 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1259 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1261 struct dwc3 *dwc = dep->dwc;
1264 if (!dep->endpoint.desc) {
1265 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1270 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1271 &req->request, req->dep->name))
1274 pm_runtime_get(dwc->dev);
1276 req->request.actual = 0;
1277 req->request.status = -EINPROGRESS;
1278 req->direction = dep->direction;
1279 req->epnum = dep->number;
1281 trace_dwc3_ep_queue(req);
1283 list_add_tail(&req->list, &dep->pending_list);
1286 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1287 * wait for a XferNotReady event so we will know what's the current
1288 * (micro-)frame number.
1290 * Without this trick, we are very, very likely gonna get Bus Expiry
1291 * errors which will force us issue EndTransfer command.
1293 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1294 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1295 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1296 dwc3_stop_active_transfer(dwc, dep->number, true);
1297 dep->flags = DWC3_EP_ENABLED;
1301 cur_uf = __dwc3_gadget_get_frame(dwc);
1302 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1303 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1308 if ((dep->flags & DWC3_EP_BUSY) &&
1309 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1310 WARN_ON_ONCE(!dep->resource_index);
1311 ret = __dwc3_gadget_kick_transfer(dep,
1312 dep->resource_index);
1318 if (!dwc3_calc_trbs_left(dep))
1321 ret = __dwc3_gadget_kick_transfer(dep, 0);
1329 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1332 struct dwc3_request *req = to_dwc3_request(request);
1333 struct dwc3_ep *dep = to_dwc3_ep(ep);
1334 struct dwc3 *dwc = dep->dwc;
1336 unsigned long flags;
1340 spin_lock_irqsave(&dwc->lock, flags);
1341 ret = __dwc3_gadget_ep_queue(dep, req);
1342 spin_unlock_irqrestore(&dwc->lock, flags);
1347 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1348 struct usb_request *request)
1350 struct dwc3_request *req = to_dwc3_request(request);
1351 struct dwc3_request *r = NULL;
1353 struct dwc3_ep *dep = to_dwc3_ep(ep);
1354 struct dwc3 *dwc = dep->dwc;
1356 unsigned long flags;
1359 trace_dwc3_ep_dequeue(req);
1361 spin_lock_irqsave(&dwc->lock, flags);
1363 list_for_each_entry(r, &dep->pending_list, list) {
1369 list_for_each_entry(r, &dep->started_list, list) {
1374 /* wait until it is processed */
1375 dwc3_stop_active_transfer(dwc, dep->number, true);
1378 * If request was already started, this means we had to
1379 * stop the transfer. With that we also need to ignore
1380 * all TRBs used by the request, however TRBs can only
1381 * be modified after completion of END_TRANSFER
1382 * command. So what we do here is that we wait for
1383 * END_TRANSFER completion and only after that, we jump
1384 * over TRBs by clearing HWO and incrementing dequeue
1387 * Note that we have 2 possible types of transfers here:
1389 * i) Linear buffer request
1390 * ii) SG-list based request
1392 * SG-list based requests will have r->num_pending_sgs
1393 * set to a valid number (> 0). Linear requests,
1394 * normally use a single TRB.
1396 * For each of these two cases, if r->unaligned flag is
1397 * set, one extra TRB has been used to align transfer
1398 * size to wMaxPacketSize.
1400 * All of these cases need to be taken into
1401 * consideration so we don't mess up our TRB ring
1404 wait_event_lock_irq(dep->wait_end_transfer,
1405 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1411 if (r->num_pending_sgs) {
1412 struct dwc3_trb *trb;
1415 for (i = 0; i < r->num_pending_sgs; i++) {
1417 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1418 dwc3_ep_inc_deq(dep);
1421 if (r->unaligned || r->zero) {
1422 trb = r->trb + r->num_pending_sgs + 1;
1423 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1424 dwc3_ep_inc_deq(dep);
1427 struct dwc3_trb *trb = r->trb;
1429 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1430 dwc3_ep_inc_deq(dep);
1432 if (r->unaligned || r->zero) {
1434 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1435 dwc3_ep_inc_deq(dep);
1440 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1447 /* giveback the request */
1448 dep->queued_requests--;
1449 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1452 spin_unlock_irqrestore(&dwc->lock, flags);
1457 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1459 struct dwc3_gadget_ep_cmd_params params;
1460 struct dwc3 *dwc = dep->dwc;
1463 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1464 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1468 memset(¶ms, 0x00, sizeof(params));
1471 struct dwc3_trb *trb;
1473 unsigned transfer_in_flight;
1476 if (dep->flags & DWC3_EP_STALL)
1479 if (dep->number > 1)
1480 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1482 trb = &dwc->ep0_trb[dep->trb_enqueue];
1484 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1485 started = !list_empty(&dep->started_list);
1487 if (!protocol && ((dep->direction && transfer_in_flight) ||
1488 (!dep->direction && started))) {
1492 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1495 dev_err(dwc->dev, "failed to set STALL on %s\n",
1498 dep->flags |= DWC3_EP_STALL;
1500 if (!(dep->flags & DWC3_EP_STALL))
1503 ret = dwc3_send_clear_stall_ep_cmd(dep);
1505 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1508 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1514 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1516 struct dwc3_ep *dep = to_dwc3_ep(ep);
1517 struct dwc3 *dwc = dep->dwc;
1519 unsigned long flags;
1523 spin_lock_irqsave(&dwc->lock, flags);
1524 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1525 spin_unlock_irqrestore(&dwc->lock, flags);
1530 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1532 struct dwc3_ep *dep = to_dwc3_ep(ep);
1533 struct dwc3 *dwc = dep->dwc;
1534 unsigned long flags;
1537 spin_lock_irqsave(&dwc->lock, flags);
1538 dep->flags |= DWC3_EP_WEDGE;
1540 if (dep->number == 0 || dep->number == 1)
1541 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1543 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1544 spin_unlock_irqrestore(&dwc->lock, flags);
1549 /* -------------------------------------------------------------------------- */
1551 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1552 .bLength = USB_DT_ENDPOINT_SIZE,
1553 .bDescriptorType = USB_DT_ENDPOINT,
1554 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1557 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1558 .enable = dwc3_gadget_ep0_enable,
1559 .disable = dwc3_gadget_ep0_disable,
1560 .alloc_request = dwc3_gadget_ep_alloc_request,
1561 .free_request = dwc3_gadget_ep_free_request,
1562 .queue = dwc3_gadget_ep0_queue,
1563 .dequeue = dwc3_gadget_ep_dequeue,
1564 .set_halt = dwc3_gadget_ep0_set_halt,
1565 .set_wedge = dwc3_gadget_ep_set_wedge,
1568 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1569 .enable = dwc3_gadget_ep_enable,
1570 .disable = dwc3_gadget_ep_disable,
1571 .alloc_request = dwc3_gadget_ep_alloc_request,
1572 .free_request = dwc3_gadget_ep_free_request,
1573 .queue = dwc3_gadget_ep_queue,
1574 .dequeue = dwc3_gadget_ep_dequeue,
1575 .set_halt = dwc3_gadget_ep_set_halt,
1576 .set_wedge = dwc3_gadget_ep_set_wedge,
1579 /* -------------------------------------------------------------------------- */
1581 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1583 struct dwc3 *dwc = gadget_to_dwc(g);
1585 return __dwc3_gadget_get_frame(dwc);
1588 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1599 * According to the Databook Remote wakeup request should
1600 * be issued only when the device is in early suspend state.
1602 * We can check that via USB Link State bits in DSTS register.
1604 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1606 speed = reg & DWC3_DSTS_CONNECTSPD;
1607 if ((speed == DWC3_DSTS_SUPERSPEED) ||
1608 (speed == DWC3_DSTS_SUPERSPEED_PLUS))
1611 link_state = DWC3_DSTS_USBLNKST(reg);
1613 switch (link_state) {
1614 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1615 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1621 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1623 dev_err(dwc->dev, "failed to put link in Recovery\n");
1627 /* Recent versions do this automatically */
1628 if (dwc->revision < DWC3_REVISION_194A) {
1629 /* write zeroes to Link Change Request */
1630 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1631 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1632 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1635 /* poll until Link State changes to ON */
1639 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1641 /* in HS, means ON */
1642 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1646 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1647 dev_err(dwc->dev, "failed to send remote wakeup\n");
1654 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1656 struct dwc3 *dwc = gadget_to_dwc(g);
1657 unsigned long flags;
1660 spin_lock_irqsave(&dwc->lock, flags);
1661 ret = __dwc3_gadget_wakeup(dwc);
1662 spin_unlock_irqrestore(&dwc->lock, flags);
1667 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1670 struct dwc3 *dwc = gadget_to_dwc(g);
1671 unsigned long flags;
1673 spin_lock_irqsave(&dwc->lock, flags);
1674 g->is_selfpowered = !!is_selfpowered;
1675 spin_unlock_irqrestore(&dwc->lock, flags);
1680 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1685 if (pm_runtime_suspended(dwc->dev))
1688 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1690 if (dwc->revision <= DWC3_REVISION_187A) {
1691 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1692 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1695 if (dwc->revision >= DWC3_REVISION_194A)
1696 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1697 reg |= DWC3_DCTL_RUN_STOP;
1699 if (dwc->has_hibernation)
1700 reg |= DWC3_DCTL_KEEP_CONNECT;
1702 dwc->pullups_connected = true;
1704 reg &= ~DWC3_DCTL_RUN_STOP;
1706 if (dwc->has_hibernation && !suspend)
1707 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1709 dwc->pullups_connected = false;
1712 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1715 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1716 reg &= DWC3_DSTS_DEVCTRLHLT;
1717 } while (--timeout && !(!is_on ^ !reg));
1725 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1727 struct dwc3 *dwc = gadget_to_dwc(g);
1728 unsigned long flags;
1734 * Per databook, when we want to stop the gadget, if a control transfer
1735 * is still in process, complete it and get the core into setup phase.
1737 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1738 reinit_completion(&dwc->ep0_in_setup);
1740 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1741 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1743 dev_err(dwc->dev, "timed out waiting for SETUP phase\n");
1748 spin_lock_irqsave(&dwc->lock, flags);
1749 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1750 spin_unlock_irqrestore(&dwc->lock, flags);
1755 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1759 /* Enable all but Start and End of Frame IRQs */
1760 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1761 DWC3_DEVTEN_EVNTOVERFLOWEN |
1762 DWC3_DEVTEN_CMDCMPLTEN |
1763 DWC3_DEVTEN_ERRTICERREN |
1764 DWC3_DEVTEN_WKUPEVTEN |
1765 DWC3_DEVTEN_CONNECTDONEEN |
1766 DWC3_DEVTEN_USBRSTEN |
1767 DWC3_DEVTEN_DISCONNEVTEN);
1769 if (dwc->revision < DWC3_REVISION_250A)
1770 reg |= DWC3_DEVTEN_ULSTCNGEN;
1772 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1775 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1777 /* mask all interrupts */
1778 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1781 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1782 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1785 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1786 * @dwc: pointer to our context structure
1788 * The following looks like complex but it's actually very simple. In order to
1789 * calculate the number of packets we can burst at once on OUT transfers, we're
1790 * gonna use RxFIFO size.
1792 * To calculate RxFIFO size we need two numbers:
1793 * MDWIDTH = size, in bits, of the internal memory bus
1794 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1796 * Given these two numbers, the formula is simple:
1798 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1800 * 24 bytes is for 3x SETUP packets
1801 * 16 bytes is a clock domain crossing tolerance
1803 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1805 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1812 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1813 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1815 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1816 nump = min_t(u32, nump, 16);
1819 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1820 reg &= ~DWC3_DCFG_NUMP_MASK;
1821 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1822 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1825 static int __dwc3_gadget_start(struct dwc3 *dwc)
1827 struct dwc3_ep *dep;
1832 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1833 * the core supports IMOD, disable it.
1835 if (dwc->imod_interval) {
1836 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1837 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1838 } else if (dwc3_has_imod(dwc)) {
1839 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1843 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1844 * field instead of letting dwc3 itself calculate that automatically.
1846 * This way, we maximize the chances that we'll be able to get several
1847 * bursts of data without going through any sort of endpoint throttling.
1849 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1850 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1851 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1853 dwc3_gadget_setup_nump(dwc);
1855 /* Start with SuperSpeed Default */
1856 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1859 ret = __dwc3_gadget_ep_enable(dep, false, false);
1861 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1866 ret = __dwc3_gadget_ep_enable(dep, false, false);
1868 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1872 /* begin to receive SETUP packets */
1873 dwc->ep0state = EP0_SETUP_PHASE;
1874 dwc3_ep0_out_start(dwc);
1876 dwc3_gadget_enable_irq(dwc);
1881 __dwc3_gadget_ep_disable(dwc->eps[0]);
1887 static int dwc3_gadget_start(struct usb_gadget *g,
1888 struct usb_gadget_driver *driver)
1890 struct dwc3 *dwc = gadget_to_dwc(g);
1891 unsigned long flags;
1895 irq = dwc->irq_gadget;
1896 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1897 IRQF_SHARED, "dwc3", dwc->ev_buf);
1899 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1904 spin_lock_irqsave(&dwc->lock, flags);
1905 if (dwc->gadget_driver) {
1906 dev_err(dwc->dev, "%s is already bound to %s\n",
1908 dwc->gadget_driver->driver.name);
1913 dwc->gadget_driver = driver;
1915 if (pm_runtime_active(dwc->dev))
1916 __dwc3_gadget_start(dwc);
1918 spin_unlock_irqrestore(&dwc->lock, flags);
1923 spin_unlock_irqrestore(&dwc->lock, flags);
1930 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1932 dwc3_gadget_disable_irq(dwc);
1933 __dwc3_gadget_ep_disable(dwc->eps[0]);
1934 __dwc3_gadget_ep_disable(dwc->eps[1]);
1937 static int dwc3_gadget_stop(struct usb_gadget *g)
1939 struct dwc3 *dwc = gadget_to_dwc(g);
1940 unsigned long flags;
1943 spin_lock_irqsave(&dwc->lock, flags);
1945 if (pm_runtime_suspended(dwc->dev))
1948 __dwc3_gadget_stop(dwc);
1950 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1951 struct dwc3_ep *dep = dwc->eps[epnum];
1956 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
1959 wait_event_lock_irq(dep->wait_end_transfer,
1960 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1965 dwc->gadget_driver = NULL;
1966 spin_unlock_irqrestore(&dwc->lock, flags);
1968 free_irq(dwc->irq_gadget, dwc->ev_buf);
1973 static void dwc3_gadget_set_speed(struct usb_gadget *g,
1974 enum usb_device_speed speed)
1976 struct dwc3 *dwc = gadget_to_dwc(g);
1977 unsigned long flags;
1980 spin_lock_irqsave(&dwc->lock, flags);
1981 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1982 reg &= ~(DWC3_DCFG_SPEED_MASK);
1985 * WORKAROUND: DWC3 revision < 2.20a have an issue
1986 * which would cause metastability state on Run/Stop
1987 * bit if we try to force the IP to USB2-only mode.
1989 * Because of that, we cannot configure the IP to any
1990 * speed other than the SuperSpeed
1994 * STAR#9000525659: Clock Domain Crossing on DCTL in
1997 if (dwc->revision < DWC3_REVISION_220A) {
1998 reg |= DWC3_DCFG_SUPERSPEED;
2002 reg |= DWC3_DCFG_LOWSPEED;
2004 case USB_SPEED_FULL:
2005 reg |= DWC3_DCFG_FULLSPEED;
2007 case USB_SPEED_HIGH:
2008 reg |= DWC3_DCFG_HIGHSPEED;
2010 case USB_SPEED_SUPER:
2011 reg |= DWC3_DCFG_SUPERSPEED;
2013 case USB_SPEED_SUPER_PLUS:
2014 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2017 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2019 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2020 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2022 reg |= DWC3_DCFG_SUPERSPEED;
2025 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2027 spin_unlock_irqrestore(&dwc->lock, flags);
2030 static const struct usb_gadget_ops dwc3_gadget_ops = {
2031 .get_frame = dwc3_gadget_get_frame,
2032 .wakeup = dwc3_gadget_wakeup,
2033 .set_selfpowered = dwc3_gadget_set_selfpowered,
2034 .pullup = dwc3_gadget_pullup,
2035 .udc_start = dwc3_gadget_start,
2036 .udc_stop = dwc3_gadget_stop,
2037 .udc_set_speed = dwc3_gadget_set_speed,
2040 /* -------------------------------------------------------------------------- */
2042 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2044 struct dwc3_ep *dep;
2047 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2049 for (epnum = 0; epnum < total; epnum++) {
2050 bool direction = epnum & 1;
2051 u8 num = epnum >> 1;
2053 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2058 dep->number = epnum;
2059 dep->direction = direction;
2060 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2061 dwc->eps[epnum] = dep;
2063 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2064 direction ? "in" : "out");
2066 dep->endpoint.name = dep->name;
2068 if (!(dep->number > 1)) {
2069 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2070 dep->endpoint.comp_desc = NULL;
2073 spin_lock_init(&dep->lock);
2076 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2077 dep->endpoint.maxburst = 1;
2078 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2080 dwc->gadget.ep0 = &dep->endpoint;
2081 } else if (direction) {
2087 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2088 /* MDWIDTH is represented in bits, we need it in bytes */
2091 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2092 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2094 /* FIFO Depth is in MDWDITH bytes. Multiply */
2097 kbytes = size / 1024;
2102 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2103 * internal overhead. We don't really know how these are used,
2104 * but documentation say it exists.
2106 size -= mdwidth * (kbytes + 1);
2109 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2111 dep->endpoint.max_streams = 15;
2112 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2113 list_add_tail(&dep->endpoint.ep_list,
2114 &dwc->gadget.ep_list);
2116 ret = dwc3_alloc_trb_pool(dep);
2122 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2123 dep->endpoint.max_streams = 15;
2124 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2125 list_add_tail(&dep->endpoint.ep_list,
2126 &dwc->gadget.ep_list);
2128 ret = dwc3_alloc_trb_pool(dep);
2134 dep->endpoint.caps.type_control = true;
2136 dep->endpoint.caps.type_iso = true;
2137 dep->endpoint.caps.type_bulk = true;
2138 dep->endpoint.caps.type_int = true;
2141 dep->endpoint.caps.dir_in = direction;
2142 dep->endpoint.caps.dir_out = !direction;
2144 INIT_LIST_HEAD(&dep->pending_list);
2145 INIT_LIST_HEAD(&dep->started_list);
2151 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2153 struct dwc3_ep *dep;
2156 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2157 dep = dwc->eps[epnum];
2161 * Physical endpoints 0 and 1 are special; they form the
2162 * bi-directional USB endpoint 0.
2164 * For those two physical endpoints, we don't allocate a TRB
2165 * pool nor do we add them the endpoints list. Due to that, we
2166 * shouldn't do these two operations otherwise we would end up
2167 * with all sorts of bugs when removing dwc3.ko.
2169 if (epnum != 0 && epnum != 1) {
2170 dwc3_free_trb_pool(dep);
2171 list_del(&dep->endpoint.ep_list);
2178 /* -------------------------------------------------------------------------- */
2180 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2181 struct dwc3_request *req, struct dwc3_trb *trb,
2182 const struct dwc3_event_depevt *event, int status,
2186 unsigned int s_pkt = 0;
2187 unsigned int trb_status;
2189 dwc3_ep_inc_deq(dep);
2191 if (req->trb == trb)
2192 dep->queued_requests--;
2194 trace_dwc3_complete_trb(dep, trb);
2197 * If we're in the middle of series of chained TRBs and we
2198 * receive a short transfer along the way, DWC3 will skip
2199 * through all TRBs including the last TRB in the chain (the
2200 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2201 * bit and SW has to do it manually.
2203 * We're going to do that here to avoid problems of HW trying
2204 * to use bogus TRBs for transfers.
2206 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2207 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2210 * If we're dealing with unaligned size OUT transfer, we will be left
2211 * with one TRB pending in the ring. We need to manually clear HWO bit
2214 if ((req->zero || req->unaligned) && (trb->ctrl & DWC3_TRB_CTRL_HWO)) {
2215 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2219 count = trb->size & DWC3_TRB_SIZE_MASK;
2220 req->remaining += count;
2222 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2225 if (dep->direction) {
2227 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2228 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2230 * If missed isoc occurred and there is
2231 * no request queued then issue END
2232 * TRANSFER, so that core generates
2233 * next xfernotready and we will issue
2234 * a fresh START TRANSFER.
2235 * If there are still queued request
2236 * then wait, do not issue either END
2237 * or UPDATE TRANSFER, just attach next
2238 * request in pending_list during
2239 * giveback.If any future queued request
2240 * is successfully transferred then we
2241 * will issue UPDATE TRANSFER for all
2242 * request in the pending_list.
2244 dep->flags |= DWC3_EP_MISSED_ISOC;
2246 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2248 status = -ECONNRESET;
2251 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2254 if (count && (event->status & DEPEVT_STATUS_SHORT))
2258 if (s_pkt && !chain)
2261 if ((event->status & DEPEVT_STATUS_IOC) &&
2262 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2268 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2269 const struct dwc3_event_depevt *event, int status)
2271 struct dwc3_request *req, *n;
2272 struct dwc3_trb *trb;
2276 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2280 length = req->request.length;
2281 chain = req->num_pending_sgs > 0;
2283 struct scatterlist *sg = req->sg;
2284 struct scatterlist *s;
2285 unsigned int pending = req->num_pending_sgs;
2288 for_each_sg(sg, s, pending, i) {
2289 trb = &dep->trb_pool[dep->trb_dequeue];
2291 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2294 req->sg = sg_next(s);
2295 req->num_pending_sgs--;
2297 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2298 event, status, chain);
2303 trb = &dep->trb_pool[dep->trb_dequeue];
2304 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2305 event, status, chain);
2308 if (req->unaligned || req->zero) {
2309 trb = &dep->trb_pool[dep->trb_dequeue];
2310 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2311 event, status, false);
2312 req->unaligned = false;
2316 req->request.actual = length - req->remaining;
2318 if ((req->request.actual < length) && req->num_pending_sgs)
2319 return __dwc3_gadget_kick_transfer(dep, 0);
2321 dwc3_gadget_giveback(dep, req, status);
2324 if ((event->status & DEPEVT_STATUS_IOC) &&
2325 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2332 * Our endpoint might get disabled by another thread during
2333 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2334 * early on so DWC3_EP_BUSY flag gets cleared
2336 if (!dep->endpoint.desc)
2339 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2340 list_empty(&dep->started_list)) {
2341 if (list_empty(&dep->pending_list)) {
2343 * If there is no entry in request list then do
2344 * not issue END TRANSFER now. Just set PENDING
2345 * flag, so that END TRANSFER is issued when an
2346 * entry is added into request list.
2348 dep->flags = DWC3_EP_PENDING_REQUEST;
2350 dwc3_stop_active_transfer(dwc, dep->number, true);
2351 dep->flags = DWC3_EP_ENABLED;
2356 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2362 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2363 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2365 unsigned status = 0;
2367 u32 is_xfer_complete;
2369 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2371 if (event->status & DEPEVT_STATUS_BUSERR)
2372 status = -ECONNRESET;
2374 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2375 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2376 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2377 dep->flags &= ~DWC3_EP_BUSY;
2380 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2381 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2383 if (dwc->revision < DWC3_REVISION_183A) {
2387 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2390 if (!(dep->flags & DWC3_EP_ENABLED))
2393 if (!list_empty(&dep->started_list))
2397 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2399 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2405 * Our endpoint might get disabled by another thread during
2406 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2407 * early on so DWC3_EP_BUSY flag gets cleared
2409 if (!dep->endpoint.desc)
2412 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2415 ret = __dwc3_gadget_kick_transfer(dep, 0);
2416 if (!ret || ret == -EBUSY)
2421 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2422 const struct dwc3_event_depevt *event)
2424 struct dwc3_ep *dep;
2425 u8 epnum = event->endpoint_number;
2428 dep = dwc->eps[epnum];
2430 if (!(dep->flags & DWC3_EP_ENABLED)) {
2431 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2434 /* Handle only EPCMDCMPLT when EP disabled */
2435 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2439 if (epnum == 0 || epnum == 1) {
2440 dwc3_ep0_interrupt(dwc, event);
2444 switch (event->endpoint_event) {
2445 case DWC3_DEPEVT_XFERCOMPLETE:
2446 dep->resource_index = 0;
2448 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2449 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2453 dwc3_endpoint_transfer_complete(dwc, dep, event);
2455 case DWC3_DEPEVT_XFERINPROGRESS:
2456 dwc3_endpoint_transfer_complete(dwc, dep, event);
2458 case DWC3_DEPEVT_XFERNOTREADY:
2459 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2460 dwc3_gadget_start_isoc(dwc, dep, event);
2464 ret = __dwc3_gadget_kick_transfer(dep, 0);
2465 if (!ret || ret == -EBUSY)
2470 case DWC3_DEPEVT_STREAMEVT:
2471 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2472 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2477 case DWC3_DEPEVT_EPCMDCMPLT:
2478 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2480 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2481 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2482 wake_up(&dep->wait_end_transfer);
2485 case DWC3_DEPEVT_RXTXFIFOEVT:
2490 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2492 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2493 spin_unlock(&dwc->lock);
2494 dwc->gadget_driver->disconnect(&dwc->gadget);
2495 spin_lock(&dwc->lock);
2499 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2501 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2502 spin_unlock(&dwc->lock);
2503 dwc->gadget_driver->suspend(&dwc->gadget);
2504 spin_lock(&dwc->lock);
2508 static void dwc3_resume_gadget(struct dwc3 *dwc)
2510 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2511 spin_unlock(&dwc->lock);
2512 dwc->gadget_driver->resume(&dwc->gadget);
2513 spin_lock(&dwc->lock);
2517 static void dwc3_reset_gadget(struct dwc3 *dwc)
2519 if (!dwc->gadget_driver)
2522 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2523 spin_unlock(&dwc->lock);
2524 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2525 spin_lock(&dwc->lock);
2529 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2531 struct dwc3_ep *dep;
2532 struct dwc3_gadget_ep_cmd_params params;
2536 dep = dwc->eps[epnum];
2538 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2539 !dep->resource_index)
2543 * NOTICE: We are violating what the Databook says about the
2544 * EndTransfer command. Ideally we would _always_ wait for the
2545 * EndTransfer Command Completion IRQ, but that's causing too
2546 * much trouble synchronizing between us and gadget driver.
2548 * We have discussed this with the IP Provider and it was
2549 * suggested to giveback all requests here, but give HW some
2550 * extra time to synchronize with the interconnect. We're using
2551 * an arbitrary 100us delay for that.
2553 * Note also that a similar handling was tested by Synopsys
2554 * (thanks a lot Paul) and nothing bad has come out of it.
2555 * In short, what we're doing is:
2557 * - Issue EndTransfer WITH CMDIOC bit set
2560 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2561 * supports a mode to work around the above limitation. The
2562 * software can poll the CMDACT bit in the DEPCMD register
2563 * after issuing a EndTransfer command. This mode is enabled
2564 * by writing GUCTL2[14]. This polling is already done in the
2565 * dwc3_send_gadget_ep_cmd() function so if the mode is
2566 * enabled, the EndTransfer command will have completed upon
2567 * returning from this function and we don't need to delay for
2570 * This mode is NOT available on the DWC_usb31 IP.
2573 cmd = DWC3_DEPCMD_ENDTRANSFER;
2574 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2575 cmd |= DWC3_DEPCMD_CMDIOC;
2576 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2577 memset(¶ms, 0, sizeof(params));
2578 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2580 dep->resource_index = 0;
2581 dep->flags &= ~DWC3_EP_BUSY;
2583 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2584 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2589 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2593 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2594 struct dwc3_ep *dep;
2597 dep = dwc->eps[epnum];
2601 if (!(dep->flags & DWC3_EP_STALL))
2604 dep->flags &= ~DWC3_EP_STALL;
2606 ret = dwc3_send_clear_stall_ep_cmd(dep);
2611 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2615 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2616 reg &= ~DWC3_DCTL_INITU1ENA;
2617 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2619 reg &= ~DWC3_DCTL_INITU2ENA;
2620 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2622 dwc3_disconnect_gadget(dwc);
2624 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2625 dwc->setup_packet_pending = false;
2626 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2628 dwc->connected = false;
2631 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2635 dwc->connected = true;
2638 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2639 * would cause a missing Disconnect Event if there's a
2640 * pending Setup Packet in the FIFO.
2642 * There's no suggested workaround on the official Bug
2643 * report, which states that "unless the driver/application
2644 * is doing any special handling of a disconnect event,
2645 * there is no functional issue".
2647 * Unfortunately, it turns out that we _do_ some special
2648 * handling of a disconnect event, namely complete all
2649 * pending transfers, notify gadget driver of the
2650 * disconnection, and so on.
2652 * Our suggested workaround is to follow the Disconnect
2653 * Event steps here, instead, based on a setup_packet_pending
2654 * flag. Such flag gets set whenever we have a SETUP_PENDING
2655 * status for EP0 TRBs and gets cleared on XferComplete for the
2660 * STAR#9000466709: RTL: Device : Disconnect event not
2661 * generated if setup packet pending in FIFO
2663 if (dwc->revision < DWC3_REVISION_188A) {
2664 if (dwc->setup_packet_pending)
2665 dwc3_gadget_disconnect_interrupt(dwc);
2668 dwc3_reset_gadget(dwc);
2670 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2671 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2672 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2673 dwc->test_mode = false;
2674 dwc3_clear_stall_all_ep(dwc);
2676 /* Reset device address to zero */
2677 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2678 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2679 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2682 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2684 struct dwc3_ep *dep;
2689 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2690 speed = reg & DWC3_DSTS_CONNECTSPD;
2694 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2695 * each time on Connect Done.
2697 * Currently we always use the reset value. If any platform
2698 * wants to set this to a different value, we need to add a
2699 * setting and update GCTL.RAMCLKSEL here.
2703 case DWC3_DSTS_SUPERSPEED_PLUS:
2704 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2705 dwc->gadget.ep0->maxpacket = 512;
2706 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2708 case DWC3_DSTS_SUPERSPEED:
2710 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2711 * would cause a missing USB3 Reset event.
2713 * In such situations, we should force a USB3 Reset
2714 * event by calling our dwc3_gadget_reset_interrupt()
2719 * STAR#9000483510: RTL: SS : USB3 reset event may
2720 * not be generated always when the link enters poll
2722 if (dwc->revision < DWC3_REVISION_190A)
2723 dwc3_gadget_reset_interrupt(dwc);
2725 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2726 dwc->gadget.ep0->maxpacket = 512;
2727 dwc->gadget.speed = USB_SPEED_SUPER;
2729 case DWC3_DSTS_HIGHSPEED:
2730 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2731 dwc->gadget.ep0->maxpacket = 64;
2732 dwc->gadget.speed = USB_SPEED_HIGH;
2734 case DWC3_DSTS_FULLSPEED:
2735 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2736 dwc->gadget.ep0->maxpacket = 64;
2737 dwc->gadget.speed = USB_SPEED_FULL;
2739 case DWC3_DSTS_LOWSPEED:
2740 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2741 dwc->gadget.ep0->maxpacket = 8;
2742 dwc->gadget.speed = USB_SPEED_LOW;
2746 /* Enable USB2 LPM Capability */
2748 if ((dwc->revision > DWC3_REVISION_194A) &&
2749 (speed != DWC3_DSTS_SUPERSPEED) &&
2750 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2751 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2752 reg |= DWC3_DCFG_LPM_CAP;
2753 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2755 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2756 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2758 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2761 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2762 * DCFG.LPMCap is set, core responses with an ACK and the
2763 * BESL value in the LPM token is less than or equal to LPM
2766 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2767 && dwc->has_lpm_erratum,
2768 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2770 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2771 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2773 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2775 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2776 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2777 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2781 ret = __dwc3_gadget_ep_enable(dep, true, false);
2783 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2788 ret = __dwc3_gadget_ep_enable(dep, true, false);
2790 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2795 * Configure PHY via GUSB3PIPECTLn if required.
2797 * Update GTXFIFOSIZn
2799 * In both cases reset values should be sufficient.
2803 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2806 * TODO take core out of low power mode when that's
2810 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2811 spin_unlock(&dwc->lock);
2812 dwc->gadget_driver->resume(&dwc->gadget);
2813 spin_lock(&dwc->lock);
2817 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2818 unsigned int evtinfo)
2820 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2821 unsigned int pwropt;
2824 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2825 * Hibernation mode enabled which would show up when device detects
2826 * host-initiated U3 exit.
2828 * In that case, device will generate a Link State Change Interrupt
2829 * from U3 to RESUME which is only necessary if Hibernation is
2832 * There are no functional changes due to such spurious event and we
2833 * just need to ignore it.
2837 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2840 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2841 if ((dwc->revision < DWC3_REVISION_250A) &&
2842 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2843 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2844 (next == DWC3_LINK_STATE_RESUME)) {
2850 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2851 * on the link partner, the USB session might do multiple entry/exit
2852 * of low power states before a transfer takes place.
2854 * Due to this problem, we might experience lower throughput. The
2855 * suggested workaround is to disable DCTL[12:9] bits if we're
2856 * transitioning from U1/U2 to U0 and enable those bits again
2857 * after a transfer completes and there are no pending transfers
2858 * on any of the enabled endpoints.
2860 * This is the first half of that workaround.
2864 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2865 * core send LGO_Ux entering U0
2867 if (dwc->revision < DWC3_REVISION_183A) {
2868 if (next == DWC3_LINK_STATE_U0) {
2872 switch (dwc->link_state) {
2873 case DWC3_LINK_STATE_U1:
2874 case DWC3_LINK_STATE_U2:
2875 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2876 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2877 | DWC3_DCTL_ACCEPTU2ENA
2878 | DWC3_DCTL_INITU1ENA
2879 | DWC3_DCTL_ACCEPTU1ENA);
2882 dwc->u1u2 = reg & u1u2;
2886 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2896 case DWC3_LINK_STATE_U1:
2897 if (dwc->speed == USB_SPEED_SUPER)
2898 dwc3_suspend_gadget(dwc);
2900 case DWC3_LINK_STATE_U2:
2901 case DWC3_LINK_STATE_U3:
2902 dwc3_suspend_gadget(dwc);
2904 case DWC3_LINK_STATE_RESUME:
2905 dwc3_resume_gadget(dwc);
2912 dwc->link_state = next;
2915 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
2916 unsigned int evtinfo)
2918 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2920 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
2921 dwc3_suspend_gadget(dwc);
2923 dwc->link_state = next;
2926 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2927 unsigned int evtinfo)
2929 unsigned int is_ss = evtinfo & BIT(4);
2932 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2933 * have a known issue which can cause USB CV TD.9.23 to fail
2936 * Because of this issue, core could generate bogus hibernation
2937 * events which SW needs to ignore.
2941 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2942 * Device Fallback from SuperSpeed
2944 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2947 /* enter hibernation here */
2950 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2951 const struct dwc3_event_devt *event)
2953 switch (event->type) {
2954 case DWC3_DEVICE_EVENT_DISCONNECT:
2955 dwc3_gadget_disconnect_interrupt(dwc);
2957 case DWC3_DEVICE_EVENT_RESET:
2958 dwc3_gadget_reset_interrupt(dwc);
2960 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2961 dwc3_gadget_conndone_interrupt(dwc);
2963 case DWC3_DEVICE_EVENT_WAKEUP:
2964 dwc3_gadget_wakeup_interrupt(dwc);
2966 case DWC3_DEVICE_EVENT_HIBER_REQ:
2967 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2968 "unexpected hibernation event\n"))
2971 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2973 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2974 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2976 case DWC3_DEVICE_EVENT_EOPF:
2977 /* It changed to be suspend event for version 2.30a and above */
2978 if (dwc->revision >= DWC3_REVISION_230A) {
2980 * Ignore suspend event until the gadget enters into
2981 * USB_STATE_CONFIGURED state.
2983 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
2984 dwc3_gadget_suspend_interrupt(dwc,
2988 case DWC3_DEVICE_EVENT_SOF:
2989 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2990 case DWC3_DEVICE_EVENT_CMD_CMPL:
2991 case DWC3_DEVICE_EVENT_OVERFLOW:
2994 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2998 static void dwc3_process_event_entry(struct dwc3 *dwc,
2999 const union dwc3_event *event)
3001 trace_dwc3_event(event->raw, dwc);
3003 if (!event->type.is_devspec)
3004 dwc3_endpoint_interrupt(dwc, &event->depevt);
3005 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3006 dwc3_gadget_interrupt(dwc, &event->devt);
3008 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3011 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3013 struct dwc3 *dwc = evt->dwc;
3014 irqreturn_t ret = IRQ_NONE;
3020 if (!(evt->flags & DWC3_EVENT_PENDING))
3024 union dwc3_event event;
3026 event.raw = *(u32 *) (evt->cache + evt->lpos);
3028 dwc3_process_event_entry(dwc, &event);
3031 * FIXME we wrap around correctly to the next entry as
3032 * almost all entries are 4 bytes in size. There is one
3033 * entry which has 12 bytes which is a regular entry
3034 * followed by 8 bytes data. ATM I don't know how
3035 * things are organized if we get next to the a
3036 * boundary so I worry about that once we try to handle
3039 evt->lpos = (evt->lpos + 4) % evt->length;
3044 evt->flags &= ~DWC3_EVENT_PENDING;
3047 /* Unmask interrupt */
3048 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3049 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3050 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3052 if (dwc->imod_interval) {
3053 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3054 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3060 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3062 struct dwc3_event_buffer *evt = _evt;
3063 struct dwc3 *dwc = evt->dwc;
3064 unsigned long flags;
3065 irqreturn_t ret = IRQ_NONE;
3067 spin_lock_irqsave(&dwc->lock, flags);
3068 ret = dwc3_process_event_buf(evt);
3069 spin_unlock_irqrestore(&dwc->lock, flags);
3074 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3076 struct dwc3 *dwc = evt->dwc;
3081 if (pm_runtime_suspended(dwc->dev)) {
3082 pm_runtime_get(dwc->dev);
3083 disable_irq_nosync(dwc->irq_gadget);
3084 dwc->pending_events = true;
3089 * With PCIe legacy interrupt, test shows that top-half irq handler can
3090 * be called again after HW interrupt deassertion. Check if bottom-half
3091 * irq event handler completes before caching new event to prevent
3094 if (evt->flags & DWC3_EVENT_PENDING)
3097 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3098 count &= DWC3_GEVNTCOUNT_MASK;
3103 evt->flags |= DWC3_EVENT_PENDING;
3105 /* Mask interrupt */
3106 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3107 reg |= DWC3_GEVNTSIZ_INTMASK;
3108 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3110 amount = min(count, evt->length - evt->lpos);
3111 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3114 memcpy(evt->cache, evt->buf, count - amount);
3116 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3118 return IRQ_WAKE_THREAD;
3121 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3123 struct dwc3_event_buffer *evt = _evt;
3125 return dwc3_check_event_buf(evt);
3128 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3130 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3133 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3137 if (irq == -EPROBE_DEFER)
3140 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3144 if (irq == -EPROBE_DEFER)
3147 irq = platform_get_irq(dwc3_pdev, 0);
3151 if (irq != -EPROBE_DEFER)
3152 dev_err(dwc->dev, "missing peripheral IRQ\n");
3162 * dwc3_gadget_init - initializes gadget related registers
3163 * @dwc: pointer to our controller context structure
3165 * Returns 0 on success otherwise negative errno.
3167 int dwc3_gadget_init(struct dwc3 *dwc)
3172 irq = dwc3_gadget_get_irq(dwc);
3178 dwc->irq_gadget = irq;
3180 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3181 sizeof(*dwc->ep0_trb) * 2,
3182 &dwc->ep0_trb_addr, GFP_KERNEL);
3183 if (!dwc->ep0_trb) {
3184 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3189 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3190 if (!dwc->setup_buf) {
3195 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3196 &dwc->bounce_addr, GFP_KERNEL);
3202 init_completion(&dwc->ep0_in_setup);
3204 dwc->gadget.ops = &dwc3_gadget_ops;
3205 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3206 dwc->gadget.sg_supported = true;
3207 dwc->gadget.name = "dwc3-gadget";
3208 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
3211 * FIXME We might be setting max_speed to <SUPER, however versions
3212 * <2.20a of dwc3 have an issue with metastability (documented
3213 * elsewhere in this driver) which tells us we can't set max speed to
3214 * anything lower than SUPER.
3216 * Because gadget.max_speed is only used by composite.c and function
3217 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3218 * to happen so we avoid sending SuperSpeed Capability descriptor
3219 * together with our BOS descriptor as that could confuse host into
3220 * thinking we can handle super speed.
3222 * Note that, in fact, we won't even support GetBOS requests when speed
3223 * is less than super speed because we don't have means, yet, to tell
3224 * composite.c that we are USB 2.0 + LPM ECN.
3226 if (dwc->revision < DWC3_REVISION_220A)
3227 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3230 dwc->gadget.max_speed = dwc->maximum_speed;
3233 * REVISIT: Here we should clear all pending IRQs to be
3234 * sure we're starting from a well known location.
3237 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3241 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3243 dev_err(dwc->dev, "failed to register udc\n");
3250 dwc3_gadget_free_endpoints(dwc);
3253 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3257 kfree(dwc->setup_buf);
3260 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3261 dwc->ep0_trb, dwc->ep0_trb_addr);
3267 /* -------------------------------------------------------------------------- */
3269 void dwc3_gadget_exit(struct dwc3 *dwc)
3271 usb_del_gadget_udc(&dwc->gadget);
3272 dwc3_gadget_free_endpoints(dwc);
3273 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3275 kfree(dwc->setup_buf);
3276 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3277 dwc->ep0_trb, dwc->ep0_trb_addr);
3280 int dwc3_gadget_suspend(struct dwc3 *dwc)
3282 if (!dwc->gadget_driver)
3285 dwc3_gadget_run_stop(dwc, false, false);
3286 dwc3_disconnect_gadget(dwc);
3287 __dwc3_gadget_stop(dwc);
3292 int dwc3_gadget_resume(struct dwc3 *dwc)
3296 if (!dwc->gadget_driver)
3299 ret = __dwc3_gadget_start(dwc);
3303 ret = dwc3_gadget_run_stop(dwc, true, false);
3310 __dwc3_gadget_stop(dwc);
3316 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3318 if (dwc->pending_events) {
3319 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3320 dwc->pending_events = false;
3321 enable_irq(dwc->irq_gadget);