drivers/usb/gadget/udc/fsl_udc_core.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
   4  * All rights reserved.
   5  *
   6  * Author: Li Yang <leoli@freescale.com>
   7  *         Jiang Bo <tanya.jiang@freescale.com>
   8  *
   9  * Description:
  10  * Freescale high-speed USB SOC DR module device controller driver.
  11  * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
  12  * The driver is previously named as mpc_udc.  Based on bare board
  13  * code from Dave Liu and Shlomi Gridish.
  14  */
  15
  16 #undef VERBOSE
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/ioport.h>
  21 #include <linux/types.h>
  22 #include <linux/errno.h>
  23 #include <linux/err.h>
  24 #include <linux/slab.h>
  25 #include <linux/init.h>
  26 #include <linux/list.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/proc_fs.h>
  29 #include <linux/mm.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/device.h>
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/otg.h>
  35 #include <linux/dma-mapping.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38 #include <linux/dmapool.h>
  39 #include <linux/delay.h>
  40 #include <linux/of_device.h>
  41
  42 #include <asm/byteorder.h>
  43 #include <asm/io.h>
  44 #include <asm/unaligned.h>
  45 #include <asm/dma.h>
  46
  47 #include "fsl_usb2_udc.h"
  48
  49 #define DRIVER_DESC     "Freescale High-Speed USB SOC Device Controller driver"
  50 #define DRIVER_AUTHOR   "Li Yang/Jiang Bo"
  51 #define DRIVER_VERSION  "Apr 20, 2007"
  52
  53 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  54
  55 static const char driver_name[] = "fsl-usb2-udc";
  56 static const char driver_desc[] = DRIVER_DESC;
  57
  58 static struct usb_dr_device __iomem *dr_regs;
  59
  60 static struct usb_sys_interface __iomem *usb_sys_regs;
  61
  62 /* it is initialized in probe()  */
  63 static struct fsl_udc *udc_controller = NULL;
  64
  65 static const struct usb_endpoint_descriptor
  66 fsl_ep0_desc = {
  67         .bLength =              USB_DT_ENDPOINT_SIZE,
  68         .bDescriptorType =      USB_DT_ENDPOINT,
  69         .bEndpointAddress =     0,
  70         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  71         .wMaxPacketSize =       USB_MAX_CTRL_PAYLOAD,
  72 };
  73
  74 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
  75
  76 #ifdef CONFIG_PPC32
  77 /*
  78  * On some SoCs, the USB controller registers can be big or little endian,
  79  * depending on the version of the chip. In order to be able to run the
  80  * same kernel binary on 2 different versions of an SoC, the BE/LE decision
  81  * must be made at run time. _fsl_readl and fsl_writel are pointers to the
  82  * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
  83  * call through those pointers. Platform code for SoCs that have BE USB
  84  * registers should set pdata->big_endian_mmio flag.
  85  *
  86  * This also applies to controller-to-cpu accessors for the USB descriptors,
  87  * since their endianness is also SoC dependant. Platform code for SoCs that
  88  * have BE USB descriptors should set pdata->big_endian_desc flag.
  89  */
  90 static u32 _fsl_readl_be(const unsigned __iomem *p)
  91 {
  92         return in_be32(p);
  93 }
  94
  95 static u32 _fsl_readl_le(const unsigned __iomem *p)
  96 {
  97         return in_le32(p);
  98 }
  99
 100 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
 101 {
 102         out_be32(p, v);
 103 }
 104
 105 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
 106 {
 107         out_le32(p, v);
 108 }
 109
 110 static u32 (*_fsl_readl)(const unsigned __iomem *p);
 111 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
 112
 113 #define fsl_readl(p)            (*_fsl_readl)((p))
 114 #define fsl_writel(v, p)        (*_fsl_writel)((v), (p))
 115
 116 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
 117 {
 118         if (pdata->big_endian_mmio) {
 119                 _fsl_readl = _fsl_readl_be;
 120                 _fsl_writel = _fsl_writel_be;
 121         } else {
 122                 _fsl_readl = _fsl_readl_le;
 123                 _fsl_writel = _fsl_writel_le;
 124         }
 125 }
 126
 127 static inline u32 cpu_to_hc32(const u32 x)
 128 {
 129         return udc_controller->pdata->big_endian_desc
 130                 ? (__force u32)cpu_to_be32(x)
 131                 : (__force u32)cpu_to_le32(x);
 132 }
 133
 134 static inline u32 hc32_to_cpu(const u32 x)
 135 {
 136         return udc_controller->pdata->big_endian_desc
 137                 ? be32_to_cpu((__force __be32)x)
 138                 : le32_to_cpu((__force __le32)x);
 139 }
 140 #else /* !CONFIG_PPC32 */
 141 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
 142
 143 #define fsl_readl(addr)         readl(addr)
 144 #define fsl_writel(val32, addr) writel(val32, addr)
 145 #define cpu_to_hc32(x)          cpu_to_le32(x)
 146 #define hc32_to_cpu(x)          le32_to_cpu(x)
 147 #endif /* CONFIG_PPC32 */
 148
 149 /********************************************************************
 150  *      Internal Used Function
 151 ********************************************************************/
 152 /*-----------------------------------------------------------------
 153  * done() - retire a request; caller blocked irqs
 154  * @status : request status to be set, only works when
 155  *      request is still in progress.
 156  *--------------------------------------------------------------*/
 157 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
 158 __releases(ep->udc->lock)
 159 __acquires(ep->udc->lock)
 160 {
 161         struct fsl_udc *udc = NULL;
 162         unsigned char stopped = ep->stopped;
 163         struct ep_td_struct *curr_td, *next_td;
 164         int j;
 165
 166         udc = (struct fsl_udc *)ep->udc;
 167         /* Removed the req from fsl_ep->queue */
 168         list_del_init(&req->queue);
 169
 170         /* req.status should be set as -EINPROGRESS in ep_queue() */
 171         if (req->req.status == -EINPROGRESS)
 172                 req->req.status = status;
 173         else
 174                 status = req->req.status;
 175
 176         /* Free dtd for the request */
 177         next_td = req->head;
 178         for (j = 0; j < req->dtd_count; j++) {
 179                 curr_td = next_td;
 180                 if (j != req->dtd_count - 1) {
 181                         next_td = curr_td->next_td_virt;
 182                 }
 183                 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
 184         }
 185
 186         usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 187
 188         if (status && (status != -ESHUTDOWN))
 189                 VDBG("complete %s req %p stat %d len %u/%u",
 190                         ep->ep.name, &req->req, status,
 191                         req->req.actual, req->req.length);
 192
 193         ep->stopped = 1;
 194
 195         spin_unlock(&ep->udc->lock);
 196
 197         usb_gadget_giveback_request(&ep->ep, &req->req);
 198
 199         spin_lock(&ep->udc->lock);
 200         ep->stopped = stopped;
 201 }
 202
 203 /*-----------------------------------------------------------------
 204  * nuke(): delete all requests related to this ep
 205  * called with spinlock held
 206  *--------------------------------------------------------------*/
 207 static void nuke(struct fsl_ep *ep, int status)
 208 {
 209         ep->stopped = 1;
 210
 211         /* Flush fifo */
 212         fsl_ep_fifo_flush(&ep->ep);
 213
 214         /* Whether this eq has request linked */
 215         while (!list_empty(&ep->queue)) {
 216                 struct fsl_req *req = NULL;
 217
 218                 req = list_entry(ep->queue.next, struct fsl_req, queue);
 219                 done(ep, req, status);
 220         }
 221 }
 222
 223 /*------------------------------------------------------------------
 224         Internal Hardware related function
 225  ------------------------------------------------------------------*/
 226
 227 static int dr_controller_setup(struct fsl_udc *udc)
 228 {
 229         unsigned int tmp, portctrl, ep_num;
 230         unsigned int max_no_of_ep;
 231         unsigned int ctrl;
 232         unsigned long timeout;
 233
 234 #define FSL_UDC_RESET_TIMEOUT 1000
 235
 236         /* Config PHY interface */
 237         portctrl = fsl_readl(&dr_regs->portsc1);
 238         portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
 239         switch (udc->phy_mode) {
 240         case FSL_USB2_PHY_ULPI:
 241                 if (udc->pdata->have_sysif_regs) {
 242                         if (udc->pdata->controller_ver) {
 243                                 /* controller version 1.6 or above */
 244                                 ctrl = __raw_readl(&usb_sys_regs->control);
 245                                 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
 246                                 ctrl |= USB_CTRL_USB_EN;
 247                                 __raw_writel(ctrl, &usb_sys_regs->control);
 248                         }
 249                 }
 250                 portctrl |= PORTSCX_PTS_ULPI;
 251                 break;
 252         case FSL_USB2_PHY_UTMI_WIDE:
 253                 portctrl |= PORTSCX_PTW_16BIT;
 254                 /* fall through */
 255         case FSL_USB2_PHY_UTMI:
 256         case FSL_USB2_PHY_UTMI_DUAL:
 257                 if (udc->pdata->have_sysif_regs) {
 258                         if (udc->pdata->controller_ver) {
 259                                 /* controller version 1.6 or above */
 260                                 ctrl = __raw_readl(&usb_sys_regs->control);
 261                                 ctrl |= (USB_CTRL_UTMI_PHY_EN |
 262                                         USB_CTRL_USB_EN);
 263                                 __raw_writel(ctrl, &usb_sys_regs->control);
 264                                 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
 265                                         PHY CLK to become stable - 10ms*/
 266                         }
 267                 }
 268                 portctrl |= PORTSCX_PTS_UTMI;
 269                 break;
 270         case FSL_USB2_PHY_SERIAL:
 271                 portctrl |= PORTSCX_PTS_FSLS;
 272                 break;
 273         default:
 274                 return -EINVAL;
 275         }
 276         fsl_writel(portctrl, &dr_regs->portsc1);
 277
 278         /* Stop and reset the usb controller */
 279         tmp = fsl_readl(&dr_regs->usbcmd);
 280         tmp &= ~USB_CMD_RUN_STOP;
 281         fsl_writel(tmp, &dr_regs->usbcmd);
 282
 283         tmp = fsl_readl(&dr_regs->usbcmd);
 284         tmp |= USB_CMD_CTRL_RESET;
 285         fsl_writel(tmp, &dr_regs->usbcmd);
 286
 287         /* Wait for reset to complete */
 288         timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
 289         while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
 290                 if (time_after(jiffies, timeout)) {
 291                         ERR("udc reset timeout!\n");
 292                         return -ETIMEDOUT;
 293                 }
 294                 cpu_relax();
 295         }
 296
 297         /* Set the controller as device mode */
 298         tmp = fsl_readl(&dr_regs->usbmode);
 299         tmp &= ~USB_MODE_CTRL_MODE_MASK;        /* clear mode bits */
 300         tmp |= USB_MODE_CTRL_MODE_DEVICE;
 301         /* Disable Setup Lockout */
 302         tmp |= USB_MODE_SETUP_LOCK_OFF;
 303         if (udc->pdata->es)
 304                 tmp |= USB_MODE_ES;
 305         fsl_writel(tmp, &dr_regs->usbmode);
 306
 307         /* Clear the setup status */
 308         fsl_writel(0, &dr_regs->usbsts);
 309
 310         tmp = udc->ep_qh_dma;
 311         tmp &= USB_EP_LIST_ADDRESS_MASK;
 312         fsl_writel(tmp, &dr_regs->endpointlistaddr);
 313
 314         VDBG("vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x",
 315                 udc->ep_qh, (int)tmp,
 316                 fsl_readl(&dr_regs->endpointlistaddr));
 317
 318         max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
 319         for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
 320                 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
 321                 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
 322                 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
 323                 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
 324                 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
 325         }
 326         /* Config control enable i/o output, cpu endian register */
 327 #ifndef CONFIG_ARCH_MXC
 328         if (udc->pdata->have_sysif_regs) {
 329                 ctrl = __raw_readl(&usb_sys_regs->control);
 330                 ctrl |= USB_CTRL_IOENB;
 331                 __raw_writel(ctrl, &usb_sys_regs->control);
 332         }
 333 #endif
 334
 335 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
 336         /* Turn on cache snooping hardware, since some PowerPC platforms
 337          * wholly rely on hardware to deal with cache coherent. */
 338
 339         if (udc->pdata->have_sysif_regs) {
 340                 /* Setup Snooping for all the 4GB space */
 341                 tmp = SNOOP_SIZE_2GB;   /* starts from 0x0, size 2G */
 342                 __raw_writel(tmp, &usb_sys_regs->snoop1);
 343                 tmp |= 0x80000000;      /* starts from 0x8000000, size 2G */
 344                 __raw_writel(tmp, &usb_sys_regs->snoop2);
 345         }
 346 #endif
 347
 348         return 0;
 349 }
 350
 351 /* Enable DR irq and set controller to run state */
 352 static void dr_controller_run(struct fsl_udc *udc)
 353 {
 354         u32 temp;
 355
 356         /* Enable DR irq reg */
 357         temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
 358                 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
 359                 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
 360
 361         fsl_writel(temp, &dr_regs->usbintr);
 362
 363         /* Clear stopped bit */
 364         udc->stopped = 0;
 365
 366         /* Set the controller as device mode */
 367         temp = fsl_readl(&dr_regs->usbmode);
 368         temp |= USB_MODE_CTRL_MODE_DEVICE;
 369         fsl_writel(temp, &dr_regs->usbmode);
 370
 371         /* Set controller to Run */
 372         temp = fsl_readl(&dr_regs->usbcmd);
 373         temp |= USB_CMD_RUN_STOP;
 374         fsl_writel(temp, &dr_regs->usbcmd);
 375 }
 376
 377 static void dr_controller_stop(struct fsl_udc *udc)
 378 {
 379         unsigned int tmp;
 380
 381         pr_debug("%s\n", __func__);
 382
 383         /* if we're in OTG mode, and the Host is currently using the port,
 384          * stop now and don't rip the controller out from under the
 385          * ehci driver
 386          */
 387         if (udc->gadget.is_otg) {
 388                 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
 389                         pr_debug("udc: Leaving early\n");
 390                         return;
 391                 }
 392         }
 393
 394         /* disable all INTR */
 395         fsl_writel(0, &dr_regs->usbintr);
 396
 397         /* Set stopped bit for isr */
 398         udc->stopped = 1;
 399
 400         /* disable IO output */
 401 /*      usb_sys_regs->control = 0; */
 402
 403         /* set controller to Stop */
 404         tmp = fsl_readl(&dr_regs->usbcmd);
 405         tmp &= ~USB_CMD_RUN_STOP;
 406         fsl_writel(tmp, &dr_regs->usbcmd);
 407 }
 408
 409 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
 410                         unsigned char ep_type)
 411 {
 412         unsigned int tmp_epctrl = 0;
 413
 414         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 415         if (dir) {
 416                 if (ep_num)
 417                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 418                 tmp_epctrl |= EPCTRL_TX_ENABLE;
 419                 tmp_epctrl &= ~EPCTRL_TX_TYPE;
 420                 tmp_epctrl |= ((unsigned int)(ep_type)
 421                                 << EPCTRL_TX_EP_TYPE_SHIFT);
 422         } else {
 423                 if (ep_num)
 424                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 425                 tmp_epctrl |= EPCTRL_RX_ENABLE;
 426                 tmp_epctrl &= ~EPCTRL_RX_TYPE;
 427                 tmp_epctrl |= ((unsigned int)(ep_type)
 428                                 << EPCTRL_RX_EP_TYPE_SHIFT);
 429         }
 430
 431         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 432 }
 433
 434 static void
 435 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
 436 {
 437         u32 tmp_epctrl = 0;
 438
 439         tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 440
 441         if (value) {
 442                 /* set the stall bit */
 443                 if (dir)
 444                         tmp_epctrl |= EPCTRL_TX_EP_STALL;
 445                 else
 446                         tmp_epctrl |= EPCTRL_RX_EP_STALL;
 447         } else {
 448                 /* clear the stall bit and reset data toggle */
 449                 if (dir) {
 450                         tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
 451                         tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
 452                 } else {
 453                         tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
 454                         tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
 455                 }
 456         }
 457         fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
 458 }
 459
 460 /* Get stall status of a specific ep
 461    Return: 0: not stalled; 1:stalled */
 462 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
 463 {
 464         u32 epctrl;
 465
 466         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 467         if (dir)
 468                 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
 469         else
 470                 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
 471 }
 472
 473 /********************************************************************
 474         Internal Structure Build up functions
 475 ********************************************************************/
 476
 477 /*------------------------------------------------------------------
 478 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
 479  * @zlt: Zero Length Termination Select (1: disable; 0: enable)
 480  * @mult: Mult field
 481  ------------------------------------------------------------------*/
 482 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
 483                 unsigned char dir, unsigned char ep_type,
 484                 unsigned int max_pkt_len,
 485                 unsigned int zlt, unsigned char mult)
 486 {
 487         struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
 488         unsigned int tmp = 0;
 489
 490         /* set the Endpoint Capabilites in QH */
 491         switch (ep_type) {
 492         case USB_ENDPOINT_XFER_CONTROL:
 493                 /* Interrupt On Setup (IOS). for control ep  */
 494                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 495                         | EP_QUEUE_HEAD_IOS;
 496                 break;
 497         case USB_ENDPOINT_XFER_ISOC:
 498                 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
 499                         | (mult << EP_QUEUE_HEAD_MULT_POS);
 500                 break;
 501         case USB_ENDPOINT_XFER_BULK:
 502         case USB_ENDPOINT_XFER_INT:
 503                 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
 504                 break;
 505         default:
 506                 VDBG("error ep type is %d", ep_type);
 507                 return;
 508         }
 509         if (zlt)
 510                 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
 511
 512         p_QH->max_pkt_length = cpu_to_hc32(tmp);
 513         p_QH->next_dtd_ptr = 1;
 514         p_QH->size_ioc_int_sts = 0;
 515 }
 516
 517 /* Setup qh structure and ep register for ep0. */
 518 static void ep0_setup(struct fsl_udc *udc)
 519 {
 520         /* the initialization of an ep includes: fields in QH, Regs,
 521          * fsl_ep struct */
 522         struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
 523                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 524         struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
 525                         USB_MAX_CTRL_PAYLOAD, 0, 0);
 526         dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
 527         dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
 528
 529         return;
 530
 531 }
 532
 533 /***********************************************************************
 534                 Endpoint Management Functions
 535 ***********************************************************************/
 536
 537 /*-------------------------------------------------------------------------
 538  * when configurations are set, or when interface settings change
 539  * for example the do_set_interface() in gadget layer,
 540  * the driver will enable or disable the relevant endpoints
 541  * ep0 doesn't use this routine. It is always enabled.
 542 -------------------------------------------------------------------------*/
 543 static int fsl_ep_enable(struct usb_ep *_ep,
 544                 const struct usb_endpoint_descriptor *desc)
 545 {
 546         struct fsl_udc *udc = NULL;
 547         struct fsl_ep *ep = NULL;
 548         unsigned short max = 0;
 549         unsigned char mult = 0, zlt;
 550         int retval = -EINVAL;
 551         unsigned long flags = 0;
 552
 553         ep = container_of(_ep, struct fsl_ep, ep);
 554
 555         /* catch various bogus parameters */
 556         if (!_ep || !desc
 557                         || (desc->bDescriptorType != USB_DT_ENDPOINT))
 558                 return -EINVAL;
 559
 560         udc = ep->udc;
 561
 562         if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
 563                 return -ESHUTDOWN;
 564
 565         max = usb_endpoint_maxp(desc);
 566
 567         /* Disable automatic zlp generation.  Driver is responsible to indicate
 568          * explicitly through req->req.zero.  This is needed to enable multi-td
 569          * request. */
 570         zlt = 1;
 571
 572         /* Assume the max packet size from gadget is always correct */
 573         switch (desc->bmAttributes & 0x03) {
 574         case USB_ENDPOINT_XFER_CONTROL:
 575         case USB_ENDPOINT_XFER_BULK:
 576         case USB_ENDPOINT_XFER_INT:
 577                 /* mult = 0.  Execute N Transactions as demonstrated by
 578                  * the USB variable length packet protocol where N is
 579                  * computed using the Maximum Packet Length (dQH) and
 580                  * the Total Bytes field (dTD) */
 581                 mult = 0;
 582                 break;
 583         case USB_ENDPOINT_XFER_ISOC:
 584                 /* Calculate transactions needed for high bandwidth iso */
 585                 mult = usb_endpoint_maxp_mult(desc);
 586                 /* 3 transactions at most */
 587                 if (mult > 3)
 588                         goto en_done;
 589                 break;
 590         default:
 591                 goto en_done;
 592         }
 593
 594         spin_lock_irqsave(&udc->lock, flags);
 595         ep->ep.maxpacket = max;
 596         ep->ep.desc = desc;
 597         ep->stopped = 0;
 598
 599         /* Controller related setup */
 600         /* Init EPx Queue Head (Ep Capabilites field in QH
 601          * according to max, zlt, mult) */
 602         struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
 603                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 604                                         ?  USB_SEND : USB_RECV),
 605                         (unsigned char) (desc->bmAttributes
 606                                         & USB_ENDPOINT_XFERTYPE_MASK),
 607                         max, zlt, mult);
 608
 609         /* Init endpoint ctrl register */
 610         dr_ep_setup((unsigned char) ep_index(ep),
 611                         (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
 612                                         ? USB_SEND : USB_RECV),
 613                         (unsigned char) (desc->bmAttributes
 614                                         & USB_ENDPOINT_XFERTYPE_MASK));
 615
 616         spin_unlock_irqrestore(&udc->lock, flags);
 617         retval = 0;
 618
 619         VDBG("enabled %s (ep%d%s) maxpacket %d",ep->ep.name,
 620                         ep->ep.desc->bEndpointAddress & 0x0f,
 621                         (desc->bEndpointAddress & USB_DIR_IN)
 622                                 ? "in" : "out", max);
 623 en_done:
 624         return retval;
 625 }
 626
 627 /*---------------------------------------------------------------------
 628  * @ep : the ep being unconfigured. May not be ep0
 629  * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
 630 *---------------------------------------------------------------------*/
 631 static int fsl_ep_disable(struct usb_ep *_ep)
 632 {
 633         struct fsl_udc *udc = NULL;
 634         struct fsl_ep *ep = NULL;
 635         unsigned long flags = 0;
 636         u32 epctrl;
 637         int ep_num;
 638
 639         ep = container_of(_ep, struct fsl_ep, ep);
 640         if (!_ep || !ep->ep.desc) {
 641                 VDBG("%s not enabled", _ep ? ep->ep.name : NULL);
 642                 return -EINVAL;
 643         }
 644
 645         /* disable ep on controller */
 646         ep_num = ep_index(ep);
 647         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 648         if (ep_is_in(ep)) {
 649                 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
 650                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
 651         } else {
 652                 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
 653                 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
 654         }
 655         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 656
 657         udc = (struct fsl_udc *)ep->udc;
 658         spin_lock_irqsave(&udc->lock, flags);
 659
 660         /* nuke all pending requests (does flush) */
 661         nuke(ep, -ESHUTDOWN);
 662
 663         ep->ep.desc = NULL;
 664         ep->stopped = 1;
 665         spin_unlock_irqrestore(&udc->lock, flags);
 666
 667         VDBG("disabled %s OK", _ep->name);
 668         return 0;
 669 }
 670
 671 /*---------------------------------------------------------------------
 672  * allocate a request object used by this endpoint
 673  * the main operation is to insert the req->queue to the eq->queue
 674  * Returns the request, or null if one could not be allocated
 675 *---------------------------------------------------------------------*/
 676 static struct usb_request *
 677 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 678 {
 679         struct fsl_req *req = NULL;
 680
 681         req = kzalloc(sizeof *req, gfp_flags);
 682         if (!req)
 683                 return NULL;
 684
 685         req->req.dma = DMA_ADDR_INVALID;
 686         INIT_LIST_HEAD(&req->queue);
 687
 688         return &req->req;
 689 }
 690
 691 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
 692 {
 693         struct fsl_req *req = NULL;
 694
 695         req = container_of(_req, struct fsl_req, req);
 696
 697         if (_req)
 698                 kfree(req);
 699 }
 700
 701 /* Actually add a dTD chain to an empty dQH and let go */
 702 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
 703 {
 704         struct ep_queue_head *qh = get_qh_by_ep(ep);
 705
 706         /* Write dQH next pointer and terminate bit to 0 */
 707         qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
 708                         & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
 709
 710         /* Clear active and halt bit */
 711         qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
 712                                         | EP_QUEUE_HEAD_STATUS_HALT));
 713
 714         /* Ensure that updates to the QH will occur before priming. */
 715         wmb();
 716
 717         /* Prime endpoint by writing correct bit to ENDPTPRIME */
 718         fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
 719                         : (1 << (ep_index(ep))), &dr_regs->endpointprime);
 720 }
 721
 722 /* Add dTD chain to the dQH of an EP */
 723 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
 724 {
 725         u32 temp, bitmask, tmp_stat;
 726
 727         /* VDBG("QH addr Register 0x%8x", dr_regs->endpointlistaddr);
 728         VDBG("ep_qh[%d] addr is 0x%8x", i, (u32)&(ep->udc->ep_qh[i])); */
 729
 730         bitmask = ep_is_in(ep)
 731                 ? (1 << (ep_index(ep) + 16))
 732                 : (1 << (ep_index(ep)));
 733
 734         /* check if the pipe is empty */
 735         if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
 736                 /* Add td to the end */
 737                 struct fsl_req *lastreq;
 738                 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
 739                 lastreq->tail->next_td_ptr =
 740                         cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
 741                 /* Ensure dTD's next dtd pointer to be updated */
 742                 wmb();
 743                 /* Read prime bit, if 1 goto done */
 744                 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
 745                         return;
 746
 747                 do {
 748                         /* Set ATDTW bit in USBCMD */
 749                         temp = fsl_readl(&dr_regs->usbcmd);
 750                         fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
 751
 752                         /* Read correct status bit */
 753                         tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
 754
 755                 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
 756
 757                 /* Write ATDTW bit to 0 */
 758                 temp = fsl_readl(&dr_regs->usbcmd);
 759                 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
 760
 761                 if (tmp_stat)
 762                         return;
 763         }
 764
 765         fsl_prime_ep(ep, req->head);
 766 }
 767
 768 /* Fill in the dTD structure
 769  * @req: request that the transfer belongs to
 770  * @length: return actually data length of the dTD
 771  * @dma: return dma address of the dTD
 772  * @is_last: return flag if it is the last dTD of the request
 773  * return: pointer to the built dTD */
 774 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
 775                 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
 776 {
 777         u32 swap_temp;
 778         struct ep_td_struct *dtd;
 779
 780         /* how big will this transfer be? */
 781         *length = min(req->req.length - req->req.actual,
 782                         (unsigned)EP_MAX_LENGTH_TRANSFER);
 783
 784         dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
 785         if (dtd == NULL)
 786                 return dtd;
 787
 788         dtd->td_dma = *dma;
 789         /* Clear reserved field */
 790         swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
 791         swap_temp &= ~DTD_RESERVED_FIELDS;
 792         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 793
 794         /* Init all of buffer page pointers */
 795         swap_temp = (u32) (req->req.dma + req->req.actual);
 796         dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
 797         dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
 798         dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
 799         dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
 800         dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
 801
 802         req->req.actual += *length;
 803
 804         /* zlp is needed if req->req.zero is set */
 805         if (req->req.zero) {
 806                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 807                         *is_last = 1;
 808                 else
 809                         *is_last = 0;
 810         } else if (req->req.length == req->req.actual)
 811                 *is_last = 1;
 812         else
 813                 *is_last = 0;
 814
 815         if ((*is_last) == 0)
 816                 VDBG("multi-dtd request!");
 817         /* Fill in the transfer size; set active bit */
 818         swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
 819
 820         /* Enable interrupt for the last dtd of a request */
 821         if (*is_last && !req->req.no_interrupt)
 822                 swap_temp |= DTD_IOC;
 823
 824         dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
 825
 826         mb();
 827
 828         VDBG("length = %d address= 0x%x", *length, (int)*dma);
 829
 830         return dtd;
 831 }
 832
 833 /* Generate dtd chain for a request */
 834 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
 835 {
 836         unsigned        count;
 837         int             is_last;
 838         int             is_first =1;
 839         struct ep_td_struct     *last_dtd = NULL, *dtd;
 840         dma_addr_t dma;
 841
 842         do {
 843                 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
 844                 if (dtd == NULL)
 845                         return -ENOMEM;
 846
 847                 if (is_first) {
 848                         is_first = 0;
 849                         req->head = dtd;
 850                 } else {
 851                         last_dtd->next_td_ptr = cpu_to_hc32(dma);
 852                         last_dtd->next_td_virt = dtd;
 853                 }
 854                 last_dtd = dtd;
 855
 856                 req->dtd_count++;
 857         } while (!is_last);
 858
 859         dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
 860
 861         req->tail = dtd;
 862
 863         return 0;
 864 }
 865
 866 /* queues (submits) an I/O request to an endpoint */
 867 static int
 868 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 869 {
 870         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 871         struct fsl_req *req = container_of(_req, struct fsl_req, req);
 872         struct fsl_udc *udc;
 873         unsigned long flags;
 874         int ret;
 875
 876         /* catch various bogus parameters */
 877         if (!_req || !req->req.complete || !req->req.buf
 878                         || !list_empty(&req->queue)) {
 879                 VDBG("%s, bad params", __func__);
 880                 return -EINVAL;
 881         }
 882         if (unlikely(!_ep || !ep->ep.desc)) {
 883                 VDBG("%s, bad ep", __func__);
 884                 return -EINVAL;
 885         }
 886         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
 887                 if (req->req.length > ep->ep.maxpacket)
 888                         return -EMSGSIZE;
 889         }
 890
 891         udc = ep->udc;
 892         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
 893                 return -ESHUTDOWN;
 894
 895         req->ep = ep;
 896
 897         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
 898         if (ret)
 899                 return ret;
 900
 901         req->req.status = -EINPROGRESS;
 902         req->req.actual = 0;
 903         req->dtd_count = 0;
 904
 905         /* build dtds and push them to device queue */
 906         if (!fsl_req_to_dtd(req, gfp_flags)) {
 907                 spin_lock_irqsave(&udc->lock, flags);
 908                 fsl_queue_td(ep, req);
 909         } else {
 910                 return -ENOMEM;
 911         }
 912
 913         /* irq handler advances the queue */
 914         if (req != NULL)
 915                 list_add_tail(&req->queue, &ep->queue);
 916         spin_unlock_irqrestore(&udc->lock, flags);
 917
 918         return 0;
 919 }
 920
 921 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 922 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 923 {
 924         struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
 925         struct fsl_req *req;
 926         unsigned long flags;
 927         int ep_num, stopped, ret = 0;
 928         u32 epctrl;
 929
 930         if (!_ep || !_req)
 931                 return -EINVAL;
 932
 933         spin_lock_irqsave(&ep->udc->lock, flags);
 934         stopped = ep->stopped;
 935
 936         /* Stop the ep before we deal with the queue */
 937         ep->stopped = 1;
 938         ep_num = ep_index(ep);
 939         epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 940         if (ep_is_in(ep))
 941                 epctrl &= ~EPCTRL_TX_ENABLE;
 942         else
 943                 epctrl &= ~EPCTRL_RX_ENABLE;
 944         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 945
 946         /* make sure it's actually queued on this endpoint */
 947         list_for_each_entry(req, &ep->queue, queue) {
 948                 if (&req->req == _req)
 949                         break;
 950         }
 951         if (&req->req != _req) {
 952                 ret = -EINVAL;
 953                 goto out;
 954         }
 955
 956         /* The request is in progress, or completed but not dequeued */
 957         if (ep->queue.next == &req->queue) {
 958                 _req->status = -ECONNRESET;
 959                 fsl_ep_fifo_flush(_ep); /* flush current transfer */
 960
 961                 /* The request isn't the last request in this ep queue */
 962                 if (req->queue.next != &ep->queue) {
 963                         struct fsl_req *next_req;
 964
 965                         next_req = list_entry(req->queue.next, struct fsl_req,
 966                                         queue);
 967
 968                         /* prime with dTD of next request */
 969                         fsl_prime_ep(ep, next_req->head);
 970                 }
 971         /* The request hasn't been processed, patch up the TD chain */
 972         } else {
 973                 struct fsl_req *prev_req;
 974
 975                 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
 976                 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
 977         }
 978
 979         done(ep, req, -ECONNRESET);
 980
 981         /* Enable EP */
 982 out:    epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
 983         if (ep_is_in(ep))
 984                 epctrl |= EPCTRL_TX_ENABLE;
 985         else
 986                 epctrl |= EPCTRL_RX_ENABLE;
 987         fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
 988         ep->stopped = stopped;
 989
 990         spin_unlock_irqrestore(&ep->udc->lock, flags);
 991         return ret;
 992 }
 993
 994 /*-------------------------------------------------------------------------*/
 995
 996 /*-----------------------------------------------------------------
 997  * modify the endpoint halt feature
 998  * @ep: the non-isochronous endpoint being stalled
 999  * @value: 1--set halt  0--clear halt
1000  * Returns zero, or a negative error code.
1001 *----------------------------------------------------------------*/
1002 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
1003 {
1004         struct fsl_ep *ep = NULL;
1005         unsigned long flags = 0;
1006         int status = -EOPNOTSUPP;       /* operation not supported */
1007         unsigned char ep_dir = 0, ep_num = 0;
1008         struct fsl_udc *udc = NULL;
1009
1010         ep = container_of(_ep, struct fsl_ep, ep);
1011         udc = ep->udc;
1012         if (!_ep || !ep->ep.desc) {
1013                 status = -EINVAL;
1014                 goto out;
1015         }
1016
1017         if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1018                 status = -EOPNOTSUPP;
1019                 goto out;
1020         }
1021
1022         /* Attempt to halt IN ep will fail if any transfer requests
1023          * are still queue */
1024         if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1025                 status = -EAGAIN;
1026                 goto out;
1027         }
1028
1029         status = 0;
1030         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1031         ep_num = (unsigned char)(ep_index(ep));
1032         spin_lock_irqsave(&ep->udc->lock, flags);
1033         dr_ep_change_stall(ep_num, ep_dir, value);
1034         spin_unlock_irqrestore(&ep->udc->lock, flags);
1035
1036         if (ep_index(ep) == 0) {
1037                 udc->ep0_state = WAIT_FOR_SETUP;
1038                 udc->ep0_dir = 0;
1039         }
1040 out:
1041         VDBG(" %s %s halt stat %d", ep->ep.name,
1042                         value ?  "set" : "clear", status);
1043
1044         return status;
1045 }
1046
1047 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1048 {
1049         struct fsl_ep *ep;
1050         struct fsl_udc *udc;
1051         int size = 0;
1052         u32 bitmask;
1053         struct ep_queue_head *qh;
1054
1055         if (!_ep || _ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1056                 return -ENODEV;
1057
1058         ep = container_of(_ep, struct fsl_ep, ep);
1059
1060         udc = (struct fsl_udc *)ep->udc;
1061
1062         if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1063                 return -ESHUTDOWN;
1064
1065         qh = get_qh_by_ep(ep);
1066
1067         bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1068             (1 << (ep_index(ep)));
1069
1070         if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1071                 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1072                     >> DTD_LENGTH_BIT_POS;
1073
1074         pr_debug("%s %u\n", __func__, size);
1075         return size;
1076 }
1077
1078 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1079 {
1080         struct fsl_ep *ep;
1081         int ep_num, ep_dir;
1082         u32 bits;
1083         unsigned long timeout;
1084 #define FSL_UDC_FLUSH_TIMEOUT 1000
1085
1086         if (!_ep) {
1087                 return;
1088         } else {
1089                 ep = container_of(_ep, struct fsl_ep, ep);
1090                 if (!ep->ep.desc)
1091                         return;
1092         }
1093         ep_num = ep_index(ep);
1094         ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1095
1096         if (ep_num == 0)
1097                 bits = (1 << 16) | 1;
1098         else if (ep_dir == USB_SEND)
1099                 bits = 1 << (16 + ep_num);
1100         else
1101                 bits = 1 << ep_num;
1102
1103         timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1104         do {
1105                 fsl_writel(bits, &dr_regs->endptflush);
1106
1107                 /* Wait until flush complete */
1108                 while (fsl_readl(&dr_regs->endptflush)) {
1109                         if (time_after(jiffies, timeout)) {
1110                                 ERR("ep flush timeout\n");
1111                                 return;
1112                         }
1113                         cpu_relax();
1114                 }
1115                 /* See if we need to flush again */
1116         } while (fsl_readl(&dr_regs->endptstatus) & bits);
1117 }
1118
1119 static const struct usb_ep_ops fsl_ep_ops = {
1120         .enable = fsl_ep_enable,
1121         .disable = fsl_ep_disable,
1122
1123         .alloc_request = fsl_alloc_request,
1124         .free_request = fsl_free_request,
1125
1126         .queue = fsl_ep_queue,
1127         .dequeue = fsl_ep_dequeue,
1128
1129         .set_halt = fsl_ep_set_halt,
1130         .fifo_status = fsl_ep_fifo_status,
1131         .fifo_flush = fsl_ep_fifo_flush,        /* flush fifo */
1132 };
1133
1134 /*-------------------------------------------------------------------------
1135                 Gadget Driver Layer Operations
1136 -------------------------------------------------------------------------*/
1137
1138 /*----------------------------------------------------------------------
1139  * Get the current frame number (from DR frame_index Reg )
1140  *----------------------------------------------------------------------*/
1141 static int fsl_get_frame(struct usb_gadget *gadget)
1142 {
1143         return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1144 }
1145
1146 /*-----------------------------------------------------------------------
1147  * Tries to wake up the host connected to this gadget
1148  -----------------------------------------------------------------------*/
1149 static int fsl_wakeup(struct usb_gadget *gadget)
1150 {
1151         struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1152         u32 portsc;
1153
1154         /* Remote wakeup feature not enabled by host */
1155         if (!udc->remote_wakeup)
1156                 return -ENOTSUPP;
1157
1158         portsc = fsl_readl(&dr_regs->portsc1);
1159         /* not suspended? */
1160         if (!(portsc & PORTSCX_PORT_SUSPEND))
1161                 return 0;
1162         /* trigger force resume */
1163         portsc |= PORTSCX_PORT_FORCE_RESUME;
1164         fsl_writel(portsc, &dr_regs->portsc1);
1165         return 0;
1166 }
1167
1168 static int can_pullup(struct fsl_udc *udc)
1169 {
1170         return udc->driver && udc->softconnect && udc->vbus_active;
1171 }
1172
1173 /* Notify controller that VBUS is powered, Called by whatever
1174    detects VBUS sessions */
1175 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1176 {
1177         struct fsl_udc  *udc;
1178         unsigned long   flags;
1179
1180         udc = container_of(gadget, struct fsl_udc, gadget);
1181         spin_lock_irqsave(&udc->lock, flags);
1182         VDBG("VBUS %s", is_active ? "on" : "off");
1183         udc->vbus_active = (is_active != 0);
1184         if (can_pullup(udc))
1185                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1186                                 &dr_regs->usbcmd);
1187         else
1188                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1189                                 &dr_regs->usbcmd);
1190         spin_unlock_irqrestore(&udc->lock, flags);
1191         return 0;
1192 }
1193
1194 /* constrain controller's VBUS power usage
1195  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1196  * reporting how much power the device may consume.  For example, this
1197  * could affect how quickly batteries are recharged.
1198  *
1199  * Returns zero on success, else negative errno.
1200  */
1201 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1202 {
1203         struct fsl_udc *udc;
1204
1205         udc = container_of(gadget, struct fsl_udc, gadget);
1206         if (!IS_ERR_OR_NULL(udc->transceiver))
1207                 return usb_phy_set_power(udc->transceiver, mA);
1208         return -ENOTSUPP;
1209 }
1210
1211 /* Change Data+ pullup status
1212  * this func is used by usb_gadget_connect/disconnect
1213  */
1214 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1215 {
1216         struct fsl_udc *udc;
1217
1218         udc = container_of(gadget, struct fsl_udc, gadget);
1219
1220         if (!udc->vbus_active)
1221                 return -EOPNOTSUPP;
1222
1223         udc->softconnect = (is_on != 0);
1224         if (can_pullup(udc))
1225                 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1226                                 &dr_regs->usbcmd);
1227         else
1228                 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1229                                 &dr_regs->usbcmd);
1230
1231         return 0;
1232 }
1233
1234 static int fsl_udc_start(struct usb_gadget *g,
1235                 struct usb_gadget_driver *driver);
1236 static int fsl_udc_stop(struct usb_gadget *g);
1237
1238 static const struct usb_gadget_ops fsl_gadget_ops = {
1239         .get_frame = fsl_get_frame,
1240         .wakeup = fsl_wakeup,
1241 /*      .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1242         .vbus_session = fsl_vbus_session,
1243         .vbus_draw = fsl_vbus_draw,
1244         .pullup = fsl_pullup,
1245         .udc_start = fsl_udc_start,
1246         .udc_stop = fsl_udc_stop,
1247 };
1248
1249 /*
1250  * Empty complete function used by this driver to fill in the req->complete
1251  * field when creating a request since the complete field is mandatory.
1252  */
1253 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1254
1255 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1256    on new transaction */
1257 static void ep0stall(struct fsl_udc *udc)
1258 {
1259         u32 tmp;
1260
1261         /* must set tx and rx to stall at the same time */
1262         tmp = fsl_readl(&dr_regs->endptctrl[0]);
1263         tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1264         fsl_writel(tmp, &dr_regs->endptctrl[0]);
1265         udc->ep0_state = WAIT_FOR_SETUP;
1266         udc->ep0_dir = 0;
1267 }
1268
1269 /* Prime a status phase for ep0 */
1270 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1271 {
1272         struct fsl_req *req = udc->status_req;
1273         struct fsl_ep *ep;
1274         int ret;
1275
1276         if (direction == EP_DIR_IN)
1277                 udc->ep0_dir = USB_DIR_IN;
1278         else
1279                 udc->ep0_dir = USB_DIR_OUT;
1280
1281         ep = &udc->eps[0];
1282         if (udc->ep0_state != DATA_STATE_XMIT)
1283                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1284
1285         req->ep = ep;
1286         req->req.length = 0;
1287         req->req.status = -EINPROGRESS;
1288         req->req.actual = 0;
1289         req->req.complete = fsl_noop_complete;
1290         req->dtd_count = 0;
1291
1292         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1293         if (ret)
1294                 return ret;
1295
1296         if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1297                 fsl_queue_td(ep, req);
1298         else
1299                 return -ENOMEM;
1300
1301         list_add_tail(&req->queue, &ep->queue);
1302
1303         return 0;
1304 }
1305
1306 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1307 {
1308         struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1309
1310         if (ep->ep.name)
1311                 nuke(ep, -ESHUTDOWN);
1312 }
1313
1314 /*
1315  * ch9 Set address
1316  */
1317 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1318 {
1319         /* Save the new address to device struct */
1320         udc->device_address = (u8) value;
1321         /* Update usb state */
1322         udc->usb_state = USB_STATE_ADDRESS;
1323         /* Status phase */
1324         if (ep0_prime_status(udc, EP_DIR_IN))
1325                 ep0stall(udc);
1326 }
1327
1328 /*
1329  * ch9 Get status
1330  */
1331 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1332                 u16 index, u16 length)
1333 {
1334         u16 tmp = 0;            /* Status, cpu endian */
1335         struct fsl_req *req;
1336         struct fsl_ep *ep;
1337         int ret;
1338
1339         ep = &udc->eps[0];
1340
1341         if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1342                 /* Get device status */
1343                 tmp = udc->gadget.is_selfpowered;
1344                 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1345         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1346                 /* Get interface status */
1347                 /* We don't have interface information in udc driver */
1348                 tmp = 0;
1349         } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1350                 /* Get endpoint status */
1351                 struct fsl_ep *target_ep;
1352
1353                 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1354
1355                 /* stall if endpoint doesn't exist */
1356                 if (!target_ep->ep.desc)
1357                         goto stall;
1358                 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1359                                 << USB_ENDPOINT_HALT;
1360         }
1361
1362         udc->ep0_dir = USB_DIR_IN;
1363         /* Borrow the per device status_req */
1364         req = udc->status_req;
1365         /* Fill in the reqest structure */
1366         *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1367
1368         req->ep = ep;
1369         req->req.length = 2;
1370         req->req.status = -EINPROGRESS;
1371         req->req.actual = 0;
1372         req->req.complete = fsl_noop_complete;
1373         req->dtd_count = 0;
1374
1375         ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1376         if (ret)
1377                 goto stall;
1378
1379         /* prime the data phase */
1380         if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1381                 fsl_queue_td(ep, req);
1382         else                    /* no mem */
1383                 goto stall;
1384
1385         list_add_tail(&req->queue, &ep->queue);
1386         udc->ep0_state = DATA_STATE_XMIT;
1387         if (ep0_prime_status(udc, EP_DIR_OUT))
1388                 ep0stall(udc);
1389
1390         return;
1391 stall:
1392         ep0stall(udc);
1393 }
1394
1395 static void setup_received_irq(struct fsl_udc *udc,
1396                 struct usb_ctrlrequest *setup)
1397 __releases(udc->lock)
1398 __acquires(udc->lock)
1399 {
1400         u16 wValue = le16_to_cpu(setup->wValue);
1401         u16 wIndex = le16_to_cpu(setup->wIndex);
1402         u16 wLength = le16_to_cpu(setup->wLength);
1403
1404         udc_reset_ep_queue(udc, 0);
1405
1406         /* We process some stardard setup requests here */
1407         switch (setup->bRequest) {
1408         case USB_REQ_GET_STATUS:
1409                 /* Data+Status phase from udc */
1410                 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1411                                         != (USB_DIR_IN | USB_TYPE_STANDARD))
1412                         break;
1413                 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1414                 return;
1415
1416         case USB_REQ_SET_ADDRESS:
1417                 /* Status phase from udc */
1418                 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1419                                                 | USB_RECIP_DEVICE))
1420                         break;
1421                 ch9setaddress(udc, wValue, wIndex, wLength);
1422                 return;
1423
1424         case USB_REQ_CLEAR_FEATURE:
1425         case USB_REQ_SET_FEATURE:
1426                 /* Status phase from udc */
1427         {
1428                 int rc = -EOPNOTSUPP;
1429                 u16 ptc = 0;
1430
1431                 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1432                                 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1433                         int pipe = get_pipe_by_windex(wIndex);
1434                         struct fsl_ep *ep;
1435
1436                         if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1437                                 break;
1438                         ep = get_ep_by_pipe(udc, pipe);
1439
1440                         spin_unlock(&udc->lock);
1441                         rc = fsl_ep_set_halt(&ep->ep,
1442                                         (setup->bRequest == USB_REQ_SET_FEATURE)
1443                                                 ? 1 : 0);
1444                         spin_lock(&udc->lock);
1445
1446                 } else if ((setup->bRequestType & (USB_RECIP_MASK
1447                                 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1448                                 | USB_TYPE_STANDARD)) {
1449                         /* Note: The driver has not include OTG support yet.
1450                          * This will be set when OTG support is added */
1451                         if (wValue == USB_DEVICE_TEST_MODE)
1452                                 ptc = wIndex >> 8;
1453                         else if (gadget_is_otg(&udc->gadget)) {
1454                                 if (setup->bRequest ==
1455                                     USB_DEVICE_B_HNP_ENABLE)
1456                                         udc->gadget.b_hnp_enable = 1;
1457                                 else if (setup->bRequest ==
1458                                          USB_DEVICE_A_HNP_SUPPORT)
1459                                         udc->gadget.a_hnp_support = 1;
1460                                 else if (setup->bRequest ==
1461                                          USB_DEVICE_A_ALT_HNP_SUPPORT)
1462                                         udc->gadget.a_alt_hnp_support = 1;
1463                         }
1464                         rc = 0;
1465                 } else
1466                         break;
1467
1468                 if (rc == 0) {
1469                         if (ep0_prime_status(udc, EP_DIR_IN))
1470                                 ep0stall(udc);
1471                 }
1472                 if (ptc) {
1473                         u32 tmp;
1474
1475                         mdelay(10);
1476                         tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1477                         fsl_writel(tmp, &dr_regs->portsc1);
1478                         printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1479                 }
1480
1481                 return;
1482         }
1483
1484         default:
1485                 break;
1486         }
1487
1488         /* Requests handled by gadget */
1489         if (wLength) {
1490                 /* Data phase from gadget, status phase from udc */
1491                 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1492                                 ?  USB_DIR_IN : USB_DIR_OUT;
1493                 spin_unlock(&udc->lock);
1494                 if (udc->driver->setup(&udc->gadget,
1495                                 &udc->local_setup_buff) < 0)
1496                         ep0stall(udc);
1497                 spin_lock(&udc->lock);
1498                 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1499                                 ?  DATA_STATE_XMIT : DATA_STATE_RECV;
1500                 /*
1501                  * If the data stage is IN, send status prime immediately.
1502                  * See 2.0 Spec chapter 8.5.3.3 for detail.
1503                  */
1504                 if (udc->ep0_state == DATA_STATE_XMIT)
1505                         if (ep0_prime_status(udc, EP_DIR_OUT))
1506                                 ep0stall(udc);
1507
1508         } else {
1509                 /* No data phase, IN status from gadget */
1510                 udc->ep0_dir = USB_DIR_IN;
1511                 spin_unlock(&udc->lock);
1512                 if (udc->driver->setup(&udc->gadget,
1513                                 &udc->local_setup_buff) < 0)
1514                         ep0stall(udc);
1515                 spin_lock(&udc->lock);
1516                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1517         }
1518 }
1519
1520 /* Process request for Data or Status phase of ep0
1521  * prime status phase if needed */
1522 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1523                 struct fsl_req *req)
1524 {
1525         if (udc->usb_state == USB_STATE_ADDRESS) {
1526                 /* Set the new address */
1527                 u32 new_address = (u32) udc->device_address;
1528                 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1529                                 &dr_regs->deviceaddr);
1530         }
1531
1532         done(ep0, req, 0);
1533
1534         switch (udc->ep0_state) {
1535         case DATA_STATE_XMIT:
1536                 /* already primed at setup_received_irq */
1537                 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1538                 break;
1539         case DATA_STATE_RECV:
1540                 /* send status phase */
1541                 if (ep0_prime_status(udc, EP_DIR_IN))
1542                         ep0stall(udc);
1543                 break;
1544         case WAIT_FOR_OUT_STATUS:
1545                 udc->ep0_state = WAIT_FOR_SETUP;
1546                 break;
1547         case WAIT_FOR_SETUP:
1548                 ERR("Unexpected ep0 packets\n");
1549                 break;
1550         default:
1551                 ep0stall(udc);
1552                 break;
1553         }
1554 }
1555
1556 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1557  * being corrupted by another incoming setup packet */
1558 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1559 {
1560         u32 temp;
1561         struct ep_queue_head *qh;
1562         struct fsl_usb2_platform_data *pdata = udc->pdata;
1563
1564         qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1565
1566         /* Clear bit in ENDPTSETUPSTAT */
1567         temp = fsl_readl(&dr_regs->endptsetupstat);
1568         fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1569
1570         /* while a hazard exists when setup package arrives */
1571         do {
1572                 /* Set Setup Tripwire */
1573                 temp = fsl_readl(&dr_regs->usbcmd);
1574                 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1575
1576                 /* Copy the setup packet to local buffer */
1577                 if (pdata->le_setup_buf) {
1578                         u32 *p = (u32 *)buffer_ptr;
1579                         u32 *s = (u32 *)qh->setup_buffer;
1580
1581                         /* Convert little endian setup buffer to CPU endian */
1582                         *p++ = le32_to_cpu(*s++);
1583                         *p = le32_to_cpu(*s);
1584                 } else {
1585                         memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1586                 }
1587         } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1588
1589         /* Clear Setup Tripwire */
1590         temp = fsl_readl(&dr_regs->usbcmd);
1591         fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1592 }
1593
1594 /* process-ep_req(): free the completed Tds for this req */
1595 static int process_ep_req(struct fsl_udc *udc, int pipe,
1596                 struct fsl_req *curr_req)
1597 {
1598         struct ep_td_struct *curr_td;
1599         int     actual, remaining_length, j, tmp;
1600         int     status = 0;
1601         int     errors = 0;
1602         struct  ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1603         int direction = pipe % 2;
1604
1605         curr_td = curr_req->head;
1606         actual = curr_req->req.length;
1607
1608         for (j = 0; j < curr_req->dtd_count; j++) {
1609                 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1610                                         & DTD_PACKET_SIZE)
1611                                 >> DTD_LENGTH_BIT_POS;
1612                 actual -= remaining_length;
1613
1614                 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1615                 if (errors & DTD_ERROR_MASK) {
1616                         if (errors & DTD_STATUS_HALTED) {
1617                                 ERR("dTD error %08x QH=%d\n", errors, pipe);
1618                                 /* Clear the errors and Halt condition */
1619                                 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1620                                 tmp &= ~errors;
1621                                 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1622                                 status = -EPIPE;
1623                                 /* FIXME: continue with next queued TD? */
1624
1625                                 break;
1626                         }
1627                         if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1628                                 VDBG("Transfer overflow");
1629                                 status = -EPROTO;
1630                                 break;
1631                         } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1632                                 VDBG("ISO error");
1633                                 status = -EILSEQ;
1634                                 break;
1635                         } else
1636                                 ERR("Unknown error has occurred (0x%x)!\n",
1637                                         errors);
1638
1639                 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1640                                 & DTD_STATUS_ACTIVE) {
1641                         VDBG("Request not complete");
1642                         status = REQ_UNCOMPLETE;
1643                         return status;
1644                 } else if (remaining_length) {
1645                         if (direction) {
1646                                 VDBG("Transmit dTD remaining length not zero");
1647                                 status = -EPROTO;
1648                                 break;
1649                         } else {
1650                                 break;
1651                         }
1652                 } else {
1653                         VDBG("dTD transmitted successful");
1654                 }
1655
1656                 if (j != curr_req->dtd_count - 1)
1657                         curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1658         }
1659
1660         if (status)
1661                 return status;
1662
1663         curr_req->req.actual = actual;
1664
1665         return 0;
1666 }
1667
1668 /* Process a DTD completion interrupt */
1669 static void dtd_complete_irq(struct fsl_udc *udc)
1670 {
1671         u32 bit_pos;
1672         int i, ep_num, direction, bit_mask, status;
1673         struct fsl_ep *curr_ep;
1674         struct fsl_req *curr_req, *temp_req;
1675
1676         /* Clear the bits in the register */
1677         bit_pos = fsl_readl(&dr_regs->endptcomplete);
1678         fsl_writel(bit_pos, &dr_regs->endptcomplete);
1679
1680         if (!bit_pos)
1681                 return;
1682
1683         for (i = 0; i < udc->max_ep; i++) {
1684                 ep_num = i >> 1;
1685                 direction = i % 2;
1686
1687                 bit_mask = 1 << (ep_num + 16 * direction);
1688
1689                 if (!(bit_pos & bit_mask))
1690                         continue;
1691
1692                 curr_ep = get_ep_by_pipe(udc, i);
1693
1694                 /* If the ep is configured */
1695                 if (!curr_ep->ep.name) {
1696                         WARNING("Invalid EP?");
1697                         continue;
1698                 }
1699
1700                 /* process the req queue until an uncomplete request */
1701                 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1702                                 queue) {
1703                         status = process_ep_req(udc, i, curr_req);
1704
1705                         VDBG("status of process_ep_req= %d, ep = %d",
1706                                         status, ep_num);
1707                         if (status == REQ_UNCOMPLETE)
1708                                 break;
1709                         /* write back status to req */
1710                         curr_req->req.status = status;
1711
1712                         if (ep_num == 0) {
1713                                 ep0_req_complete(udc, curr_ep, curr_req);
1714                                 break;
1715                         } else
1716                                 done(curr_ep, curr_req, status);
1717                 }
1718         }
1719 }
1720
1721 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1722 {
1723         switch (reg & PORTSCX_PORT_SPEED_MASK) {
1724         case PORTSCX_PORT_SPEED_HIGH:
1725                 return USB_SPEED_HIGH;
1726         case PORTSCX_PORT_SPEED_FULL:
1727                 return USB_SPEED_FULL;
1728         case PORTSCX_PORT_SPEED_LOW:
1729                 return USB_SPEED_LOW;
1730         default:
1731                 return USB_SPEED_UNKNOWN;
1732         }
1733 }
1734
1735 /* Process a port change interrupt */
1736 static void port_change_irq(struct fsl_udc *udc)
1737 {
1738         if (udc->bus_reset)
1739                 udc->bus_reset = 0;
1740
1741         /* Bus resetting is finished */
1742         if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1743                 /* Get the speed */
1744                 udc->gadget.speed =
1745                         portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1746
1747         /* Update USB state */
1748         if (!udc->resume_state)
1749                 udc->usb_state = USB_STATE_DEFAULT;
1750 }
1751
1752 /* Process suspend interrupt */
1753 static void suspend_irq(struct fsl_udc *udc)
1754 {
1755         udc->resume_state = udc->usb_state;
1756         udc->usb_state = USB_STATE_SUSPENDED;
1757
1758         /* report suspend to the driver, serial.c does not support this */
1759         if (udc->driver->suspend)
1760                 udc->driver->suspend(&udc->gadget);
1761 }
1762
1763 static void bus_resume(struct fsl_udc *udc)
1764 {
1765         udc->usb_state = udc->resume_state;
1766         udc->resume_state = 0;
1767
1768         /* report resume to the driver, serial.c does not support this */
1769         if (udc->driver->resume)
1770                 udc->driver->resume(&udc->gadget);
1771 }
1772
1773 /* Clear up all ep queues */
1774 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1775 {
1776         u8 pipe;
1777
1778         for (pipe = 0; pipe < udc->max_pipes; pipe++)
1779                 udc_reset_ep_queue(udc, pipe);
1780
1781         /* report disconnect; the driver is already quiesced */
1782         spin_unlock(&udc->lock);
1783         if (bus_reset)
1784                 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1785         else
1786                 udc->driver->disconnect(&udc->gadget);
1787         spin_lock(&udc->lock);
1788
1789         return 0;
1790 }
1791
1792 /* Process reset interrupt */
1793 static void reset_irq(struct fsl_udc *udc)
1794 {
1795         u32 temp;
1796         unsigned long timeout;
1797
1798         /* Clear the device address */
1799         temp = fsl_readl(&dr_regs->deviceaddr);
1800         fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1801
1802         udc->device_address = 0;
1803
1804         /* Clear usb state */
1805         udc->resume_state = 0;
1806         udc->ep0_dir = 0;
1807         udc->ep0_state = WAIT_FOR_SETUP;
1808         udc->remote_wakeup = 0; /* default to 0 on reset */
1809         udc->gadget.b_hnp_enable = 0;
1810         udc->gadget.a_hnp_support = 0;
1811         udc->gadget.a_alt_hnp_support = 0;
1812
1813         /* Clear all the setup token semaphores */
1814         temp = fsl_readl(&dr_regs->endptsetupstat);
1815         fsl_writel(temp, &dr_regs->endptsetupstat);
1816
1817         /* Clear all the endpoint complete status bits */
1818         temp = fsl_readl(&dr_regs->endptcomplete);
1819         fsl_writel(temp, &dr_regs->endptcomplete);
1820
1821         timeout = jiffies + 100;
1822         while (fsl_readl(&dr_regs->endpointprime)) {
1823                 /* Wait until all endptprime bits cleared */
1824                 if (time_after(jiffies, timeout)) {
1825                         ERR("Timeout for reset\n");
1826                         break;
1827                 }
1828                 cpu_relax();
1829         }
1830
1831         /* Write 1s to the flush register */
1832         fsl_writel(0xffffffff, &dr_regs->endptflush);
1833
1834         if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1835                 VDBG("Bus reset");
1836                 /* Bus is reseting */
1837                 udc->bus_reset = 1;
1838                 /* Reset all the queues, include XD, dTD, EP queue
1839                  * head and TR Queue */
1840                 reset_queues(udc, true);
1841                 udc->usb_state = USB_STATE_DEFAULT;
1842         } else {
1843                 VDBG("Controller reset");
1844                 /* initialize usb hw reg except for regs for EP, not
1845                  * touch usbintr reg */
1846                 dr_controller_setup(udc);
1847
1848                 /* Reset all internal used Queues */
1849                 reset_queues(udc, false);
1850
1851                 ep0_setup(udc);
1852
1853                 /* Enable DR IRQ reg, Set Run bit, change udc state */
1854                 dr_controller_run(udc);
1855                 udc->usb_state = USB_STATE_ATTACHED;
1856         }
1857 }
1858
1859 /*
1860  * USB device controller interrupt handler
1861  */
1862 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1863 {
1864         struct fsl_udc *udc = _udc;
1865         u32 irq_src;
1866         irqreturn_t status = IRQ_NONE;
1867         unsigned long flags;
1868
1869         /* Disable ISR for OTG host mode */
1870         if (udc->stopped)
1871                 return IRQ_NONE;
1872         spin_lock_irqsave(&udc->lock, flags);
1873         irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1874         /* Clear notification bits */
1875         fsl_writel(irq_src, &dr_regs->usbsts);
1876
1877         /* VDBG("irq_src [0x%8x]", irq_src); */
1878
1879         /* Need to resume? */
1880         if (udc->usb_state == USB_STATE_SUSPENDED)
1881                 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1882                         bus_resume(udc);
1883
1884         /* USB Interrupt */
1885         if (irq_src & USB_STS_INT) {
1886                 VDBG("Packet int");
1887                 /* Setup package, we only support ep0 as control ep */
1888                 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1889                         tripwire_handler(udc, 0,
1890                                         (u8 *) (&udc->local_setup_buff));
1891                         setup_received_irq(udc, &udc->local_setup_buff);
1892                         status = IRQ_HANDLED;
1893                 }
1894
1895                 /* completion of dtd */
1896                 if (fsl_readl(&dr_regs->endptcomplete)) {
1897                         dtd_complete_irq(udc);
1898                         status = IRQ_HANDLED;
1899                 }
1900         }
1901
1902         /* SOF (for ISO transfer) */
1903         if (irq_src & USB_STS_SOF) {
1904                 status = IRQ_HANDLED;
1905         }
1906
1907         /* Port Change */
1908         if (irq_src & USB_STS_PORT_CHANGE) {
1909                 port_change_irq(udc);
1910                 status = IRQ_HANDLED;
1911         }
1912
1913         /* Reset Received */
1914         if (irq_src & USB_STS_RESET) {
1915                 VDBG("reset int");
1916                 reset_irq(udc);
1917                 status = IRQ_HANDLED;
1918         }
1919
1920         /* Sleep Enable (Suspend) */
1921         if (irq_src & USB_STS_SUSPEND) {
1922                 suspend_irq(udc);
1923                 status = IRQ_HANDLED;
1924         }
1925
1926         if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1927                 VDBG("Error IRQ %x", irq_src);
1928         }
1929
1930         spin_unlock_irqrestore(&udc->lock, flags);
1931         return status;
1932 }
1933
1934 /*----------------------------------------------------------------*
1935  * Hook to gadget drivers
1936  * Called by initialization code of gadget drivers
1937 *----------------------------------------------------------------*/
1938 static int fsl_udc_start(struct usb_gadget *g,
1939                 struct usb_gadget_driver *driver)
1940 {
1941         int retval = 0;
1942         unsigned long flags = 0;
1943
1944         /* lock is needed but whether should use this lock or another */
1945         spin_lock_irqsave(&udc_controller->lock, flags);
1946
1947         driver->driver.bus = NULL;
1948         /* hook up the driver */
1949         udc_controller->driver = driver;
1950         spin_unlock_irqrestore(&udc_controller->lock, flags);
1951         g->is_selfpowered = 1;
1952
1953         if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1954                 /* Suspend the controller until OTG enable it */
1955                 udc_controller->stopped = 1;
1956                 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1957
1958                 /* connect to bus through transceiver */
1959                 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1960                         retval = otg_set_peripheral(
1961                                         udc_controller->transceiver->otg,
1962                                                     &udc_controller->gadget);
1963                         if (retval < 0) {
1964                                 ERR("can't bind to transceiver\n");
1965                                 udc_controller->driver = NULL;
1966                                 return retval;
1967                         }
1968                 }
1969         } else {
1970                 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1971                 dr_controller_run(udc_controller);
1972                 udc_controller->usb_state = USB_STATE_ATTACHED;
1973                 udc_controller->ep0_state = WAIT_FOR_SETUP;
1974                 udc_controller->ep0_dir = 0;
1975         }
1976
1977         return retval;
1978 }
1979
1980 /* Disconnect from gadget driver */
1981 static int fsl_udc_stop(struct usb_gadget *g)
1982 {
1983         struct fsl_ep *loop_ep;
1984         unsigned long flags;
1985
1986         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1987                 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1988
1989         /* stop DR, disable intr */
1990         dr_controller_stop(udc_controller);
1991
1992         /* in fact, no needed */
1993         udc_controller->usb_state = USB_STATE_ATTACHED;
1994         udc_controller->ep0_state = WAIT_FOR_SETUP;
1995         udc_controller->ep0_dir = 0;
1996
1997         /* stand operation */
1998         spin_lock_irqsave(&udc_controller->lock, flags);
1999         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2000         nuke(&udc_controller->eps[0], -ESHUTDOWN);
2001         list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
2002                         ep.ep_list)
2003                 nuke(loop_ep, -ESHUTDOWN);
2004         spin_unlock_irqrestore(&udc_controller->lock, flags);
2005
2006         udc_controller->driver = NULL;
2007
2008         return 0;
2009 }
2010
2011 /*-------------------------------------------------------------------------
2012                 PROC File System Support
2013 -------------------------------------------------------------------------*/
2014 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2015
2016 #include <linux/seq_file.h>
2017
2018 static const char proc_filename[] = "driver/fsl_usb2_udc";
2019
2020 static int fsl_proc_read(struct seq_file *m, void *v)
2021 {
2022         unsigned long flags;
2023         int i;
2024         u32 tmp_reg;
2025         struct fsl_ep *ep = NULL;
2026         struct fsl_req *req;
2027
2028         struct fsl_udc *udc = udc_controller;
2029
2030         spin_lock_irqsave(&udc->lock, flags);
2031
2032         /* ------basic driver information ---- */
2033         seq_printf(m,
2034                         DRIVER_DESC "\n"
2035                         "%s version: %s\n"
2036                         "Gadget driver: %s\n\n",
2037                         driver_name, DRIVER_VERSION,
2038                         udc->driver ? udc->driver->driver.name : "(none)");
2039
2040         /* ------ DR Registers ----- */
2041         tmp_reg = fsl_readl(&dr_regs->usbcmd);
2042         seq_printf(m,
2043                         "USBCMD reg:\n"
2044                         "SetupTW: %d\n"
2045                         "Run/Stop: %s\n\n",
2046                         (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2047                         (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2048
2049         tmp_reg = fsl_readl(&dr_regs->usbsts);
2050         seq_printf(m,
2051                         "USB Status Reg:\n"
2052                         "Dr Suspend: %d Reset Received: %d System Error: %s "
2053                         "USB Error Interrupt: %s\n\n",
2054                         (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2055                         (tmp_reg & USB_STS_RESET) ? 1 : 0,
2056                         (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2057                         (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2058
2059         tmp_reg = fsl_readl(&dr_regs->usbintr);
2060         seq_printf(m,
2061                         "USB Interrupt Enable Reg:\n"
2062                         "Sleep Enable: %d SOF Received Enable: %d "
2063                         "Reset Enable: %d\n"
2064                         "System Error Enable: %d "
2065                         "Port Change Dectected Enable: %d\n"
2066                         "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2067                         (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2068                         (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2069                         (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2070                         (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2071                         (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2072                         (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2073                         (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2074
2075         tmp_reg = fsl_readl(&dr_regs->frindex);
2076         seq_printf(m,
2077                         "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2078                         (tmp_reg & USB_FRINDEX_MASKS));
2079
2080         tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2081         seq_printf(m,
2082                         "USB Device Address Reg: Device Addr is 0x%x\n\n",
2083                         (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2084
2085         tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2086         seq_printf(m,
2087                         "USB Endpoint List Address Reg: "
2088                         "Device Addr is 0x%x\n\n",
2089                         (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2090
2091         tmp_reg = fsl_readl(&dr_regs->portsc1);
2092         seq_printf(m,
2093                 "USB Port Status&Control Reg:\n"
2094                 "Port Transceiver Type : %s Port Speed: %s\n"
2095                 "PHY Low Power Suspend: %s Port Reset: %s "
2096                 "Port Suspend Mode: %s\n"
2097                 "Over-current Change: %s "
2098                 "Port Enable/Disable Change: %s\n"
2099                 "Port Enabled/Disabled: %s "
2100                 "Current Connect Status: %s\n\n", ( {
2101                         const char *s;
2102                         switch (tmp_reg & PORTSCX_PTS_FSLS) {
2103                         case PORTSCX_PTS_UTMI:
2104                                 s = "UTMI"; break;
2105                         case PORTSCX_PTS_ULPI:
2106                                 s = "ULPI "; break;
2107                         case PORTSCX_PTS_FSLS:
2108                                 s = "FS/LS Serial"; break;
2109                         default:
2110                                 s = "None"; break;
2111                         }
2112                         s;} ),
2113                 usb_speed_string(portscx_device_speed(tmp_reg)),
2114                 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2115                 "Normal PHY mode" : "Low power mode",
2116                 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2117                 "Not in Reset",
2118                 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2119                 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2120                 "No",
2121                 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2122                 "Not change",
2123                 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2124                 "Not correct",
2125                 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2126                 "Attached" : "Not-Att");
2127
2128         tmp_reg = fsl_readl(&dr_regs->usbmode);
2129         seq_printf(m,
2130                         "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2131                                 const char *s;
2132                                 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2133                                 case USB_MODE_CTRL_MODE_IDLE:
2134                                         s = "Idle"; break;
2135                                 case USB_MODE_CTRL_MODE_DEVICE:
2136                                         s = "Device Controller"; break;
2137                                 case USB_MODE_CTRL_MODE_HOST:
2138                                         s = "Host Controller"; break;
2139                                 default:
2140                                         s = "None"; break;
2141                                 }
2142                                 s;
2143                         } ));
2144
2145         tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2146         seq_printf(m,
2147                         "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2148                         (tmp_reg & EP_SETUP_STATUS_MASK));
2149
2150         for (i = 0; i < udc->max_ep / 2; i++) {
2151                 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2152                 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2153         }
2154         tmp_reg = fsl_readl(&dr_regs->endpointprime);
2155         seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2156
2157 #ifndef CONFIG_ARCH_MXC
2158         if (udc->pdata->have_sysif_regs) {
2159                 tmp_reg = usb_sys_regs->snoop1;
2160                 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2161
2162                 tmp_reg = usb_sys_regs->control;
2163                 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2164         }
2165 #endif
2166
2167         /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2168         ep = &udc->eps[0];
2169         seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2170                         ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2171
2172         if (list_empty(&ep->queue)) {
2173                 seq_puts(m, "its req queue is empty\n\n");
2174         } else {
2175                 list_for_each_entry(req, &ep->queue, queue) {
2176                         seq_printf(m,
2177                                 "req %p actual 0x%x length 0x%x buf %p\n",
2178                                 &req->req, req->req.actual,
2179                                 req->req.length, req->req.buf);
2180                 }
2181         }
2182         /* other gadget->eplist ep */
2183         list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2184                 if (ep->ep.desc) {
2185                         seq_printf(m,
2186                                         "\nFor %s Maxpkt is 0x%x "
2187                                         "index is 0x%x\n",
2188                                         ep->ep.name, ep_maxpacket(ep),
2189                                         ep_index(ep));
2190
2191                         if (list_empty(&ep->queue)) {
2192                                 seq_puts(m, "its req queue is empty\n\n");
2193                         } else {
2194                                 list_for_each_entry(req, &ep->queue, queue) {
2195                                         seq_printf(m,
2196                                                 "req %p actual 0x%x length "
2197                                                 "0x%x  buf %p\n",
2198                                                 &req->req, req->req.actual,
2199                                                 req->req.length, req->req.buf);
2200                                 }       /* end for each_entry of ep req */
2201                         }       /* end for else */
2202                 }       /* end for if(ep->queue) */
2203         }       /* end (ep->desc) */
2204
2205         spin_unlock_irqrestore(&udc->lock, flags);
2206         return 0;
2207 }
2208
2209 #define create_proc_file() \
2210         proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2211 #define remove_proc_file()      remove_proc_entry(proc_filename, NULL)
2212
2213 #else                           /* !CONFIG_USB_GADGET_DEBUG_FILES */
2214
2215 #define create_proc_file()      do {} while (0)
2216 #define remove_proc_file()      do {} while (0)
2217
2218 #endif                          /* CONFIG_USB_GADGET_DEBUG_FILES */
2219
2220 /*-------------------------------------------------------------------------*/
2221
2222 /* Release udc structures */
2223 static void fsl_udc_release(struct device *dev)
2224 {
2225         complete(udc_controller->done);
2226         dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2227                         udc_controller->ep_qh, udc_controller->ep_qh_dma);
2228         kfree(udc_controller);
2229 }
2230
2231 /******************************************************************
2232         Internal structure setup functions
2233 *******************************************************************/
2234 /*------------------------------------------------------------------
2235  * init resource for global controller called by fsl_udc_probe()
2236  * On success the udc handle is initialized, on failure it is
2237  * unchanged (reset).
2238  * Return 0 on success and -1 on allocation failure
2239  ------------------------------------------------------------------*/
2240 static int struct_udc_setup(struct fsl_udc *udc,
2241                 struct platform_device *pdev)
2242 {
2243         struct fsl_usb2_platform_data *pdata;
2244         size_t size;
2245
2246         pdata = dev_get_platdata(&pdev->dev);
2247         udc->phy_mode = pdata->phy_mode;
2248
2249         udc->eps = kcalloc(udc->max_ep, sizeof(struct fsl_ep), GFP_KERNEL);
2250         if (!udc->eps) {
2251                 ERR("kmalloc udc endpoint status failed\n");
2252                 goto eps_alloc_failed;
2253         }
2254
2255         /* initialized QHs, take care of alignment */
2256         size = udc->max_ep * sizeof(struct ep_queue_head);
2257         if (size < QH_ALIGNMENT)
2258                 size = QH_ALIGNMENT;
2259         else if ((size % QH_ALIGNMENT) != 0) {
2260                 size += QH_ALIGNMENT + 1;
2261                 size &= ~(QH_ALIGNMENT - 1);
2262         }
2263         udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2264                                         &udc->ep_qh_dma, GFP_KERNEL);
2265         if (!udc->ep_qh) {
2266                 ERR("malloc QHs for udc failed\n");
2267                 goto ep_queue_alloc_failed;
2268         }
2269
2270         udc->ep_qh_size = size;
2271
2272         /* Initialize ep0 status request structure */
2273         /* FIXME: fsl_alloc_request() ignores ep argument */
2274         udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2275                         struct fsl_req, req);
2276         if (!udc->status_req) {
2277                 ERR("kzalloc for udc status request failed\n");
2278                 goto udc_status_alloc_failed;
2279         }
2280
2281         /* allocate a small amount of memory to get valid address */
2282         udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2283         if (!udc->status_req->req.buf) {
2284                 ERR("kzalloc for udc request buffer failed\n");
2285                 goto udc_req_buf_alloc_failed;
2286         }
2287
2288         udc->resume_state = USB_STATE_NOTATTACHED;
2289         udc->usb_state = USB_STATE_POWERED;
2290         udc->ep0_dir = 0;
2291         udc->remote_wakeup = 0; /* default to 0 on reset */
2292
2293         return 0;
2294
2295 udc_req_buf_alloc_failed:
2296         kfree(udc->status_req);
2297 udc_status_alloc_failed:
2298         kfree(udc->ep_qh);
2299         udc->ep_qh_size = 0;
2300 ep_queue_alloc_failed:
2301         kfree(udc->eps);
2302 eps_alloc_failed:
2303         udc->phy_mode = 0;
2304         return -1;
2305
2306 }
2307
2308 /*----------------------------------------------------------------
2309  * Setup the fsl_ep struct for eps
2310  * Link fsl_ep->ep to gadget->ep_list
2311  * ep0out is not used so do nothing here
2312  * ep0in should be taken care
2313  *--------------------------------------------------------------*/
2314 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2315                 char *name, int link)
2316 {
2317         struct fsl_ep *ep = &udc->eps[index];
2318
2319         ep->udc = udc;
2320         strcpy(ep->name, name);
2321         ep->ep.name = ep->name;
2322
2323         ep->ep.ops = &fsl_ep_ops;
2324         ep->stopped = 0;
2325
2326         if (index == 0) {
2327                 ep->ep.caps.type_control = true;
2328         } else {
2329                 ep->ep.caps.type_iso = true;
2330                 ep->ep.caps.type_bulk = true;
2331                 ep->ep.caps.type_int = true;
2332         }
2333
2334         if (index & 1)
2335                 ep->ep.caps.dir_in = true;
2336         else
2337                 ep->ep.caps.dir_out = true;
2338
2339         /* for ep0: maxP defined in desc
2340          * for other eps, maxP is set by epautoconfig() called by gadget layer
2341          */
2342         usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2343
2344         /* the queue lists any req for this ep */
2345         INIT_LIST_HEAD(&ep->queue);
2346
2347         /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2348         if (link)
2349                 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2350         ep->gadget = &udc->gadget;
2351         ep->qh = &udc->ep_qh[index];
2352
2353         return 0;
2354 }
2355
2356 /* Driver probe function
2357  * all initialization operations implemented here except enabling usb_intr reg
2358  * board setup should have been done in the platform code
2359  */
2360 static int fsl_udc_probe(struct platform_device *pdev)
2361 {
2362         struct fsl_usb2_platform_data *pdata;
2363         struct resource *res;
2364         int ret = -ENODEV;
2365         unsigned int i;
2366         u32 dccparams;
2367
2368         udc_controller = kzalloc(sizeof(struct fsl_udc), GFP_KERNEL);
2369         if (udc_controller == NULL)
2370                 return -ENOMEM;
2371
2372         pdata = dev_get_platdata(&pdev->dev);
2373         udc_controller->pdata = pdata;
2374         spin_lock_init(&udc_controller->lock);
2375         udc_controller->stopped = 1;
2376
2377 #ifdef CONFIG_USB_OTG
2378         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2379                 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2380                 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2381                         ERR("Can't find OTG driver!\n");
2382                         ret = -ENODEV;
2383                         goto err_kfree;
2384                 }
2385         }
2386 #endif
2387
2388         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2389         if (!res) {
2390                 ret = -ENXIO;
2391                 goto err_kfree;
2392         }
2393
2394         if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2395                 if (!request_mem_region(res->start, resource_size(res),
2396                                         driver_name)) {
2397                         ERR("request mem region for %s failed\n", pdev->name);
2398                         ret = -EBUSY;
2399                         goto err_kfree;
2400                 }
2401         }
2402
2403         dr_regs = ioremap(res->start, resource_size(res));
2404         if (!dr_regs) {
2405                 ret = -ENOMEM;
2406                 goto err_release_mem_region;
2407         }
2408
2409         pdata->regs = (void __iomem *)dr_regs;
2410
2411         /*
2412          * do platform specific init: check the clock, grab/config pins, etc.
2413          */
2414         if (pdata->init && pdata->init(pdev)) {
2415                 ret = -ENODEV;
2416                 goto err_iounmap_noclk;
2417         }
2418
2419         /* Set accessors only after pdata->init() ! */
2420         fsl_set_accessors(pdata);
2421
2422 #ifndef CONFIG_ARCH_MXC
2423         if (pdata->have_sysif_regs)
2424                 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2425 #endif
2426
2427         /* Initialize USB clocks */
2428         ret = fsl_udc_clk_init(pdev);
2429         if (ret < 0)
2430                 goto err_iounmap_noclk;
2431
2432         /* Read Device Controller Capability Parameters register */
2433         dccparams = fsl_readl(&dr_regs->dccparams);
2434         if (!(dccparams & DCCPARAMS_DC)) {
2435                 ERR("This SOC doesn't support device role\n");
2436                 ret = -ENODEV;
2437                 goto err_iounmap;
2438         }
2439         /* Get max device endpoints */
2440         /* DEN is bidirectional ep number, max_ep doubles the number */
2441         udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2442
2443         udc_controller->irq = platform_get_irq(pdev, 0);
2444         if (!udc_controller->irq) {
2445                 ret = -ENODEV;
2446                 goto err_iounmap;
2447         }
2448
2449         ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2450                         driver_name, udc_controller);
2451         if (ret != 0) {
2452                 ERR("cannot request irq %d err %d\n",
2453                                 udc_controller->irq, ret);
2454                 goto err_iounmap;
2455         }
2456
2457         /* Initialize the udc structure including QH member and other member */
2458         if (struct_udc_setup(udc_controller, pdev)) {
2459                 ERR("Can't initialize udc data structure\n");
2460                 ret = -ENOMEM;
2461                 goto err_free_irq;
2462         }
2463
2464         if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2465                 /* initialize usb hw reg except for regs for EP,
2466                  * leave usbintr reg untouched */
2467                 dr_controller_setup(udc_controller);
2468         }
2469
2470         ret = fsl_udc_clk_finalize(pdev);
2471         if (ret)
2472                 goto err_free_irq;
2473
2474         /* Setup gadget structure */
2475         udc_controller->gadget.ops = &fsl_gadget_ops;
2476         udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2477         udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2478         INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2479         udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2480         udc_controller->gadget.name = driver_name;
2481
2482         /* Setup gadget.dev and register with kernel */
2483         dev_set_name(&udc_controller->gadget.dev, "gadget");
2484         udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2485
2486         if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2487                 udc_controller->gadget.is_otg = 1;
2488
2489         /* setup QH and epctrl for ep0 */
2490         ep0_setup(udc_controller);
2491
2492         /* setup udc->eps[] for ep0 */
2493         struct_ep_setup(udc_controller, 0, "ep0", 0);
2494         /* for ep0: the desc defined here;
2495          * for other eps, gadget layer called ep_enable with defined desc
2496          */
2497         udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2498         usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2499                                    USB_MAX_CTRL_PAYLOAD);
2500
2501         /* setup the udc->eps[] for non-control endpoints and link
2502          * to gadget.ep_list */
2503         for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2504                 char name[14];
2505
2506                 sprintf(name, "ep%dout", i);
2507                 struct_ep_setup(udc_controller, i * 2, name, 1);
2508                 sprintf(name, "ep%din", i);
2509                 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2510         }
2511
2512         /* use dma_pool for TD management */
2513         udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2514                         sizeof(struct ep_td_struct),
2515                         DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2516         if (udc_controller->td_pool == NULL) {
2517                 ret = -ENOMEM;
2518                 goto err_free_irq;
2519         }
2520
2521         ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2522                         fsl_udc_release);
2523         if (ret)
2524                 goto err_del_udc;
2525
2526         create_proc_file();
2527         return 0;
2528
2529 err_del_udc:
2530         dma_pool_destroy(udc_controller->td_pool);
2531 err_free_irq:
2532         free_irq(udc_controller->irq, udc_controller);
2533 err_iounmap:
2534         if (pdata->exit)
2535                 pdata->exit(pdev);
2536         fsl_udc_clk_release();
2537 err_iounmap_noclk:
2538         iounmap(dr_regs);
2539 err_release_mem_region:
2540         if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2541                 release_mem_region(res->start, resource_size(res));
2542 err_kfree:
2543         kfree(udc_controller);
2544         udc_controller = NULL;
2545         return ret;
2546 }
2547
2548 /* Driver removal function
2549  * Free resources and finish pending transactions
2550  */
2551 static int fsl_udc_remove(struct platform_device *pdev)
2552 {
2553         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2554         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2555
2556         DECLARE_COMPLETION_ONSTACK(done);
2557
2558         if (!udc_controller)
2559                 return -ENODEV;
2560
2561         udc_controller->done = &done;
2562         usb_del_gadget_udc(&udc_controller->gadget);
2563
2564         fsl_udc_clk_release();
2565
2566         /* DR has been stopped in usb_gadget_unregister_driver() */
2567         remove_proc_file();
2568
2569         /* Free allocated memory */
2570         kfree(udc_controller->status_req->req.buf);
2571         kfree(udc_controller->status_req);
2572         kfree(udc_controller->eps);
2573
2574         dma_pool_destroy(udc_controller->td_pool);
2575         free_irq(udc_controller->irq, udc_controller);
2576         iounmap(dr_regs);
2577         if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2578                 release_mem_region(res->start, resource_size(res));
2579
2580         /* free udc --wait for the release() finished */
2581         wait_for_completion(&done);
2582
2583         /*
2584          * do platform specific un-initialization:
2585          * release iomux pins, etc.
2586          */
2587         if (pdata->exit)
2588                 pdata->exit(pdev);
2589
2590         return 0;
2591 }
2592
2593 /*-----------------------------------------------------------------
2594  * Modify Power management attributes
2595  * Used by OTG statemachine to disable gadget temporarily
2596  -----------------------------------------------------------------*/
2597 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2598 {
2599         dr_controller_stop(udc_controller);
2600         return 0;
2601 }
2602
2603 /*-----------------------------------------------------------------
2604  * Invoked on USB resume. May be called in_interrupt.
2605  * Here we start the DR controller and enable the irq
2606  *-----------------------------------------------------------------*/
2607 static int fsl_udc_resume(struct platform_device *pdev)
2608 {
2609         /* Enable DR irq reg and set controller Run */
2610         if (udc_controller->stopped) {
2611                 dr_controller_setup(udc_controller);
2612                 dr_controller_run(udc_controller);
2613         }
2614         udc_controller->usb_state = USB_STATE_ATTACHED;
2615         udc_controller->ep0_state = WAIT_FOR_SETUP;
2616         udc_controller->ep0_dir = 0;
2617         return 0;
2618 }
2619
2620 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2621 {
2622         struct fsl_udc *udc = udc_controller;
2623         u32 mode, usbcmd;
2624
2625         mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2626
2627         pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2628
2629         /*
2630          * If the controller is already stopped, then this must be a
2631          * PM suspend.  Remember this fact, so that we will leave the
2632          * controller stopped at PM resume time.
2633          */
2634         if (udc->stopped) {
2635                 pr_debug("gadget already stopped, leaving early\n");
2636                 udc->already_stopped = 1;
2637                 return 0;
2638         }
2639
2640         if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2641                 pr_debug("gadget not in device mode, leaving early\n");
2642                 return 0;
2643         }
2644
2645         /* stop the controller */
2646         usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2647         fsl_writel(usbcmd, &dr_regs->usbcmd);
2648
2649         udc->stopped = 1;
2650
2651         pr_info("USB Gadget suspended\n");
2652
2653         return 0;
2654 }
2655
2656 static int fsl_udc_otg_resume(struct device *dev)
2657 {
2658         pr_debug("%s(): stopped %d  already_stopped %d\n", __func__,
2659                  udc_controller->stopped, udc_controller->already_stopped);
2660
2661         /*
2662          * If the controller was stopped at suspend time, then
2663          * don't resume it now.
2664          */
2665         if (udc_controller->already_stopped) {
2666                 udc_controller->already_stopped = 0;
2667                 pr_debug("gadget was already stopped, leaving early\n");
2668                 return 0;
2669         }
2670
2671         pr_info("USB Gadget resume\n");
2672
2673         return fsl_udc_resume(NULL);
2674 }
2675 /*-------------------------------------------------------------------------
2676         Register entry point for the peripheral controller driver
2677 --------------------------------------------------------------------------*/
2678 static const struct platform_device_id fsl_udc_devtype[] = {
2679         {
2680                 .name = "imx-udc-mx27",
2681         }, {
2682                 .name = "imx-udc-mx51",
2683         }, {
2684                 .name = "fsl-usb2-udc",
2685         }, {
2686                 /* sentinel */
2687         }
2688 };
2689 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2690 static struct platform_driver udc_driver = {
2691         .remove         = fsl_udc_remove,
2692         /* Just for FSL i.mx SoC currently */
2693         .id_table       = fsl_udc_devtype,
2694         /* these suspend and resume are not usb suspend and resume */
2695         .suspend        = fsl_udc_suspend,
2696         .resume         = fsl_udc_resume,
2697         .driver         = {
2698                         .name = driver_name,
2699                         /* udc suspend/resume called from OTG driver */
2700                         .suspend = fsl_udc_otg_suspend,
2701                         .resume  = fsl_udc_otg_resume,
2702         },
2703 };
2704
2705 module_platform_driver_probe(udc_driver, fsl_udc_probe);
2706
2707 MODULE_DESCRIPTION(DRIVER_DESC);
2708 MODULE_AUTHOR(DRIVER_AUTHOR);
2709 MODULE_LICENSE("GPL");
2710 MODULE_ALIAS("platform:fsl-usb2-udc");