2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include <linux/slab.h>
25 #include <asm/unaligned.h>
28 #include "xhci-trace.h"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
32 PORT_RC | PORT_PLC | PORT_PE)
34 /* USB 3 BOS descriptor and a capability descriptors, combined.
35 * Fields will be adjusted and added later in xhci_create_usb3_bos_desc()
37 static u8 usb_bos_descriptor [] = {
38 USB_DT_BOS_SIZE, /* __u8 bLength, 5 bytes */
39 USB_DT_BOS, /* __u8 bDescriptorType */
40 0x0F, 0x00, /* __le16 wTotalLength, 15 bytes */
41 0x1, /* __u8 bNumDeviceCaps */
42 /* First device capability, SuperSpeed */
43 USB_DT_USB_SS_CAP_SIZE, /* __u8 bLength, 10 bytes */
44 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
45 USB_SS_CAP_TYPE, /* bDevCapabilityType, SUPERSPEED_USB */
46 0x00, /* bmAttributes, LTM off by default */
47 USB_5GBPS_OPERATION, 0x00, /* wSpeedsSupported, 5Gbps only */
48 0x03, /* bFunctionalitySupport,
50 0x00, /* bU1DevExitLat, set later. */
51 0x00, 0x00, /* __le16 bU2DevExitLat, set later. */
52 /* Second device capability, SuperSpeedPlus */
53 0x1c, /* bLength 28, will be adjusted later */
54 USB_DT_DEVICE_CAPABILITY, /* Device Capability */
55 USB_SSP_CAP_TYPE, /* bDevCapabilityType SUPERSPEED_PLUS */
56 0x00, /* bReserved 0 */
57 0x23, 0x00, 0x00, 0x00, /* bmAttributes, SSAC=3 SSIC=1 */
58 0x01, 0x00, /* wFunctionalitySupport */
59 0x00, 0x00, /* wReserved 0 */
60 /* Default Sublink Speed Attributes, overwrite if custom PSI exists */
61 0x34, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, rx, ID = 4 */
62 0xb4, 0x00, 0x05, 0x00, /* 5Gbps, symmetric, tx, ID = 4 */
63 0x35, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, rx, ID = 5 */
64 0xb5, 0x40, 0x0a, 0x00, /* 10Gbps, SSP, symmetric, tx, ID = 5 */
67 static int xhci_create_usb3_bos_desc(struct xhci_hcd *xhci, char *buf,
72 u16 desc_size, ssp_cap_size, ssa_size = 0;
75 desc_size = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
76 ssp_cap_size = sizeof(usb_bos_descriptor) - desc_size;
78 /* does xhci support USB 3.1 Enhanced SuperSpeed */
79 if (xhci->usb3_rhub.min_rev >= 0x01) {
80 /* does xhci provide a PSI table for SSA speed attributes? */
81 if (xhci->usb3_rhub.psi_count) {
82 /* two SSA entries for each unique PSI ID, RX and TX */
83 ssa_count = xhci->usb3_rhub.psi_uid_count * 2;
84 ssa_size = ssa_count * sizeof(u32);
85 ssp_cap_size -= 16; /* skip copying the default SSA */
87 desc_size += ssp_cap_size;
90 memcpy(buf, &usb_bos_descriptor, min(desc_size, wLength));
93 /* modify bos descriptor bNumDeviceCaps and wTotalLength */
95 put_unaligned_le16(desc_size + ssa_size, &buf[2]);
98 if (wLength < USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE)
101 /* Indicate whether the host has LTM support. */
102 temp = readl(&xhci->cap_regs->hcc_params);
104 buf[8] |= USB_LTM_SUPPORT;
106 /* Set the U1 and U2 exit latencies. */
107 if ((xhci->quirks & XHCI_LPM_SUPPORT)) {
108 temp = readl(&xhci->cap_regs->hcs_params3);
109 buf[12] = HCS_U1_LATENCY(temp);
110 put_unaligned_le16(HCS_U2_LATENCY(temp), &buf[13]);
113 /* If PSI table exists, add the custom speed attributes from it */
114 if (usb3_1 && xhci->usb3_rhub.psi_count) {
115 u32 ssp_cap_base, bm_attrib, psi;
118 ssp_cap_base = USB_DT_BOS_SIZE + USB_DT_USB_SS_CAP_SIZE;
120 if (wLength < desc_size)
122 buf[ssp_cap_base] = ssp_cap_size + ssa_size;
124 /* attribute count SSAC bits 4:0 and ID count SSIC bits 8:5 */
125 bm_attrib = (ssa_count - 1) & 0x1f;
126 bm_attrib |= (xhci->usb3_rhub.psi_uid_count - 1) << 5;
127 put_unaligned_le32(bm_attrib, &buf[ssp_cap_base + 4]);
129 if (wLength < desc_size + ssa_size)
132 * Create the Sublink Speed Attributes (SSA) array.
133 * The xhci PSI field and USB 3.1 SSA fields are very similar,
134 * but link type bits 7:6 differ for values 01b and 10b.
135 * xhci has also only one PSI entry for a symmetric link when
136 * USB 3.1 requires two SSA entries (RX and TX) for every link
139 for (i = 0; i < xhci->usb3_rhub.psi_count; i++) {
140 psi = xhci->usb3_rhub.psi[i];
141 psi &= ~USB_SSP_SUBLINK_SPEED_RSVD;
142 if ((psi & PLT_MASK) == PLT_SYM) {
143 /* Symmetric, create SSA RX and TX from one PSI entry */
144 put_unaligned_le32(psi, &buf[offset]);
145 psi |= 1 << 7; /* turn entry to TX */
147 if (offset >= desc_size + ssa_size)
148 return desc_size + ssa_size;
149 } else if ((psi & PLT_MASK) == PLT_ASYM_RX) {
150 /* Asymetric RX, flip bits 7:6 for SSA */
153 put_unaligned_le32(psi, &buf[offset]);
155 if (offset >= desc_size + ssa_size)
156 return desc_size + ssa_size;
159 /* ssa_size is 0 for other than usb 3.1 hosts */
160 return desc_size + ssa_size;
163 static void xhci_common_hub_descriptor(struct xhci_hcd *xhci,
164 struct usb_hub_descriptor *desc, int ports)
168 desc->bPwrOn2PwrGood = 10; /* xhci section 5.4.9 says 20ms max */
169 desc->bHubContrCurrent = 0;
171 desc->bNbrPorts = ports;
173 /* Bits 1:0 - support per-port power switching, or power always on */
174 if (HCC_PPC(xhci->hcc_params))
175 temp |= HUB_CHAR_INDV_PORT_LPSM;
177 temp |= HUB_CHAR_NO_LPSM;
178 /* Bit 2 - root hubs are not part of a compound device */
179 /* Bits 4:3 - individual port over current protection */
180 temp |= HUB_CHAR_INDV_PORT_OCPM;
181 /* Bits 6:5 - no TTs in root ports */
182 /* Bit 7 - no port indicators */
183 desc->wHubCharacteristics = cpu_to_le16(temp);
186 /* Fill in the USB 2.0 roothub descriptor */
187 static void xhci_usb2_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
188 struct usb_hub_descriptor *desc)
192 __u8 port_removable[(USB_MAXCHILDREN + 1 + 7) / 8];
196 ports = xhci->num_usb2_ports;
198 xhci_common_hub_descriptor(xhci, desc, ports);
199 desc->bDescriptorType = USB_DT_HUB;
200 temp = 1 + (ports / 8);
201 desc->bDescLength = USB_DT_HUB_NONVAR_SIZE + 2 * temp;
203 /* The Device Removable bits are reported on a byte granularity.
204 * If the port doesn't exist within that byte, the bit is set to 0.
206 memset(port_removable, 0, sizeof(port_removable));
207 for (i = 0; i < ports; i++) {
208 portsc = readl(xhci->usb2_ports[i]);
209 /* If a device is removable, PORTSC reports a 0, same as in the
210 * hub descriptor DeviceRemovable bits.
212 if (portsc & PORT_DEV_REMOVE)
213 /* This math is hairy because bit 0 of DeviceRemovable
214 * is reserved, and bit 1 is for port 1, etc.
216 port_removable[(i + 1) / 8] |= 1 << ((i + 1) % 8);
219 /* ch11.h defines a hub descriptor that has room for USB_MAXCHILDREN
220 * ports on it. The USB 2.0 specification says that there are two
221 * variable length fields at the end of the hub descriptor:
222 * DeviceRemovable and PortPwrCtrlMask. But since we can have less than
223 * USB_MAXCHILDREN ports, we may need to use the DeviceRemovable array
224 * to set PortPwrCtrlMask bits. PortPwrCtrlMask must always be set to
225 * 0xFF, so we initialize the both arrays (DeviceRemovable and
226 * PortPwrCtrlMask) to 0xFF. Then we set the DeviceRemovable for each
227 * set of ports that actually exist.
229 memset(desc->u.hs.DeviceRemovable, 0xff,
230 sizeof(desc->u.hs.DeviceRemovable));
231 memset(desc->u.hs.PortPwrCtrlMask, 0xff,
232 sizeof(desc->u.hs.PortPwrCtrlMask));
234 for (i = 0; i < (ports + 1 + 7) / 8; i++)
235 memset(&desc->u.hs.DeviceRemovable[i], port_removable[i],
239 /* Fill in the USB 3.0 roothub descriptor */
240 static void xhci_usb3_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
241 struct usb_hub_descriptor *desc)
248 ports = xhci->num_usb3_ports;
249 xhci_common_hub_descriptor(xhci, desc, ports);
250 desc->bDescriptorType = USB_DT_SS_HUB;
251 desc->bDescLength = USB_DT_SS_HUB_SIZE;
253 /* header decode latency should be zero for roothubs,
254 * see section 4.23.5.2.
256 desc->u.ss.bHubHdrDecLat = 0;
257 desc->u.ss.wHubDelay = 0;
260 /* bit 0 is reserved, bit 1 is for port 1, etc. */
261 for (i = 0; i < ports; i++) {
262 portsc = readl(xhci->usb3_ports[i]);
263 if (portsc & PORT_DEV_REMOVE)
264 port_removable |= 1 << (i + 1);
267 desc->u.ss.DeviceRemovable = cpu_to_le16(port_removable);
270 static void xhci_hub_descriptor(struct usb_hcd *hcd, struct xhci_hcd *xhci,
271 struct usb_hub_descriptor *desc)
274 if (hcd->speed >= HCD_USB3)
275 xhci_usb3_hub_descriptor(hcd, xhci, desc);
277 xhci_usb2_hub_descriptor(hcd, xhci, desc);
281 static unsigned int xhci_port_speed(unsigned int port_status)
283 if (DEV_LOWSPEED(port_status))
284 return USB_PORT_STAT_LOW_SPEED;
285 if (DEV_HIGHSPEED(port_status))
286 return USB_PORT_STAT_HIGH_SPEED;
288 * FIXME: Yes, we should check for full speed, but the core uses that as
289 * a default in portspeed() in usb/core/hub.c (which is the only place
290 * USB_PORT_STAT_*_SPEED is used).
296 * These bits are Read Only (RO) and should be saved and written to the
297 * registers: 0, 3, 10:13, 30
298 * connect status, over-current status, port speed, and device removable.
299 * connect status and port speed are also sticky - meaning they're in
300 * the AUX well and they aren't changed by a hot, warm, or cold reset.
302 #define XHCI_PORT_RO ((1<<0) | (1<<3) | (0xf<<10) | (1<<30))
304 * These bits are RW; writing a 0 clears the bit, writing a 1 sets the bit:
305 * bits 5:8, 9, 14:15, 25:27
306 * link state, port power, port indicator state, "wake on" enable state
308 #define XHCI_PORT_RWS ((0xf<<5) | (1<<9) | (0x3<<14) | (0x7<<25))
310 * These bits are RW; writing a 1 sets the bit, writing a 0 has no effect:
313 #define XHCI_PORT_RW1S ((1<<4))
315 * These bits are RW; writing a 1 clears the bit, writing a 0 has no effect:
316 * bits 1, 17, 18, 19, 20, 21, 22, 23
317 * port enable/disable, and
318 * change bits: connect, PED, warm port reset changed (reserved zero for USB 2.0 ports),
319 * over-current, reset, link state, and L1 change
321 #define XHCI_PORT_RW1CS ((1<<1) | (0x7f<<17))
323 * Bit 16 is RW, and writing a '1' to it causes the link state control to be
326 #define XHCI_PORT_RW ((1<<16))
328 * These bits are Reserved Zero (RsvdZ) and zero should be written to them:
331 #define XHCI_PORT_RZ ((1<<2) | (1<<24) | (0xf<<28))
334 * Given a port state, this function returns a value that would result in the
335 * port being in the same state, if the value was written to the port status
337 * Save Read Only (RO) bits and save read/write bits where
338 * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
339 * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
341 u32 xhci_port_state_to_neutral(u32 state)
343 /* Save read-only status and port state */
344 return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
348 * find slot id based on port number.
349 * @port: The one-based port number from one of the two split roothubs.
351 int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
356 enum usb_device_speed speed;
359 for (i = 0; i < MAX_HC_SLOTS; i++) {
362 speed = xhci->devs[i]->udev->speed;
363 if (((speed >= USB_SPEED_SUPER) == (hcd->speed >= HCD_USB3))
364 && xhci->devs[i]->fake_port == port) {
375 * It issues stop endpoint command for EP 0 to 30. And wait the last command
377 * suspend will set to 1, if suspend bit need to set in command.
379 static int xhci_stop_device(struct xhci_hcd *xhci, int slot_id, int suspend)
381 struct xhci_virt_device *virt_dev;
382 struct xhci_command *cmd;
388 virt_dev = xhci->devs[slot_id];
392 trace_xhci_stop_device(virt_dev);
394 cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
398 spin_lock_irqsave(&xhci->lock, flags);
399 for (i = LAST_EP_INDEX; i > 0; i--) {
400 if (virt_dev->eps[i].ring && virt_dev->eps[i].ring->dequeue) {
401 struct xhci_ep_ctx *ep_ctx;
402 struct xhci_command *command;
404 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->out_ctx, i);
406 /* Check ep is running, required by AMD SNPS 3.1 xHC */
407 if (GET_EP_CTX_STATE(ep_ctx) != EP_STATE_RUNNING)
410 command = xhci_alloc_command(xhci, false, false,
413 spin_unlock_irqrestore(&xhci->lock, flags);
414 xhci_free_command(xhci, cmd);
417 xhci_queue_stop_endpoint(xhci, command, slot_id, i,
421 xhci_queue_stop_endpoint(xhci, cmd, slot_id, 0, suspend);
422 xhci_ring_cmd_db(xhci);
423 spin_unlock_irqrestore(&xhci->lock, flags);
425 /* Wait for last stop endpoint command to finish */
426 wait_for_completion(cmd->completion);
428 if (cmd->status == COMP_COMMAND_ABORTED ||
429 cmd->status == COMP_COMMAND_RING_STOPPED) {
430 xhci_warn(xhci, "Timeout while waiting for stop endpoint command\n");
433 xhci_free_command(xhci, cmd);
438 * Ring device, it rings the all doorbells unconditionally.
440 void xhci_ring_device(struct xhci_hcd *xhci, int slot_id)
443 struct xhci_virt_ep *ep;
445 for (i = 0; i < LAST_EP_INDEX + 1; i++) {
446 ep = &xhci->devs[slot_id]->eps[i];
448 if (ep->ep_state & EP_HAS_STREAMS) {
449 for (s = 1; s < ep->stream_info->num_streams; s++)
450 xhci_ring_ep_doorbell(xhci, slot_id, i, s);
451 } else if (ep->ring && ep->ring->dequeue) {
452 xhci_ring_ep_doorbell(xhci, slot_id, i, 0);
459 static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
460 u16 wIndex, __le32 __iomem *addr, u32 port_status)
462 /* Don't allow the USB core to disable SuperSpeed ports. */
463 if (hcd->speed >= HCD_USB3) {
464 xhci_dbg(xhci, "Ignoring request to disable "
465 "SuperSpeed port.\n");
469 if (xhci->quirks & XHCI_BROKEN_PORT_PED) {
471 "Broken Port Enabled/Disabled, ignoring port disable request.\n");
475 /* Write 1 to disable the port */
476 writel(port_status | PORT_PE, addr);
477 port_status = readl(addr);
478 xhci_dbg(xhci, "disable port, actual port %d status = 0x%x\n",
479 wIndex, port_status);
482 static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
483 u16 wIndex, __le32 __iomem *addr, u32 port_status)
485 char *port_change_bit;
489 case USB_PORT_FEAT_C_RESET:
491 port_change_bit = "reset";
493 case USB_PORT_FEAT_C_BH_PORT_RESET:
495 port_change_bit = "warm(BH) reset";
497 case USB_PORT_FEAT_C_CONNECTION:
499 port_change_bit = "connect";
501 case USB_PORT_FEAT_C_OVER_CURRENT:
503 port_change_bit = "over-current";
505 case USB_PORT_FEAT_C_ENABLE:
507 port_change_bit = "enable/disable";
509 case USB_PORT_FEAT_C_SUSPEND:
511 port_change_bit = "suspend/resume";
513 case USB_PORT_FEAT_C_PORT_LINK_STATE:
515 port_change_bit = "link state";
517 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
519 port_change_bit = "config error";
522 /* Should never happen */
525 /* Change bits are all write 1 to clear */
526 writel(port_status | status, addr);
527 port_status = readl(addr);
528 xhci_dbg(xhci, "clear port %s change, actual port %d status = 0x%x\n",
529 port_change_bit, wIndex, port_status);
532 static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
535 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
537 if (hcd->speed >= HCD_USB3) {
538 max_ports = xhci->num_usb3_ports;
539 *port_array = xhci->usb3_ports;
541 max_ports = xhci->num_usb2_ports;
542 *port_array = xhci->usb2_ports;
548 static __le32 __iomem *xhci_get_port_io_addr(struct usb_hcd *hcd, int index)
550 __le32 __iomem **port_array;
552 xhci_get_ports(hcd, &port_array);
553 return port_array[index];
557 * xhci_set_port_power() must be called with xhci->lock held.
558 * It will release and re-aquire the lock while calling ACPI
561 static void xhci_set_port_power(struct xhci_hcd *xhci, struct usb_hcd *hcd,
562 u16 index, bool on, unsigned long *flags)
564 __le32 __iomem *addr;
567 addr = xhci_get_port_io_addr(hcd, index);
569 temp = xhci_port_state_to_neutral(temp);
572 writel(temp | PORT_POWER, addr);
574 xhci_dbg(xhci, "set port power, actual port %d status = 0x%x\n",
578 writel(temp & ~PORT_POWER, addr);
581 spin_unlock_irqrestore(&xhci->lock, *flags);
582 temp = usb_acpi_power_manageable(hcd->self.root_hub,
585 usb_acpi_set_power_state(hcd->self.root_hub,
587 spin_lock_irqsave(&xhci->lock, *flags);
590 static void xhci_port_set_test_mode(struct xhci_hcd *xhci,
591 u16 test_mode, u16 wIndex)
594 __le32 __iomem *addr;
596 /* xhci only supports test mode for usb2 ports, i.e. xhci->main_hcd */
597 addr = xhci_get_port_io_addr(xhci->main_hcd, wIndex);
598 temp = readl(addr + PORTPMSC);
599 temp |= test_mode << PORT_TEST_MODE_SHIFT;
600 writel(temp, addr + PORTPMSC);
601 xhci->test_mode = test_mode;
602 if (test_mode == TEST_FORCE_EN)
606 static int xhci_enter_test_mode(struct xhci_hcd *xhci,
607 u16 test_mode, u16 wIndex, unsigned long *flags)
611 /* Disable all Device Slots */
612 xhci_dbg(xhci, "Disable all slots\n");
613 spin_unlock_irqrestore(&xhci->lock, *flags);
614 for (i = 1; i <= HCS_MAX_SLOTS(xhci->hcs_params1); i++) {
615 retval = xhci_disable_slot(xhci, NULL, i);
617 xhci_err(xhci, "Failed to disable slot %d, %d. Enter test mode anyway\n",
620 spin_lock_irqsave(&xhci->lock, *flags);
621 /* Put all ports to the Disable state by clear PP */
622 xhci_dbg(xhci, "Disable all port (PP = 0)\n");
623 /* Power off USB3 ports*/
624 for (i = 0; i < xhci->num_usb3_ports; i++)
625 xhci_set_port_power(xhci, xhci->shared_hcd, i, false, flags);
626 /* Power off USB2 ports*/
627 for (i = 0; i < xhci->num_usb2_ports; i++)
628 xhci_set_port_power(xhci, xhci->main_hcd, i, false, flags);
629 /* Stop the controller */
630 xhci_dbg(xhci, "Stop controller\n");
631 retval = xhci_halt(xhci);
634 /* Disable runtime PM for test mode */
635 pm_runtime_forbid(xhci_to_hcd(xhci)->self.controller);
636 /* Set PORTPMSC.PTC field to enter selected test mode */
637 /* Port is selected by wIndex. port_id = wIndex + 1 */
638 xhci_dbg(xhci, "Enter Test Mode: %d, Port_id=%d\n",
639 test_mode, wIndex + 1);
640 xhci_port_set_test_mode(xhci, test_mode, wIndex);
644 static int xhci_exit_test_mode(struct xhci_hcd *xhci)
648 if (!xhci->test_mode) {
649 xhci_err(xhci, "Not in test mode, do nothing.\n");
652 if (xhci->test_mode == TEST_FORCE_EN &&
653 !(xhci->xhc_state & XHCI_STATE_HALTED)) {
654 retval = xhci_halt(xhci);
658 pm_runtime_allow(xhci_to_hcd(xhci)->self.controller);
660 return xhci_reset(xhci);
663 void xhci_set_link_state(struct xhci_hcd *xhci, __le32 __iomem **port_array,
664 int port_id, u32 link_state)
668 temp = readl(port_array[port_id]);
669 temp = xhci_port_state_to_neutral(temp);
670 temp &= ~PORT_PLS_MASK;
671 temp |= PORT_LINK_STROBE | link_state;
672 writel(temp, port_array[port_id]);
675 static void xhci_set_remote_wake_mask(struct xhci_hcd *xhci,
676 __le32 __iomem **port_array, int port_id, u16 wake_mask)
680 temp = readl(port_array[port_id]);
681 temp = xhci_port_state_to_neutral(temp);
683 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_CONNECT)
684 temp |= PORT_WKCONN_E;
686 temp &= ~PORT_WKCONN_E;
688 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_DISCONNECT)
689 temp |= PORT_WKDISC_E;
691 temp &= ~PORT_WKDISC_E;
693 if (wake_mask & USB_PORT_FEAT_REMOTE_WAKE_OVER_CURRENT)
696 temp &= ~PORT_WKOC_E;
698 writel(temp, port_array[port_id]);
701 /* Test and clear port RWC bit */
702 void xhci_test_and_clear_bit(struct xhci_hcd *xhci, __le32 __iomem **port_array,
703 int port_id, u32 port_bit)
707 temp = readl(port_array[port_id]);
708 if (temp & port_bit) {
709 temp = xhci_port_state_to_neutral(temp);
711 writel(temp, port_array[port_id]);
715 /* Updates Link Status for USB 2.1 port */
716 static void xhci_hub_report_usb2_link_state(u32 *status, u32 status_reg)
718 if ((status_reg & PORT_PLS_MASK) == XDEV_U2)
719 *status |= USB_PORT_STAT_L1;
722 /* Updates Link Status for super Speed port */
723 static void xhci_hub_report_usb3_link_state(struct xhci_hcd *xhci,
724 u32 *status, u32 status_reg)
726 u32 pls = status_reg & PORT_PLS_MASK;
728 /* resume state is a xHCI internal state.
729 * Do not report it to usb core, instead, pretend to be U3,
730 * thus usb core knows it's not ready for transfer
732 if (pls == XDEV_RESUME) {
733 *status |= USB_SS_PORT_LS_U3;
737 /* When the CAS bit is set then warm reset
738 * should be performed on port
740 if (status_reg & PORT_CAS) {
741 /* The CAS bit can be set while the port is
743 * Only roothubs have CAS bit, so we
744 * pretend to be in compliance mode
745 * unless we're already in compliance
746 * or the inactive state.
748 if (pls != USB_SS_PORT_LS_COMP_MOD &&
749 pls != USB_SS_PORT_LS_SS_INACTIVE) {
750 pls = USB_SS_PORT_LS_COMP_MOD;
752 /* Return also connection bit -
753 * hub state machine resets port
754 * when this bit is set.
756 pls |= USB_PORT_STAT_CONNECTION;
759 * If CAS bit isn't set but the Port is already at
760 * Compliance Mode, fake a connection so the USB core
761 * notices the Compliance state and resets the port.
762 * This resolves an issue generated by the SN65LVPE502CP
763 * in which sometimes the port enters compliance mode
764 * caused by a delay on the host-device negotiation.
766 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
767 (pls == USB_SS_PORT_LS_COMP_MOD))
768 pls |= USB_PORT_STAT_CONNECTION;
771 /* update status field */
776 * Function for Compliance Mode Quirk.
778 * This Function verifies if all xhc USB3 ports have entered U0, if so,
779 * the compliance mode timer is deleted. A port won't enter
780 * compliance mode if it has previously entered U0.
782 static void xhci_del_comp_mod_timer(struct xhci_hcd *xhci, u32 status,
785 u32 all_ports_seen_u0 = ((1 << xhci->num_usb3_ports)-1);
786 bool port_in_u0 = ((status & PORT_PLS_MASK) == XDEV_U0);
788 if (!(xhci->quirks & XHCI_COMP_MODE_QUIRK))
791 if ((xhci->port_status_u0 != all_ports_seen_u0) && port_in_u0) {
792 xhci->port_status_u0 |= 1 << wIndex;
793 if (xhci->port_status_u0 == all_ports_seen_u0) {
794 del_timer_sync(&xhci->comp_mode_recovery_timer);
795 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
796 "All USB3 ports have entered U0 already!");
797 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
798 "Compliance Mode Recovery Timer Deleted.");
803 static u32 xhci_get_ext_port_status(u32 raw_port_status, u32 port_li)
808 /* only support rx and tx lane counts of 1 in usb3.1 spec */
809 speed_id = DEV_PORT_SPEED(raw_port_status);
810 ext_stat |= speed_id; /* bits 3:0, RX speed id */
811 ext_stat |= speed_id << 4; /* bits 7:4, TX speed id */
813 ext_stat |= PORT_RX_LANES(port_li) << 8; /* bits 11:8 Rx lane count */
814 ext_stat |= PORT_TX_LANES(port_li) << 12; /* bits 15:12 Tx lane count */
820 * Converts a raw xHCI port status into the format that external USB 2.0 or USB
823 * Possible side effects:
824 * - Mark a port as being done with device resume,
825 * and ring the endpoint doorbells.
826 * - Stop the Synopsys redriver Compliance Mode polling.
827 * - Drop and reacquire the xHCI lock, in order to wait for port resume.
829 static u32 xhci_get_port_status(struct usb_hcd *hcd,
830 struct xhci_bus_state *bus_state,
831 __le32 __iomem **port_array,
832 u16 wIndex, u32 raw_port_status,
834 __releases(&xhci->lock)
835 __acquires(&xhci->lock)
837 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
841 /* wPortChange bits */
842 if (raw_port_status & PORT_CSC)
843 status |= USB_PORT_STAT_C_CONNECTION << 16;
844 if (raw_port_status & PORT_PEC)
845 status |= USB_PORT_STAT_C_ENABLE << 16;
846 if ((raw_port_status & PORT_OCC))
847 status |= USB_PORT_STAT_C_OVERCURRENT << 16;
848 if ((raw_port_status & PORT_RC))
849 status |= USB_PORT_STAT_C_RESET << 16;
851 if (hcd->speed >= HCD_USB3) {
852 /* Port link change with port in resume state should not be
853 * reported to usbcore, as this is an internal state to be
854 * handled by xhci driver. Reporting PLC to usbcore may
855 * cause usbcore clearing PLC first and port change event
856 * irq won't be generated.
858 if ((raw_port_status & PORT_PLC) &&
859 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME)
860 status |= USB_PORT_STAT_C_LINK_STATE << 16;
861 if ((raw_port_status & PORT_WRC))
862 status |= USB_PORT_STAT_C_BH_RESET << 16;
863 if ((raw_port_status & PORT_CEC))
864 status |= USB_PORT_STAT_C_CONFIG_ERROR << 16;
867 if (hcd->speed < HCD_USB3) {
868 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U3
869 && (raw_port_status & PORT_POWER))
870 status |= USB_PORT_STAT_SUSPEND;
872 if ((raw_port_status & PORT_PLS_MASK) == XDEV_RESUME &&
873 !DEV_SUPERSPEED_ANY(raw_port_status)) {
874 if ((raw_port_status & PORT_RESET) ||
875 !(raw_port_status & PORT_PE))
877 /* did port event handler already start resume timing? */
878 if (!bus_state->resume_done[wIndex]) {
879 /* If not, maybe we are in a host initated resume? */
880 if (test_bit(wIndex, &bus_state->resuming_ports)) {
881 /* Host initated resume doesn't time the resume
882 * signalling using resume_done[].
883 * It manually sets RESUME state, sleeps 20ms
884 * and sets U0 state. This should probably be
885 * changed, but not right now.
888 /* port resume was discovered now and here,
889 * start resume timing
891 unsigned long timeout = jiffies +
892 msecs_to_jiffies(USB_RESUME_TIMEOUT);
894 set_bit(wIndex, &bus_state->resuming_ports);
895 bus_state->resume_done[wIndex] = timeout;
896 mod_timer(&hcd->rh_timer, timeout);
898 /* Has resume been signalled for USB_RESUME_TIME yet? */
899 } else if (time_after_eq(jiffies,
900 bus_state->resume_done[wIndex])) {
903 xhci_dbg(xhci, "Resume USB2 port %d\n",
905 bus_state->resume_done[wIndex] = 0;
906 clear_bit(wIndex, &bus_state->resuming_ports);
908 set_bit(wIndex, &bus_state->rexit_ports);
910 xhci_test_and_clear_bit(xhci, port_array, wIndex,
912 xhci_set_link_state(xhci, port_array, wIndex,
915 spin_unlock_irqrestore(&xhci->lock, flags);
916 time_left = wait_for_completion_timeout(
917 &bus_state->rexit_done[wIndex],
919 XHCI_MAX_REXIT_TIMEOUT));
920 spin_lock_irqsave(&xhci->lock, flags);
923 slot_id = xhci_find_slot_id_by_port(hcd,
926 xhci_dbg(xhci, "slot_id is zero\n");
929 xhci_ring_device(xhci, slot_id);
931 int port_status = readl(port_array[wIndex]);
932 xhci_warn(xhci, "Port resume took longer than %i msec, port status = 0x%x\n",
933 XHCI_MAX_REXIT_TIMEOUT,
935 status |= USB_PORT_STAT_SUSPEND;
936 clear_bit(wIndex, &bus_state->rexit_ports);
939 bus_state->port_c_suspend |= 1 << wIndex;
940 bus_state->suspended_ports &= ~(1 << wIndex);
943 * The resume has been signaling for less than
944 * USB_RESUME_TIME. Report the port status as SUSPEND,
945 * let the usbcore check port status again and clear
946 * resume signaling later.
948 status |= USB_PORT_STAT_SUSPEND;
952 * Clear stale usb2 resume signalling variables in case port changed
953 * state during resume signalling. For example on error
955 if ((bus_state->resume_done[wIndex] ||
956 test_bit(wIndex, &bus_state->resuming_ports)) &&
957 (raw_port_status & PORT_PLS_MASK) != XDEV_U3 &&
958 (raw_port_status & PORT_PLS_MASK) != XDEV_RESUME) {
959 bus_state->resume_done[wIndex] = 0;
960 clear_bit(wIndex, &bus_state->resuming_ports);
964 if ((raw_port_status & PORT_PLS_MASK) == XDEV_U0 &&
965 (raw_port_status & PORT_POWER)) {
966 if (bus_state->suspended_ports & (1 << wIndex)) {
967 bus_state->suspended_ports &= ~(1 << wIndex);
968 if (hcd->speed < HCD_USB3)
969 bus_state->port_c_suspend |= 1 << wIndex;
971 bus_state->resume_done[wIndex] = 0;
972 clear_bit(wIndex, &bus_state->resuming_ports);
974 if (raw_port_status & PORT_CONNECT) {
975 status |= USB_PORT_STAT_CONNECTION;
976 status |= xhci_port_speed(raw_port_status);
978 if (raw_port_status & PORT_PE)
979 status |= USB_PORT_STAT_ENABLE;
980 if (raw_port_status & PORT_OC)
981 status |= USB_PORT_STAT_OVERCURRENT;
982 if (raw_port_status & PORT_RESET)
983 status |= USB_PORT_STAT_RESET;
984 if (raw_port_status & PORT_POWER) {
985 if (hcd->speed >= HCD_USB3)
986 status |= USB_SS_PORT_STAT_POWER;
988 status |= USB_PORT_STAT_POWER;
990 /* Update Port Link State */
991 if (hcd->speed >= HCD_USB3) {
992 xhci_hub_report_usb3_link_state(xhci, &status, raw_port_status);
994 * Verify if all USB3 Ports Have entered U0 already.
995 * Delete Compliance Mode Timer if so.
997 xhci_del_comp_mod_timer(xhci, raw_port_status, wIndex);
999 xhci_hub_report_usb2_link_state(&status, raw_port_status);
1001 if (bus_state->port_c_suspend & (1 << wIndex))
1002 status |= USB_PORT_STAT_C_SUSPEND << 16;
1007 int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
1008 u16 wIndex, char *buf, u16 wLength)
1010 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1012 unsigned long flags;
1015 __le32 __iomem **port_array;
1017 struct xhci_bus_state *bus_state;
1023 max_ports = xhci_get_ports(hcd, &port_array);
1024 bus_state = &xhci->bus_state[hcd_index(hcd)];
1026 spin_lock_irqsave(&xhci->lock, flags);
1029 /* No power source, over-current reported per port */
1032 case GetHubDescriptor:
1033 /* Check to make sure userspace is asking for the USB 3.0 hub
1034 * descriptor for the USB 3.0 roothub. If not, we stall the
1035 * endpoint, like external hubs do.
1037 if (hcd->speed >= HCD_USB3 &&
1038 (wLength < USB_DT_SS_HUB_SIZE ||
1039 wValue != (USB_DT_SS_HUB << 8))) {
1040 xhci_dbg(xhci, "Wrong hub descriptor type for "
1041 "USB 3.0 roothub.\n");
1044 xhci_hub_descriptor(hcd, xhci,
1045 (struct usb_hub_descriptor *) buf);
1047 case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
1048 if ((wValue & 0xff00) != (USB_DT_BOS << 8))
1051 if (hcd->speed < HCD_USB3)
1054 retval = xhci_create_usb3_bos_desc(xhci, buf, wLength);
1055 spin_unlock_irqrestore(&xhci->lock, flags);
1058 if (!wIndex || wIndex > max_ports)
1061 temp = readl(port_array[wIndex]);
1062 if (temp == ~(u32)0) {
1067 status = xhci_get_port_status(hcd, bus_state, port_array,
1068 wIndex, temp, flags);
1069 if (status == 0xffffffff)
1072 xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n",
1074 xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
1076 put_unaligned(cpu_to_le32(status), (__le32 *) buf);
1077 /* if USB 3.1 extended port status return additional 4 bytes */
1078 if (wValue == 0x02) {
1081 if (hcd->speed < HCD_USB31 || wLength != 8) {
1082 xhci_err(xhci, "get ext port status invalid parameter\n");
1086 port_li = readl(port_array[wIndex] + PORTLI);
1087 status = xhci_get_ext_port_status(temp, port_li);
1088 put_unaligned_le32(cpu_to_le32(status), &buf[4]);
1091 case SetPortFeature:
1092 if (wValue == USB_PORT_FEAT_LINK_STATE)
1093 link_state = (wIndex & 0xff00) >> 3;
1094 if (wValue == USB_PORT_FEAT_REMOTE_WAKE_MASK)
1095 wake_mask = wIndex & 0xff00;
1096 if (wValue == USB_PORT_FEAT_TEST)
1097 test_mode = (wIndex & 0xff00) >> 8;
1098 /* The MSB of wIndex is the U1/U2 timeout */
1099 timeout = (wIndex & 0xff00) >> 8;
1101 if (!wIndex || wIndex > max_ports)
1104 temp = readl(port_array[wIndex]);
1105 if (temp == ~(u32)0) {
1110 temp = xhci_port_state_to_neutral(temp);
1111 /* FIXME: What new port features do we need to support? */
1113 case USB_PORT_FEAT_SUSPEND:
1114 temp = readl(port_array[wIndex]);
1115 if ((temp & PORT_PLS_MASK) != XDEV_U0) {
1116 /* Resume the port to U0 first */
1117 xhci_set_link_state(xhci, port_array, wIndex,
1119 spin_unlock_irqrestore(&xhci->lock, flags);
1121 spin_lock_irqsave(&xhci->lock, flags);
1123 /* In spec software should not attempt to suspend
1124 * a port unless the port reports that it is in the
1125 * enabled (PED = ‘1’,PLS < ‘3’) state.
1127 temp = readl(port_array[wIndex]);
1128 if ((temp & PORT_PE) == 0 || (temp & PORT_RESET)
1129 || (temp & PORT_PLS_MASK) >= XDEV_U3) {
1130 xhci_warn(xhci, "USB core suspending device not in U0/U1/U2.\n");
1134 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1137 xhci_warn(xhci, "slot_id is zero\n");
1140 /* unlock to execute stop endpoint commands */
1141 spin_unlock_irqrestore(&xhci->lock, flags);
1142 xhci_stop_device(xhci, slot_id, 1);
1143 spin_lock_irqsave(&xhci->lock, flags);
1145 xhci_set_link_state(xhci, port_array, wIndex, XDEV_U3);
1147 spin_unlock_irqrestore(&xhci->lock, flags);
1148 msleep(10); /* wait device to enter */
1149 spin_lock_irqsave(&xhci->lock, flags);
1151 temp = readl(port_array[wIndex]);
1152 bus_state->suspended_ports |= 1 << wIndex;
1154 case USB_PORT_FEAT_LINK_STATE:
1155 temp = readl(port_array[wIndex]);
1158 if (link_state == USB_SS_PORT_LS_SS_DISABLED) {
1159 xhci_dbg(xhci, "Disable port %d\n", wIndex);
1160 temp = xhci_port_state_to_neutral(temp);
1162 * Clear all change bits, so that we get a new
1165 temp |= PORT_CSC | PORT_PEC | PORT_WRC |
1166 PORT_OCC | PORT_RC | PORT_PLC |
1168 writel(temp | PORT_PE, port_array[wIndex]);
1169 temp = readl(port_array[wIndex]);
1173 /* Put link in RxDetect (enable port) */
1174 if (link_state == USB_SS_PORT_LS_RX_DETECT) {
1175 xhci_dbg(xhci, "Enable port %d\n", wIndex);
1176 xhci_set_link_state(xhci, port_array, wIndex,
1178 temp = readl(port_array[wIndex]);
1182 /* Software should not attempt to set
1183 * port link state above '3' (U3) and the port
1186 if ((temp & PORT_PE) == 0 ||
1187 (link_state > USB_SS_PORT_LS_U3)) {
1188 xhci_warn(xhci, "Cannot set link state.\n");
1192 if (link_state == USB_SS_PORT_LS_U3) {
1193 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1196 /* unlock to execute stop endpoint
1198 spin_unlock_irqrestore(&xhci->lock,
1200 xhci_stop_device(xhci, slot_id, 1);
1201 spin_lock_irqsave(&xhci->lock, flags);
1205 xhci_set_link_state(xhci, port_array, wIndex,
1208 spin_unlock_irqrestore(&xhci->lock, flags);
1209 msleep(20); /* wait device to enter */
1210 spin_lock_irqsave(&xhci->lock, flags);
1212 temp = readl(port_array[wIndex]);
1213 if (link_state == USB_SS_PORT_LS_U3)
1214 bus_state->suspended_ports |= 1 << wIndex;
1216 case USB_PORT_FEAT_POWER:
1218 * Turn on ports, even if there isn't per-port switching.
1219 * HC will report connect events even before this is set.
1220 * However, hub_wq will ignore the roothub events until
1221 * the roothub is registered.
1223 xhci_set_port_power(xhci, hcd, wIndex, true, &flags);
1225 case USB_PORT_FEAT_RESET:
1226 temp = (temp | PORT_RESET);
1227 writel(temp, port_array[wIndex]);
1229 temp = readl(port_array[wIndex]);
1230 xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
1232 case USB_PORT_FEAT_REMOTE_WAKE_MASK:
1233 xhci_set_remote_wake_mask(xhci, port_array,
1235 temp = readl(port_array[wIndex]);
1236 xhci_dbg(xhci, "set port remote wake mask, "
1237 "actual port %d status = 0x%x\n",
1240 case USB_PORT_FEAT_BH_PORT_RESET:
1242 writel(temp, port_array[wIndex]);
1244 temp = readl(port_array[wIndex]);
1246 case USB_PORT_FEAT_U1_TIMEOUT:
1247 if (hcd->speed < HCD_USB3)
1249 temp = readl(port_array[wIndex] + PORTPMSC);
1250 temp &= ~PORT_U1_TIMEOUT_MASK;
1251 temp |= PORT_U1_TIMEOUT(timeout);
1252 writel(temp, port_array[wIndex] + PORTPMSC);
1254 case USB_PORT_FEAT_U2_TIMEOUT:
1255 if (hcd->speed < HCD_USB3)
1257 temp = readl(port_array[wIndex] + PORTPMSC);
1258 temp &= ~PORT_U2_TIMEOUT_MASK;
1259 temp |= PORT_U2_TIMEOUT(timeout);
1260 writel(temp, port_array[wIndex] + PORTPMSC);
1262 case USB_PORT_FEAT_TEST:
1263 /* 4.19.6 Port Test Modes (USB2 Test Mode) */
1264 if (hcd->speed != HCD_USB2)
1266 if (test_mode > TEST_FORCE_EN || test_mode < TEST_J)
1268 retval = xhci_enter_test_mode(xhci, test_mode, wIndex,
1274 /* unblock any posted writes */
1275 temp = readl(port_array[wIndex]);
1277 case ClearPortFeature:
1278 if (!wIndex || wIndex > max_ports)
1281 temp = readl(port_array[wIndex]);
1282 if (temp == ~(u32)0) {
1287 /* FIXME: What new port features do we need to support? */
1288 temp = xhci_port_state_to_neutral(temp);
1290 case USB_PORT_FEAT_SUSPEND:
1291 temp = readl(port_array[wIndex]);
1292 xhci_dbg(xhci, "clear USB_PORT_FEAT_SUSPEND\n");
1293 xhci_dbg(xhci, "PORTSC %04x\n", temp);
1294 if (temp & PORT_RESET)
1296 if ((temp & PORT_PLS_MASK) == XDEV_U3) {
1297 if ((temp & PORT_PE) == 0)
1300 set_bit(wIndex, &bus_state->resuming_ports);
1301 xhci_set_link_state(xhci, port_array, wIndex,
1303 spin_unlock_irqrestore(&xhci->lock, flags);
1304 msleep(USB_RESUME_TIMEOUT);
1305 spin_lock_irqsave(&xhci->lock, flags);
1306 xhci_set_link_state(xhci, port_array, wIndex,
1308 clear_bit(wIndex, &bus_state->resuming_ports);
1310 bus_state->port_c_suspend |= 1 << wIndex;
1312 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1315 xhci_dbg(xhci, "slot_id is zero\n");
1318 xhci_ring_device(xhci, slot_id);
1320 case USB_PORT_FEAT_C_SUSPEND:
1321 bus_state->port_c_suspend &= ~(1 << wIndex);
1322 case USB_PORT_FEAT_C_RESET:
1323 case USB_PORT_FEAT_C_BH_PORT_RESET:
1324 case USB_PORT_FEAT_C_CONNECTION:
1325 case USB_PORT_FEAT_C_OVER_CURRENT:
1326 case USB_PORT_FEAT_C_ENABLE:
1327 case USB_PORT_FEAT_C_PORT_LINK_STATE:
1328 case USB_PORT_FEAT_C_PORT_CONFIG_ERROR:
1329 xhci_clear_port_change_bit(xhci, wValue, wIndex,
1330 port_array[wIndex], temp);
1332 case USB_PORT_FEAT_ENABLE:
1333 xhci_disable_port(hcd, xhci, wIndex,
1334 port_array[wIndex], temp);
1336 case USB_PORT_FEAT_POWER:
1337 xhci_set_port_power(xhci, hcd, wIndex, false, &flags);
1339 case USB_PORT_FEAT_TEST:
1340 retval = xhci_exit_test_mode(xhci);
1348 /* "stall" on error */
1351 spin_unlock_irqrestore(&xhci->lock, flags);
1356 * Returns 0 if the status hasn't changed, or the number of bytes in buf.
1357 * Ports are 0-indexed from the HCD point of view,
1358 * and 1-indexed from the USB core pointer of view.
1360 * Note that the status change bits will be cleared as soon as a port status
1361 * change event is generated, so we use the saved status from that event.
1363 int xhci_hub_status_data(struct usb_hcd *hcd, char *buf)
1365 unsigned long flags;
1369 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1371 __le32 __iomem **port_array;
1372 struct xhci_bus_state *bus_state;
1373 bool reset_change = false;
1375 max_ports = xhci_get_ports(hcd, &port_array);
1376 bus_state = &xhci->bus_state[hcd_index(hcd)];
1378 /* Initial status is no changes */
1379 retval = (max_ports + 8) / 8;
1380 memset(buf, 0, retval);
1383 * Inform the usbcore about resume-in-progress by returning
1384 * a non-zero value even if there are no status changes.
1386 status = bus_state->resuming_ports;
1388 mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC | PORT_WRC | PORT_CEC;
1390 spin_lock_irqsave(&xhci->lock, flags);
1391 /* For each port, did anything change? If so, set that bit in buf. */
1392 for (i = 0; i < max_ports; i++) {
1393 temp = readl(port_array[i]);
1394 if (temp == ~(u32)0) {
1399 if ((temp & mask) != 0 ||
1400 (bus_state->port_c_suspend & 1 << i) ||
1401 (bus_state->resume_done[i] && time_after_eq(
1402 jiffies, bus_state->resume_done[i]))) {
1403 buf[(i + 1) / 8] |= 1 << (i + 1) % 8;
1406 if ((temp & PORT_RC))
1407 reset_change = true;
1409 if (!status && !reset_change) {
1410 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
1411 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1413 spin_unlock_irqrestore(&xhci->lock, flags);
1414 return status ? retval : 0;
1419 int xhci_bus_suspend(struct usb_hcd *hcd)
1421 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1422 int max_ports, port_index;
1423 __le32 __iomem **port_array;
1424 struct xhci_bus_state *bus_state;
1425 unsigned long flags;
1427 max_ports = xhci_get_ports(hcd, &port_array);
1428 bus_state = &xhci->bus_state[hcd_index(hcd)];
1430 spin_lock_irqsave(&xhci->lock, flags);
1432 if (hcd->self.root_hub->do_remote_wakeup) {
1433 if (bus_state->resuming_ports || /* USB2 */
1434 bus_state->port_remote_wakeup) { /* USB3 */
1435 spin_unlock_irqrestore(&xhci->lock, flags);
1436 xhci_dbg(xhci, "suspend failed because a port is resuming\n");
1441 port_index = max_ports;
1442 bus_state->bus_suspended = 0;
1443 while (port_index--) {
1444 /* suspend the port if the port is not suspended */
1448 t1 = readl(port_array[port_index]);
1449 t2 = xhci_port_state_to_neutral(t1);
1451 if ((t1 & PORT_PE) && !(t1 & PORT_PLS_MASK)) {
1452 xhci_dbg(xhci, "port %d not suspended\n", port_index);
1453 slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1456 spin_unlock_irqrestore(&xhci->lock, flags);
1457 xhci_stop_device(xhci, slot_id, 1);
1458 spin_lock_irqsave(&xhci->lock, flags);
1460 t2 &= ~PORT_PLS_MASK;
1461 t2 |= PORT_LINK_STROBE | XDEV_U3;
1462 set_bit(port_index, &bus_state->bus_suspended);
1464 /* USB core sets remote wake mask for USB 3.0 hubs,
1465 * including the USB 3.0 roothub, but only if CONFIG_PM
1466 * is enabled, so also enable remote wake here.
1468 if (hcd->self.root_hub->do_remote_wakeup) {
1469 if (t1 & PORT_CONNECT) {
1470 t2 |= PORT_WKOC_E | PORT_WKDISC_E;
1471 t2 &= ~PORT_WKCONN_E;
1473 t2 |= PORT_WKOC_E | PORT_WKCONN_E;
1474 t2 &= ~PORT_WKDISC_E;
1476 if ((xhci->quirks & XHCI_U2_DISABLE_WAKE) &&
1477 (hcd->speed < HCD_USB3))
1478 t2 &= ~PORT_WAKE_BITS;
1480 t2 &= ~PORT_WAKE_BITS;
1482 t1 = xhci_port_state_to_neutral(t1);
1484 writel(t2, port_array[port_index]);
1486 hcd->state = HC_STATE_SUSPENDED;
1487 bus_state->next_statechange = jiffies + msecs_to_jiffies(10);
1488 spin_unlock_irqrestore(&xhci->lock, flags);
1493 * Workaround for missing Cold Attach Status (CAS) if device re-plugged in S3.
1494 * warm reset a USB3 device stuck in polling or compliance mode after resume.
1495 * See Intel 100/c230 series PCH specification update Doc #332692-006 Errata #8
1497 static bool xhci_port_missing_cas_quirk(int port_index,
1498 __le32 __iomem **port_array)
1502 portsc = readl(port_array[port_index]);
1504 /* if any of these are set we are not stuck */
1505 if (portsc & (PORT_CONNECT | PORT_CAS))
1508 if (((portsc & PORT_PLS_MASK) != XDEV_POLLING) &&
1509 ((portsc & PORT_PLS_MASK) != XDEV_COMP_MODE))
1512 /* clear wakeup/change bits, and do a warm port reset */
1513 portsc &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1515 writel(portsc, port_array[port_index]);
1517 readl(port_array[port_index]);
1521 int xhci_bus_resume(struct usb_hcd *hcd)
1523 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1524 int max_ports, port_index;
1525 __le32 __iomem **port_array;
1526 struct xhci_bus_state *bus_state;
1528 unsigned long flags;
1529 unsigned long port_was_suspended = 0;
1530 bool need_usb2_u3_exit = false;
1534 max_ports = xhci_get_ports(hcd, &port_array);
1535 bus_state = &xhci->bus_state[hcd_index(hcd)];
1537 if (time_before(jiffies, bus_state->next_statechange))
1540 spin_lock_irqsave(&xhci->lock, flags);
1541 if (!HCD_HW_ACCESSIBLE(hcd)) {
1542 spin_unlock_irqrestore(&xhci->lock, flags);
1546 /* delay the irqs */
1547 temp = readl(&xhci->op_regs->command);
1549 writel(temp, &xhci->op_regs->command);
1551 port_index = max_ports;
1552 while (port_index--) {
1553 /* Check whether need resume ports. If needed
1554 resume port and disable remote wakeup */
1557 temp = readl(port_array[port_index]);
1559 /* warm reset CAS limited ports stuck in polling/compliance */
1560 if ((xhci->quirks & XHCI_MISSING_CAS) &&
1561 (hcd->speed >= HCD_USB3) &&
1562 xhci_port_missing_cas_quirk(port_index, port_array)) {
1563 xhci_dbg(xhci, "reset stuck port %d\n", port_index);
1566 if (DEV_SUPERSPEED_ANY(temp))
1567 temp &= ~(PORT_RWC_BITS | PORT_CEC | PORT_WAKE_BITS);
1569 temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
1570 if (test_bit(port_index, &bus_state->bus_suspended) &&
1571 (temp & PORT_PLS_MASK)) {
1572 set_bit(port_index, &port_was_suspended);
1573 if (!DEV_SUPERSPEED_ANY(temp)) {
1574 xhci_set_link_state(xhci, port_array,
1575 port_index, XDEV_RESUME);
1576 need_usb2_u3_exit = true;
1579 writel(temp, port_array[port_index]);
1582 if (need_usb2_u3_exit) {
1583 spin_unlock_irqrestore(&xhci->lock, flags);
1584 msleep(USB_RESUME_TIMEOUT);
1585 spin_lock_irqsave(&xhci->lock, flags);
1588 port_index = max_ports;
1589 while (port_index--) {
1590 if (!(port_was_suspended & BIT(port_index)))
1592 /* Clear PLC to poll it later after XDEV_U0 */
1593 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1594 xhci_set_link_state(xhci, port_array, port_index, XDEV_U0);
1597 port_index = max_ports;
1598 while (port_index--) {
1599 if (!(port_was_suspended & BIT(port_index)))
1601 /* Poll and Clear PLC */
1602 sret = xhci_handshake(port_array[port_index], PORT_PLC,
1603 PORT_PLC, 10 * 1000);
1605 xhci_warn(xhci, "port %d resume PLC timeout\n",
1607 xhci_test_and_clear_bit(xhci, port_array, port_index, PORT_PLC);
1608 slot_id = xhci_find_slot_id_by_port(hcd, xhci, port_index + 1);
1610 xhci_ring_device(xhci, slot_id);
1613 (void) readl(&xhci->op_regs->command);
1615 bus_state->next_statechange = jiffies + msecs_to_jiffies(5);
1616 /* re-enable irqs */
1617 temp = readl(&xhci->op_regs->command);
1619 writel(temp, &xhci->op_regs->command);
1620 temp = readl(&xhci->op_regs->command);
1622 spin_unlock_irqrestore(&xhci->lock, flags);
1626 #endif /* CONFIG_PM */