2 * xHCI host controller driver PCI Bus Glue.
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/pci.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/acpi.h>
29 #include "xhci-trace.h"
31 #define SSIC_PORT_NUM 2
32 #define SSIC_PORT_CFG2 0x880c
33 #define SSIC_PORT_CFG2_OFFSET 0x30
34 #define PROG_DONE (1 << 30)
35 #define SSIC_PORT_UNUSED (1 << 31)
37 /* Device for a quirk */
38 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
39 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
40 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
41 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
43 #define PCI_VENDOR_ID_ETRON 0x1b6f
44 #define PCI_DEVICE_ID_EJ168 0x7023
46 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
47 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
48 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
49 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
50 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
51 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
52 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
53 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
54 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
55 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
57 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
58 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
59 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
60 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
62 static const char hcd_name[] = "xhci_hcd";
64 static struct hc_driver __read_mostly xhci_pci_hc_driver;
66 static int xhci_pci_setup(struct usb_hcd *hcd);
68 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
69 .reset = xhci_pci_setup,
72 /* called after powerup, by probe or system-pm "wakeup" */
73 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
76 * TODO: Implement finding debug ports later.
77 * TODO: see if there are any quirks that need to be added to handle
78 * new extended capabilities.
81 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
82 if (!pci_set_mwi(pdev))
83 xhci_dbg(xhci, "MWI active\n");
85 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
89 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
91 struct pci_dev *pdev = to_pci_dev(dev);
93 /* Look for vendor-specific quirks */
94 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
95 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
96 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
97 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
98 pdev->revision == 0x0) {
99 xhci->quirks |= XHCI_RESET_EP_QUIRK;
100 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
101 "QUIRK: Fresco Logic xHC needs configure"
102 " endpoint cmd after reset endpoint");
104 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
105 pdev->revision == 0x4) {
106 xhci->quirks |= XHCI_SLOW_SUSPEND;
107 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
108 "QUIRK: Fresco Logic xHC revision %u"
109 "must be suspended extra slowly",
112 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
113 xhci->quirks |= XHCI_BROKEN_STREAMS;
114 /* Fresco Logic confirms: all revisions of this chip do not
115 * support MSI, even though some of them claim to in their PCI
118 xhci->quirks |= XHCI_BROKEN_MSI;
119 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
120 "QUIRK: Fresco Logic revision %u "
121 "has broken MSI implementation",
123 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
126 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
127 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
128 xhci->quirks |= XHCI_BROKEN_STREAMS;
130 if (pdev->vendor == PCI_VENDOR_ID_NEC)
131 xhci->quirks |= XHCI_NEC_HOST;
133 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
134 xhci->quirks |= XHCI_AMD_0x96_HOST;
137 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
138 xhci->quirks |= XHCI_AMD_PLL_FIX;
140 if (pdev->vendor == PCI_VENDOR_ID_AMD)
141 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
143 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
144 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
145 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
146 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
147 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
148 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
150 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
151 xhci->quirks |= XHCI_LPM_SUPPORT;
152 xhci->quirks |= XHCI_INTEL_HOST;
153 xhci->quirks |= XHCI_AVOID_BEI;
155 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
156 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
157 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
158 xhci->limit_active_eps = 64;
159 xhci->quirks |= XHCI_SW_BW_CHECKING;
161 * PPT desktop boards DH77EB and DH77DF will power back on after
162 * a few seconds of being shutdown. The fix for this is to
163 * switch the ports from xHCI to EHCI on shutdown. We can't use
164 * DMI information to find those particular boards (since each
165 * vendor will change the board name), so we have to key off all
168 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
170 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
171 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
172 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
173 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
174 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
176 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
177 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
178 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
179 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
180 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
181 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
182 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
183 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI)) {
184 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
186 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
187 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI) {
188 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
190 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
191 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
192 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
193 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
194 xhci->quirks |= XHCI_MISSING_CAS;
196 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
197 pdev->device == PCI_DEVICE_ID_EJ168) {
198 xhci->quirks |= XHCI_RESET_ON_RESUME;
199 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
200 xhci->quirks |= XHCI_BROKEN_STREAMS;
202 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
203 pdev->device == 0x0015)
204 xhci->quirks |= XHCI_RESET_ON_RESUME;
205 if (pdev->vendor == PCI_VENDOR_ID_VIA)
206 xhci->quirks |= XHCI_RESET_ON_RESUME;
208 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
209 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
210 pdev->device == 0x3432)
211 xhci->quirks |= XHCI_BROKEN_STREAMS;
213 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
214 pdev->device == 0x1042)
215 xhci->quirks |= XHCI_BROKEN_STREAMS;
216 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
217 pdev->device == 0x1142)
218 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
220 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
221 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
223 if (xhci->quirks & XHCI_RESET_ON_RESUME)
224 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
225 "QUIRK: Resetting on resume");
229 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
231 static const guid_t intel_dsm_guid =
232 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
233 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
234 union acpi_object *obj;
236 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
241 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
242 #endif /* CONFIG_ACPI */
244 /* called during probe() after chip reset completes */
245 static int xhci_pci_setup(struct usb_hcd *hcd)
247 struct xhci_hcd *xhci;
248 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
251 xhci = hcd_to_xhci(hcd);
253 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
255 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
259 if (!usb_hcd_is_primary_hcd(hcd))
262 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
264 /* Find any debug ports */
265 return xhci_pci_reinit(xhci, pdev);
269 * We need to register our own PCI probe function (instead of the USB core's
270 * function) in order to create a second roothub under xHCI.
272 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
275 struct xhci_hcd *xhci;
276 struct hc_driver *driver;
279 driver = (struct hc_driver *)id->driver_data;
281 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
282 pm_runtime_get_noresume(&dev->dev);
284 /* Register the USB 2.0 roothub.
285 * FIXME: USB core must know to register the USB 2.0 roothub first.
286 * This is sort of silly, because we could just set the HCD driver flags
287 * to say USB 2.0, but I'm not sure what the implications would be in
288 * the other parts of the HCD code.
290 retval = usb_hcd_pci_probe(dev, id);
295 /* USB 2.0 roothub is stored in the PCI device now. */
296 hcd = dev_get_drvdata(&dev->dev);
297 xhci = hcd_to_xhci(hcd);
298 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
300 if (!xhci->shared_hcd) {
302 goto dealloc_usb2_hcd;
305 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
309 /* Roothub already marked as USB 3.0 speed */
311 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
312 HCC_MAX_PSA(xhci->hcc_params) >= 4)
313 xhci->shared_hcd->can_do_streams = 1;
315 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
316 xhci_pme_acpi_rtd3_enable(dev);
318 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
319 pm_runtime_put_noidle(&dev->dev);
324 usb_put_hcd(xhci->shared_hcd);
326 usb_hcd_pci_remove(dev);
328 pm_runtime_put_noidle(&dev->dev);
332 static void xhci_pci_remove(struct pci_dev *dev)
334 struct xhci_hcd *xhci;
336 xhci = hcd_to_xhci(pci_get_drvdata(dev));
337 xhci->xhc_state |= XHCI_STATE_REMOVING;
338 if (xhci->shared_hcd) {
339 usb_remove_hcd(xhci->shared_hcd);
340 usb_put_hcd(xhci->shared_hcd);
343 /* Workaround for spurious wakeups at shutdown with HSW */
344 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
345 pci_set_power_state(dev, PCI_D3hot);
347 usb_hcd_pci_remove(dev);
352 * In some Intel xHCI controllers, in order to get D3 working,
353 * through a vendor specific SSIC CONFIG register at offset 0x883c,
354 * SSIC PORT need to be marked as "unused" before putting xHCI
355 * into D3. After D3 exit, the SSIC port need to be marked as "used".
356 * Without this change, xHCI might not enter D3 state.
358 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
360 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
365 for (i = 0; i < SSIC_PORT_NUM; i++) {
366 reg = (void __iomem *) xhci->cap_regs +
368 i * SSIC_PORT_CFG2_OFFSET;
370 /* Notify SSIC that SSIC profile programming is not done. */
371 val = readl(reg) & ~PROG_DONE;
374 /* Mark SSIC port as unused(suspend) or used(resume) */
377 val |= SSIC_PORT_UNUSED;
379 val &= ~SSIC_PORT_UNUSED;
382 /* Notify SSIC that SSIC profile programming is done */
383 val = readl(reg) | PROG_DONE;
390 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
391 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
393 static void xhci_pme_quirk(struct usb_hcd *hcd)
395 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
399 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
401 writel(val | BIT(28), reg);
405 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
407 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
408 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
412 * Systems with the TI redriver that loses port status change events
413 * need to have the registers polled during D3, so avoid D3cold.
415 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
416 pci_d3cold_disable(pdev);
418 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
421 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
422 xhci_ssic_port_unused_quirk(hcd, true);
424 ret = xhci_suspend(xhci, do_wakeup);
425 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
426 xhci_ssic_port_unused_quirk(hcd, false);
431 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
433 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
434 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
437 /* The BIOS on systems with the Intel Panther Point chipset may or may
438 * not support xHCI natively. That means that during system resume, it
439 * may switch the ports back to EHCI so that users can use their
440 * keyboard to select a kernel from GRUB after resume from hibernate.
442 * The BIOS is supposed to remember whether the OS had xHCI ports
443 * enabled before resume, and switch the ports back to xHCI when the
444 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
447 * Unconditionally switch the ports back to xHCI after a system resume.
448 * It should not matter whether the EHCI or xHCI controller is
449 * resumed first. It's enough to do the switchover in xHCI because
450 * USB core won't notice anything as the hub driver doesn't start
451 * running again until after all the devices (including both EHCI and
452 * xHCI host controllers) have been resumed.
455 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
456 usb_enable_intel_xhci_ports(pdev);
458 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
459 xhci_ssic_port_unused_quirk(hcd, false);
461 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
464 retval = xhci_resume(xhci, hibernated);
467 #endif /* CONFIG_PM */
469 /*-------------------------------------------------------------------------*/
471 /* PCI driver selection metadata; PCI hotplugging uses this */
472 static const struct pci_device_id pci_ids[] = { {
473 /* handle any USB 3.0 xHCI controller */
474 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
475 .driver_data = (unsigned long) &xhci_pci_hc_driver,
477 { /* end: all zeroes */ }
479 MODULE_DEVICE_TABLE(pci, pci_ids);
481 /* pci driver glue; this is a "new style" PCI driver module */
482 static struct pci_driver xhci_pci_driver = {
483 .name = (char *) hcd_name,
486 .probe = xhci_pci_probe,
487 .remove = xhci_pci_remove,
488 /* suspend and resume implemented later */
490 .shutdown = usb_hcd_pci_shutdown,
493 .pm = &usb_hcd_pci_pm_ops
498 static int __init xhci_pci_init(void)
500 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
502 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
503 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
505 return pci_register_driver(&xhci_pci_driver);
507 module_init(xhci_pci_init);
509 static void __exit xhci_pci_exit(void)
511 pci_unregister_driver(&xhci_pci_driver);
513 module_exit(xhci_pci_exit);
515 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
516 MODULE_LICENSE("GPL");