1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/iopoll.h>
13 #include <linux/irq.h>
14 #include <linux/log2.h>
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/slab.h>
18 #include <linux/dmi.h>
19 #include <linux/dma-mapping.h>
22 #include "xhci-trace.h"
24 #include "xhci-debugfs.h"
25 #include "xhci-dbgcap.h"
27 #define DRIVER_AUTHOR "Sarah Sharp"
28 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
30 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
32 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
33 static int link_quirk;
34 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
37 static unsigned long long quirks;
38 module_param(quirks, ullong, S_IRUGO);
39 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
41 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
43 struct xhci_segment *seg = ring->first_seg;
45 if (!td || !td->start_seg)
48 if (seg == td->start_seg)
51 } while (seg && seg != ring->first_seg);
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
74 ret = readl_poll_timeout_atomic(ptr, result,
75 (result & mask) == done ||
78 if (result == U32_MAX) /* card removed */
85 * Disable interrupts and begin the xHCI halting process.
87 void xhci_quiesce(struct xhci_hcd *xhci)
94 halted = readl(&xhci->op_regs->status) & STS_HALT;
98 cmd = readl(&xhci->op_regs->command);
100 writel(cmd, &xhci->op_regs->command);
104 * Force HC into halt state.
106 * Disable any IRQs and clear the run/stop bit.
107 * HC will complete any current and actively pipelined transactions, and
108 * should halt within 16 ms of the run/stop bit being cleared.
109 * Read HC Halted bit in the status register to see when the HC is finished.
111 int xhci_halt(struct xhci_hcd *xhci)
114 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
117 ret = xhci_handshake(&xhci->op_regs->status,
118 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
120 xhci_warn(xhci, "Host halt failed, %d\n", ret);
123 xhci->xhc_state |= XHCI_STATE_HALTED;
124 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
129 * Set the run bit and wait for the host to be running.
131 int xhci_start(struct xhci_hcd *xhci)
136 temp = readl(&xhci->op_regs->command);
138 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
140 writel(temp, &xhci->op_regs->command);
143 * Wait for the HCHalted Status bit to be 0 to indicate the host is
146 ret = xhci_handshake(&xhci->op_regs->status,
147 STS_HALT, 0, XHCI_MAX_HALT_USEC);
148 if (ret == -ETIMEDOUT)
149 xhci_err(xhci, "Host took too long to start, "
150 "waited %u microseconds.\n",
153 /* clear state flags. Including dying, halted or removing */
162 * This resets pipelines, timers, counters, state machines, etc.
163 * Transactions will be terminated immediately, and operational registers
164 * will be set to their defaults.
166 int xhci_reset(struct xhci_hcd *xhci)
172 state = readl(&xhci->op_regs->status);
174 if (state == ~(u32)0) {
175 xhci_warn(xhci, "Host not accessible, reset failed.\n");
179 if ((state & STS_HALT) == 0) {
180 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
184 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
185 command = readl(&xhci->op_regs->command);
186 command |= CMD_RESET;
187 writel(command, &xhci->op_regs->command);
189 /* Existing Intel xHCI controllers require a delay of 1 mS,
190 * after setting the CMD_RESET bit, and before accessing any
191 * HC registers. This allows the HC to complete the
192 * reset operation and be ready for HC register access.
193 * Without this delay, the subsequent HC register access,
194 * may result in a system hang very rarely.
196 if (xhci->quirks & XHCI_INTEL_HOST)
199 ret = xhci_handshake(&xhci->op_regs->command,
200 CMD_RESET, 0, 10 * 1000 * 1000);
204 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
205 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
207 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
208 "Wait for controller to be ready for doorbell rings");
210 * xHCI cannot write to any doorbells or operational registers other
211 * than status until the "Controller Not Ready" flag is cleared.
213 ret = xhci_handshake(&xhci->op_regs->status,
214 STS_CNR, 0, 10 * 1000 * 1000);
216 xhci->usb2_rhub.bus_state.port_c_suspend = 0;
217 xhci->usb2_rhub.bus_state.suspended_ports = 0;
218 xhci->usb2_rhub.bus_state.resuming_ports = 0;
219 xhci->usb3_rhub.bus_state.port_c_suspend = 0;
220 xhci->usb3_rhub.bus_state.suspended_ports = 0;
221 xhci->usb3_rhub.bus_state.resuming_ports = 0;
226 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
228 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
233 * Some Renesas controllers get into a weird state if they are
234 * reset while programmed with 64bit addresses (they will preserve
235 * the top half of the address in internal, non visible
236 * registers). You end up with half the address coming from the
237 * kernel, and the other half coming from the firmware. Also,
238 * changing the programming leads to extra accesses even if the
239 * controller is supposed to be halted. The controller ends up with
240 * a fatal fault, and is then ripe for being properly reset.
242 * Special care is taken to only apply this if the device is behind
243 * an iommu. Doing anything when there is no iommu is definitely
246 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !device_iommu_mapped(dev))
249 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
251 /* Clear HSEIE so that faults do not get signaled */
252 val = readl(&xhci->op_regs->command);
254 writel(val, &xhci->op_regs->command);
256 /* Clear HSE (aka FATAL) */
257 val = readl(&xhci->op_regs->status);
259 writel(val, &xhci->op_regs->status);
261 /* Now zero the registers, and brace for impact */
262 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
263 if (upper_32_bits(val))
264 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
265 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
266 if (upper_32_bits(val))
267 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
269 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
270 struct xhci_intr_reg __iomem *ir;
272 ir = &xhci->run_regs->ir_set[i];
273 val = xhci_read_64(xhci, &ir->erst_base);
274 if (upper_32_bits(val))
275 xhci_write_64(xhci, 0, &ir->erst_base);
276 val= xhci_read_64(xhci, &ir->erst_dequeue);
277 if (upper_32_bits(val))
278 xhci_write_64(xhci, 0, &ir->erst_dequeue);
281 /* Wait for the fault to appear. It will be cleared on reset */
282 err = xhci_handshake(&xhci->op_regs->status,
283 STS_FATAL, STS_FATAL,
286 xhci_info(xhci, "Fault detected\n");
289 #ifdef CONFIG_USB_PCI
293 static int xhci_setup_msi(struct xhci_hcd *xhci)
297 * TODO:Check with MSI Soc for sysdev
299 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
301 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
303 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
304 "failed to allocate MSI entry");
308 ret = request_irq(pdev->irq, xhci_msi_irq,
309 0, "xhci_hcd", xhci_to_hcd(xhci));
311 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
312 "disable MSI interrupt");
313 pci_free_irq_vectors(pdev);
322 static int xhci_setup_msix(struct xhci_hcd *xhci)
325 struct usb_hcd *hcd = xhci_to_hcd(xhci);
326 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
329 * calculate number of msi-x vectors supported.
330 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
331 * with max number of interrupters based on the xhci HCSPARAMS1.
332 * - num_online_cpus: maximum msi-x vectors per CPUs core.
333 * Add additional 1 vector to ensure always available interrupt.
335 xhci->msix_count = min(num_online_cpus() + 1,
336 HCS_MAX_INTRS(xhci->hcs_params1));
338 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
341 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
342 "Failed to enable MSI-X");
346 for (i = 0; i < xhci->msix_count; i++) {
347 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
348 "xhci_hcd", xhci_to_hcd(xhci));
353 hcd->msix_enabled = 1;
357 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
359 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
360 pci_free_irq_vectors(pdev);
364 /* Free any IRQs and disable MSI-X */
365 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
367 struct usb_hcd *hcd = xhci_to_hcd(xhci);
368 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
370 if (xhci->quirks & XHCI_PLAT)
373 /* return if using legacy interrupt */
377 if (hcd->msix_enabled) {
380 for (i = 0; i < xhci->msix_count; i++)
381 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
383 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
386 pci_free_irq_vectors(pdev);
387 hcd->msix_enabled = 0;
390 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
392 struct usb_hcd *hcd = xhci_to_hcd(xhci);
394 if (hcd->msix_enabled) {
395 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
398 for (i = 0; i < xhci->msix_count; i++)
399 synchronize_irq(pci_irq_vector(pdev, i));
403 static int xhci_try_enable_msi(struct usb_hcd *hcd)
405 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
406 struct pci_dev *pdev;
409 /* The xhci platform device has set up IRQs through usb_add_hcd. */
410 if (xhci->quirks & XHCI_PLAT)
413 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
415 * Some Fresco Logic host controllers advertise MSI, but fail to
416 * generate interrupts. Don't even try to enable MSI.
418 if (xhci->quirks & XHCI_BROKEN_MSI)
421 /* unregister the legacy interrupt */
423 free_irq(hcd->irq, hcd);
426 ret = xhci_setup_msix(xhci);
428 /* fall back to msi*/
429 ret = xhci_setup_msi(xhci);
432 hcd->msi_enabled = 1;
437 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
442 if (!strlen(hcd->irq_descr))
443 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
444 hcd->driver->description, hcd->self.busnum);
446 /* fall back to legacy interrupt*/
447 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
448 hcd->irq_descr, hcd);
450 xhci_err(xhci, "request interrupt %d failed\n",
454 hcd->irq = pdev->irq;
460 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
465 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
469 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
475 static void compliance_mode_recovery(struct timer_list *t)
477 struct xhci_hcd *xhci;
479 struct xhci_hub *rhub;
483 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
484 rhub = &xhci->usb3_rhub;
486 for (i = 0; i < rhub->num_ports; i++) {
487 temp = readl(rhub->ports[i]->addr);
488 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
490 * Compliance Mode Detected. Letting USB Core
491 * handle the Warm Reset
493 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
494 "Compliance mode detected->port %d",
496 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
497 "Attempting compliance mode recovery");
498 hcd = xhci->shared_hcd;
500 if (hcd->state == HC_STATE_SUSPENDED)
501 usb_hcd_resume_root_hub(hcd);
503 usb_hcd_poll_rh_status(hcd);
507 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
508 mod_timer(&xhci->comp_mode_recovery_timer,
509 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
513 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
514 * that causes ports behind that hardware to enter compliance mode sometimes.
515 * The quirk creates a timer that polls every 2 seconds the link state of
516 * each host controller's port and recovers it by issuing a Warm reset
517 * if Compliance mode is detected, otherwise the port will become "dead" (no
518 * device connections or disconnections will be detected anymore). Becasue no
519 * status event is generated when entering compliance mode (per xhci spec),
520 * this quirk is needed on systems that have the failing hardware installed.
522 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
524 xhci->port_status_u0 = 0;
525 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
527 xhci->comp_mode_recovery_timer.expires = jiffies +
528 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
530 add_timer(&xhci->comp_mode_recovery_timer);
531 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
532 "Compliance mode recovery timer initialized");
536 * This function identifies the systems that have installed the SN65LVPE502CP
537 * USB3.0 re-driver and that need the Compliance Mode Quirk.
539 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
541 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
543 const char *dmi_product_name, *dmi_sys_vendor;
545 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
546 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
547 if (!dmi_product_name || !dmi_sys_vendor)
550 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
553 if (strstr(dmi_product_name, "Z420") ||
554 strstr(dmi_product_name, "Z620") ||
555 strstr(dmi_product_name, "Z820") ||
556 strstr(dmi_product_name, "Z1 Workstation"))
562 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
564 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
569 * Initialize memory for HCD and xHC (one-time init).
571 * Program the PAGESIZE register, initialize the device context array, create
572 * device contexts (?), set up a command ring segment (or two?), create event
573 * ring (one for now).
575 static int xhci_init(struct usb_hcd *hcd)
577 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
580 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
581 spin_lock_init(&xhci->lock);
582 if (xhci->hci_version == 0x95 && link_quirk) {
583 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
584 "QUIRK: Not clearing Link TRB chain bits.");
585 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
587 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
588 "xHCI doesn't need link TRB QUIRK");
590 retval = xhci_mem_init(xhci, GFP_KERNEL);
591 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
593 /* Initializing Compliance Mode Recovery Data If Needed */
594 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
595 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
596 compliance_mode_recovery_timer_init(xhci);
602 /*-------------------------------------------------------------------------*/
605 static int xhci_run_finished(struct xhci_hcd *xhci)
607 if (xhci_start(xhci)) {
611 xhci->shared_hcd->state = HC_STATE_RUNNING;
612 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
614 if (xhci->quirks & XHCI_NEC_HOST)
615 xhci_ring_cmd_db(xhci);
617 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
618 "Finished xhci_run for USB3 roothub");
623 * Start the HC after it was halted.
625 * This function is called by the USB core when the HC driver is added.
626 * Its opposite is xhci_stop().
628 * xhci_init() must be called once before this function can be called.
629 * Reset the HC, enable device slot contexts, program DCBAAP, and
630 * set command ring pointer and event ring pointer.
632 * Setup MSI-X vectors and enable interrupts.
634 int xhci_run(struct usb_hcd *hcd)
639 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
641 /* Start the xHCI host controller running only after the USB 2.0 roothub
645 hcd->uses_new_polling = 1;
646 if (!usb_hcd_is_primary_hcd(hcd))
647 return xhci_run_finished(xhci);
649 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
651 ret = xhci_try_enable_msi(hcd);
655 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
656 temp_64 &= ~ERST_PTR_MASK;
657 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
658 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
660 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
661 "// Set the interrupt modulation register");
662 temp = readl(&xhci->ir_set->irq_control);
663 temp &= ~ER_IRQ_INTERVAL_MASK;
664 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
665 writel(temp, &xhci->ir_set->irq_control);
667 /* Set the HCD state before we enable the irqs */
668 temp = readl(&xhci->op_regs->command);
670 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
671 "// Enable interrupts, cmd = 0x%x.", temp);
672 writel(temp, &xhci->op_regs->command);
674 temp = readl(&xhci->ir_set->irq_pending);
675 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
676 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
677 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
678 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
680 if (xhci->quirks & XHCI_NEC_HOST) {
681 struct xhci_command *command;
683 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
687 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
688 TRB_TYPE(TRB_NEC_GET_FW));
690 xhci_free_command(xhci, command);
692 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
693 "Finished xhci_run for USB2 roothub");
697 xhci_debugfs_init(xhci);
701 EXPORT_SYMBOL_GPL(xhci_run);
706 * This function is called by the USB core when the HC driver is removed.
707 * Its opposite is xhci_run().
709 * Disable device contexts, disable IRQs, and quiesce the HC.
710 * Reset the HC, finish any completed transactions, and cleanup memory.
712 static void xhci_stop(struct usb_hcd *hcd)
715 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
717 mutex_lock(&xhci->mutex);
719 /* Only halt host and free memory after both hcds are removed */
720 if (!usb_hcd_is_primary_hcd(hcd)) {
721 mutex_unlock(&xhci->mutex);
727 spin_lock_irq(&xhci->lock);
728 xhci->xhc_state |= XHCI_STATE_HALTED;
729 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
732 spin_unlock_irq(&xhci->lock);
734 xhci_cleanup_msix(xhci);
736 /* Deleting Compliance Mode Recovery Timer */
737 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
738 (!(xhci_all_ports_seen_u0(xhci)))) {
739 del_timer_sync(&xhci->comp_mode_recovery_timer);
740 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
741 "%s: compliance mode recovery timer deleted",
745 if (xhci->quirks & XHCI_AMD_PLL_FIX)
748 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
749 "// Disabling event ring interrupts");
750 temp = readl(&xhci->op_regs->status);
751 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
752 temp = readl(&xhci->ir_set->irq_pending);
753 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
755 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
756 xhci_mem_cleanup(xhci);
757 xhci_debugfs_exit(xhci);
758 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
759 "xhci_stop completed - status = %x",
760 readl(&xhci->op_regs->status));
761 mutex_unlock(&xhci->mutex);
765 * Shutdown HC (not bus-specific)
767 * This is called when the machine is rebooting or halting. We assume that the
768 * machine will be powered off, and the HC's internal state will be reset.
769 * Don't bother to free memory.
771 * This will only ever be called with the main usb_hcd (the USB3 roothub).
773 static void xhci_shutdown(struct usb_hcd *hcd)
775 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
777 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
778 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
780 spin_lock_irq(&xhci->lock);
782 /* Workaround for spurious wakeups at shutdown with HSW */
783 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
785 spin_unlock_irq(&xhci->lock);
787 xhci_cleanup_msix(xhci);
789 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
790 "xhci_shutdown completed - status = %x",
791 readl(&xhci->op_regs->status));
793 /* Yet another workaround for spurious wakeups at shutdown with HSW */
794 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
795 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
799 static void xhci_save_registers(struct xhci_hcd *xhci)
801 xhci->s3.command = readl(&xhci->op_regs->command);
802 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
803 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
804 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
805 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
806 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
807 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
808 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
809 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
812 static void xhci_restore_registers(struct xhci_hcd *xhci)
814 writel(xhci->s3.command, &xhci->op_regs->command);
815 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
816 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
817 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
818 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
819 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
820 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
821 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
822 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
825 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
829 /* step 2: initialize command ring buffer */
830 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
831 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
832 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
833 xhci->cmd_ring->dequeue) &
834 (u64) ~CMD_RING_RSVD_BITS) |
835 xhci->cmd_ring->cycle_state;
836 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
837 "// Setting command ring address to 0x%llx",
838 (long unsigned long) val_64);
839 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
843 * The whole command ring must be cleared to zero when we suspend the host.
845 * The host doesn't save the command ring pointer in the suspend well, so we
846 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
847 * aligned, because of the reserved bits in the command ring dequeue pointer
848 * register. Therefore, we can't just set the dequeue pointer back in the
849 * middle of the ring (TRBs are 16-byte aligned).
851 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
853 struct xhci_ring *ring;
854 struct xhci_segment *seg;
856 ring = xhci->cmd_ring;
860 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
861 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
862 cpu_to_le32(~TRB_CYCLE);
864 } while (seg != ring->deq_seg);
866 /* Reset the software enqueue and dequeue pointers */
867 ring->deq_seg = ring->first_seg;
868 ring->dequeue = ring->first_seg->trbs;
869 ring->enq_seg = ring->deq_seg;
870 ring->enqueue = ring->dequeue;
872 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
874 * Ring is now zeroed, so the HW should look for change of ownership
875 * when the cycle bit is set to 1.
877 ring->cycle_state = 1;
880 * Reset the hardware dequeue pointer.
881 * Yes, this will need to be re-written after resume, but we're paranoid
882 * and want to make sure the hardware doesn't access bogus memory
883 * because, say, the BIOS or an SMI started the host without changing
884 * the command ring pointers.
886 xhci_set_cmd_ring_deq(xhci);
889 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
891 struct xhci_port **ports;
896 spin_lock_irqsave(&xhci->lock, flags);
898 /* disable usb3 ports Wake bits */
899 port_index = xhci->usb3_rhub.num_ports;
900 ports = xhci->usb3_rhub.ports;
901 while (port_index--) {
902 t1 = readl(ports[port_index]->addr);
904 t1 = xhci_port_state_to_neutral(t1);
905 t2 = t1 & ~PORT_WAKE_BITS;
907 writel(t2, ports[port_index]->addr);
908 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
909 xhci->usb3_rhub.hcd->self.busnum,
910 port_index + 1, portsc, t2);
914 /* disable usb2 ports Wake bits */
915 port_index = xhci->usb2_rhub.num_ports;
916 ports = xhci->usb2_rhub.ports;
917 while (port_index--) {
918 t1 = readl(ports[port_index]->addr);
920 t1 = xhci_port_state_to_neutral(t1);
921 t2 = t1 & ~PORT_WAKE_BITS;
923 writel(t2, ports[port_index]->addr);
924 xhci_dbg(xhci, "disable wake bits port %d-%d, portsc: 0x%x, write: 0x%x\n",
925 xhci->usb2_rhub.hcd->self.busnum,
926 port_index + 1, portsc, t2);
929 spin_unlock_irqrestore(&xhci->lock, flags);
932 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
934 struct xhci_port **ports;
939 status = readl(&xhci->op_regs->status);
940 if (status & STS_EINT)
943 * Checking STS_EINT is not enough as there is a lag between a change
944 * bit being set and the Port Status Change Event that it generated
945 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
948 port_index = xhci->usb2_rhub.num_ports;
949 ports = xhci->usb2_rhub.ports;
950 while (port_index--) {
951 portsc = readl(ports[port_index]->addr);
952 if (portsc & PORT_CHANGE_MASK ||
953 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
956 port_index = xhci->usb3_rhub.num_ports;
957 ports = xhci->usb3_rhub.ports;
958 while (port_index--) {
959 portsc = readl(ports[port_index]->addr);
960 if (portsc & PORT_CHANGE_MASK ||
961 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
968 * Stop HC (not bus-specific)
970 * This is called when the machine transition into S3/S4 mode.
973 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
976 unsigned int delay = XHCI_MAX_HALT_USEC;
977 struct usb_hcd *hcd = xhci_to_hcd(xhci);
984 if (hcd->state != HC_STATE_SUSPENDED ||
985 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
988 xhci_dbc_suspend(xhci);
990 /* Clear root port wake on bits if wakeup not allowed. */
992 xhci_disable_port_wake_on_bits(xhci);
994 /* Don't poll the roothubs on bus suspend. */
995 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
996 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
997 del_timer_sync(&hcd->rh_timer);
998 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
999 del_timer_sync(&xhci->shared_hcd->rh_timer);
1001 if (xhci->quirks & XHCI_SUSPEND_DELAY)
1002 usleep_range(1000, 1500);
1004 spin_lock_irq(&xhci->lock);
1005 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1006 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1007 /* step 1: stop endpoint */
1008 /* skipped assuming that port suspend has done */
1010 /* step 2: clear Run/Stop bit */
1011 command = readl(&xhci->op_regs->command);
1012 command &= ~CMD_RUN;
1013 writel(command, &xhci->op_regs->command);
1015 /* Some chips from Fresco Logic need an extraordinary delay */
1016 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1018 if (xhci_handshake(&xhci->op_regs->status,
1019 STS_HALT, STS_HALT, delay)) {
1020 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1021 spin_unlock_irq(&xhci->lock);
1024 xhci_clear_command_ring(xhci);
1026 /* step 3: save registers */
1027 xhci_save_registers(xhci);
1029 /* step 4: set CSS flag */
1030 command = readl(&xhci->op_regs->command);
1032 writel(command, &xhci->op_regs->command);
1033 xhci->broken_suspend = 0;
1034 if (xhci_handshake(&xhci->op_regs->status,
1035 STS_SAVE, 0, 10 * 1000)) {
1037 * AMD SNPS xHC 3.0 occasionally does not clear the
1038 * SSS bit of USBSTS and when driver tries to poll
1039 * to see if the xHC clears BIT(8) which never happens
1040 * and driver assumes that controller is not responding
1041 * and times out. To workaround this, its good to check
1042 * if SRE and HCE bits are not set (as per xhci
1043 * Section 5.4.2) and bypass the timeout.
1045 res = readl(&xhci->op_regs->status);
1046 if ((xhci->quirks & XHCI_SNPS_BROKEN_SUSPEND) &&
1047 (((res & STS_SRE) == 0) &&
1048 ((res & STS_HCE) == 0))) {
1049 xhci->broken_suspend = 1;
1051 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1052 spin_unlock_irq(&xhci->lock);
1056 spin_unlock_irq(&xhci->lock);
1059 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1060 * is about to be suspended.
1062 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1063 (!(xhci_all_ports_seen_u0(xhci)))) {
1064 del_timer_sync(&xhci->comp_mode_recovery_timer);
1065 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1066 "%s: compliance mode recovery timer deleted",
1070 /* step 5: remove core well power */
1071 /* synchronize irq when using MSI-X */
1072 xhci_msix_sync_irqs(xhci);
1076 EXPORT_SYMBOL_GPL(xhci_suspend);
1079 * start xHC (not bus-specific)
1081 * This is called when the machine transition from S3/S4 mode.
1084 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1086 u32 command, temp = 0;
1087 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1088 struct usb_hcd *secondary_hcd;
1090 bool comp_timer_running = false;
1095 /* Wait a bit if either of the roothubs need to settle from the
1096 * transition into bus suspend.
1099 if (time_before(jiffies, xhci->usb2_rhub.bus_state.next_statechange) ||
1100 time_before(jiffies, xhci->usb3_rhub.bus_state.next_statechange))
1103 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1104 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1106 spin_lock_irq(&xhci->lock);
1107 if ((xhci->quirks & XHCI_RESET_ON_RESUME) || xhci->broken_suspend)
1111 /* step 1: restore register */
1112 xhci_restore_registers(xhci);
1113 /* step 2: initialize command ring buffer */
1114 xhci_set_cmd_ring_deq(xhci);
1115 /* step 3: restore state and start state*/
1116 /* step 3: set CRS flag */
1117 command = readl(&xhci->op_regs->command);
1119 writel(command, &xhci->op_regs->command);
1121 * Some controllers take up to 55+ ms to complete the controller
1122 * restore so setting the timeout to 100ms. Xhci specification
1123 * doesn't mention any timeout value.
1125 if (xhci_handshake(&xhci->op_regs->status,
1126 STS_RESTORE, 0, 100 * 1000)) {
1127 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1128 spin_unlock_irq(&xhci->lock);
1131 temp = readl(&xhci->op_regs->status);
1134 /* If restore operation fails, re-initialize the HC during resume */
1135 if ((temp & STS_SRE) || hibernated) {
1137 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1138 !(xhci_all_ports_seen_u0(xhci))) {
1139 del_timer_sync(&xhci->comp_mode_recovery_timer);
1140 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1141 "Compliance Mode Recovery Timer deleted!");
1144 /* Let the USB core know _both_ roothubs lost power. */
1145 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1146 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1148 xhci_dbg(xhci, "Stop HCD\n");
1150 xhci_zero_64b_regs(xhci);
1152 spin_unlock_irq(&xhci->lock);
1153 xhci_cleanup_msix(xhci);
1155 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1156 temp = readl(&xhci->op_regs->status);
1157 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1158 temp = readl(&xhci->ir_set->irq_pending);
1159 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1161 xhci_dbg(xhci, "cleaning up memory\n");
1162 xhci_mem_cleanup(xhci);
1163 xhci_debugfs_exit(xhci);
1164 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1165 readl(&xhci->op_regs->status));
1167 /* USB core calls the PCI reinit and start functions twice:
1168 * first with the primary HCD, and then with the secondary HCD.
1169 * If we don't do the same, the host will never be started.
1171 if (!usb_hcd_is_primary_hcd(hcd))
1172 secondary_hcd = hcd;
1174 secondary_hcd = xhci->shared_hcd;
1176 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1177 retval = xhci_init(hcd->primary_hcd);
1180 comp_timer_running = true;
1182 xhci_dbg(xhci, "Start the primary HCD\n");
1183 retval = xhci_run(hcd->primary_hcd);
1185 xhci_dbg(xhci, "Start the secondary HCD\n");
1186 retval = xhci_run(secondary_hcd);
1188 hcd->state = HC_STATE_SUSPENDED;
1189 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1193 /* step 4: set Run/Stop bit */
1194 command = readl(&xhci->op_regs->command);
1196 writel(command, &xhci->op_regs->command);
1197 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1200 /* step 5: walk topology and initialize portsc,
1201 * portpmsc and portli
1203 /* this is done in bus_resume */
1205 /* step 6: restart each of the previously
1206 * Running endpoints by ringing their doorbells
1209 spin_unlock_irq(&xhci->lock);
1211 xhci_dbc_resume(xhci);
1215 /* Resume root hubs only when have pending events. */
1216 if (xhci_pending_portevent(xhci)) {
1217 usb_hcd_resume_root_hub(xhci->shared_hcd);
1218 usb_hcd_resume_root_hub(hcd);
1223 * If system is subject to the Quirk, Compliance Mode Timer needs to
1224 * be re-initialized Always after a system resume. Ports are subject
1225 * to suffer the Compliance Mode issue again. It doesn't matter if
1226 * ports have entered previously to U0 before system's suspension.
1228 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1229 compliance_mode_recovery_timer_init(xhci);
1231 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1232 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1234 /* Re-enable port polling. */
1235 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1236 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1237 usb_hcd_poll_rh_status(xhci->shared_hcd);
1238 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1239 usb_hcd_poll_rh_status(hcd);
1243 EXPORT_SYMBOL_GPL(xhci_resume);
1244 #endif /* CONFIG_PM */
1246 /*-------------------------------------------------------------------------*/
1249 * Bypass the DMA mapping if URB is suitable for Immediate Transfer (IDT),
1250 * we'll copy the actual data into the TRB address register. This is limited to
1251 * transfers up to 8 bytes on output endpoints of any kind with wMaxPacketSize
1252 * >= 8 bytes. If suitable for IDT only one Transfer TRB per TD is allowed.
1254 static int xhci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
1257 if (xhci_urb_suitable_for_idt(urb))
1260 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
1264 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1265 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1266 * value to right shift 1 for the bitmask.
1268 * Index = (epnum * 2) + direction - 1,
1269 * where direction = 0 for OUT, 1 for IN.
1270 * For control endpoints, the IN index is used (OUT index is unused), so
1271 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1273 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1276 if (usb_endpoint_xfer_control(desc))
1277 index = (unsigned int) (usb_endpoint_num(desc)*2);
1279 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1280 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1284 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1285 * address from the XHCI endpoint index.
1287 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1289 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1290 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1291 return direction | number;
1294 /* Find the flag for this endpoint (for use in the control context). Use the
1295 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1298 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1300 return 1 << (xhci_get_endpoint_index(desc) + 1);
1303 /* Find the flag for this endpoint (for use in the control context). Use the
1304 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1307 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1309 return 1 << (ep_index + 1);
1312 /* Compute the last valid endpoint context index. Basically, this is the
1313 * endpoint index plus one. For slot contexts with more than valid endpoint,
1314 * we find the most significant bit set in the added contexts flags.
1315 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1316 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1318 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1320 return fls(added_ctxs) - 1;
1323 /* Returns 1 if the arguments are OK;
1324 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1326 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1327 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1329 struct xhci_hcd *xhci;
1330 struct xhci_virt_device *virt_dev;
1332 if (!hcd || (check_ep && !ep) || !udev) {
1333 pr_debug("xHCI %s called with invalid args\n", func);
1336 if (!udev->parent) {
1337 pr_debug("xHCI %s called for root hub\n", func);
1341 xhci = hcd_to_xhci(hcd);
1342 if (check_virt_dev) {
1343 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1344 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1349 virt_dev = xhci->devs[udev->slot_id];
1350 if (virt_dev->udev != udev) {
1351 xhci_dbg(xhci, "xHCI %s called with udev and "
1352 "virt_dev does not match\n", func);
1357 if (xhci->xhc_state & XHCI_STATE_HALTED)
1363 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1364 struct usb_device *udev, struct xhci_command *command,
1365 bool ctx_change, bool must_succeed);
1368 * Full speed devices may have a max packet size greater than 8 bytes, but the
1369 * USB core doesn't know that until it reads the first 8 bytes of the
1370 * descriptor. If the usb_device's max packet size changes after that point,
1371 * we need to issue an evaluate context command and wait on it.
1373 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1374 unsigned int ep_index, struct urb *urb)
1376 struct xhci_container_ctx *out_ctx;
1377 struct xhci_input_control_ctx *ctrl_ctx;
1378 struct xhci_ep_ctx *ep_ctx;
1379 struct xhci_command *command;
1380 int max_packet_size;
1381 int hw_max_packet_size;
1384 out_ctx = xhci->devs[slot_id]->out_ctx;
1385 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1386 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1387 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1388 if (hw_max_packet_size != max_packet_size) {
1389 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1390 "Max Packet Size for ep 0 changed.");
1391 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1392 "Max packet size in usb_device = %d",
1394 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1395 "Max packet size in xHCI HW = %d",
1396 hw_max_packet_size);
1397 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1398 "Issuing evaluate context command.");
1400 /* Set up the input context flags for the command */
1401 /* FIXME: This won't work if a non-default control endpoint
1402 * changes max packet sizes.
1405 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1409 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1410 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1412 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1415 goto command_cleanup;
1417 /* Set up the modified control endpoint 0 */
1418 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1419 xhci->devs[slot_id]->out_ctx, ep_index);
1421 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1422 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1423 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1425 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1426 ctrl_ctx->drop_flags = 0;
1428 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1431 /* Clean up the input context for later use by bandwidth
1434 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1436 kfree(command->completion);
1443 * non-error returns are a promise to giveback() the urb later
1444 * we drop ownership so next owner (or urb unlink) can get it
1446 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1448 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1449 unsigned long flags;
1451 unsigned int slot_id, ep_index;
1452 unsigned int *ep_state;
1453 struct urb_priv *urb_priv;
1456 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1457 true, true, __func__) <= 0)
1460 slot_id = urb->dev->slot_id;
1461 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1462 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1464 if (!HCD_HW_ACCESSIBLE(hcd)) {
1465 if (!in_interrupt())
1466 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1469 if (xhci->devs[slot_id]->flags & VDEV_PORT_ERROR) {
1470 xhci_dbg(xhci, "Can't queue urb, port error, link inactive\n");
1474 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1475 num_tds = urb->number_of_packets;
1476 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1477 urb->transfer_buffer_length > 0 &&
1478 urb->transfer_flags & URB_ZERO_PACKET &&
1479 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1484 urb_priv = kzalloc(struct_size(urb_priv, td, num_tds), mem_flags);
1488 urb_priv->num_tds = num_tds;
1489 urb_priv->num_tds_done = 0;
1490 urb->hcpriv = urb_priv;
1492 trace_xhci_urb_enqueue(urb);
1494 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1495 /* Check to see if the max packet size for the default control
1496 * endpoint changed during FS device enumeration
1498 if (urb->dev->speed == USB_SPEED_FULL) {
1499 ret = xhci_check_maxpacket(xhci, slot_id,
1502 xhci_urb_free_priv(urb_priv);
1509 spin_lock_irqsave(&xhci->lock, flags);
1511 if (xhci->xhc_state & XHCI_STATE_DYING) {
1512 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1513 urb->ep->desc.bEndpointAddress, urb);
1517 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1518 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1523 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1524 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1529 switch (usb_endpoint_type(&urb->ep->desc)) {
1531 case USB_ENDPOINT_XFER_CONTROL:
1532 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1535 case USB_ENDPOINT_XFER_BULK:
1536 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1539 case USB_ENDPOINT_XFER_INT:
1540 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1543 case USB_ENDPOINT_XFER_ISOC:
1544 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1550 xhci_urb_free_priv(urb_priv);
1553 spin_unlock_irqrestore(&xhci->lock, flags);
1558 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1559 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1560 * should pick up where it left off in the TD, unless a Set Transfer Ring
1561 * Dequeue Pointer is issued.
1563 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1564 * the ring. Since the ring is a contiguous structure, they can't be physically
1565 * removed. Instead, there are two options:
1567 * 1) If the HC is in the middle of processing the URB to be canceled, we
1568 * simply move the ring's dequeue pointer past those TRBs using the Set
1569 * Transfer Ring Dequeue Pointer command. This will be the common case,
1570 * when drivers timeout on the last submitted URB and attempt to cancel.
1572 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1573 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1574 * HC will need to invalidate the any TRBs it has cached after the stop
1575 * endpoint command, as noted in the xHCI 0.95 errata.
1577 * 3) The TD may have completed by the time the Stop Endpoint Command
1578 * completes, so software needs to handle that case too.
1580 * This function should protect against the TD enqueueing code ringing the
1581 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1582 * It also needs to account for multiple cancellations on happening at the same
1583 * time for the same endpoint.
1585 * Note that this function can be called in any context, or so says
1586 * usb_hcd_unlink_urb()
1588 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1590 unsigned long flags;
1593 struct xhci_hcd *xhci;
1594 struct urb_priv *urb_priv;
1596 unsigned int ep_index;
1597 struct xhci_ring *ep_ring;
1598 struct xhci_virt_ep *ep;
1599 struct xhci_command *command;
1600 struct xhci_virt_device *vdev;
1602 xhci = hcd_to_xhci(hcd);
1603 spin_lock_irqsave(&xhci->lock, flags);
1605 trace_xhci_urb_dequeue(urb);
1607 /* Make sure the URB hasn't completed or been unlinked already */
1608 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1612 /* give back URB now if we can't queue it for cancel */
1613 vdev = xhci->devs[urb->dev->slot_id];
1614 urb_priv = urb->hcpriv;
1615 if (!vdev || !urb_priv)
1618 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1619 ep = &vdev->eps[ep_index];
1620 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1621 if (!ep || !ep_ring)
1624 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1625 temp = readl(&xhci->op_regs->status);
1626 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1632 * check ring is not re-allocated since URB was enqueued. If it is, then
1633 * make sure none of the ring related pointers in this URB private data
1634 * are touched, such as td_list, otherwise we overwrite freed data
1636 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1637 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1638 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1639 td = &urb_priv->td[i];
1640 if (!list_empty(&td->cancelled_td_list))
1641 list_del_init(&td->cancelled_td_list);
1646 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1647 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1648 "HC halted, freeing TD manually.");
1649 for (i = urb_priv->num_tds_done;
1650 i < urb_priv->num_tds;
1652 td = &urb_priv->td[i];
1653 if (!list_empty(&td->td_list))
1654 list_del_init(&td->td_list);
1655 if (!list_empty(&td->cancelled_td_list))
1656 list_del_init(&td->cancelled_td_list);
1661 i = urb_priv->num_tds_done;
1662 if (i < urb_priv->num_tds)
1663 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1664 "Cancel URB %p, dev %s, ep 0x%x, "
1665 "starting at offset 0x%llx",
1666 urb, urb->dev->devpath,
1667 urb->ep->desc.bEndpointAddress,
1668 (unsigned long long) xhci_trb_virt_to_dma(
1669 urb_priv->td[i].start_seg,
1670 urb_priv->td[i].first_trb));
1672 for (; i < urb_priv->num_tds; i++) {
1673 td = &urb_priv->td[i];
1674 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1677 /* Queue a stop endpoint command, but only if this is
1678 * the first cancellation to be handled.
1680 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1681 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1686 ep->ep_state |= EP_STOP_CMD_PENDING;
1687 ep->stop_cmd_timer.expires = jiffies +
1688 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1689 add_timer(&ep->stop_cmd_timer);
1690 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1692 xhci_ring_cmd_db(xhci);
1695 spin_unlock_irqrestore(&xhci->lock, flags);
1700 xhci_urb_free_priv(urb_priv);
1701 usb_hcd_unlink_urb_from_ep(hcd, urb);
1702 spin_unlock_irqrestore(&xhci->lock, flags);
1703 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1707 /* Drop an endpoint from a new bandwidth configuration for this device.
1708 * Only one call to this function is allowed per endpoint before
1709 * check_bandwidth() or reset_bandwidth() must be called.
1710 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1711 * add the endpoint to the schedule with possibly new parameters denoted by a
1712 * different endpoint descriptor in usb_host_endpoint.
1713 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1716 * The USB core will not allow URBs to be queued to an endpoint that is being
1717 * disabled, so there's no need for mutual exclusion to protect
1718 * the xhci->devs[slot_id] structure.
1720 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1721 struct usb_host_endpoint *ep)
1723 struct xhci_hcd *xhci;
1724 struct xhci_container_ctx *in_ctx, *out_ctx;
1725 struct xhci_input_control_ctx *ctrl_ctx;
1726 unsigned int ep_index;
1727 struct xhci_ep_ctx *ep_ctx;
1729 u32 new_add_flags, new_drop_flags;
1732 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1735 xhci = hcd_to_xhci(hcd);
1736 if (xhci->xhc_state & XHCI_STATE_DYING)
1739 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1740 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1741 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1742 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1743 __func__, drop_flag);
1747 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1748 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1749 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1751 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1756 ep_index = xhci_get_endpoint_index(&ep->desc);
1757 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1758 /* If the HC already knows the endpoint is disabled,
1759 * or the HCD has noted it is disabled, ignore this request
1761 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1762 le32_to_cpu(ctrl_ctx->drop_flags) &
1763 xhci_get_endpoint_flag(&ep->desc)) {
1764 /* Do not warn when called after a usb_device_reset */
1765 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1766 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1771 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1772 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1774 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1775 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1777 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1779 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1781 if (xhci->quirks & XHCI_MTK_HOST)
1782 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1784 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1785 (unsigned int) ep->desc.bEndpointAddress,
1787 (unsigned int) new_drop_flags,
1788 (unsigned int) new_add_flags);
1792 /* Add an endpoint to a new possible bandwidth configuration for this device.
1793 * Only one call to this function is allowed per endpoint before
1794 * check_bandwidth() or reset_bandwidth() must be called.
1795 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1796 * add the endpoint to the schedule with possibly new parameters denoted by a
1797 * different endpoint descriptor in usb_host_endpoint.
1798 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1801 * The USB core will not allow URBs to be queued to an endpoint until the
1802 * configuration or alt setting is installed in the device, so there's no need
1803 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1805 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1806 struct usb_host_endpoint *ep)
1808 struct xhci_hcd *xhci;
1809 struct xhci_container_ctx *in_ctx;
1810 unsigned int ep_index;
1811 struct xhci_input_control_ctx *ctrl_ctx;
1812 struct xhci_ep_ctx *ep_ctx;
1814 u32 new_add_flags, new_drop_flags;
1815 struct xhci_virt_device *virt_dev;
1818 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1820 /* So we won't queue a reset ep command for a root hub */
1824 xhci = hcd_to_xhci(hcd);
1825 if (xhci->xhc_state & XHCI_STATE_DYING)
1828 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1829 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1830 /* FIXME when we have to issue an evaluate endpoint command to
1831 * deal with ep0 max packet size changing once we get the
1834 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1835 __func__, added_ctxs);
1839 virt_dev = xhci->devs[udev->slot_id];
1840 in_ctx = virt_dev->in_ctx;
1841 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1843 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1848 ep_index = xhci_get_endpoint_index(&ep->desc);
1849 /* If this endpoint is already in use, and the upper layers are trying
1850 * to add it again without dropping it, reject the addition.
1852 if (virt_dev->eps[ep_index].ring &&
1853 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1854 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1855 "without dropping it.\n",
1856 (unsigned int) ep->desc.bEndpointAddress);
1860 /* If the HCD has already noted the endpoint is enabled,
1861 * ignore this request.
1863 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1864 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1870 * Configuration and alternate setting changes must be done in
1871 * process context, not interrupt context (or so documenation
1872 * for usb_set_interface() and usb_set_configuration() claim).
1874 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1875 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1876 __func__, ep->desc.bEndpointAddress);
1880 if (xhci->quirks & XHCI_MTK_HOST) {
1881 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1883 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1884 virt_dev->eps[ep_index].new_ring = NULL;
1889 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1890 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1892 /* If xhci_endpoint_disable() was called for this endpoint, but the
1893 * xHC hasn't been notified yet through the check_bandwidth() call,
1894 * this re-adds a new state for the endpoint from the new endpoint
1895 * descriptors. We must drop and re-add this endpoint, so we leave the
1898 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1900 /* Store the usb_device pointer for later use */
1903 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1904 trace_xhci_add_endpoint(ep_ctx);
1906 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1908 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1909 (unsigned int) ep->desc.bEndpointAddress,
1911 (unsigned int) new_drop_flags,
1912 (unsigned int) new_add_flags);
1916 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1918 struct xhci_input_control_ctx *ctrl_ctx;
1919 struct xhci_ep_ctx *ep_ctx;
1920 struct xhci_slot_ctx *slot_ctx;
1923 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1925 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1930 /* When a device's add flag and drop flag are zero, any subsequent
1931 * configure endpoint command will leave that endpoint's state
1932 * untouched. Make sure we don't leave any old state in the input
1933 * endpoint contexts.
1935 ctrl_ctx->drop_flags = 0;
1936 ctrl_ctx->add_flags = 0;
1937 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1938 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1939 /* Endpoint 0 is always valid */
1940 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1941 for (i = 1; i < 31; i++) {
1942 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1943 ep_ctx->ep_info = 0;
1944 ep_ctx->ep_info2 = 0;
1946 ep_ctx->tx_info = 0;
1950 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1951 struct usb_device *udev, u32 *cmd_status)
1955 switch (*cmd_status) {
1956 case COMP_COMMAND_ABORTED:
1957 case COMP_COMMAND_RING_STOPPED:
1958 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1961 case COMP_RESOURCE_ERROR:
1962 dev_warn(&udev->dev,
1963 "Not enough host controller resources for new device state.\n");
1965 /* FIXME: can we allocate more resources for the HC? */
1967 case COMP_BANDWIDTH_ERROR:
1968 case COMP_SECONDARY_BANDWIDTH_ERROR:
1969 dev_warn(&udev->dev,
1970 "Not enough bandwidth for new device state.\n");
1972 /* FIXME: can we go back to the old state? */
1974 case COMP_TRB_ERROR:
1975 /* the HCD set up something wrong */
1976 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1978 "and endpoint is not disabled.\n");
1981 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1982 dev_warn(&udev->dev,
1983 "ERROR: Incompatible device for endpoint configure command.\n");
1987 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1988 "Successful Endpoint Configure command");
1992 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2000 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
2001 struct usb_device *udev, u32 *cmd_status)
2005 switch (*cmd_status) {
2006 case COMP_COMMAND_ABORTED:
2007 case COMP_COMMAND_RING_STOPPED:
2008 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
2011 case COMP_PARAMETER_ERROR:
2012 dev_warn(&udev->dev,
2013 "WARN: xHCI driver setup invalid evaluate context command.\n");
2016 case COMP_SLOT_NOT_ENABLED_ERROR:
2017 dev_warn(&udev->dev,
2018 "WARN: slot not enabled for evaluate context command.\n");
2021 case COMP_CONTEXT_STATE_ERROR:
2022 dev_warn(&udev->dev,
2023 "WARN: invalid context state for evaluate context command.\n");
2026 case COMP_INCOMPATIBLE_DEVICE_ERROR:
2027 dev_warn(&udev->dev,
2028 "ERROR: Incompatible device for evaluate context command.\n");
2031 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
2032 /* Max Exit Latency too large error */
2033 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
2037 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2038 "Successful evaluate context command");
2042 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2050 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2051 struct xhci_input_control_ctx *ctrl_ctx)
2053 u32 valid_add_flags;
2054 u32 valid_drop_flags;
2056 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2057 * (bit 1). The default control endpoint is added during the Address
2058 * Device command and is never removed until the slot is disabled.
2060 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2061 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2063 /* Use hweight32 to count the number of ones in the add flags, or
2064 * number of endpoints added. Don't count endpoints that are changed
2065 * (both added and dropped).
2067 return hweight32(valid_add_flags) -
2068 hweight32(valid_add_flags & valid_drop_flags);
2071 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2072 struct xhci_input_control_ctx *ctrl_ctx)
2074 u32 valid_add_flags;
2075 u32 valid_drop_flags;
2077 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2078 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2080 return hweight32(valid_drop_flags) -
2081 hweight32(valid_add_flags & valid_drop_flags);
2085 * We need to reserve the new number of endpoints before the configure endpoint
2086 * command completes. We can't subtract the dropped endpoints from the number
2087 * of active endpoints until the command completes because we can oversubscribe
2088 * the host in this case:
2090 * - the first configure endpoint command drops more endpoints than it adds
2091 * - a second configure endpoint command that adds more endpoints is queued
2092 * - the first configure endpoint command fails, so the config is unchanged
2093 * - the second command may succeed, even though there isn't enough resources
2095 * Must be called with xhci->lock held.
2097 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2098 struct xhci_input_control_ctx *ctrl_ctx)
2102 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2103 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2104 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2105 "Not enough ep ctxs: "
2106 "%u active, need to add %u, limit is %u.",
2107 xhci->num_active_eps, added_eps,
2108 xhci->limit_active_eps);
2111 xhci->num_active_eps += added_eps;
2112 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2113 "Adding %u ep ctxs, %u now active.", added_eps,
2114 xhci->num_active_eps);
2119 * The configure endpoint was failed by the xHC for some other reason, so we
2120 * need to revert the resources that failed configuration would have used.
2122 * Must be called with xhci->lock held.
2124 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2125 struct xhci_input_control_ctx *ctrl_ctx)
2129 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2130 xhci->num_active_eps -= num_failed_eps;
2131 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2132 "Removing %u failed ep ctxs, %u now active.",
2134 xhci->num_active_eps);
2138 * Now that the command has completed, clean up the active endpoint count by
2139 * subtracting out the endpoints that were dropped (but not changed).
2141 * Must be called with xhci->lock held.
2143 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2144 struct xhci_input_control_ctx *ctrl_ctx)
2146 u32 num_dropped_eps;
2148 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2149 xhci->num_active_eps -= num_dropped_eps;
2150 if (num_dropped_eps)
2151 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2152 "Removing %u dropped ep ctxs, %u now active.",
2154 xhci->num_active_eps);
2157 static unsigned int xhci_get_block_size(struct usb_device *udev)
2159 switch (udev->speed) {
2161 case USB_SPEED_FULL:
2163 case USB_SPEED_HIGH:
2165 case USB_SPEED_SUPER:
2166 case USB_SPEED_SUPER_PLUS:
2168 case USB_SPEED_UNKNOWN:
2169 case USB_SPEED_WIRELESS:
2171 /* Should never happen */
2177 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2179 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2181 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2186 /* If we are changing a LS/FS device under a HS hub,
2187 * make sure (if we are activating a new TT) that the HS bus has enough
2188 * bandwidth for this new TT.
2190 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2191 struct xhci_virt_device *virt_dev,
2194 struct xhci_interval_bw_table *bw_table;
2195 struct xhci_tt_bw_info *tt_info;
2197 /* Find the bandwidth table for the root port this TT is attached to. */
2198 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2199 tt_info = virt_dev->tt_info;
2200 /* If this TT already had active endpoints, the bandwidth for this TT
2201 * has already been added. Removing all periodic endpoints (and thus
2202 * making the TT enactive) will only decrease the bandwidth used.
2206 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2207 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2211 /* Not sure why we would have no new active endpoints...
2213 * Maybe because of an Evaluate Context change for a hub update or a
2214 * control endpoint 0 max packet size change?
2215 * FIXME: skip the bandwidth calculation in that case.
2220 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2221 struct xhci_virt_device *virt_dev)
2223 unsigned int bw_reserved;
2225 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2226 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2229 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2230 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2237 * This algorithm is a very conservative estimate of the worst-case scheduling
2238 * scenario for any one interval. The hardware dynamically schedules the
2239 * packets, so we can't tell which microframe could be the limiting factor in
2240 * the bandwidth scheduling. This only takes into account periodic endpoints.
2242 * Obviously, we can't solve an NP complete problem to find the minimum worst
2243 * case scenario. Instead, we come up with an estimate that is no less than
2244 * the worst case bandwidth used for any one microframe, but may be an
2247 * We walk the requirements for each endpoint by interval, starting with the
2248 * smallest interval, and place packets in the schedule where there is only one
2249 * possible way to schedule packets for that interval. In order to simplify
2250 * this algorithm, we record the largest max packet size for each interval, and
2251 * assume all packets will be that size.
2253 * For interval 0, we obviously must schedule all packets for each interval.
2254 * The bandwidth for interval 0 is just the amount of data to be transmitted
2255 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2256 * the number of packets).
2258 * For interval 1, we have two possible microframes to schedule those packets
2259 * in. For this algorithm, if we can schedule the same number of packets for
2260 * each possible scheduling opportunity (each microframe), we will do so. The
2261 * remaining number of packets will be saved to be transmitted in the gaps in
2262 * the next interval's scheduling sequence.
2264 * As we move those remaining packets to be scheduled with interval 2 packets,
2265 * we have to double the number of remaining packets to transmit. This is
2266 * because the intervals are actually powers of 2, and we would be transmitting
2267 * the previous interval's packets twice in this interval. We also have to be
2268 * sure that when we look at the largest max packet size for this interval, we
2269 * also look at the largest max packet size for the remaining packets and take
2270 * the greater of the two.
2272 * The algorithm continues to evenly distribute packets in each scheduling
2273 * opportunity, and push the remaining packets out, until we get to the last
2274 * interval. Then those packets and their associated overhead are just added
2275 * to the bandwidth used.
2277 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2278 struct xhci_virt_device *virt_dev,
2281 unsigned int bw_reserved;
2282 unsigned int max_bandwidth;
2283 unsigned int bw_used;
2284 unsigned int block_size;
2285 struct xhci_interval_bw_table *bw_table;
2286 unsigned int packet_size = 0;
2287 unsigned int overhead = 0;
2288 unsigned int packets_transmitted = 0;
2289 unsigned int packets_remaining = 0;
2292 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2293 return xhci_check_ss_bw(xhci, virt_dev);
2295 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2296 max_bandwidth = HS_BW_LIMIT;
2297 /* Convert percent of bus BW reserved to blocks reserved */
2298 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2300 max_bandwidth = FS_BW_LIMIT;
2301 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2304 bw_table = virt_dev->bw_table;
2305 /* We need to translate the max packet size and max ESIT payloads into
2306 * the units the hardware uses.
2308 block_size = xhci_get_block_size(virt_dev->udev);
2310 /* If we are manipulating a LS/FS device under a HS hub, double check
2311 * that the HS bus has enough bandwidth if we are activing a new TT.
2313 if (virt_dev->tt_info) {
2314 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2315 "Recalculating BW for rootport %u",
2316 virt_dev->real_port);
2317 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2318 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2319 "newly activated TT.\n");
2322 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2323 "Recalculating BW for TT slot %u port %u",
2324 virt_dev->tt_info->slot_id,
2325 virt_dev->tt_info->ttport);
2327 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2328 "Recalculating BW for rootport %u",
2329 virt_dev->real_port);
2332 /* Add in how much bandwidth will be used for interval zero, or the
2333 * rounded max ESIT payload + number of packets * largest overhead.
2335 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2336 bw_table->interval_bw[0].num_packets *
2337 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2339 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2340 unsigned int bw_added;
2341 unsigned int largest_mps;
2342 unsigned int interval_overhead;
2345 * How many packets could we transmit in this interval?
2346 * If packets didn't fit in the previous interval, we will need
2347 * to transmit that many packets twice within this interval.
2349 packets_remaining = 2 * packets_remaining +
2350 bw_table->interval_bw[i].num_packets;
2352 /* Find the largest max packet size of this or the previous
2355 if (list_empty(&bw_table->interval_bw[i].endpoints))
2358 struct xhci_virt_ep *virt_ep;
2359 struct list_head *ep_entry;
2361 ep_entry = bw_table->interval_bw[i].endpoints.next;
2362 virt_ep = list_entry(ep_entry,
2363 struct xhci_virt_ep, bw_endpoint_list);
2364 /* Convert to blocks, rounding up */
2365 largest_mps = DIV_ROUND_UP(
2366 virt_ep->bw_info.max_packet_size,
2369 if (largest_mps > packet_size)
2370 packet_size = largest_mps;
2372 /* Use the larger overhead of this or the previous interval. */
2373 interval_overhead = xhci_get_largest_overhead(
2374 &bw_table->interval_bw[i]);
2375 if (interval_overhead > overhead)
2376 overhead = interval_overhead;
2378 /* How many packets can we evenly distribute across
2379 * (1 << (i + 1)) possible scheduling opportunities?
2381 packets_transmitted = packets_remaining >> (i + 1);
2383 /* Add in the bandwidth used for those scheduled packets */
2384 bw_added = packets_transmitted * (overhead + packet_size);
2386 /* How many packets do we have remaining to transmit? */
2387 packets_remaining = packets_remaining % (1 << (i + 1));
2389 /* What largest max packet size should those packets have? */
2390 /* If we've transmitted all packets, don't carry over the
2391 * largest packet size.
2393 if (packets_remaining == 0) {
2396 } else if (packets_transmitted > 0) {
2397 /* Otherwise if we do have remaining packets, and we've
2398 * scheduled some packets in this interval, take the
2399 * largest max packet size from endpoints with this
2402 packet_size = largest_mps;
2403 overhead = interval_overhead;
2405 /* Otherwise carry over packet_size and overhead from the last
2406 * time we had a remainder.
2408 bw_used += bw_added;
2409 if (bw_used > max_bandwidth) {
2410 xhci_warn(xhci, "Not enough bandwidth. "
2411 "Proposed: %u, Max: %u\n",
2412 bw_used, max_bandwidth);
2417 * Ok, we know we have some packets left over after even-handedly
2418 * scheduling interval 15. We don't know which microframes they will
2419 * fit into, so we over-schedule and say they will be scheduled every
2422 if (packets_remaining > 0)
2423 bw_used += overhead + packet_size;
2425 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2426 unsigned int port_index = virt_dev->real_port - 1;
2428 /* OK, we're manipulating a HS device attached to a
2429 * root port bandwidth domain. Include the number of active TTs
2430 * in the bandwidth used.
2432 bw_used += TT_HS_OVERHEAD *
2433 xhci->rh_bw[port_index].num_active_tts;
2436 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2437 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2438 "Available: %u " "percent",
2439 bw_used, max_bandwidth, bw_reserved,
2440 (max_bandwidth - bw_used - bw_reserved) * 100 /
2443 bw_used += bw_reserved;
2444 if (bw_used > max_bandwidth) {
2445 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2446 bw_used, max_bandwidth);
2450 bw_table->bw_used = bw_used;
2454 static bool xhci_is_async_ep(unsigned int ep_type)
2456 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2457 ep_type != ISOC_IN_EP &&
2458 ep_type != INT_IN_EP);
2461 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2463 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2466 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2468 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2470 if (ep_bw->ep_interval == 0)
2471 return SS_OVERHEAD_BURST +
2472 (ep_bw->mult * ep_bw->num_packets *
2473 (SS_OVERHEAD + mps));
2474 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2475 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2476 1 << ep_bw->ep_interval);
2480 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2481 struct xhci_bw_info *ep_bw,
2482 struct xhci_interval_bw_table *bw_table,
2483 struct usb_device *udev,
2484 struct xhci_virt_ep *virt_ep,
2485 struct xhci_tt_bw_info *tt_info)
2487 struct xhci_interval_bw *interval_bw;
2488 int normalized_interval;
2490 if (xhci_is_async_ep(ep_bw->type))
2493 if (udev->speed >= USB_SPEED_SUPER) {
2494 if (xhci_is_sync_in_ep(ep_bw->type))
2495 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2496 xhci_get_ss_bw_consumed(ep_bw);
2498 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2499 xhci_get_ss_bw_consumed(ep_bw);
2503 /* SuperSpeed endpoints never get added to intervals in the table, so
2504 * this check is only valid for HS/FS/LS devices.
2506 if (list_empty(&virt_ep->bw_endpoint_list))
2508 /* For LS/FS devices, we need to translate the interval expressed in
2509 * microframes to frames.
2511 if (udev->speed == USB_SPEED_HIGH)
2512 normalized_interval = ep_bw->ep_interval;
2514 normalized_interval = ep_bw->ep_interval - 3;
2516 if (normalized_interval == 0)
2517 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2518 interval_bw = &bw_table->interval_bw[normalized_interval];
2519 interval_bw->num_packets -= ep_bw->num_packets;
2520 switch (udev->speed) {
2522 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2524 case USB_SPEED_FULL:
2525 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2527 case USB_SPEED_HIGH:
2528 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2530 case USB_SPEED_SUPER:
2531 case USB_SPEED_SUPER_PLUS:
2532 case USB_SPEED_UNKNOWN:
2533 case USB_SPEED_WIRELESS:
2534 /* Should never happen because only LS/FS/HS endpoints will get
2535 * added to the endpoint list.
2540 tt_info->active_eps -= 1;
2541 list_del_init(&virt_ep->bw_endpoint_list);
2544 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2545 struct xhci_bw_info *ep_bw,
2546 struct xhci_interval_bw_table *bw_table,
2547 struct usb_device *udev,
2548 struct xhci_virt_ep *virt_ep,
2549 struct xhci_tt_bw_info *tt_info)
2551 struct xhci_interval_bw *interval_bw;
2552 struct xhci_virt_ep *smaller_ep;
2553 int normalized_interval;
2555 if (xhci_is_async_ep(ep_bw->type))
2558 if (udev->speed == USB_SPEED_SUPER) {
2559 if (xhci_is_sync_in_ep(ep_bw->type))
2560 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2561 xhci_get_ss_bw_consumed(ep_bw);
2563 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2564 xhci_get_ss_bw_consumed(ep_bw);
2568 /* For LS/FS devices, we need to translate the interval expressed in
2569 * microframes to frames.
2571 if (udev->speed == USB_SPEED_HIGH)
2572 normalized_interval = ep_bw->ep_interval;
2574 normalized_interval = ep_bw->ep_interval - 3;
2576 if (normalized_interval == 0)
2577 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2578 interval_bw = &bw_table->interval_bw[normalized_interval];
2579 interval_bw->num_packets += ep_bw->num_packets;
2580 switch (udev->speed) {
2582 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2584 case USB_SPEED_FULL:
2585 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2587 case USB_SPEED_HIGH:
2588 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2590 case USB_SPEED_SUPER:
2591 case USB_SPEED_SUPER_PLUS:
2592 case USB_SPEED_UNKNOWN:
2593 case USB_SPEED_WIRELESS:
2594 /* Should never happen because only LS/FS/HS endpoints will get
2595 * added to the endpoint list.
2601 tt_info->active_eps += 1;
2602 /* Insert the endpoint into the list, largest max packet size first. */
2603 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2605 if (ep_bw->max_packet_size >=
2606 smaller_ep->bw_info.max_packet_size) {
2607 /* Add the new ep before the smaller endpoint */
2608 list_add_tail(&virt_ep->bw_endpoint_list,
2609 &smaller_ep->bw_endpoint_list);
2613 /* Add the new endpoint at the end of the list. */
2614 list_add_tail(&virt_ep->bw_endpoint_list,
2615 &interval_bw->endpoints);
2618 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2619 struct xhci_virt_device *virt_dev,
2622 struct xhci_root_port_bw_info *rh_bw_info;
2623 if (!virt_dev->tt_info)
2626 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2627 if (old_active_eps == 0 &&
2628 virt_dev->tt_info->active_eps != 0) {
2629 rh_bw_info->num_active_tts += 1;
2630 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2631 } else if (old_active_eps != 0 &&
2632 virt_dev->tt_info->active_eps == 0) {
2633 rh_bw_info->num_active_tts -= 1;
2634 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2638 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2639 struct xhci_virt_device *virt_dev,
2640 struct xhci_container_ctx *in_ctx)
2642 struct xhci_bw_info ep_bw_info[31];
2644 struct xhci_input_control_ctx *ctrl_ctx;
2645 int old_active_eps = 0;
2647 if (virt_dev->tt_info)
2648 old_active_eps = virt_dev->tt_info->active_eps;
2650 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2652 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2657 for (i = 0; i < 31; i++) {
2658 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2661 /* Make a copy of the BW info in case we need to revert this */
2662 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2663 sizeof(ep_bw_info[i]));
2664 /* Drop the endpoint from the interval table if the endpoint is
2665 * being dropped or changed.
2667 if (EP_IS_DROPPED(ctrl_ctx, i))
2668 xhci_drop_ep_from_interval_table(xhci,
2669 &virt_dev->eps[i].bw_info,
2675 /* Overwrite the information stored in the endpoints' bw_info */
2676 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2677 for (i = 0; i < 31; i++) {
2678 /* Add any changed or added endpoints to the interval table */
2679 if (EP_IS_ADDED(ctrl_ctx, i))
2680 xhci_add_ep_to_interval_table(xhci,
2681 &virt_dev->eps[i].bw_info,
2688 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2689 /* Ok, this fits in the bandwidth we have.
2690 * Update the number of active TTs.
2692 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2696 /* We don't have enough bandwidth for this, revert the stored info. */
2697 for (i = 0; i < 31; i++) {
2698 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2701 /* Drop the new copies of any added or changed endpoints from
2702 * the interval table.
2704 if (EP_IS_ADDED(ctrl_ctx, i)) {
2705 xhci_drop_ep_from_interval_table(xhci,
2706 &virt_dev->eps[i].bw_info,
2712 /* Revert the endpoint back to its old information */
2713 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2714 sizeof(ep_bw_info[i]));
2715 /* Add any changed or dropped endpoints back into the table */
2716 if (EP_IS_DROPPED(ctrl_ctx, i))
2717 xhci_add_ep_to_interval_table(xhci,
2718 &virt_dev->eps[i].bw_info,
2728 /* Issue a configure endpoint command or evaluate context command
2729 * and wait for it to finish.
2731 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2732 struct usb_device *udev,
2733 struct xhci_command *command,
2734 bool ctx_change, bool must_succeed)
2737 unsigned long flags;
2738 struct xhci_input_control_ctx *ctrl_ctx;
2739 struct xhci_virt_device *virt_dev;
2740 struct xhci_slot_ctx *slot_ctx;
2745 spin_lock_irqsave(&xhci->lock, flags);
2747 if (xhci->xhc_state & XHCI_STATE_DYING) {
2748 spin_unlock_irqrestore(&xhci->lock, flags);
2752 virt_dev = xhci->devs[udev->slot_id];
2754 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2756 spin_unlock_irqrestore(&xhci->lock, flags);
2757 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2762 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2763 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2764 spin_unlock_irqrestore(&xhci->lock, flags);
2765 xhci_warn(xhci, "Not enough host resources, "
2766 "active endpoint contexts = %u\n",
2767 xhci->num_active_eps);
2770 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2771 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2772 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2773 xhci_free_host_resources(xhci, ctrl_ctx);
2774 spin_unlock_irqrestore(&xhci->lock, flags);
2775 xhci_warn(xhci, "Not enough bandwidth\n");
2779 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2781 trace_xhci_configure_endpoint_ctrl_ctx(ctrl_ctx);
2782 trace_xhci_configure_endpoint(slot_ctx);
2785 ret = xhci_queue_configure_endpoint(xhci, command,
2786 command->in_ctx->dma,
2787 udev->slot_id, must_succeed);
2789 ret = xhci_queue_evaluate_context(xhci, command,
2790 command->in_ctx->dma,
2791 udev->slot_id, must_succeed);
2793 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2794 xhci_free_host_resources(xhci, ctrl_ctx);
2795 spin_unlock_irqrestore(&xhci->lock, flags);
2796 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2797 "FIXME allocate a new ring segment");
2800 xhci_ring_cmd_db(xhci);
2801 spin_unlock_irqrestore(&xhci->lock, flags);
2803 /* Wait for the configure endpoint command to complete */
2804 wait_for_completion(command->completion);
2807 ret = xhci_configure_endpoint_result(xhci, udev,
2810 ret = xhci_evaluate_context_result(xhci, udev,
2813 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2814 spin_lock_irqsave(&xhci->lock, flags);
2815 /* If the command failed, remove the reserved resources.
2816 * Otherwise, clean up the estimate to include dropped eps.
2819 xhci_free_host_resources(xhci, ctrl_ctx);
2821 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2822 spin_unlock_irqrestore(&xhci->lock, flags);
2827 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2828 struct xhci_virt_device *vdev, int i)
2830 struct xhci_virt_ep *ep = &vdev->eps[i];
2832 if (ep->ep_state & EP_HAS_STREAMS) {
2833 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2834 xhci_get_endpoint_address(i));
2835 xhci_free_stream_info(xhci, ep->stream_info);
2836 ep->stream_info = NULL;
2837 ep->ep_state &= ~EP_HAS_STREAMS;
2841 /* Called after one or more calls to xhci_add_endpoint() or
2842 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2843 * to call xhci_reset_bandwidth().
2845 * Since we are in the middle of changing either configuration or
2846 * installing a new alt setting, the USB core won't allow URBs to be
2847 * enqueued for any endpoint on the old config or interface. Nothing
2848 * else should be touching the xhci->devs[slot_id] structure, so we
2849 * don't need to take the xhci->lock for manipulating that.
2851 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2855 struct xhci_hcd *xhci;
2856 struct xhci_virt_device *virt_dev;
2857 struct xhci_input_control_ctx *ctrl_ctx;
2858 struct xhci_slot_ctx *slot_ctx;
2859 struct xhci_command *command;
2861 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2864 xhci = hcd_to_xhci(hcd);
2865 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2866 (xhci->xhc_state & XHCI_STATE_REMOVING))
2869 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2870 virt_dev = xhci->devs[udev->slot_id];
2872 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2876 command->in_ctx = virt_dev->in_ctx;
2878 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2879 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2881 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2884 goto command_cleanup;
2886 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2887 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2888 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2890 /* Don't issue the command if there's no endpoints to update. */
2891 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2892 ctrl_ctx->drop_flags == 0) {
2894 goto command_cleanup;
2896 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2897 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2898 for (i = 31; i >= 1; i--) {
2899 __le32 le32 = cpu_to_le32(BIT(i));
2901 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2902 || (ctrl_ctx->add_flags & le32) || i == 1) {
2903 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2904 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2909 ret = xhci_configure_endpoint(xhci, udev, command,
2912 /* Callee should call reset_bandwidth() */
2913 goto command_cleanup;
2915 /* Free any rings that were dropped, but not changed. */
2916 for (i = 1; i < 31; i++) {
2917 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2918 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2919 xhci_free_endpoint_ring(xhci, virt_dev, i);
2920 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2923 xhci_zero_in_ctx(xhci, virt_dev);
2925 * Install any rings for completely new endpoints or changed endpoints,
2926 * and free any old rings from changed endpoints.
2928 for (i = 1; i < 31; i++) {
2929 if (!virt_dev->eps[i].new_ring)
2931 /* Only free the old ring if it exists.
2932 * It may not if this is the first add of an endpoint.
2934 if (virt_dev->eps[i].ring) {
2935 xhci_free_endpoint_ring(xhci, virt_dev, i);
2937 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2938 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2939 virt_dev->eps[i].new_ring = NULL;
2942 kfree(command->completion);
2948 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2950 struct xhci_hcd *xhci;
2951 struct xhci_virt_device *virt_dev;
2954 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2957 xhci = hcd_to_xhci(hcd);
2959 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2960 virt_dev = xhci->devs[udev->slot_id];
2961 /* Free any rings allocated for added endpoints */
2962 for (i = 0; i < 31; i++) {
2963 if (virt_dev->eps[i].new_ring) {
2964 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2965 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2966 virt_dev->eps[i].new_ring = NULL;
2969 xhci_zero_in_ctx(xhci, virt_dev);
2972 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2973 struct xhci_container_ctx *in_ctx,
2974 struct xhci_container_ctx *out_ctx,
2975 struct xhci_input_control_ctx *ctrl_ctx,
2976 u32 add_flags, u32 drop_flags)
2978 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2979 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2980 xhci_slot_copy(xhci, in_ctx, out_ctx);
2981 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2984 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2985 unsigned int slot_id, unsigned int ep_index,
2986 struct xhci_dequeue_state *deq_state)
2988 struct xhci_input_control_ctx *ctrl_ctx;
2989 struct xhci_container_ctx *in_ctx;
2990 struct xhci_ep_ctx *ep_ctx;
2994 in_ctx = xhci->devs[slot_id]->in_ctx;
2995 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2997 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3002 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
3003 xhci->devs[slot_id]->out_ctx, ep_index);
3004 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
3005 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
3006 deq_state->new_deq_ptr);
3008 xhci_warn(xhci, "WARN Cannot submit config ep after "
3009 "reset ep command\n");
3010 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
3011 deq_state->new_deq_seg,
3012 deq_state->new_deq_ptr);
3015 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
3017 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
3018 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
3019 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
3020 added_ctxs, added_ctxs);
3023 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
3024 unsigned int stream_id, struct xhci_td *td)
3026 struct xhci_dequeue_state deq_state;
3027 struct usb_device *udev = td->urb->dev;
3029 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3030 "Cleaning up stalled endpoint ring");
3031 /* We need to move the HW's dequeue pointer past this TD,
3032 * or it will attempt to resend it on the next doorbell ring.
3034 xhci_find_new_dequeue_state(xhci, udev->slot_id,
3035 ep_index, stream_id, td, &deq_state);
3037 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
3040 /* HW with the reset endpoint quirk will use the saved dequeue state to
3041 * issue a configure endpoint command later.
3043 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
3044 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
3045 "Queueing new dequeue state");
3046 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
3047 ep_index, &deq_state);
3049 /* Better hope no one uses the input context between now and the
3050 * reset endpoint completion!
3051 * XXX: No idea how this hardware will react when stream rings
3054 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3055 "Setting up input context for "
3056 "configure endpoint command");
3057 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3058 ep_index, &deq_state);
3063 * Called after usb core issues a clear halt control message.
3064 * The host side of the halt should already be cleared by a reset endpoint
3065 * command issued when the STALL event was received.
3067 * The reset endpoint command may only be issued to endpoints in the halted
3068 * state. For software that wishes to reset the data toggle or sequence number
3069 * of an endpoint that isn't in the halted state this function will issue a
3070 * configure endpoint command with the Drop and Add bits set for the target
3071 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3074 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3075 struct usb_host_endpoint *host_ep)
3077 struct xhci_hcd *xhci;
3078 struct usb_device *udev;
3079 struct xhci_virt_device *vdev;
3080 struct xhci_virt_ep *ep;
3081 struct xhci_input_control_ctx *ctrl_ctx;
3082 struct xhci_command *stop_cmd, *cfg_cmd;
3083 unsigned int ep_index;
3084 unsigned long flags;
3087 xhci = hcd_to_xhci(hcd);
3088 if (!host_ep->hcpriv)
3090 udev = (struct usb_device *) host_ep->hcpriv;
3091 vdev = xhci->devs[udev->slot_id];
3094 * vdev may be lost due to xHC restore error and re-initialization
3095 * during S3/S4 resume. A new vdev will be allocated later by
3096 * xhci_discover_or_reset_device()
3098 if (!udev->slot_id || !vdev)
3100 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3101 ep = &vdev->eps[ep_index];
3105 /* Bail out if toggle is already being cleared by a endpoint reset */
3106 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3107 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3110 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3111 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3112 usb_endpoint_xfer_isoc(&host_ep->desc))
3115 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3117 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3120 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3124 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3128 spin_lock_irqsave(&xhci->lock, flags);
3130 /* block queuing new trbs and ringing ep doorbell */
3131 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3134 * Make sure endpoint ring is empty before resetting the toggle/seq.
3135 * Driver is required to synchronously cancel all transfer request.
3136 * Stop the endpoint to force xHC to update the output context
3139 if (!list_empty(&ep->ring->td_list)) {
3140 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3141 spin_unlock_irqrestore(&xhci->lock, flags);
3142 xhci_free_command(xhci, cfg_cmd);
3145 xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
3146 xhci_ring_cmd_db(xhci);
3147 spin_unlock_irqrestore(&xhci->lock, flags);
3149 wait_for_completion(stop_cmd->completion);
3151 spin_lock_irqsave(&xhci->lock, flags);
3153 /* config ep command clears toggle if add and drop ep flags are set */
3154 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3155 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3156 ctrl_ctx, ep_flag, ep_flag);
3157 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3159 xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3160 udev->slot_id, false);
3161 xhci_ring_cmd_db(xhci);
3162 spin_unlock_irqrestore(&xhci->lock, flags);
3164 wait_for_completion(cfg_cmd->completion);
3166 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3167 xhci_free_command(xhci, cfg_cmd);
3169 xhci_free_command(xhci, stop_cmd);
3172 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3173 struct usb_device *udev, struct usb_host_endpoint *ep,
3174 unsigned int slot_id)
3177 unsigned int ep_index;
3178 unsigned int ep_state;
3182 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3185 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3186 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3187 " descriptor for ep 0x%x does not support streams\n",
3188 ep->desc.bEndpointAddress);
3192 ep_index = xhci_get_endpoint_index(&ep->desc);
3193 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3194 if (ep_state & EP_HAS_STREAMS ||
3195 ep_state & EP_GETTING_STREAMS) {
3196 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3197 "already has streams set up.\n",
3198 ep->desc.bEndpointAddress);
3199 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3200 "dynamic stream context array reallocation.\n");
3203 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3204 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3205 "endpoint 0x%x; URBs are pending.\n",
3206 ep->desc.bEndpointAddress);
3212 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3213 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3215 unsigned int max_streams;
3217 /* The stream context array size must be a power of two */
3218 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3220 * Find out how many primary stream array entries the host controller
3221 * supports. Later we may use secondary stream arrays (similar to 2nd
3222 * level page entries), but that's an optional feature for xHCI host
3223 * controllers. xHCs must support at least 4 stream IDs.
3225 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3226 if (*num_stream_ctxs > max_streams) {
3227 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3229 *num_stream_ctxs = max_streams;
3230 *num_streams = max_streams;
3234 /* Returns an error code if one of the endpoint already has streams.
3235 * This does not change any data structures, it only checks and gathers
3238 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3239 struct usb_device *udev,
3240 struct usb_host_endpoint **eps, unsigned int num_eps,
3241 unsigned int *num_streams, u32 *changed_ep_bitmask)
3243 unsigned int max_streams;
3244 unsigned int endpoint_flag;
3248 for (i = 0; i < num_eps; i++) {
3249 ret = xhci_check_streams_endpoint(xhci, udev,
3250 eps[i], udev->slot_id);
3254 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3255 if (max_streams < (*num_streams - 1)) {
3256 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3257 eps[i]->desc.bEndpointAddress,
3259 *num_streams = max_streams+1;
3262 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3263 if (*changed_ep_bitmask & endpoint_flag)
3265 *changed_ep_bitmask |= endpoint_flag;
3270 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3271 struct usb_device *udev,
3272 struct usb_host_endpoint **eps, unsigned int num_eps)
3274 u32 changed_ep_bitmask = 0;
3275 unsigned int slot_id;
3276 unsigned int ep_index;
3277 unsigned int ep_state;
3280 slot_id = udev->slot_id;
3281 if (!xhci->devs[slot_id])
3284 for (i = 0; i < num_eps; i++) {
3285 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3286 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3287 /* Are streams already being freed for the endpoint? */
3288 if (ep_state & EP_GETTING_NO_STREAMS) {
3289 xhci_warn(xhci, "WARN Can't disable streams for "
3291 "streams are being disabled already\n",
3292 eps[i]->desc.bEndpointAddress);
3295 /* Are there actually any streams to free? */
3296 if (!(ep_state & EP_HAS_STREAMS) &&
3297 !(ep_state & EP_GETTING_STREAMS)) {
3298 xhci_warn(xhci, "WARN Can't disable streams for "
3300 "streams are already disabled!\n",
3301 eps[i]->desc.bEndpointAddress);
3302 xhci_warn(xhci, "WARN xhci_free_streams() called "
3303 "with non-streams endpoint\n");
3306 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3308 return changed_ep_bitmask;
3312 * The USB device drivers use this function (through the HCD interface in USB
3313 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3314 * coordinate mass storage command queueing across multiple endpoints (basically
3315 * a stream ID == a task ID).
3317 * Setting up streams involves allocating the same size stream context array
3318 * for each endpoint and issuing a configure endpoint command for all endpoints.
3320 * Don't allow the call to succeed if one endpoint only supports one stream
3321 * (which means it doesn't support streams at all).
3323 * Drivers may get less stream IDs than they asked for, if the host controller
3324 * hardware or endpoints claim they can't support the number of requested
3327 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3328 struct usb_host_endpoint **eps, unsigned int num_eps,
3329 unsigned int num_streams, gfp_t mem_flags)
3332 struct xhci_hcd *xhci;
3333 struct xhci_virt_device *vdev;
3334 struct xhci_command *config_cmd;
3335 struct xhci_input_control_ctx *ctrl_ctx;
3336 unsigned int ep_index;
3337 unsigned int num_stream_ctxs;
3338 unsigned int max_packet;
3339 unsigned long flags;
3340 u32 changed_ep_bitmask = 0;
3345 /* Add one to the number of streams requested to account for
3346 * stream 0 that is reserved for xHCI usage.
3349 xhci = hcd_to_xhci(hcd);
3350 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3353 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3354 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3355 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3356 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3360 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3364 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3366 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3368 xhci_free_command(xhci, config_cmd);
3372 /* Check to make sure all endpoints are not already configured for
3373 * streams. While we're at it, find the maximum number of streams that
3374 * all the endpoints will support and check for duplicate endpoints.
3376 spin_lock_irqsave(&xhci->lock, flags);
3377 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3378 num_eps, &num_streams, &changed_ep_bitmask);
3380 xhci_free_command(xhci, config_cmd);
3381 spin_unlock_irqrestore(&xhci->lock, flags);
3384 if (num_streams <= 1) {
3385 xhci_warn(xhci, "WARN: endpoints can't handle "
3386 "more than one stream.\n");
3387 xhci_free_command(xhci, config_cmd);
3388 spin_unlock_irqrestore(&xhci->lock, flags);
3391 vdev = xhci->devs[udev->slot_id];
3392 /* Mark each endpoint as being in transition, so
3393 * xhci_urb_enqueue() will reject all URBs.
3395 for (i = 0; i < num_eps; i++) {
3396 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3397 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3399 spin_unlock_irqrestore(&xhci->lock, flags);
3401 /* Setup internal data structures and allocate HW data structures for
3402 * streams (but don't install the HW structures in the input context
3403 * until we're sure all memory allocation succeeded).
3405 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3406 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3407 num_stream_ctxs, num_streams);
3409 for (i = 0; i < num_eps; i++) {
3410 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3411 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3412 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3415 max_packet, mem_flags);
3416 if (!vdev->eps[ep_index].stream_info)
3418 /* Set maxPstreams in endpoint context and update deq ptr to
3419 * point to stream context array. FIXME
3423 /* Set up the input context for a configure endpoint command. */
3424 for (i = 0; i < num_eps; i++) {
3425 struct xhci_ep_ctx *ep_ctx;
3427 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3428 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3430 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3431 vdev->out_ctx, ep_index);
3432 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3433 vdev->eps[ep_index].stream_info);
3435 /* Tell the HW to drop its old copy of the endpoint context info
3436 * and add the updated copy from the input context.
3438 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3439 vdev->out_ctx, ctrl_ctx,
3440 changed_ep_bitmask, changed_ep_bitmask);
3442 /* Issue and wait for the configure endpoint command */
3443 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3446 /* xHC rejected the configure endpoint command for some reason, so we
3447 * leave the old ring intact and free our internal streams data
3453 spin_lock_irqsave(&xhci->lock, flags);
3454 for (i = 0; i < num_eps; i++) {
3455 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3456 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3457 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3458 udev->slot_id, ep_index);
3459 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3461 xhci_free_command(xhci, config_cmd);
3462 spin_unlock_irqrestore(&xhci->lock, flags);
3464 /* Subtract 1 for stream 0, which drivers can't use */
3465 return num_streams - 1;
3468 /* If it didn't work, free the streams! */
3469 for (i = 0; i < num_eps; i++) {
3470 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3471 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3472 vdev->eps[ep_index].stream_info = NULL;
3473 /* FIXME Unset maxPstreams in endpoint context and
3474 * update deq ptr to point to normal string ring.
3476 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3477 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3478 xhci_endpoint_zero(xhci, vdev, eps[i]);
3480 xhci_free_command(xhci, config_cmd);
3484 /* Transition the endpoint from using streams to being a "normal" endpoint
3487 * Modify the endpoint context state, submit a configure endpoint command,
3488 * and free all endpoint rings for streams if that completes successfully.
3490 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3491 struct usb_host_endpoint **eps, unsigned int num_eps,
3495 struct xhci_hcd *xhci;
3496 struct xhci_virt_device *vdev;
3497 struct xhci_command *command;
3498 struct xhci_input_control_ctx *ctrl_ctx;
3499 unsigned int ep_index;
3500 unsigned long flags;
3501 u32 changed_ep_bitmask;
3503 xhci = hcd_to_xhci(hcd);
3504 vdev = xhci->devs[udev->slot_id];
3506 /* Set up a configure endpoint command to remove the streams rings */
3507 spin_lock_irqsave(&xhci->lock, flags);
3508 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3509 udev, eps, num_eps);
3510 if (changed_ep_bitmask == 0) {
3511 spin_unlock_irqrestore(&xhci->lock, flags);
3515 /* Use the xhci_command structure from the first endpoint. We may have
3516 * allocated too many, but the driver may call xhci_free_streams() for
3517 * each endpoint it grouped into one call to xhci_alloc_streams().
3519 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3520 command = vdev->eps[ep_index].stream_info->free_streams_command;
3521 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3523 spin_unlock_irqrestore(&xhci->lock, flags);
3524 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3529 for (i = 0; i < num_eps; i++) {
3530 struct xhci_ep_ctx *ep_ctx;
3532 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3533 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3534 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3535 EP_GETTING_NO_STREAMS;
3537 xhci_endpoint_copy(xhci, command->in_ctx,
3538 vdev->out_ctx, ep_index);
3539 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3540 &vdev->eps[ep_index]);
3542 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3543 vdev->out_ctx, ctrl_ctx,
3544 changed_ep_bitmask, changed_ep_bitmask);
3545 spin_unlock_irqrestore(&xhci->lock, flags);
3547 /* Issue and wait for the configure endpoint command,
3548 * which must succeed.
3550 ret = xhci_configure_endpoint(xhci, udev, command,
3553 /* xHC rejected the configure endpoint command for some reason, so we
3554 * leave the streams rings intact.
3559 spin_lock_irqsave(&xhci->lock, flags);
3560 for (i = 0; i < num_eps; i++) {
3561 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3562 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3563 vdev->eps[ep_index].stream_info = NULL;
3564 /* FIXME Unset maxPstreams in endpoint context and
3565 * update deq ptr to point to normal string ring.
3567 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3568 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3570 spin_unlock_irqrestore(&xhci->lock, flags);
3576 * Deletes endpoint resources for endpoints that were active before a Reset
3577 * Device command, or a Disable Slot command. The Reset Device command leaves
3578 * the control endpoint intact, whereas the Disable Slot command deletes it.
3580 * Must be called with xhci->lock held.
3582 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3583 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3586 unsigned int num_dropped_eps = 0;
3587 unsigned int drop_flags = 0;
3589 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3590 if (virt_dev->eps[i].ring) {
3591 drop_flags |= 1 << i;
3595 xhci->num_active_eps -= num_dropped_eps;
3596 if (num_dropped_eps)
3597 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3598 "Dropped %u ep ctxs, flags = 0x%x, "
3600 num_dropped_eps, drop_flags,
3601 xhci->num_active_eps);
3605 * This submits a Reset Device Command, which will set the device state to 0,
3606 * set the device address to 0, and disable all the endpoints except the default
3607 * control endpoint. The USB core should come back and call
3608 * xhci_address_device(), and then re-set up the configuration. If this is
3609 * called because of a usb_reset_and_verify_device(), then the old alternate
3610 * settings will be re-installed through the normal bandwidth allocation
3613 * Wait for the Reset Device command to finish. Remove all structures
3614 * associated with the endpoints that were disabled. Clear the input device
3615 * structure? Reset the control endpoint 0 max packet size?
3617 * If the virt_dev to be reset does not exist or does not match the udev,
3618 * it means the device is lost, possibly due to the xHC restore error and
3619 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3620 * re-allocate the device.
3622 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3623 struct usb_device *udev)
3626 unsigned long flags;
3627 struct xhci_hcd *xhci;
3628 unsigned int slot_id;
3629 struct xhci_virt_device *virt_dev;
3630 struct xhci_command *reset_device_cmd;
3631 struct xhci_slot_ctx *slot_ctx;
3632 int old_active_eps = 0;
3634 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3637 xhci = hcd_to_xhci(hcd);
3638 slot_id = udev->slot_id;
3639 virt_dev = xhci->devs[slot_id];
3641 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3642 "not exist. Re-allocate the device\n", slot_id);
3643 ret = xhci_alloc_dev(hcd, udev);
3650 if (virt_dev->tt_info)
3651 old_active_eps = virt_dev->tt_info->active_eps;
3653 if (virt_dev->udev != udev) {
3654 /* If the virt_dev and the udev does not match, this virt_dev
3655 * may belong to another udev.
3656 * Re-allocate the device.
3658 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3659 "not match the udev. Re-allocate the device\n",
3661 ret = xhci_alloc_dev(hcd, udev);
3668 /* If device is not setup, there is no point in resetting it */
3669 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3670 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3671 SLOT_STATE_DISABLED)
3674 trace_xhci_discover_or_reset_device(slot_ctx);
3676 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3677 /* Allocate the command structure that holds the struct completion.
3678 * Assume we're in process context, since the normal device reset
3679 * process has to wait for the device anyway. Storage devices are
3680 * reset as part of error handling, so use GFP_NOIO instead of
3683 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3684 if (!reset_device_cmd) {
3685 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3689 /* Attempt to submit the Reset Device command to the command ring */
3690 spin_lock_irqsave(&xhci->lock, flags);
3692 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3694 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3695 spin_unlock_irqrestore(&xhci->lock, flags);
3696 goto command_cleanup;
3698 xhci_ring_cmd_db(xhci);
3699 spin_unlock_irqrestore(&xhci->lock, flags);
3701 /* Wait for the Reset Device command to finish */
3702 wait_for_completion(reset_device_cmd->completion);
3704 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3705 * unless we tried to reset a slot ID that wasn't enabled,
3706 * or the device wasn't in the addressed or configured state.
3708 ret = reset_device_cmd->status;
3710 case COMP_COMMAND_ABORTED:
3711 case COMP_COMMAND_RING_STOPPED:
3712 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3714 goto command_cleanup;
3715 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3716 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3717 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3719 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3720 xhci_dbg(xhci, "Not freeing device rings.\n");
3721 /* Don't treat this as an error. May change my mind later. */
3723 goto command_cleanup;
3725 xhci_dbg(xhci, "Successful reset device command.\n");
3728 if (xhci_is_vendor_info_code(xhci, ret))
3730 xhci_warn(xhci, "Unknown completion code %u for "
3731 "reset device command.\n", ret);
3733 goto command_cleanup;
3736 /* Free up host controller endpoint resources */
3737 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3738 spin_lock_irqsave(&xhci->lock, flags);
3739 /* Don't delete the default control endpoint resources */
3740 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3741 spin_unlock_irqrestore(&xhci->lock, flags);
3744 /* Everything but endpoint 0 is disabled, so free the rings. */
3745 for (i = 1; i < 31; i++) {
3746 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3748 if (ep->ep_state & EP_HAS_STREAMS) {
3749 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3750 xhci_get_endpoint_address(i));
3751 xhci_free_stream_info(xhci, ep->stream_info);
3752 ep->stream_info = NULL;
3753 ep->ep_state &= ~EP_HAS_STREAMS;
3757 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3758 xhci_free_endpoint_ring(xhci, virt_dev, i);
3760 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3761 xhci_drop_ep_from_interval_table(xhci,
3762 &virt_dev->eps[i].bw_info,
3767 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3769 /* If necessary, update the number of active TTs on this root port */
3770 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3771 virt_dev->flags = 0;
3775 xhci_free_command(xhci, reset_device_cmd);
3780 * At this point, the struct usb_device is about to go away, the device has
3781 * disconnected, and all traffic has been stopped and the endpoints have been
3782 * disabled. Free any HC data structures associated with that device.
3784 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3786 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3787 struct xhci_virt_device *virt_dev;
3788 struct xhci_slot_ctx *slot_ctx;
3791 #ifndef CONFIG_USB_DEFAULT_PERSIST
3793 * We called pm_runtime_get_noresume when the device was attached.
3794 * Decrement the counter here to allow controller to runtime suspend
3795 * if no devices remain.
3797 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3798 pm_runtime_put_noidle(hcd->self.controller);
3801 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3802 /* If the host is halted due to driver unload, we still need to free the
3805 if (ret <= 0 && ret != -ENODEV)
3808 virt_dev = xhci->devs[udev->slot_id];
3809 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3810 trace_xhci_free_dev(slot_ctx);
3812 /* Stop any wayward timer functions (which may grab the lock) */
3813 for (i = 0; i < 31; i++) {
3814 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3815 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3817 virt_dev->udev = NULL;
3818 ret = xhci_disable_slot(xhci, udev->slot_id);
3820 xhci_free_virt_device(xhci, udev->slot_id);
3823 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3825 struct xhci_command *command;
3826 unsigned long flags;
3830 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3834 xhci_debugfs_remove_slot(xhci, slot_id);
3836 spin_lock_irqsave(&xhci->lock, flags);
3837 /* Don't disable the slot if the host controller is dead. */
3838 state = readl(&xhci->op_regs->status);
3839 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3840 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3841 spin_unlock_irqrestore(&xhci->lock, flags);
3846 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3849 spin_unlock_irqrestore(&xhci->lock, flags);
3853 xhci_ring_cmd_db(xhci);
3854 spin_unlock_irqrestore(&xhci->lock, flags);
3859 * Checks if we have enough host controller resources for the default control
3862 * Must be called with xhci->lock held.
3864 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3866 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3867 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3868 "Not enough ep ctxs: "
3869 "%u active, need to add 1, limit is %u.",
3870 xhci->num_active_eps, xhci->limit_active_eps);
3873 xhci->num_active_eps += 1;
3874 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3875 "Adding 1 ep ctx, %u now active.",
3876 xhci->num_active_eps);
3882 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3883 * timed out, or allocating memory failed. Returns 1 on success.
3885 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3887 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3888 struct xhci_virt_device *vdev;
3889 struct xhci_slot_ctx *slot_ctx;
3890 unsigned long flags;
3892 struct xhci_command *command;
3894 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3898 spin_lock_irqsave(&xhci->lock, flags);
3899 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3901 spin_unlock_irqrestore(&xhci->lock, flags);
3902 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3903 xhci_free_command(xhci, command);
3906 xhci_ring_cmd_db(xhci);
3907 spin_unlock_irqrestore(&xhci->lock, flags);
3909 wait_for_completion(command->completion);
3910 slot_id = command->slot_id;
3912 if (!slot_id || command->status != COMP_SUCCESS) {
3913 xhci_err(xhci, "Error while assigning device slot ID\n");
3914 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3916 readl(&xhci->cap_regs->hcs_params1)));
3917 xhci_free_command(xhci, command);
3921 xhci_free_command(xhci, command);
3923 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3924 spin_lock_irqsave(&xhci->lock, flags);
3925 ret = xhci_reserve_host_control_ep_resources(xhci);
3927 spin_unlock_irqrestore(&xhci->lock, flags);
3928 xhci_warn(xhci, "Not enough host resources, "
3929 "active endpoint contexts = %u\n",
3930 xhci->num_active_eps);
3933 spin_unlock_irqrestore(&xhci->lock, flags);
3935 /* Use GFP_NOIO, since this function can be called from
3936 * xhci_discover_or_reset_device(), which may be called as part of
3937 * mass storage driver error handling.
3939 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3940 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3943 vdev = xhci->devs[slot_id];
3944 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3945 trace_xhci_alloc_dev(slot_ctx);
3947 udev->slot_id = slot_id;
3949 xhci_debugfs_create_slot(xhci, slot_id);
3951 #ifndef CONFIG_USB_DEFAULT_PERSIST
3953 * If resetting upon resume, we can't put the controller into runtime
3954 * suspend if there is a device attached.
3956 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3957 pm_runtime_get_noresume(hcd->self.controller);
3960 /* Is this a LS or FS device under a HS hub? */
3961 /* Hub or peripherial? */
3965 ret = xhci_disable_slot(xhci, udev->slot_id);
3967 xhci_free_virt_device(xhci, udev->slot_id);
3973 * Issue an Address Device command and optionally send a corresponding
3974 * SetAddress request to the device.
3976 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3977 enum xhci_setup_dev setup)
3979 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3980 unsigned long flags;
3981 struct xhci_virt_device *virt_dev;
3983 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3984 struct xhci_slot_ctx *slot_ctx;
3985 struct xhci_input_control_ctx *ctrl_ctx;
3987 struct xhci_command *command = NULL;
3989 mutex_lock(&xhci->mutex);
3991 if (xhci->xhc_state) { /* dying, removing or halted */
3996 if (!udev->slot_id) {
3997 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3998 "Bad Slot ID %d", udev->slot_id);
4003 virt_dev = xhci->devs[udev->slot_id];
4005 if (WARN_ON(!virt_dev)) {
4007 * In plug/unplug torture test with an NEC controller,
4008 * a zero-dereference was observed once due to virt_dev = 0.
4009 * Print useful debug rather than crash if it is observed again!
4011 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
4016 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4017 trace_xhci_setup_device_slot(slot_ctx);
4019 if (setup == SETUP_CONTEXT_ONLY) {
4020 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
4021 SLOT_STATE_DEFAULT) {
4022 xhci_dbg(xhci, "Slot already in default state\n");
4027 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
4033 command->in_ctx = virt_dev->in_ctx;
4035 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
4036 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
4038 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4044 * If this is the first Set Address since device plug-in or
4045 * virt_device realloaction after a resume with an xHCI power loss,
4046 * then set up the slot context.
4048 if (!slot_ctx->dev_info)
4049 xhci_setup_addressable_virt_dev(xhci, udev);
4050 /* Otherwise, update the control endpoint ring enqueue pointer. */
4052 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
4053 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
4054 ctrl_ctx->drop_flags = 0;
4056 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4057 le32_to_cpu(slot_ctx->dev_info) >> 27);
4059 trace_xhci_address_ctrl_ctx(ctrl_ctx);
4060 spin_lock_irqsave(&xhci->lock, flags);
4061 trace_xhci_setup_device(virt_dev);
4062 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4063 udev->slot_id, setup);
4065 spin_unlock_irqrestore(&xhci->lock, flags);
4066 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4067 "FIXME: allocate a command ring segment");
4070 xhci_ring_cmd_db(xhci);
4071 spin_unlock_irqrestore(&xhci->lock, flags);
4073 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4074 wait_for_completion(command->completion);
4076 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4077 * the SetAddress() "recovery interval" required by USB and aborting the
4078 * command on a timeout.
4080 switch (command->status) {
4081 case COMP_COMMAND_ABORTED:
4082 case COMP_COMMAND_RING_STOPPED:
4083 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4086 case COMP_CONTEXT_STATE_ERROR:
4087 case COMP_SLOT_NOT_ENABLED_ERROR:
4088 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4089 act, udev->slot_id);
4092 case COMP_USB_TRANSACTION_ERROR:
4093 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4095 mutex_unlock(&xhci->mutex);
4096 ret = xhci_disable_slot(xhci, udev->slot_id);
4098 xhci_alloc_dev(hcd, udev);
4099 kfree(command->completion);
4102 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4103 dev_warn(&udev->dev,
4104 "ERROR: Incompatible device for setup %s command\n", act);
4108 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4109 "Successful setup %s command", act);
4113 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4114 act, command->status);
4115 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4121 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4122 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4123 "Op regs DCBAA ptr = %#016llx", temp_64);
4124 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4125 "Slot ID %d dcbaa entry @%p = %#016llx",
4127 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4128 (unsigned long long)
4129 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4130 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4131 "Output Context DMA address = %#08llx",
4132 (unsigned long long)virt_dev->out_ctx->dma);
4133 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4134 le32_to_cpu(slot_ctx->dev_info) >> 27);
4136 * USB core uses address 1 for the roothubs, so we add one to the
4137 * address given back to us by the HC.
4139 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4140 le32_to_cpu(slot_ctx->dev_info) >> 27);
4141 /* Zero the input context control for later use */
4142 ctrl_ctx->add_flags = 0;
4143 ctrl_ctx->drop_flags = 0;
4144 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
4145 udev->devaddr = (u8)(le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4147 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4148 "Internal device address = %d",
4149 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4151 mutex_unlock(&xhci->mutex);
4153 kfree(command->completion);
4159 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4161 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4164 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4166 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4170 * Transfer the port index into real index in the HW port status
4171 * registers. Caculate offset between the port's PORTSC register
4172 * and port status base. Divide the number of per port register
4173 * to get the real index. The raw port number bases 1.
4175 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4177 struct xhci_hub *rhub;
4179 rhub = xhci_get_rhub(hcd);
4180 return rhub->ports[port1 - 1]->hw_portnum + 1;
4184 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4185 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4187 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4188 struct usb_device *udev, u16 max_exit_latency)
4190 struct xhci_virt_device *virt_dev;
4191 struct xhci_command *command;
4192 struct xhci_input_control_ctx *ctrl_ctx;
4193 struct xhci_slot_ctx *slot_ctx;
4194 unsigned long flags;
4197 spin_lock_irqsave(&xhci->lock, flags);
4199 virt_dev = xhci->devs[udev->slot_id];
4202 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4203 * xHC was re-initialized. Exit latency will be set later after
4204 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4207 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4208 spin_unlock_irqrestore(&xhci->lock, flags);
4212 /* Attempt to issue an Evaluate Context command to change the MEL. */
4213 command = xhci->lpm_command;
4214 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4216 spin_unlock_irqrestore(&xhci->lock, flags);
4217 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4222 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4223 spin_unlock_irqrestore(&xhci->lock, flags);
4225 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4226 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4227 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4228 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4229 slot_ctx->dev_state = 0;
4231 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4232 "Set up evaluate context for LPM MEL change.");
4234 /* Issue and wait for the evaluate context command. */
4235 ret = xhci_configure_endpoint(xhci, udev, command,
4239 spin_lock_irqsave(&xhci->lock, flags);
4240 virt_dev->current_mel = max_exit_latency;
4241 spin_unlock_irqrestore(&xhci->lock, flags);
4248 /* BESL to HIRD Encoding array for USB2 LPM */
4249 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4250 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4252 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4253 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4254 struct usb_device *udev)
4256 int u2del, besl, besl_host;
4257 int besl_device = 0;
4260 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4261 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4263 if (field & USB_BESL_SUPPORT) {
4264 for (besl_host = 0; besl_host < 16; besl_host++) {
4265 if (xhci_besl_encoding[besl_host] >= u2del)
4268 /* Use baseline BESL value as default */
4269 if (field & USB_BESL_BASELINE_VALID)
4270 besl_device = USB_GET_BESL_BASELINE(field);
4271 else if (field & USB_BESL_DEEP_VALID)
4272 besl_device = USB_GET_BESL_DEEP(field);
4277 besl_host = (u2del - 51) / 75 + 1;
4280 besl = besl_host + besl_device;
4287 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4288 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4295 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4297 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4298 l1 = udev->l1_params.timeout / 256;
4300 /* device has preferred BESLD */
4301 if (field & USB_BESL_DEEP_VALID) {
4302 besld = USB_GET_BESL_DEEP(field);
4306 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4309 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4310 struct usb_device *udev, int enable)
4312 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4313 struct xhci_port **ports;
4314 __le32 __iomem *pm_addr, *hlpm_addr;
4315 u32 pm_val, hlpm_val, field;
4316 unsigned int port_num;
4317 unsigned long flags;
4318 int hird, exit_latency;
4321 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4325 if (!udev->parent || udev->parent->parent ||
4326 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4329 if (udev->usb2_hw_lpm_capable != 1)
4332 spin_lock_irqsave(&xhci->lock, flags);
4334 ports = xhci->usb2_rhub.ports;
4335 port_num = udev->portnum - 1;
4336 pm_addr = ports[port_num]->addr + PORTPMSC;
4337 pm_val = readl(pm_addr);
4338 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4340 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4341 enable ? "enable" : "disable", port_num + 1);
4343 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4344 /* Host supports BESL timeout instead of HIRD */
4345 if (udev->usb2_hw_lpm_besl_capable) {
4346 /* if device doesn't have a preferred BESL value use a
4347 * default one which works with mixed HIRD and BESL
4348 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4350 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4351 if ((field & USB_BESL_SUPPORT) &&
4352 (field & USB_BESL_BASELINE_VALID))
4353 hird = USB_GET_BESL_BASELINE(field);
4355 hird = udev->l1_params.besl;
4357 exit_latency = xhci_besl_encoding[hird];
4358 spin_unlock_irqrestore(&xhci->lock, flags);
4360 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4361 * input context for link powermanagement evaluate
4362 * context commands. It is protected by hcd->bandwidth
4363 * mutex and is shared by all devices. We need to set
4364 * the max ext latency in USB 2 BESL LPM as well, so
4365 * use the same mutex and xhci_change_max_exit_latency()
4367 mutex_lock(hcd->bandwidth_mutex);
4368 ret = xhci_change_max_exit_latency(xhci, udev,
4370 mutex_unlock(hcd->bandwidth_mutex);
4374 spin_lock_irqsave(&xhci->lock, flags);
4376 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4377 writel(hlpm_val, hlpm_addr);
4381 hird = xhci_calculate_hird_besl(xhci, udev);
4384 pm_val &= ~PORT_HIRD_MASK;
4385 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4386 writel(pm_val, pm_addr);
4387 pm_val = readl(pm_addr);
4389 writel(pm_val, pm_addr);
4393 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4394 writel(pm_val, pm_addr);
4397 if (udev->usb2_hw_lpm_besl_capable) {
4398 spin_unlock_irqrestore(&xhci->lock, flags);
4399 mutex_lock(hcd->bandwidth_mutex);
4400 xhci_change_max_exit_latency(xhci, udev, 0);
4401 mutex_unlock(hcd->bandwidth_mutex);
4406 spin_unlock_irqrestore(&xhci->lock, flags);
4410 /* check if a usb2 port supports a given extened capability protocol
4411 * only USB2 ports extended protocol capability values are cached.
4412 * Return 1 if capability is supported
4414 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4415 unsigned capability)
4417 u32 port_offset, port_count;
4420 for (i = 0; i < xhci->num_ext_caps; i++) {
4421 if (xhci->ext_caps[i] & capability) {
4422 /* port offsets starts at 1 */
4423 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4424 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4425 if (port >= port_offset &&
4426 port < port_offset + port_count)
4433 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4435 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4436 int portnum = udev->portnum - 1;
4438 if (hcd->speed >= HCD_USB3 || !udev->lpm_capable)
4441 /* we only support lpm for non-hub device connected to root hub yet */
4442 if (!udev->parent || udev->parent->parent ||
4443 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4446 if (xhci->hw_lpm_support == 1 &&
4447 xhci_check_usb2_port_capability(
4448 xhci, portnum, XHCI_HLC)) {
4449 udev->usb2_hw_lpm_capable = 1;
4450 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4451 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4452 if (xhci_check_usb2_port_capability(xhci, portnum,
4454 udev->usb2_hw_lpm_besl_capable = 1;
4460 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4462 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4463 static unsigned long long xhci_service_interval_to_ns(
4464 struct usb_endpoint_descriptor *desc)
4466 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4469 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4470 enum usb3_link_state state)
4472 unsigned long long sel;
4473 unsigned long long pel;
4474 unsigned int max_sel_pel;
4479 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4480 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4481 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4482 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4486 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4487 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4488 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4492 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4494 return USB3_LPM_DISABLED;
4497 if (sel <= max_sel_pel && pel <= max_sel_pel)
4498 return USB3_LPM_DEVICE_INITIATED;
4500 if (sel > max_sel_pel)
4501 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4502 "due to long SEL %llu ms\n",
4505 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4506 "due to long PEL %llu ms\n",
4508 return USB3_LPM_DISABLED;
4511 /* The U1 timeout should be the maximum of the following values:
4512 * - For control endpoints, U1 system exit latency (SEL) * 3
4513 * - For bulk endpoints, U1 SEL * 5
4514 * - For interrupt endpoints:
4515 * - Notification EPs, U1 SEL * 3
4516 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4517 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4519 static unsigned long long xhci_calculate_intel_u1_timeout(
4520 struct usb_device *udev,
4521 struct usb_endpoint_descriptor *desc)
4523 unsigned long long timeout_ns;
4527 ep_type = usb_endpoint_type(desc);
4529 case USB_ENDPOINT_XFER_CONTROL:
4530 timeout_ns = udev->u1_params.sel * 3;
4532 case USB_ENDPOINT_XFER_BULK:
4533 timeout_ns = udev->u1_params.sel * 5;
4535 case USB_ENDPOINT_XFER_INT:
4536 intr_type = usb_endpoint_interrupt_type(desc);
4537 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4538 timeout_ns = udev->u1_params.sel * 3;
4541 /* Otherwise the calculation is the same as isoc eps */
4543 case USB_ENDPOINT_XFER_ISOC:
4544 timeout_ns = xhci_service_interval_to_ns(desc);
4545 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4546 if (timeout_ns < udev->u1_params.sel * 2)
4547 timeout_ns = udev->u1_params.sel * 2;
4556 /* Returns the hub-encoded U1 timeout value. */
4557 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4558 struct usb_device *udev,
4559 struct usb_endpoint_descriptor *desc)
4561 unsigned long long timeout_ns;
4563 /* Prevent U1 if service interval is shorter than U1 exit latency */
4564 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4565 if (xhci_service_interval_to_ns(desc) <= udev->u1_params.mel) {
4566 dev_dbg(&udev->dev, "Disable U1, ESIT shorter than exit latency\n");
4567 return USB3_LPM_DISABLED;
4571 if (xhci->quirks & XHCI_INTEL_HOST)
4572 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4574 timeout_ns = udev->u1_params.sel;
4576 /* The U1 timeout is encoded in 1us intervals.
4577 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4579 if (timeout_ns == USB3_LPM_DISABLED)
4582 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4584 /* If the necessary timeout value is bigger than what we can set in the
4585 * USB 3.0 hub, we have to disable hub-initiated U1.
4587 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4589 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4590 "due to long timeout %llu ms\n", timeout_ns);
4591 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4594 /* The U2 timeout should be the maximum of:
4595 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4596 * - largest bInterval of any active periodic endpoint (to avoid going
4597 * into lower power link states between intervals).
4598 * - the U2 Exit Latency of the device
4600 static unsigned long long xhci_calculate_intel_u2_timeout(
4601 struct usb_device *udev,
4602 struct usb_endpoint_descriptor *desc)
4604 unsigned long long timeout_ns;
4605 unsigned long long u2_del_ns;
4607 timeout_ns = 10 * 1000 * 1000;
4609 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4610 (xhci_service_interval_to_ns(desc) > timeout_ns))
4611 timeout_ns = xhci_service_interval_to_ns(desc);
4613 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4614 if (u2_del_ns > timeout_ns)
4615 timeout_ns = u2_del_ns;
4620 /* Returns the hub-encoded U2 timeout value. */
4621 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4622 struct usb_device *udev,
4623 struct usb_endpoint_descriptor *desc)
4625 unsigned long long timeout_ns;
4627 /* Prevent U2 if service interval is shorter than U2 exit latency */
4628 if (usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) {
4629 if (xhci_service_interval_to_ns(desc) <= udev->u2_params.mel) {
4630 dev_dbg(&udev->dev, "Disable U2, ESIT shorter than exit latency\n");
4631 return USB3_LPM_DISABLED;
4635 if (xhci->quirks & XHCI_INTEL_HOST)
4636 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4638 timeout_ns = udev->u2_params.sel;
4640 /* The U2 timeout is encoded in 256us intervals */
4641 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4642 /* If the necessary timeout value is bigger than what we can set in the
4643 * USB 3.0 hub, we have to disable hub-initiated U2.
4645 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4647 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4648 "due to long timeout %llu ms\n", timeout_ns);
4649 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4652 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4653 struct usb_device *udev,
4654 struct usb_endpoint_descriptor *desc,
4655 enum usb3_link_state state,
4658 if (state == USB3_LPM_U1)
4659 return xhci_calculate_u1_timeout(xhci, udev, desc);
4660 else if (state == USB3_LPM_U2)
4661 return xhci_calculate_u2_timeout(xhci, udev, desc);
4663 return USB3_LPM_DISABLED;
4666 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4667 struct usb_device *udev,
4668 struct usb_endpoint_descriptor *desc,
4669 enum usb3_link_state state,
4674 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4675 desc, state, timeout);
4677 /* If we found we can't enable hub-initiated LPM, and
4678 * the U1 or U2 exit latency was too high to allow
4679 * device-initiated LPM as well, then we will disable LPM
4680 * for this device, so stop searching any further.
4682 if (alt_timeout == USB3_LPM_DISABLED) {
4683 *timeout = alt_timeout;
4686 if (alt_timeout > *timeout)
4687 *timeout = alt_timeout;
4691 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4692 struct usb_device *udev,
4693 struct usb_host_interface *alt,
4694 enum usb3_link_state state,
4699 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4700 if (xhci_update_timeout_for_endpoint(xhci, udev,
4701 &alt->endpoint[j].desc, state, timeout))
4708 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4709 enum usb3_link_state state)
4711 struct usb_device *parent;
4712 unsigned int num_hubs;
4714 if (state == USB3_LPM_U2)
4717 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4718 for (parent = udev->parent, num_hubs = 0; parent->parent;
4719 parent = parent->parent)
4725 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4726 " below second-tier hub.\n");
4727 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4728 "to decrease power consumption.\n");
4732 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4733 struct usb_device *udev,
4734 enum usb3_link_state state)
4736 if (xhci->quirks & XHCI_INTEL_HOST)
4737 return xhci_check_intel_tier_policy(udev, state);
4742 /* Returns the U1 or U2 timeout that should be enabled.
4743 * If the tier check or timeout setting functions return with a non-zero exit
4744 * code, that means the timeout value has been finalized and we shouldn't look
4745 * at any more endpoints.
4747 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4748 struct usb_device *udev, enum usb3_link_state state)
4750 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4751 struct usb_host_config *config;
4754 u16 timeout = USB3_LPM_DISABLED;
4756 if (state == USB3_LPM_U1)
4758 else if (state == USB3_LPM_U2)
4761 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4766 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4769 /* Gather some information about the currently installed configuration
4770 * and alternate interface settings.
4772 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4776 config = udev->actconfig;
4780 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4781 struct usb_driver *driver;
4782 struct usb_interface *intf = config->interface[i];
4787 /* Check if any currently bound drivers want hub-initiated LPM
4790 if (intf->dev.driver) {
4791 driver = to_usb_driver(intf->dev.driver);
4792 if (driver && driver->disable_hub_initiated_lpm) {
4793 dev_dbg(&udev->dev, "Hub-initiated %s disabled at request of driver %s\n",
4794 state_name, driver->name);
4795 timeout = xhci_get_timeout_no_hub_lpm(udev,
4797 if (timeout == USB3_LPM_DISABLED)
4802 /* Not sure how this could happen... */
4803 if (!intf->cur_altsetting)
4806 if (xhci_update_timeout_for_interface(xhci, udev,
4807 intf->cur_altsetting,
4814 static int calculate_max_exit_latency(struct usb_device *udev,
4815 enum usb3_link_state state_changed,
4816 u16 hub_encoded_timeout)
4818 unsigned long long u1_mel_us = 0;
4819 unsigned long long u2_mel_us = 0;
4820 unsigned long long mel_us = 0;
4826 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4827 hub_encoded_timeout == USB3_LPM_DISABLED);
4828 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4829 hub_encoded_timeout == USB3_LPM_DISABLED);
4831 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4832 hub_encoded_timeout != USB3_LPM_DISABLED);
4833 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4834 hub_encoded_timeout != USB3_LPM_DISABLED);
4836 /* If U1 was already enabled and we're not disabling it,
4837 * or we're going to enable U1, account for the U1 max exit latency.
4839 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4841 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4842 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4844 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4846 if (u1_mel_us > u2_mel_us)
4850 /* xHCI host controller max exit latency field is only 16 bits wide. */
4851 if (mel_us > MAX_EXIT) {
4852 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4853 "is too big.\n", mel_us);
4859 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4860 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4861 struct usb_device *udev, enum usb3_link_state state)
4863 struct xhci_hcd *xhci;
4864 u16 hub_encoded_timeout;
4868 xhci = hcd_to_xhci(hcd);
4869 /* The LPM timeout values are pretty host-controller specific, so don't
4870 * enable hub-initiated timeouts unless the vendor has provided
4871 * information about their timeout algorithm.
4873 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4874 !xhci->devs[udev->slot_id])
4875 return USB3_LPM_DISABLED;
4877 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4878 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4880 /* Max Exit Latency is too big, disable LPM. */
4881 hub_encoded_timeout = USB3_LPM_DISABLED;
4885 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4888 return hub_encoded_timeout;
4891 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4892 struct usb_device *udev, enum usb3_link_state state)
4894 struct xhci_hcd *xhci;
4897 xhci = hcd_to_xhci(hcd);
4898 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4899 !xhci->devs[udev->slot_id])
4902 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4903 return xhci_change_max_exit_latency(xhci, udev, mel);
4905 #else /* CONFIG_PM */
4907 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4908 struct usb_device *udev, int enable)
4913 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4918 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4919 struct usb_device *udev, enum usb3_link_state state)
4921 return USB3_LPM_DISABLED;
4924 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4925 struct usb_device *udev, enum usb3_link_state state)
4929 #endif /* CONFIG_PM */
4931 /*-------------------------------------------------------------------------*/
4933 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4934 * internal data structures for the device.
4936 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4937 struct usb_tt *tt, gfp_t mem_flags)
4939 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4940 struct xhci_virt_device *vdev;
4941 struct xhci_command *config_cmd;
4942 struct xhci_input_control_ctx *ctrl_ctx;
4943 struct xhci_slot_ctx *slot_ctx;
4944 unsigned long flags;
4945 unsigned think_time;
4948 /* Ignore root hubs */
4952 vdev = xhci->devs[hdev->slot_id];
4954 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4958 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
4962 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4964 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4966 xhci_free_command(xhci, config_cmd);
4970 spin_lock_irqsave(&xhci->lock, flags);
4971 if (hdev->speed == USB_SPEED_HIGH &&
4972 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4973 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4974 xhci_free_command(xhci, config_cmd);
4975 spin_unlock_irqrestore(&xhci->lock, flags);
4979 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4980 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4981 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4982 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4984 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4985 * but it may be already set to 1 when setup an xHCI virtual
4986 * device, so clear it anyway.
4989 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4990 else if (hdev->speed == USB_SPEED_FULL)
4991 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4993 if (xhci->hci_version > 0x95) {
4994 xhci_dbg(xhci, "xHCI version %x needs hub "
4995 "TT think time and number of ports\n",
4996 (unsigned int) xhci->hci_version);
4997 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4998 /* Set TT think time - convert from ns to FS bit times.
4999 * 0 = 8 FS bit times, 1 = 16 FS bit times,
5000 * 2 = 24 FS bit times, 3 = 32 FS bit times.
5002 * xHCI 1.0: this field shall be 0 if the device is not a
5005 think_time = tt->think_time;
5006 if (think_time != 0)
5007 think_time = (think_time / 666) - 1;
5008 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
5009 slot_ctx->tt_info |=
5010 cpu_to_le32(TT_THINK_TIME(think_time));
5012 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
5013 "TT think time or number of ports\n",
5014 (unsigned int) xhci->hci_version);
5016 slot_ctx->dev_state = 0;
5017 spin_unlock_irqrestore(&xhci->lock, flags);
5019 xhci_dbg(xhci, "Set up %s for hub device.\n",
5020 (xhci->hci_version > 0x95) ?
5021 "configure endpoint" : "evaluate context");
5023 /* Issue and wait for the configure endpoint or
5024 * evaluate context command.
5026 if (xhci->hci_version > 0x95)
5027 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5030 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
5033 xhci_free_command(xhci, config_cmd);
5037 static int xhci_get_frame(struct usb_hcd *hcd)
5039 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
5040 /* EHCI mods by the periodic size. Why? */
5041 return readl(&xhci->run_regs->microframe_index) >> 3;
5044 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
5046 struct xhci_hcd *xhci;
5048 * TODO: Check with DWC3 clients for sysdev according to
5051 struct device *dev = hcd->self.sysdev;
5052 unsigned int minor_rev;
5055 /* Accept arbitrarily long scatter-gather lists */
5056 hcd->self.sg_tablesize = ~0;
5058 /* support to build packet from discontinuous buffers */
5059 hcd->self.no_sg_constraint = 1;
5061 /* XHCI controllers don't stop the ep queue on short packets :| */
5062 hcd->self.no_stop_on_short = 1;
5064 xhci = hcd_to_xhci(hcd);
5066 if (usb_hcd_is_primary_hcd(hcd)) {
5067 xhci->main_hcd = hcd;
5068 xhci->usb2_rhub.hcd = hcd;
5069 /* Mark the first roothub as being USB 2.0.
5070 * The xHCI driver will register the USB 3.0 roothub.
5072 hcd->speed = HCD_USB2;
5073 hcd->self.root_hub->speed = USB_SPEED_HIGH;
5075 * USB 2.0 roothub under xHCI has an integrated TT,
5076 * (rate matching hub) as opposed to having an OHCI/UHCI
5077 * companion controller.
5082 * Early xHCI 1.1 spec did not mention USB 3.1 capable hosts
5083 * should return 0x31 for sbrn, or that the minor revision
5084 * is a two digit BCD containig minor and sub-minor numbers.
5085 * This was later clarified in xHCI 1.2.
5087 * Some USB 3.1 capable hosts therefore have sbrn 0x30, and
5088 * minor revision set to 0x1 instead of 0x10.
5090 if (xhci->usb3_rhub.min_rev == 0x1)
5093 minor_rev = xhci->usb3_rhub.min_rev / 0x10;
5095 switch (minor_rev) {
5097 hcd->speed = HCD_USB32;
5098 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5099 hcd->self.root_hub->rx_lanes = 2;
5100 hcd->self.root_hub->tx_lanes = 2;
5103 hcd->speed = HCD_USB31;
5104 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5107 xhci_info(xhci, "Host supports USB 3.%x %sSuperSpeed\n",
5109 minor_rev ? "Enhanced " : "");
5111 xhci->usb3_rhub.hcd = hcd;
5112 /* xHCI private pointer was set in xhci_pci_probe for the second
5113 * registered roothub.
5118 mutex_init(&xhci->mutex);
5119 xhci->cap_regs = hcd->regs;
5120 xhci->op_regs = hcd->regs +
5121 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5122 xhci->run_regs = hcd->regs +
5123 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5124 /* Cache read-only capability registers */
5125 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5126 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5127 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5128 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5129 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5130 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5131 if (xhci->hci_version > 0x100)
5132 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5134 xhci->quirks |= quirks;
5136 get_quirks(dev, xhci);
5138 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5139 * success event after a short transfer. This quirk will ignore such
5142 if (xhci->hci_version > 0x96)
5143 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5145 /* Make sure the HC is halted. */
5146 retval = xhci_halt(xhci);
5150 xhci_zero_64b_regs(xhci);
5152 xhci_dbg(xhci, "Resetting HCD\n");
5153 /* Reset the internal HC memory state and registers. */
5154 retval = xhci_reset(xhci);
5157 xhci_dbg(xhci, "Reset complete\n");
5160 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5161 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5162 * address memory pointers actually. So, this driver clears the AC64
5163 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5164 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5166 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5167 xhci->hcc_params &= ~BIT(0);
5169 /* Set dma_mask and coherent_dma_mask to 64-bits,
5170 * if xHC supports 64-bit addressing */
5171 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5172 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5173 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5174 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5177 * This is to avoid error in cases where a 32-bit USB
5178 * controller is used on a 64-bit capable system.
5180 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5183 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5184 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5187 xhci_dbg(xhci, "Calling HCD init\n");
5188 /* Initialize HCD and host controller data structures. */
5189 retval = xhci_init(hcd);
5192 xhci_dbg(xhci, "Called HCD init\n");
5194 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5195 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5199 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5201 static void xhci_clear_tt_buffer_complete(struct usb_hcd *hcd,
5202 struct usb_host_endpoint *ep)
5204 struct xhci_hcd *xhci;
5205 struct usb_device *udev;
5206 unsigned int slot_id;
5207 unsigned int ep_index;
5208 unsigned long flags;
5210 xhci = hcd_to_xhci(hcd);
5211 udev = (struct usb_device *)ep->hcpriv;
5212 slot_id = udev->slot_id;
5213 ep_index = xhci_get_endpoint_index(&ep->desc);
5215 spin_lock_irqsave(&xhci->lock, flags);
5216 xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_CLEARING_TT;
5217 xhci_ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
5218 spin_unlock_irqrestore(&xhci->lock, flags);
5221 static const struct hc_driver xhci_hc_driver = {
5222 .description = "xhci-hcd",
5223 .product_desc = "xHCI Host Controller",
5224 .hcd_priv_size = sizeof(struct xhci_hcd),
5227 * generic hardware linkage
5230 .flags = HCD_MEMORY | HCD_DMA | HCD_USB3 | HCD_SHARED,
5233 * basic lifecycle operations
5235 .reset = NULL, /* set in xhci_init_driver() */
5238 .shutdown = xhci_shutdown,
5241 * managing i/o requests and associated device resources
5243 .map_urb_for_dma = xhci_map_urb_for_dma,
5244 .urb_enqueue = xhci_urb_enqueue,
5245 .urb_dequeue = xhci_urb_dequeue,
5246 .alloc_dev = xhci_alloc_dev,
5247 .free_dev = xhci_free_dev,
5248 .alloc_streams = xhci_alloc_streams,
5249 .free_streams = xhci_free_streams,
5250 .add_endpoint = xhci_add_endpoint,
5251 .drop_endpoint = xhci_drop_endpoint,
5252 .endpoint_reset = xhci_endpoint_reset,
5253 .check_bandwidth = xhci_check_bandwidth,
5254 .reset_bandwidth = xhci_reset_bandwidth,
5255 .address_device = xhci_address_device,
5256 .enable_device = xhci_enable_device,
5257 .update_hub_device = xhci_update_hub_device,
5258 .reset_device = xhci_discover_or_reset_device,
5261 * scheduling support
5263 .get_frame_number = xhci_get_frame,
5268 .hub_control = xhci_hub_control,
5269 .hub_status_data = xhci_hub_status_data,
5270 .bus_suspend = xhci_bus_suspend,
5271 .bus_resume = xhci_bus_resume,
5272 .get_resuming_ports = xhci_get_resuming_ports,
5275 * call back when device connected and addressed
5277 .update_device = xhci_update_device,
5278 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5279 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5280 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5281 .find_raw_port_number = xhci_find_raw_port_number,
5282 .clear_tt_buffer_complete = xhci_clear_tt_buffer_complete,
5285 void xhci_init_driver(struct hc_driver *drv,
5286 const struct xhci_driver_overrides *over)
5290 /* Copy the generic table to drv then apply the overrides */
5291 *drv = xhci_hc_driver;
5294 drv->hcd_priv_size += over->extra_priv_size;
5296 drv->reset = over->reset;
5298 drv->start = over->start;
5301 EXPORT_SYMBOL_GPL(xhci_init_driver);
5303 MODULE_DESCRIPTION(DRIVER_DESC);
5304 MODULE_AUTHOR(DRIVER_AUTHOR);
5305 MODULE_LICENSE("GPL");
5307 static int __init xhci_hcd_init(void)
5310 * Check the compiler generated sizes of structures that must be laid
5311 * out in specific ways for hardware access.
5313 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5314 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5315 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5316 /* xhci_device_control has eight fields, and also
5317 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5319 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5320 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5321 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5322 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5323 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5324 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5325 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5330 xhci_debugfs_create_root();
5336 * If an init function is provided, an exit function must also be provided
5337 * to allow module unload.
5339 static void __exit xhci_hcd_fini(void)
5341 xhci_debugfs_remove_root();
5344 module_init(xhci_hcd_init);
5345 module_exit(xhci_hcd_fini);