1 // SPDX-License-Identifier: GPL-2.0
3 * xHCI host controller driver
5 * Copyright (C) 2008 Intel Corp.
8 * Some code borrowed from the Linux EHCI driver.
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/log2.h>
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/slab.h>
17 #include <linux/dmi.h>
18 #include <linux/dma-mapping.h>
21 #include "xhci-trace.h"
23 #include "xhci-debugfs.h"
24 #include "xhci-dbgcap.h"
26 #define DRIVER_AUTHOR "Sarah Sharp"
27 #define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
29 #define PORT_WAKE_BITS (PORT_WKOC_E | PORT_WKDISC_E | PORT_WKCONN_E)
31 /* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
32 static int link_quirk;
33 module_param(link_quirk, int, S_IRUGO | S_IWUSR);
34 MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
36 static unsigned long long quirks;
37 module_param(quirks, ullong, S_IRUGO);
38 MODULE_PARM_DESC(quirks, "Bit flags for quirks to be enabled as default");
40 static bool td_on_ring(struct xhci_td *td, struct xhci_ring *ring)
42 struct xhci_segment *seg = ring->first_seg;
44 if (!td || !td->start_seg)
47 if (seg == td->start_seg)
50 } while (seg && seg != ring->first_seg);
55 /* TODO: copied from ehci-hcd.c - can this be refactored? */
57 * xhci_handshake - spin reading hc until handshake completes or fails
58 * @ptr: address of hc register to be read
59 * @mask: bits to look at in result of read
60 * @done: value of those bits when handshake succeeds
61 * @usec: timeout in microseconds
63 * Returns negative errno, or zero on success
65 * Success happens when the "mask" bits have the specified value (hardware
66 * handshake done). There are two failure modes: "usec" have passed (major
67 * hardware flakeout), or the register reads as all-ones (hardware removed).
69 int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec)
75 if (result == ~(u32)0) /* card removed */
87 * Disable interrupts and begin the xHCI halting process.
89 void xhci_quiesce(struct xhci_hcd *xhci)
96 halted = readl(&xhci->op_regs->status) & STS_HALT;
100 cmd = readl(&xhci->op_regs->command);
102 writel(cmd, &xhci->op_regs->command);
106 * Force HC into halt state.
108 * Disable any IRQs and clear the run/stop bit.
109 * HC will complete any current and actively pipelined transactions, and
110 * should halt within 16 ms of the run/stop bit being cleared.
111 * Read HC Halted bit in the status register to see when the HC is finished.
113 int xhci_halt(struct xhci_hcd *xhci)
116 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Halt the HC");
119 ret = xhci_handshake(&xhci->op_regs->status,
120 STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
122 xhci_warn(xhci, "Host halt failed, %d\n", ret);
125 xhci->xhc_state |= XHCI_STATE_HALTED;
126 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
131 * Set the run bit and wait for the host to be running.
133 int xhci_start(struct xhci_hcd *xhci)
138 temp = readl(&xhci->op_regs->command);
140 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Turn on HC, cmd = 0x%x.",
142 writel(temp, &xhci->op_regs->command);
145 * Wait for the HCHalted Status bit to be 0 to indicate the host is
148 ret = xhci_handshake(&xhci->op_regs->status,
149 STS_HALT, 0, XHCI_MAX_HALT_USEC);
150 if (ret == -ETIMEDOUT)
151 xhci_err(xhci, "Host took too long to start, "
152 "waited %u microseconds.\n",
155 /* clear state flags. Including dying, halted or removing */
164 * This resets pipelines, timers, counters, state machines, etc.
165 * Transactions will be terminated immediately, and operational registers
166 * will be set to their defaults.
168 int xhci_reset(struct xhci_hcd *xhci)
174 state = readl(&xhci->op_regs->status);
176 if (state == ~(u32)0) {
177 xhci_warn(xhci, "Host not accessible, reset failed.\n");
181 if ((state & STS_HALT) == 0) {
182 xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
186 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "// Reset the HC");
187 command = readl(&xhci->op_regs->command);
188 command |= CMD_RESET;
189 writel(command, &xhci->op_regs->command);
191 /* Existing Intel xHCI controllers require a delay of 1 mS,
192 * after setting the CMD_RESET bit, and before accessing any
193 * HC registers. This allows the HC to complete the
194 * reset operation and be ready for HC register access.
195 * Without this delay, the subsequent HC register access,
196 * may result in a system hang very rarely.
198 if (xhci->quirks & XHCI_INTEL_HOST)
201 ret = xhci_handshake(&xhci->op_regs->command,
202 CMD_RESET, 0, 10 * 1000 * 1000);
206 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
207 usb_asmedia_modifyflowcontrol(to_pci_dev(xhci_to_hcd(xhci)->self.controller));
209 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
210 "Wait for controller to be ready for doorbell rings");
212 * xHCI cannot write to any doorbells or operational registers other
213 * than status until the "Controller Not Ready" flag is cleared.
215 ret = xhci_handshake(&xhci->op_regs->status,
216 STS_CNR, 0, 10 * 1000 * 1000);
218 for (i = 0; i < 2; i++) {
219 xhci->bus_state[i].port_c_suspend = 0;
220 xhci->bus_state[i].suspended_ports = 0;
221 xhci->bus_state[i].resuming_ports = 0;
227 static void xhci_zero_64b_regs(struct xhci_hcd *xhci)
229 struct device *dev = xhci_to_hcd(xhci)->self.sysdev;
234 * Some Renesas controllers get into a weird state if they are
235 * reset while programmed with 64bit addresses (they will preserve
236 * the top half of the address in internal, non visible
237 * registers). You end up with half the address coming from the
238 * kernel, and the other half coming from the firmware. Also,
239 * changing the programming leads to extra accesses even if the
240 * controller is supposed to be halted. The controller ends up with
241 * a fatal fault, and is then ripe for being properly reset.
243 * Special care is taken to only apply this if the device is behind
244 * an iommu. Doing anything when there is no iommu is definitely
247 if (!(xhci->quirks & XHCI_ZERO_64B_REGS) || !dev->iommu_group)
250 xhci_info(xhci, "Zeroing 64bit base registers, expecting fault\n");
252 /* Clear HSEIE so that faults do not get signaled */
253 val = readl(&xhci->op_regs->command);
255 writel(val, &xhci->op_regs->command);
257 /* Clear HSE (aka FATAL) */
258 val = readl(&xhci->op_regs->status);
260 writel(val, &xhci->op_regs->status);
262 /* Now zero the registers, and brace for impact */
263 val = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
264 if (upper_32_bits(val))
265 xhci_write_64(xhci, 0, &xhci->op_regs->dcbaa_ptr);
266 val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
267 if (upper_32_bits(val))
268 xhci_write_64(xhci, 0, &xhci->op_regs->cmd_ring);
270 for (i = 0; i < HCS_MAX_INTRS(xhci->hcs_params1); i++) {
271 struct xhci_intr_reg __iomem *ir;
273 ir = &xhci->run_regs->ir_set[i];
274 val = xhci_read_64(xhci, &ir->erst_base);
275 if (upper_32_bits(val))
276 xhci_write_64(xhci, 0, &ir->erst_base);
277 val= xhci_read_64(xhci, &ir->erst_dequeue);
278 if (upper_32_bits(val))
279 xhci_write_64(xhci, 0, &ir->erst_dequeue);
282 /* Wait for the fault to appear. It will be cleared on reset */
283 err = xhci_handshake(&xhci->op_regs->status,
284 STS_FATAL, STS_FATAL,
287 xhci_info(xhci, "Fault detected\n");
290 #ifdef CONFIG_USB_PCI
294 static int xhci_setup_msi(struct xhci_hcd *xhci)
298 * TODO:Check with MSI Soc for sysdev
300 struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
302 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
304 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
305 "failed to allocate MSI entry");
309 ret = request_irq(pdev->irq, xhci_msi_irq,
310 0, "xhci_hcd", xhci_to_hcd(xhci));
312 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
313 "disable MSI interrupt");
314 pci_free_irq_vectors(pdev);
323 static int xhci_setup_msix(struct xhci_hcd *xhci)
326 struct usb_hcd *hcd = xhci_to_hcd(xhci);
327 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
330 * calculate number of msi-x vectors supported.
331 * - HCS_MAX_INTRS: the max number of interrupts the host can handle,
332 * with max number of interrupters based on the xhci HCSPARAMS1.
333 * - num_online_cpus: maximum msi-x vectors per CPUs core.
334 * Add additional 1 vector to ensure always available interrupt.
336 xhci->msix_count = min(num_online_cpus() + 1,
337 HCS_MAX_INTRS(xhci->hcs_params1));
339 ret = pci_alloc_irq_vectors(pdev, xhci->msix_count, xhci->msix_count,
342 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
343 "Failed to enable MSI-X");
347 for (i = 0; i < xhci->msix_count; i++) {
348 ret = request_irq(pci_irq_vector(pdev, i), xhci_msi_irq, 0,
349 "xhci_hcd", xhci_to_hcd(xhci));
354 hcd->msix_enabled = 1;
358 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "disable MSI-X interrupt");
360 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
361 pci_free_irq_vectors(pdev);
365 /* Free any IRQs and disable MSI-X */
366 static void xhci_cleanup_msix(struct xhci_hcd *xhci)
368 struct usb_hcd *hcd = xhci_to_hcd(xhci);
369 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
371 if (xhci->quirks & XHCI_PLAT)
374 /* return if using legacy interrupt */
378 if (hcd->msix_enabled) {
381 for (i = 0; i < xhci->msix_count; i++)
382 free_irq(pci_irq_vector(pdev, i), xhci_to_hcd(xhci));
384 free_irq(pci_irq_vector(pdev, 0), xhci_to_hcd(xhci));
387 pci_free_irq_vectors(pdev);
388 hcd->msix_enabled = 0;
391 static void __maybe_unused xhci_msix_sync_irqs(struct xhci_hcd *xhci)
393 struct usb_hcd *hcd = xhci_to_hcd(xhci);
395 if (hcd->msix_enabled) {
396 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
399 for (i = 0; i < xhci->msix_count; i++)
400 synchronize_irq(pci_irq_vector(pdev, i));
404 static int xhci_try_enable_msi(struct usb_hcd *hcd)
406 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
407 struct pci_dev *pdev;
410 /* The xhci platform device has set up IRQs through usb_add_hcd. */
411 if (xhci->quirks & XHCI_PLAT)
414 pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
416 * Some Fresco Logic host controllers advertise MSI, but fail to
417 * generate interrupts. Don't even try to enable MSI.
419 if (xhci->quirks & XHCI_BROKEN_MSI)
422 /* unregister the legacy interrupt */
424 free_irq(hcd->irq, hcd);
427 ret = xhci_setup_msix(xhci);
429 /* fall back to msi*/
430 ret = xhci_setup_msi(xhci);
433 hcd->msi_enabled = 1;
438 xhci_err(xhci, "No msi-x/msi found and no IRQ in BIOS\n");
443 if (!strlen(hcd->irq_descr))
444 snprintf(hcd->irq_descr, sizeof(hcd->irq_descr), "%s:usb%d",
445 hcd->driver->description, hcd->self.busnum);
447 /* fall back to legacy interrupt*/
448 ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
449 hcd->irq_descr, hcd);
451 xhci_err(xhci, "request interrupt %d failed\n",
455 hcd->irq = pdev->irq;
461 static inline int xhci_try_enable_msi(struct usb_hcd *hcd)
466 static inline void xhci_cleanup_msix(struct xhci_hcd *xhci)
470 static inline void xhci_msix_sync_irqs(struct xhci_hcd *xhci)
476 static void compliance_mode_recovery(struct timer_list *t)
478 struct xhci_hcd *xhci;
480 struct xhci_hub *rhub;
484 xhci = from_timer(xhci, t, comp_mode_recovery_timer);
485 rhub = &xhci->usb3_rhub;
487 for (i = 0; i < rhub->num_ports; i++) {
488 temp = readl(rhub->ports[i]->addr);
489 if ((temp & PORT_PLS_MASK) == USB_SS_PORT_LS_COMP_MOD) {
491 * Compliance Mode Detected. Letting USB Core
492 * handle the Warm Reset
494 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
495 "Compliance mode detected->port %d",
497 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
498 "Attempting compliance mode recovery");
499 hcd = xhci->shared_hcd;
501 if (hcd->state == HC_STATE_SUSPENDED)
502 usb_hcd_resume_root_hub(hcd);
504 usb_hcd_poll_rh_status(hcd);
508 if (xhci->port_status_u0 != ((1 << rhub->num_ports) - 1))
509 mod_timer(&xhci->comp_mode_recovery_timer,
510 jiffies + msecs_to_jiffies(COMP_MODE_RCVRY_MSECS));
514 * Quirk to work around issue generated by the SN65LVPE502CP USB3.0 re-driver
515 * that causes ports behind that hardware to enter compliance mode sometimes.
516 * The quirk creates a timer that polls every 2 seconds the link state of
517 * each host controller's port and recovers it by issuing a Warm reset
518 * if Compliance mode is detected, otherwise the port will become "dead" (no
519 * device connections or disconnections will be detected anymore). Becasue no
520 * status event is generated when entering compliance mode (per xhci spec),
521 * this quirk is needed on systems that have the failing hardware installed.
523 static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
525 xhci->port_status_u0 = 0;
526 timer_setup(&xhci->comp_mode_recovery_timer, compliance_mode_recovery,
528 xhci->comp_mode_recovery_timer.expires = jiffies +
529 msecs_to_jiffies(COMP_MODE_RCVRY_MSECS);
531 add_timer(&xhci->comp_mode_recovery_timer);
532 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
533 "Compliance mode recovery timer initialized");
537 * This function identifies the systems that have installed the SN65LVPE502CP
538 * USB3.0 re-driver and that need the Compliance Mode Quirk.
540 * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
542 static bool xhci_compliance_mode_recovery_timer_quirk_check(void)
544 const char *dmi_product_name, *dmi_sys_vendor;
546 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
547 dmi_sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
548 if (!dmi_product_name || !dmi_sys_vendor)
551 if (!(strstr(dmi_sys_vendor, "Hewlett-Packard")))
554 if (strstr(dmi_product_name, "Z420") ||
555 strstr(dmi_product_name, "Z620") ||
556 strstr(dmi_product_name, "Z820") ||
557 strstr(dmi_product_name, "Z1 Workstation"))
563 static int xhci_all_ports_seen_u0(struct xhci_hcd *xhci)
565 return (xhci->port_status_u0 == ((1 << xhci->usb3_rhub.num_ports) - 1));
570 * Initialize memory for HCD and xHC (one-time init).
572 * Program the PAGESIZE register, initialize the device context array, create
573 * device contexts (?), set up a command ring segment (or two?), create event
574 * ring (one for now).
576 static int xhci_init(struct usb_hcd *hcd)
578 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
581 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_init");
582 spin_lock_init(&xhci->lock);
583 if (xhci->hci_version == 0x95 && link_quirk) {
584 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
585 "QUIRK: Not clearing Link TRB chain bits.");
586 xhci->quirks |= XHCI_LINK_TRB_QUIRK;
588 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
589 "xHCI doesn't need link TRB QUIRK");
591 retval = xhci_mem_init(xhci, GFP_KERNEL);
592 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "Finished xhci_init");
594 /* Initializing Compliance Mode Recovery Data If Needed */
595 if (xhci_compliance_mode_recovery_timer_quirk_check()) {
596 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
597 compliance_mode_recovery_timer_init(xhci);
603 /*-------------------------------------------------------------------------*/
606 static int xhci_run_finished(struct xhci_hcd *xhci)
608 if (xhci_start(xhci)) {
612 xhci->shared_hcd->state = HC_STATE_RUNNING;
613 xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
615 if (xhci->quirks & XHCI_NEC_HOST)
616 xhci_ring_cmd_db(xhci);
618 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
619 "Finished xhci_run for USB3 roothub");
624 * Start the HC after it was halted.
626 * This function is called by the USB core when the HC driver is added.
627 * Its opposite is xhci_stop().
629 * xhci_init() must be called once before this function can be called.
630 * Reset the HC, enable device slot contexts, program DCBAAP, and
631 * set command ring pointer and event ring pointer.
633 * Setup MSI-X vectors and enable interrupts.
635 int xhci_run(struct usb_hcd *hcd)
640 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
642 /* Start the xHCI host controller running only after the USB 2.0 roothub
646 hcd->uses_new_polling = 1;
647 if (!usb_hcd_is_primary_hcd(hcd))
648 return xhci_run_finished(xhci);
650 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "xhci_run");
652 ret = xhci_try_enable_msi(hcd);
656 temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
657 temp_64 &= ~ERST_PTR_MASK;
658 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
659 "ERST deq = 64'h%0lx", (long unsigned int) temp_64);
661 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
662 "// Set the interrupt modulation register");
663 temp = readl(&xhci->ir_set->irq_control);
664 temp &= ~ER_IRQ_INTERVAL_MASK;
665 temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
666 writel(temp, &xhci->ir_set->irq_control);
668 /* Set the HCD state before we enable the irqs */
669 temp = readl(&xhci->op_regs->command);
671 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
672 "// Enable interrupts, cmd = 0x%x.", temp);
673 writel(temp, &xhci->op_regs->command);
675 temp = readl(&xhci->ir_set->irq_pending);
676 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
677 "// Enabling event ring interrupter %p by writing 0x%x to irq_pending",
678 xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
679 writel(ER_IRQ_ENABLE(temp), &xhci->ir_set->irq_pending);
681 if (xhci->quirks & XHCI_NEC_HOST) {
682 struct xhci_command *command;
684 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
688 ret = xhci_queue_vendor_command(xhci, command, 0, 0, 0,
689 TRB_TYPE(TRB_NEC_GET_FW));
691 xhci_free_command(xhci, command);
693 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
694 "Finished xhci_run for USB2 roothub");
698 xhci_debugfs_init(xhci);
702 EXPORT_SYMBOL_GPL(xhci_run);
707 * This function is called by the USB core when the HC driver is removed.
708 * Its opposite is xhci_run().
710 * Disable device contexts, disable IRQs, and quiesce the HC.
711 * Reset the HC, finish any completed transactions, and cleanup memory.
713 static void xhci_stop(struct usb_hcd *hcd)
716 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
718 mutex_lock(&xhci->mutex);
720 /* Only halt host and free memory after both hcds are removed */
721 if (!usb_hcd_is_primary_hcd(hcd)) {
722 mutex_unlock(&xhci->mutex);
728 spin_lock_irq(&xhci->lock);
729 xhci->xhc_state |= XHCI_STATE_HALTED;
730 xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
733 spin_unlock_irq(&xhci->lock);
735 xhci_cleanup_msix(xhci);
737 /* Deleting Compliance Mode Recovery Timer */
738 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
739 (!(xhci_all_ports_seen_u0(xhci)))) {
740 del_timer_sync(&xhci->comp_mode_recovery_timer);
741 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
742 "%s: compliance mode recovery timer deleted",
746 if (xhci->quirks & XHCI_AMD_PLL_FIX)
749 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
750 "// Disabling event ring interrupts");
751 temp = readl(&xhci->op_regs->status);
752 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
753 temp = readl(&xhci->ir_set->irq_pending);
754 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
756 xhci_dbg_trace(xhci, trace_xhci_dbg_init, "cleaning up memory");
757 xhci_mem_cleanup(xhci);
758 xhci_debugfs_exit(xhci);
759 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
760 "xhci_stop completed - status = %x",
761 readl(&xhci->op_regs->status));
762 mutex_unlock(&xhci->mutex);
766 * Shutdown HC (not bus-specific)
768 * This is called when the machine is rebooting or halting. We assume that the
769 * machine will be powered off, and the HC's internal state will be reset.
770 * Don't bother to free memory.
772 * This will only ever be called with the main usb_hcd (the USB3 roothub).
774 static void xhci_shutdown(struct usb_hcd *hcd)
776 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
778 if (xhci->quirks & XHCI_SPURIOUS_REBOOT)
779 usb_disable_xhci_ports(to_pci_dev(hcd->self.sysdev));
781 spin_lock_irq(&xhci->lock);
783 /* Workaround for spurious wakeups at shutdown with HSW */
784 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
786 spin_unlock_irq(&xhci->lock);
788 xhci_cleanup_msix(xhci);
790 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
791 "xhci_shutdown completed - status = %x",
792 readl(&xhci->op_regs->status));
794 /* Yet another workaround for spurious wakeups at shutdown with HSW */
795 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
796 pci_set_power_state(to_pci_dev(hcd->self.sysdev), PCI_D3hot);
800 static void xhci_save_registers(struct xhci_hcd *xhci)
802 xhci->s3.command = readl(&xhci->op_regs->command);
803 xhci->s3.dev_nt = readl(&xhci->op_regs->dev_notification);
804 xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
805 xhci->s3.config_reg = readl(&xhci->op_regs->config_reg);
806 xhci->s3.erst_size = readl(&xhci->ir_set->erst_size);
807 xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
808 xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
809 xhci->s3.irq_pending = readl(&xhci->ir_set->irq_pending);
810 xhci->s3.irq_control = readl(&xhci->ir_set->irq_control);
813 static void xhci_restore_registers(struct xhci_hcd *xhci)
815 writel(xhci->s3.command, &xhci->op_regs->command);
816 writel(xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
817 xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
818 writel(xhci->s3.config_reg, &xhci->op_regs->config_reg);
819 writel(xhci->s3.erst_size, &xhci->ir_set->erst_size);
820 xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
821 xhci_write_64(xhci, xhci->s3.erst_dequeue, &xhci->ir_set->erst_dequeue);
822 writel(xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
823 writel(xhci->s3.irq_control, &xhci->ir_set->irq_control);
826 static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
830 /* step 2: initialize command ring buffer */
831 val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
832 val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
833 (xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
834 xhci->cmd_ring->dequeue) &
835 (u64) ~CMD_RING_RSVD_BITS) |
836 xhci->cmd_ring->cycle_state;
837 xhci_dbg_trace(xhci, trace_xhci_dbg_init,
838 "// Setting command ring address to 0x%llx",
839 (long unsigned long) val_64);
840 xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
844 * The whole command ring must be cleared to zero when we suspend the host.
846 * The host doesn't save the command ring pointer in the suspend well, so we
847 * need to re-program it on resume. Unfortunately, the pointer must be 64-byte
848 * aligned, because of the reserved bits in the command ring dequeue pointer
849 * register. Therefore, we can't just set the dequeue pointer back in the
850 * middle of the ring (TRBs are 16-byte aligned).
852 static void xhci_clear_command_ring(struct xhci_hcd *xhci)
854 struct xhci_ring *ring;
855 struct xhci_segment *seg;
857 ring = xhci->cmd_ring;
861 sizeof(union xhci_trb) * (TRBS_PER_SEGMENT - 1));
862 seg->trbs[TRBS_PER_SEGMENT - 1].link.control &=
863 cpu_to_le32(~TRB_CYCLE);
865 } while (seg != ring->deq_seg);
867 /* Reset the software enqueue and dequeue pointers */
868 ring->deq_seg = ring->first_seg;
869 ring->dequeue = ring->first_seg->trbs;
870 ring->enq_seg = ring->deq_seg;
871 ring->enqueue = ring->dequeue;
873 ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
875 * Ring is now zeroed, so the HW should look for change of ownership
876 * when the cycle bit is set to 1.
878 ring->cycle_state = 1;
881 * Reset the hardware dequeue pointer.
882 * Yes, this will need to be re-written after resume, but we're paranoid
883 * and want to make sure the hardware doesn't access bogus memory
884 * because, say, the BIOS or an SMI started the host without changing
885 * the command ring pointers.
887 xhci_set_cmd_ring_deq(xhci);
890 static void xhci_disable_port_wake_on_bits(struct xhci_hcd *xhci)
892 struct xhci_port **ports;
897 spin_lock_irqsave(&xhci->lock, flags);
899 /* disable usb3 ports Wake bits */
900 port_index = xhci->usb3_rhub.num_ports;
901 ports = xhci->usb3_rhub.ports;
902 while (port_index--) {
903 t1 = readl(ports[port_index]->addr);
904 t1 = xhci_port_state_to_neutral(t1);
905 t2 = t1 & ~PORT_WAKE_BITS;
907 writel(t2, ports[port_index]->addr);
910 /* disable usb2 ports Wake bits */
911 port_index = xhci->usb2_rhub.num_ports;
912 ports = xhci->usb2_rhub.ports;
913 while (port_index--) {
914 t1 = readl(ports[port_index]->addr);
915 t1 = xhci_port_state_to_neutral(t1);
916 t2 = t1 & ~PORT_WAKE_BITS;
918 writel(t2, ports[port_index]->addr);
921 spin_unlock_irqrestore(&xhci->lock, flags);
924 static bool xhci_pending_portevent(struct xhci_hcd *xhci)
926 struct xhci_port **ports;
931 status = readl(&xhci->op_regs->status);
932 if (status & STS_EINT)
935 * Checking STS_EINT is not enough as there is a lag between a change
936 * bit being set and the Port Status Change Event that it generated
937 * being written to the Event Ring. See note in xhci 1.1 section 4.19.2.
940 port_index = xhci->usb2_rhub.num_ports;
941 ports = xhci->usb2_rhub.ports;
942 while (port_index--) {
943 portsc = readl(ports[port_index]->addr);
944 if (portsc & PORT_CHANGE_MASK ||
945 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
948 port_index = xhci->usb3_rhub.num_ports;
949 ports = xhci->usb3_rhub.ports;
950 while (port_index--) {
951 portsc = readl(ports[port_index]->addr);
952 if (portsc & PORT_CHANGE_MASK ||
953 (portsc & PORT_PLS_MASK) == XDEV_RESUME)
960 * Stop HC (not bus-specific)
962 * This is called when the machine transition into S3/S4 mode.
965 int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup)
968 unsigned int delay = XHCI_MAX_HALT_USEC;
969 struct usb_hcd *hcd = xhci_to_hcd(xhci);
975 if (hcd->state != HC_STATE_SUSPENDED ||
976 xhci->shared_hcd->state != HC_STATE_SUSPENDED)
979 xhci_dbc_suspend(xhci);
981 /* Clear root port wake on bits if wakeup not allowed. */
983 xhci_disable_port_wake_on_bits(xhci);
985 /* Don't poll the roothubs on bus suspend. */
986 xhci_dbg(xhci, "%s: stopping port polling.\n", __func__);
987 clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
988 del_timer_sync(&hcd->rh_timer);
989 clear_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
990 del_timer_sync(&xhci->shared_hcd->rh_timer);
992 if (xhci->quirks & XHCI_SUSPEND_DELAY)
993 usleep_range(1000, 1500);
995 spin_lock_irq(&xhci->lock);
996 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
997 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
998 /* step 1: stop endpoint */
999 /* skipped assuming that port suspend has done */
1001 /* step 2: clear Run/Stop bit */
1002 command = readl(&xhci->op_regs->command);
1003 command &= ~CMD_RUN;
1004 writel(command, &xhci->op_regs->command);
1006 /* Some chips from Fresco Logic need an extraordinary delay */
1007 delay *= (xhci->quirks & XHCI_SLOW_SUSPEND) ? 10 : 1;
1009 if (xhci_handshake(&xhci->op_regs->status,
1010 STS_HALT, STS_HALT, delay)) {
1011 xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
1012 spin_unlock_irq(&xhci->lock);
1015 xhci_clear_command_ring(xhci);
1017 /* step 3: save registers */
1018 xhci_save_registers(xhci);
1020 /* step 4: set CSS flag */
1021 command = readl(&xhci->op_regs->command);
1023 writel(command, &xhci->op_regs->command);
1024 if (xhci_handshake(&xhci->op_regs->status,
1025 STS_SAVE, 0, 10 * 1000)) {
1026 xhci_warn(xhci, "WARN: xHC save state timeout\n");
1027 spin_unlock_irq(&xhci->lock);
1030 spin_unlock_irq(&xhci->lock);
1033 * Deleting Compliance Mode Recovery Timer because the xHCI Host
1034 * is about to be suspended.
1036 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1037 (!(xhci_all_ports_seen_u0(xhci)))) {
1038 del_timer_sync(&xhci->comp_mode_recovery_timer);
1039 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1040 "%s: compliance mode recovery timer deleted",
1044 /* step 5: remove core well power */
1045 /* synchronize irq when using MSI-X */
1046 xhci_msix_sync_irqs(xhci);
1050 EXPORT_SYMBOL_GPL(xhci_suspend);
1053 * start xHC (not bus-specific)
1055 * This is called when the machine transition from S3/S4 mode.
1058 int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
1060 u32 command, temp = 0;
1061 struct usb_hcd *hcd = xhci_to_hcd(xhci);
1062 struct usb_hcd *secondary_hcd;
1064 bool comp_timer_running = false;
1069 /* Wait a bit if either of the roothubs need to settle from the
1070 * transition into bus suspend.
1072 if (time_before(jiffies, xhci->bus_state[0].next_statechange) ||
1073 time_before(jiffies,
1074 xhci->bus_state[1].next_statechange))
1077 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1078 set_bit(HCD_FLAG_HW_ACCESSIBLE, &xhci->shared_hcd->flags);
1080 spin_lock_irq(&xhci->lock);
1081 if (xhci->quirks & XHCI_RESET_ON_RESUME)
1085 /* step 1: restore register */
1086 xhci_restore_registers(xhci);
1087 /* step 2: initialize command ring buffer */
1088 xhci_set_cmd_ring_deq(xhci);
1089 /* step 3: restore state and start state*/
1090 /* step 3: set CRS flag */
1091 command = readl(&xhci->op_regs->command);
1093 writel(command, &xhci->op_regs->command);
1095 * Some controllers take up to 55+ ms to complete the controller
1096 * restore so setting the timeout to 100ms. Xhci specification
1097 * doesn't mention any timeout value.
1099 if (xhci_handshake(&xhci->op_regs->status,
1100 STS_RESTORE, 0, 100 * 1000)) {
1101 xhci_warn(xhci, "WARN: xHC restore state timeout\n");
1102 spin_unlock_irq(&xhci->lock);
1105 temp = readl(&xhci->op_regs->status);
1108 /* If restore operation fails, re-initialize the HC during resume */
1109 if ((temp & STS_SRE) || hibernated) {
1111 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
1112 !(xhci_all_ports_seen_u0(xhci))) {
1113 del_timer_sync(&xhci->comp_mode_recovery_timer);
1114 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
1115 "Compliance Mode Recovery Timer deleted!");
1118 /* Let the USB core know _both_ roothubs lost power. */
1119 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
1120 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
1122 xhci_dbg(xhci, "Stop HCD\n");
1124 xhci_zero_64b_regs(xhci);
1126 spin_unlock_irq(&xhci->lock);
1127 xhci_cleanup_msix(xhci);
1129 xhci_dbg(xhci, "// Disabling event ring interrupts\n");
1130 temp = readl(&xhci->op_regs->status);
1131 writel((temp & ~0x1fff) | STS_EINT, &xhci->op_regs->status);
1132 temp = readl(&xhci->ir_set->irq_pending);
1133 writel(ER_IRQ_DISABLE(temp), &xhci->ir_set->irq_pending);
1135 xhci_dbg(xhci, "cleaning up memory\n");
1136 xhci_mem_cleanup(xhci);
1137 xhci_debugfs_exit(xhci);
1138 xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
1139 readl(&xhci->op_regs->status));
1141 /* USB core calls the PCI reinit and start functions twice:
1142 * first with the primary HCD, and then with the secondary HCD.
1143 * If we don't do the same, the host will never be started.
1145 if (!usb_hcd_is_primary_hcd(hcd))
1146 secondary_hcd = hcd;
1148 secondary_hcd = xhci->shared_hcd;
1150 xhci_dbg(xhci, "Initialize the xhci_hcd\n");
1151 retval = xhci_init(hcd->primary_hcd);
1154 comp_timer_running = true;
1156 xhci_dbg(xhci, "Start the primary HCD\n");
1157 retval = xhci_run(hcd->primary_hcd);
1159 xhci_dbg(xhci, "Start the secondary HCD\n");
1160 retval = xhci_run(secondary_hcd);
1162 hcd->state = HC_STATE_SUSPENDED;
1163 xhci->shared_hcd->state = HC_STATE_SUSPENDED;
1167 /* step 4: set Run/Stop bit */
1168 command = readl(&xhci->op_regs->command);
1170 writel(command, &xhci->op_regs->command);
1171 xhci_handshake(&xhci->op_regs->status, STS_HALT,
1174 /* step 5: walk topology and initialize portsc,
1175 * portpmsc and portli
1177 /* this is done in bus_resume */
1179 /* step 6: restart each of the previously
1180 * Running endpoints by ringing their doorbells
1183 spin_unlock_irq(&xhci->lock);
1185 xhci_dbc_resume(xhci);
1189 /* Resume root hubs only when have pending events. */
1190 if (xhci_pending_portevent(xhci)) {
1191 usb_hcd_resume_root_hub(xhci->shared_hcd);
1192 usb_hcd_resume_root_hub(hcd);
1197 * If system is subject to the Quirk, Compliance Mode Timer needs to
1198 * be re-initialized Always after a system resume. Ports are subject
1199 * to suffer the Compliance Mode issue again. It doesn't matter if
1200 * ports have entered previously to U0 before system's suspension.
1202 if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
1203 compliance_mode_recovery_timer_init(xhci);
1205 if (xhci->quirks & XHCI_ASMEDIA_MODIFY_FLOWCONTROL)
1206 usb_asmedia_modifyflowcontrol(to_pci_dev(hcd->self.controller));
1208 /* Re-enable port polling. */
1209 xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1210 set_bit(HCD_FLAG_POLL_RH, &xhci->shared_hcd->flags);
1211 usb_hcd_poll_rh_status(xhci->shared_hcd);
1212 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1213 usb_hcd_poll_rh_status(hcd);
1217 EXPORT_SYMBOL_GPL(xhci_resume);
1218 #endif /* CONFIG_PM */
1220 /*-------------------------------------------------------------------------*/
1223 * xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
1224 * HCDs. Find the index for an endpoint given its descriptor. Use the return
1225 * value to right shift 1 for the bitmask.
1227 * Index = (epnum * 2) + direction - 1,
1228 * where direction = 0 for OUT, 1 for IN.
1229 * For control endpoints, the IN index is used (OUT index is unused), so
1230 * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
1232 unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
1235 if (usb_endpoint_xfer_control(desc))
1236 index = (unsigned int) (usb_endpoint_num(desc)*2);
1238 index = (unsigned int) (usb_endpoint_num(desc)*2) +
1239 (usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
1243 /* The reverse operation to xhci_get_endpoint_index. Calculate the USB endpoint
1244 * address from the XHCI endpoint index.
1246 unsigned int xhci_get_endpoint_address(unsigned int ep_index)
1248 unsigned int number = DIV_ROUND_UP(ep_index, 2);
1249 unsigned int direction = ep_index % 2 ? USB_DIR_OUT : USB_DIR_IN;
1250 return direction | number;
1253 /* Find the flag for this endpoint (for use in the control context). Use the
1254 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1257 static unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
1259 return 1 << (xhci_get_endpoint_index(desc) + 1);
1262 /* Find the flag for this endpoint (for use in the control context). Use the
1263 * endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
1266 static unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
1268 return 1 << (ep_index + 1);
1271 /* Compute the last valid endpoint context index. Basically, this is the
1272 * endpoint index plus one. For slot contexts with more than valid endpoint,
1273 * we find the most significant bit set in the added contexts flags.
1274 * e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
1275 * fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
1277 unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
1279 return fls(added_ctxs) - 1;
1282 /* Returns 1 if the arguments are OK;
1283 * returns 0 this is a root hub; returns -EINVAL for NULL pointers.
1285 static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
1286 struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
1288 struct xhci_hcd *xhci;
1289 struct xhci_virt_device *virt_dev;
1291 if (!hcd || (check_ep && !ep) || !udev) {
1292 pr_debug("xHCI %s called with invalid args\n", func);
1295 if (!udev->parent) {
1296 pr_debug("xHCI %s called for root hub\n", func);
1300 xhci = hcd_to_xhci(hcd);
1301 if (check_virt_dev) {
1302 if (!udev->slot_id || !xhci->devs[udev->slot_id]) {
1303 xhci_dbg(xhci, "xHCI %s called with unaddressed device\n",
1308 virt_dev = xhci->devs[udev->slot_id];
1309 if (virt_dev->udev != udev) {
1310 xhci_dbg(xhci, "xHCI %s called with udev and "
1311 "virt_dev does not match\n", func);
1316 if (xhci->xhc_state & XHCI_STATE_HALTED)
1322 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
1323 struct usb_device *udev, struct xhci_command *command,
1324 bool ctx_change, bool must_succeed);
1327 * Full speed devices may have a max packet size greater than 8 bytes, but the
1328 * USB core doesn't know that until it reads the first 8 bytes of the
1329 * descriptor. If the usb_device's max packet size changes after that point,
1330 * we need to issue an evaluate context command and wait on it.
1332 static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
1333 unsigned int ep_index, struct urb *urb)
1335 struct xhci_container_ctx *out_ctx;
1336 struct xhci_input_control_ctx *ctrl_ctx;
1337 struct xhci_ep_ctx *ep_ctx;
1338 struct xhci_command *command;
1339 int max_packet_size;
1340 int hw_max_packet_size;
1343 out_ctx = xhci->devs[slot_id]->out_ctx;
1344 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1345 hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
1346 max_packet_size = usb_endpoint_maxp(&urb->dev->ep0.desc);
1347 if (hw_max_packet_size != max_packet_size) {
1348 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1349 "Max Packet Size for ep 0 changed.");
1350 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1351 "Max packet size in usb_device = %d",
1353 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1354 "Max packet size in xHCI HW = %d",
1355 hw_max_packet_size);
1356 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1357 "Issuing evaluate context command.");
1359 /* Set up the input context flags for the command */
1360 /* FIXME: This won't work if a non-default control endpoint
1361 * changes max packet sizes.
1364 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
1368 command->in_ctx = xhci->devs[slot_id]->in_ctx;
1369 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
1371 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1374 goto command_cleanup;
1376 /* Set up the modified control endpoint 0 */
1377 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
1378 xhci->devs[slot_id]->out_ctx, ep_index);
1380 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
1381 ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
1382 ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
1384 ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
1385 ctrl_ctx->drop_flags = 0;
1387 ret = xhci_configure_endpoint(xhci, urb->dev, command,
1390 /* Clean up the input context for later use by bandwidth
1393 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
1395 kfree(command->completion);
1402 * non-error returns are a promise to giveback() the urb later
1403 * we drop ownership so next owner (or urb unlink) can get it
1405 static int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
1407 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
1408 unsigned long flags;
1410 unsigned int slot_id, ep_index;
1411 unsigned int *ep_state;
1412 struct urb_priv *urb_priv;
1415 if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
1416 true, true, __func__) <= 0)
1419 slot_id = urb->dev->slot_id;
1420 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1421 ep_state = &xhci->devs[slot_id]->eps[ep_index].ep_state;
1423 if (!HCD_HW_ACCESSIBLE(hcd)) {
1424 if (!in_interrupt())
1425 xhci_dbg(xhci, "urb submitted during PCI suspend\n");
1429 if (usb_endpoint_xfer_isoc(&urb->ep->desc))
1430 num_tds = urb->number_of_packets;
1431 else if (usb_endpoint_is_bulk_out(&urb->ep->desc) &&
1432 urb->transfer_buffer_length > 0 &&
1433 urb->transfer_flags & URB_ZERO_PACKET &&
1434 !(urb->transfer_buffer_length % usb_endpoint_maxp(&urb->ep->desc)))
1439 urb_priv = kzalloc(sizeof(struct urb_priv) +
1440 num_tds * sizeof(struct xhci_td), mem_flags);
1444 urb_priv->num_tds = num_tds;
1445 urb_priv->num_tds_done = 0;
1446 urb->hcpriv = urb_priv;
1448 trace_xhci_urb_enqueue(urb);
1450 if (usb_endpoint_xfer_control(&urb->ep->desc)) {
1451 /* Check to see if the max packet size for the default control
1452 * endpoint changed during FS device enumeration
1454 if (urb->dev->speed == USB_SPEED_FULL) {
1455 ret = xhci_check_maxpacket(xhci, slot_id,
1458 xhci_urb_free_priv(urb_priv);
1465 spin_lock_irqsave(&xhci->lock, flags);
1467 if (xhci->xhc_state & XHCI_STATE_DYING) {
1468 xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for non-responsive xHCI host.\n",
1469 urb->ep->desc.bEndpointAddress, urb);
1473 if (*ep_state & (EP_GETTING_STREAMS | EP_GETTING_NO_STREAMS)) {
1474 xhci_warn(xhci, "WARN: Can't enqueue URB, ep in streams transition state %x\n",
1479 if (*ep_state & EP_SOFT_CLEAR_TOGGLE) {
1480 xhci_warn(xhci, "Can't enqueue URB while manually clearing toggle\n");
1485 switch (usb_endpoint_type(&urb->ep->desc)) {
1487 case USB_ENDPOINT_XFER_CONTROL:
1488 ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
1491 case USB_ENDPOINT_XFER_BULK:
1492 ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
1495 case USB_ENDPOINT_XFER_INT:
1496 ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
1499 case USB_ENDPOINT_XFER_ISOC:
1500 ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
1506 xhci_urb_free_priv(urb_priv);
1509 spin_unlock_irqrestore(&xhci->lock, flags);
1514 * Remove the URB's TD from the endpoint ring. This may cause the HC to stop
1515 * USB transfers, potentially stopping in the middle of a TRB buffer. The HC
1516 * should pick up where it left off in the TD, unless a Set Transfer Ring
1517 * Dequeue Pointer is issued.
1519 * The TRBs that make up the buffers for the canceled URB will be "removed" from
1520 * the ring. Since the ring is a contiguous structure, they can't be physically
1521 * removed. Instead, there are two options:
1523 * 1) If the HC is in the middle of processing the URB to be canceled, we
1524 * simply move the ring's dequeue pointer past those TRBs using the Set
1525 * Transfer Ring Dequeue Pointer command. This will be the common case,
1526 * when drivers timeout on the last submitted URB and attempt to cancel.
1528 * 2) If the HC is in the middle of a different TD, we turn the TRBs into a
1529 * series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
1530 * HC will need to invalidate the any TRBs it has cached after the stop
1531 * endpoint command, as noted in the xHCI 0.95 errata.
1533 * 3) The TD may have completed by the time the Stop Endpoint Command
1534 * completes, so software needs to handle that case too.
1536 * This function should protect against the TD enqueueing code ringing the
1537 * doorbell while this code is waiting for a Stop Endpoint command to complete.
1538 * It also needs to account for multiple cancellations on happening at the same
1539 * time for the same endpoint.
1541 * Note that this function can be called in any context, or so says
1542 * usb_hcd_unlink_urb()
1544 static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
1546 unsigned long flags;
1549 struct xhci_hcd *xhci;
1550 struct urb_priv *urb_priv;
1552 unsigned int ep_index;
1553 struct xhci_ring *ep_ring;
1554 struct xhci_virt_ep *ep;
1555 struct xhci_command *command;
1556 struct xhci_virt_device *vdev;
1558 xhci = hcd_to_xhci(hcd);
1559 spin_lock_irqsave(&xhci->lock, flags);
1561 trace_xhci_urb_dequeue(urb);
1563 /* Make sure the URB hasn't completed or been unlinked already */
1564 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
1568 /* give back URB now if we can't queue it for cancel */
1569 vdev = xhci->devs[urb->dev->slot_id];
1570 urb_priv = urb->hcpriv;
1571 if (!vdev || !urb_priv)
1574 ep_index = xhci_get_endpoint_index(&urb->ep->desc);
1575 ep = &vdev->eps[ep_index];
1576 ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
1577 if (!ep || !ep_ring)
1580 /* If xHC is dead take it down and return ALL URBs in xhci_hc_died() */
1581 temp = readl(&xhci->op_regs->status);
1582 if (temp == ~(u32)0 || xhci->xhc_state & XHCI_STATE_DYING) {
1588 * check ring is not re-allocated since URB was enqueued. If it is, then
1589 * make sure none of the ring related pointers in this URB private data
1590 * are touched, such as td_list, otherwise we overwrite freed data
1592 if (!td_on_ring(&urb_priv->td[0], ep_ring)) {
1593 xhci_err(xhci, "Canceled URB td not found on endpoint ring");
1594 for (i = urb_priv->num_tds_done; i < urb_priv->num_tds; i++) {
1595 td = &urb_priv->td[i];
1596 if (!list_empty(&td->cancelled_td_list))
1597 list_del_init(&td->cancelled_td_list);
1602 if (xhci->xhc_state & XHCI_STATE_HALTED) {
1603 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1604 "HC halted, freeing TD manually.");
1605 for (i = urb_priv->num_tds_done;
1606 i < urb_priv->num_tds;
1608 td = &urb_priv->td[i];
1609 if (!list_empty(&td->td_list))
1610 list_del_init(&td->td_list);
1611 if (!list_empty(&td->cancelled_td_list))
1612 list_del_init(&td->cancelled_td_list);
1617 i = urb_priv->num_tds_done;
1618 if (i < urb_priv->num_tds)
1619 xhci_dbg_trace(xhci, trace_xhci_dbg_cancel_urb,
1620 "Cancel URB %p, dev %s, ep 0x%x, "
1621 "starting at offset 0x%llx",
1622 urb, urb->dev->devpath,
1623 urb->ep->desc.bEndpointAddress,
1624 (unsigned long long) xhci_trb_virt_to_dma(
1625 urb_priv->td[i].start_seg,
1626 urb_priv->td[i].first_trb));
1628 for (; i < urb_priv->num_tds; i++) {
1629 td = &urb_priv->td[i];
1630 list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
1633 /* Queue a stop endpoint command, but only if this is
1634 * the first cancellation to be handled.
1636 if (!(ep->ep_state & EP_STOP_CMD_PENDING)) {
1637 command = xhci_alloc_command(xhci, false, GFP_ATOMIC);
1642 ep->ep_state |= EP_STOP_CMD_PENDING;
1643 ep->stop_cmd_timer.expires = jiffies +
1644 XHCI_STOP_EP_CMD_TIMEOUT * HZ;
1645 add_timer(&ep->stop_cmd_timer);
1646 xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
1648 xhci_ring_cmd_db(xhci);
1651 spin_unlock_irqrestore(&xhci->lock, flags);
1656 xhci_urb_free_priv(urb_priv);
1657 usb_hcd_unlink_urb_from_ep(hcd, urb);
1658 spin_unlock_irqrestore(&xhci->lock, flags);
1659 usb_hcd_giveback_urb(hcd, urb, -ESHUTDOWN);
1663 /* Drop an endpoint from a new bandwidth configuration for this device.
1664 * Only one call to this function is allowed per endpoint before
1665 * check_bandwidth() or reset_bandwidth() must be called.
1666 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1667 * add the endpoint to the schedule with possibly new parameters denoted by a
1668 * different endpoint descriptor in usb_host_endpoint.
1669 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1672 * The USB core will not allow URBs to be queued to an endpoint that is being
1673 * disabled, so there's no need for mutual exclusion to protect
1674 * the xhci->devs[slot_id] structure.
1676 static int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1677 struct usb_host_endpoint *ep)
1679 struct xhci_hcd *xhci;
1680 struct xhci_container_ctx *in_ctx, *out_ctx;
1681 struct xhci_input_control_ctx *ctrl_ctx;
1682 unsigned int ep_index;
1683 struct xhci_ep_ctx *ep_ctx;
1685 u32 new_add_flags, new_drop_flags;
1688 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1691 xhci = hcd_to_xhci(hcd);
1692 if (xhci->xhc_state & XHCI_STATE_DYING)
1695 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
1696 drop_flag = xhci_get_endpoint_flag(&ep->desc);
1697 if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
1698 xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
1699 __func__, drop_flag);
1703 in_ctx = xhci->devs[udev->slot_id]->in_ctx;
1704 out_ctx = xhci->devs[udev->slot_id]->out_ctx;
1705 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1707 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1712 ep_index = xhci_get_endpoint_index(&ep->desc);
1713 ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1714 /* If the HC already knows the endpoint is disabled,
1715 * or the HCD has noted it is disabled, ignore this request
1717 if ((GET_EP_CTX_STATE(ep_ctx) == EP_STATE_DISABLED) ||
1718 le32_to_cpu(ctrl_ctx->drop_flags) &
1719 xhci_get_endpoint_flag(&ep->desc)) {
1720 /* Do not warn when called after a usb_device_reset */
1721 if (xhci->devs[udev->slot_id]->eps[ep_index].ring != NULL)
1722 xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
1727 ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
1728 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1730 ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
1731 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1733 xhci_debugfs_remove_endpoint(xhci, xhci->devs[udev->slot_id], ep_index);
1735 xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
1737 if (xhci->quirks & XHCI_MTK_HOST)
1738 xhci_mtk_drop_ep_quirk(hcd, udev, ep);
1740 xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1741 (unsigned int) ep->desc.bEndpointAddress,
1743 (unsigned int) new_drop_flags,
1744 (unsigned int) new_add_flags);
1748 /* Add an endpoint to a new possible bandwidth configuration for this device.
1749 * Only one call to this function is allowed per endpoint before
1750 * check_bandwidth() or reset_bandwidth() must be called.
1751 * A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
1752 * add the endpoint to the schedule with possibly new parameters denoted by a
1753 * different endpoint descriptor in usb_host_endpoint.
1754 * A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
1757 * The USB core will not allow URBs to be queued to an endpoint until the
1758 * configuration or alt setting is installed in the device, so there's no need
1759 * for mutual exclusion to protect the xhci->devs[slot_id] structure.
1761 static int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
1762 struct usb_host_endpoint *ep)
1764 struct xhci_hcd *xhci;
1765 struct xhci_container_ctx *in_ctx;
1766 unsigned int ep_index;
1767 struct xhci_input_control_ctx *ctrl_ctx;
1769 u32 new_add_flags, new_drop_flags;
1770 struct xhci_virt_device *virt_dev;
1773 ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
1775 /* So we won't queue a reset ep command for a root hub */
1779 xhci = hcd_to_xhci(hcd);
1780 if (xhci->xhc_state & XHCI_STATE_DYING)
1783 added_ctxs = xhci_get_endpoint_flag(&ep->desc);
1784 if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
1785 /* FIXME when we have to issue an evaluate endpoint command to
1786 * deal with ep0 max packet size changing once we get the
1789 xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
1790 __func__, added_ctxs);
1794 virt_dev = xhci->devs[udev->slot_id];
1795 in_ctx = virt_dev->in_ctx;
1796 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
1798 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1803 ep_index = xhci_get_endpoint_index(&ep->desc);
1804 /* If this endpoint is already in use, and the upper layers are trying
1805 * to add it again without dropping it, reject the addition.
1807 if (virt_dev->eps[ep_index].ring &&
1808 !(le32_to_cpu(ctrl_ctx->drop_flags) & added_ctxs)) {
1809 xhci_warn(xhci, "Trying to add endpoint 0x%x "
1810 "without dropping it.\n",
1811 (unsigned int) ep->desc.bEndpointAddress);
1815 /* If the HCD has already noted the endpoint is enabled,
1816 * ignore this request.
1818 if (le32_to_cpu(ctrl_ctx->add_flags) & added_ctxs) {
1819 xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
1825 * Configuration and alternate setting changes must be done in
1826 * process context, not interrupt context (or so documenation
1827 * for usb_set_interface() and usb_set_configuration() claim).
1829 if (xhci_endpoint_init(xhci, virt_dev, udev, ep, GFP_NOIO) < 0) {
1830 dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
1831 __func__, ep->desc.bEndpointAddress);
1835 if (xhci->quirks & XHCI_MTK_HOST) {
1836 ret = xhci_mtk_add_ep_quirk(hcd, udev, ep);
1838 xhci_ring_free(xhci, virt_dev->eps[ep_index].new_ring);
1839 virt_dev->eps[ep_index].new_ring = NULL;
1844 ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
1845 new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
1847 /* If xhci_endpoint_disable() was called for this endpoint, but the
1848 * xHC hasn't been notified yet through the check_bandwidth() call,
1849 * this re-adds a new state for the endpoint from the new endpoint
1850 * descriptors. We must drop and re-add this endpoint, so we leave the
1853 new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
1855 /* Store the usb_device pointer for later use */
1858 xhci_debugfs_create_endpoint(xhci, virt_dev, ep_index);
1860 xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x\n",
1861 (unsigned int) ep->desc.bEndpointAddress,
1863 (unsigned int) new_drop_flags,
1864 (unsigned int) new_add_flags);
1868 static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
1870 struct xhci_input_control_ctx *ctrl_ctx;
1871 struct xhci_ep_ctx *ep_ctx;
1872 struct xhci_slot_ctx *slot_ctx;
1875 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
1877 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
1882 /* When a device's add flag and drop flag are zero, any subsequent
1883 * configure endpoint command will leave that endpoint's state
1884 * untouched. Make sure we don't leave any old state in the input
1885 * endpoint contexts.
1887 ctrl_ctx->drop_flags = 0;
1888 ctrl_ctx->add_flags = 0;
1889 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
1890 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
1891 /* Endpoint 0 is always valid */
1892 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
1893 for (i = 1; i < 31; i++) {
1894 ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
1895 ep_ctx->ep_info = 0;
1896 ep_ctx->ep_info2 = 0;
1898 ep_ctx->tx_info = 0;
1902 static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
1903 struct usb_device *udev, u32 *cmd_status)
1907 switch (*cmd_status) {
1908 case COMP_COMMAND_ABORTED:
1909 case COMP_COMMAND_RING_STOPPED:
1910 xhci_warn(xhci, "Timeout while waiting for configure endpoint command\n");
1913 case COMP_RESOURCE_ERROR:
1914 dev_warn(&udev->dev,
1915 "Not enough host controller resources for new device state.\n");
1917 /* FIXME: can we allocate more resources for the HC? */
1919 case COMP_BANDWIDTH_ERROR:
1920 case COMP_SECONDARY_BANDWIDTH_ERROR:
1921 dev_warn(&udev->dev,
1922 "Not enough bandwidth for new device state.\n");
1924 /* FIXME: can we go back to the old state? */
1926 case COMP_TRB_ERROR:
1927 /* the HCD set up something wrong */
1928 dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
1930 "and endpoint is not disabled.\n");
1933 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1934 dev_warn(&udev->dev,
1935 "ERROR: Incompatible device for endpoint configure command.\n");
1939 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1940 "Successful Endpoint Configure command");
1944 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
1952 static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
1953 struct usb_device *udev, u32 *cmd_status)
1957 switch (*cmd_status) {
1958 case COMP_COMMAND_ABORTED:
1959 case COMP_COMMAND_RING_STOPPED:
1960 xhci_warn(xhci, "Timeout while waiting for evaluate context command\n");
1963 case COMP_PARAMETER_ERROR:
1964 dev_warn(&udev->dev,
1965 "WARN: xHCI driver setup invalid evaluate context command.\n");
1968 case COMP_SLOT_NOT_ENABLED_ERROR:
1969 dev_warn(&udev->dev,
1970 "WARN: slot not enabled for evaluate context command.\n");
1973 case COMP_CONTEXT_STATE_ERROR:
1974 dev_warn(&udev->dev,
1975 "WARN: invalid context state for evaluate context command.\n");
1978 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1979 dev_warn(&udev->dev,
1980 "ERROR: Incompatible device for evaluate context command.\n");
1983 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1984 /* Max Exit Latency too large error */
1985 dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
1989 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
1990 "Successful evaluate context command");
1994 xhci_err(xhci, "ERROR: unexpected command completion code 0x%x.\n",
2002 static u32 xhci_count_num_new_endpoints(struct xhci_hcd *xhci,
2003 struct xhci_input_control_ctx *ctrl_ctx)
2005 u32 valid_add_flags;
2006 u32 valid_drop_flags;
2008 /* Ignore the slot flag (bit 0), and the default control endpoint flag
2009 * (bit 1). The default control endpoint is added during the Address
2010 * Device command and is never removed until the slot is disabled.
2012 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2013 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2015 /* Use hweight32 to count the number of ones in the add flags, or
2016 * number of endpoints added. Don't count endpoints that are changed
2017 * (both added and dropped).
2019 return hweight32(valid_add_flags) -
2020 hweight32(valid_add_flags & valid_drop_flags);
2023 static unsigned int xhci_count_num_dropped_endpoints(struct xhci_hcd *xhci,
2024 struct xhci_input_control_ctx *ctrl_ctx)
2026 u32 valid_add_flags;
2027 u32 valid_drop_flags;
2029 valid_add_flags = le32_to_cpu(ctrl_ctx->add_flags) >> 2;
2030 valid_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags) >> 2;
2032 return hweight32(valid_drop_flags) -
2033 hweight32(valid_add_flags & valid_drop_flags);
2037 * We need to reserve the new number of endpoints before the configure endpoint
2038 * command completes. We can't subtract the dropped endpoints from the number
2039 * of active endpoints until the command completes because we can oversubscribe
2040 * the host in this case:
2042 * - the first configure endpoint command drops more endpoints than it adds
2043 * - a second configure endpoint command that adds more endpoints is queued
2044 * - the first configure endpoint command fails, so the config is unchanged
2045 * - the second command may succeed, even though there isn't enough resources
2047 * Must be called with xhci->lock held.
2049 static int xhci_reserve_host_resources(struct xhci_hcd *xhci,
2050 struct xhci_input_control_ctx *ctrl_ctx)
2054 added_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2055 if (xhci->num_active_eps + added_eps > xhci->limit_active_eps) {
2056 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2057 "Not enough ep ctxs: "
2058 "%u active, need to add %u, limit is %u.",
2059 xhci->num_active_eps, added_eps,
2060 xhci->limit_active_eps);
2063 xhci->num_active_eps += added_eps;
2064 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2065 "Adding %u ep ctxs, %u now active.", added_eps,
2066 xhci->num_active_eps);
2071 * The configure endpoint was failed by the xHC for some other reason, so we
2072 * need to revert the resources that failed configuration would have used.
2074 * Must be called with xhci->lock held.
2076 static void xhci_free_host_resources(struct xhci_hcd *xhci,
2077 struct xhci_input_control_ctx *ctrl_ctx)
2081 num_failed_eps = xhci_count_num_new_endpoints(xhci, ctrl_ctx);
2082 xhci->num_active_eps -= num_failed_eps;
2083 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2084 "Removing %u failed ep ctxs, %u now active.",
2086 xhci->num_active_eps);
2090 * Now that the command has completed, clean up the active endpoint count by
2091 * subtracting out the endpoints that were dropped (but not changed).
2093 * Must be called with xhci->lock held.
2095 static void xhci_finish_resource_reservation(struct xhci_hcd *xhci,
2096 struct xhci_input_control_ctx *ctrl_ctx)
2098 u32 num_dropped_eps;
2100 num_dropped_eps = xhci_count_num_dropped_endpoints(xhci, ctrl_ctx);
2101 xhci->num_active_eps -= num_dropped_eps;
2102 if (num_dropped_eps)
2103 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2104 "Removing %u dropped ep ctxs, %u now active.",
2106 xhci->num_active_eps);
2109 static unsigned int xhci_get_block_size(struct usb_device *udev)
2111 switch (udev->speed) {
2113 case USB_SPEED_FULL:
2115 case USB_SPEED_HIGH:
2117 case USB_SPEED_SUPER:
2118 case USB_SPEED_SUPER_PLUS:
2120 case USB_SPEED_UNKNOWN:
2121 case USB_SPEED_WIRELESS:
2123 /* Should never happen */
2129 xhci_get_largest_overhead(struct xhci_interval_bw *interval_bw)
2131 if (interval_bw->overhead[LS_OVERHEAD_TYPE])
2133 if (interval_bw->overhead[FS_OVERHEAD_TYPE])
2138 /* If we are changing a LS/FS device under a HS hub,
2139 * make sure (if we are activating a new TT) that the HS bus has enough
2140 * bandwidth for this new TT.
2142 static int xhci_check_tt_bw_table(struct xhci_hcd *xhci,
2143 struct xhci_virt_device *virt_dev,
2146 struct xhci_interval_bw_table *bw_table;
2147 struct xhci_tt_bw_info *tt_info;
2149 /* Find the bandwidth table for the root port this TT is attached to. */
2150 bw_table = &xhci->rh_bw[virt_dev->real_port - 1].bw_table;
2151 tt_info = virt_dev->tt_info;
2152 /* If this TT already had active endpoints, the bandwidth for this TT
2153 * has already been added. Removing all periodic endpoints (and thus
2154 * making the TT enactive) will only decrease the bandwidth used.
2158 if (old_active_eps == 0 && tt_info->active_eps != 0) {
2159 if (bw_table->bw_used + TT_HS_OVERHEAD > HS_BW_LIMIT)
2163 /* Not sure why we would have no new active endpoints...
2165 * Maybe because of an Evaluate Context change for a hub update or a
2166 * control endpoint 0 max packet size change?
2167 * FIXME: skip the bandwidth calculation in that case.
2172 static int xhci_check_ss_bw(struct xhci_hcd *xhci,
2173 struct xhci_virt_device *virt_dev)
2175 unsigned int bw_reserved;
2177 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_IN, 100);
2178 if (virt_dev->bw_table->ss_bw_in > (SS_BW_LIMIT_IN - bw_reserved))
2181 bw_reserved = DIV_ROUND_UP(SS_BW_RESERVED*SS_BW_LIMIT_OUT, 100);
2182 if (virt_dev->bw_table->ss_bw_out > (SS_BW_LIMIT_OUT - bw_reserved))
2189 * This algorithm is a very conservative estimate of the worst-case scheduling
2190 * scenario for any one interval. The hardware dynamically schedules the
2191 * packets, so we can't tell which microframe could be the limiting factor in
2192 * the bandwidth scheduling. This only takes into account periodic endpoints.
2194 * Obviously, we can't solve an NP complete problem to find the minimum worst
2195 * case scenario. Instead, we come up with an estimate that is no less than
2196 * the worst case bandwidth used for any one microframe, but may be an
2199 * We walk the requirements for each endpoint by interval, starting with the
2200 * smallest interval, and place packets in the schedule where there is only one
2201 * possible way to schedule packets for that interval. In order to simplify
2202 * this algorithm, we record the largest max packet size for each interval, and
2203 * assume all packets will be that size.
2205 * For interval 0, we obviously must schedule all packets for each interval.
2206 * The bandwidth for interval 0 is just the amount of data to be transmitted
2207 * (the sum of all max ESIT payload sizes, plus any overhead per packet times
2208 * the number of packets).
2210 * For interval 1, we have two possible microframes to schedule those packets
2211 * in. For this algorithm, if we can schedule the same number of packets for
2212 * each possible scheduling opportunity (each microframe), we will do so. The
2213 * remaining number of packets will be saved to be transmitted in the gaps in
2214 * the next interval's scheduling sequence.
2216 * As we move those remaining packets to be scheduled with interval 2 packets,
2217 * we have to double the number of remaining packets to transmit. This is
2218 * because the intervals are actually powers of 2, and we would be transmitting
2219 * the previous interval's packets twice in this interval. We also have to be
2220 * sure that when we look at the largest max packet size for this interval, we
2221 * also look at the largest max packet size for the remaining packets and take
2222 * the greater of the two.
2224 * The algorithm continues to evenly distribute packets in each scheduling
2225 * opportunity, and push the remaining packets out, until we get to the last
2226 * interval. Then those packets and their associated overhead are just added
2227 * to the bandwidth used.
2229 static int xhci_check_bw_table(struct xhci_hcd *xhci,
2230 struct xhci_virt_device *virt_dev,
2233 unsigned int bw_reserved;
2234 unsigned int max_bandwidth;
2235 unsigned int bw_used;
2236 unsigned int block_size;
2237 struct xhci_interval_bw_table *bw_table;
2238 unsigned int packet_size = 0;
2239 unsigned int overhead = 0;
2240 unsigned int packets_transmitted = 0;
2241 unsigned int packets_remaining = 0;
2244 if (virt_dev->udev->speed >= USB_SPEED_SUPER)
2245 return xhci_check_ss_bw(xhci, virt_dev);
2247 if (virt_dev->udev->speed == USB_SPEED_HIGH) {
2248 max_bandwidth = HS_BW_LIMIT;
2249 /* Convert percent of bus BW reserved to blocks reserved */
2250 bw_reserved = DIV_ROUND_UP(HS_BW_RESERVED * max_bandwidth, 100);
2252 max_bandwidth = FS_BW_LIMIT;
2253 bw_reserved = DIV_ROUND_UP(FS_BW_RESERVED * max_bandwidth, 100);
2256 bw_table = virt_dev->bw_table;
2257 /* We need to translate the max packet size and max ESIT payloads into
2258 * the units the hardware uses.
2260 block_size = xhci_get_block_size(virt_dev->udev);
2262 /* If we are manipulating a LS/FS device under a HS hub, double check
2263 * that the HS bus has enough bandwidth if we are activing a new TT.
2265 if (virt_dev->tt_info) {
2266 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2267 "Recalculating BW for rootport %u",
2268 virt_dev->real_port);
2269 if (xhci_check_tt_bw_table(xhci, virt_dev, old_active_eps)) {
2270 xhci_warn(xhci, "Not enough bandwidth on HS bus for "
2271 "newly activated TT.\n");
2274 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2275 "Recalculating BW for TT slot %u port %u",
2276 virt_dev->tt_info->slot_id,
2277 virt_dev->tt_info->ttport);
2279 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2280 "Recalculating BW for rootport %u",
2281 virt_dev->real_port);
2284 /* Add in how much bandwidth will be used for interval zero, or the
2285 * rounded max ESIT payload + number of packets * largest overhead.
2287 bw_used = DIV_ROUND_UP(bw_table->interval0_esit_payload, block_size) +
2288 bw_table->interval_bw[0].num_packets *
2289 xhci_get_largest_overhead(&bw_table->interval_bw[0]);
2291 for (i = 1; i < XHCI_MAX_INTERVAL; i++) {
2292 unsigned int bw_added;
2293 unsigned int largest_mps;
2294 unsigned int interval_overhead;
2297 * How many packets could we transmit in this interval?
2298 * If packets didn't fit in the previous interval, we will need
2299 * to transmit that many packets twice within this interval.
2301 packets_remaining = 2 * packets_remaining +
2302 bw_table->interval_bw[i].num_packets;
2304 /* Find the largest max packet size of this or the previous
2307 if (list_empty(&bw_table->interval_bw[i].endpoints))
2310 struct xhci_virt_ep *virt_ep;
2311 struct list_head *ep_entry;
2313 ep_entry = bw_table->interval_bw[i].endpoints.next;
2314 virt_ep = list_entry(ep_entry,
2315 struct xhci_virt_ep, bw_endpoint_list);
2316 /* Convert to blocks, rounding up */
2317 largest_mps = DIV_ROUND_UP(
2318 virt_ep->bw_info.max_packet_size,
2321 if (largest_mps > packet_size)
2322 packet_size = largest_mps;
2324 /* Use the larger overhead of this or the previous interval. */
2325 interval_overhead = xhci_get_largest_overhead(
2326 &bw_table->interval_bw[i]);
2327 if (interval_overhead > overhead)
2328 overhead = interval_overhead;
2330 /* How many packets can we evenly distribute across
2331 * (1 << (i + 1)) possible scheduling opportunities?
2333 packets_transmitted = packets_remaining >> (i + 1);
2335 /* Add in the bandwidth used for those scheduled packets */
2336 bw_added = packets_transmitted * (overhead + packet_size);
2338 /* How many packets do we have remaining to transmit? */
2339 packets_remaining = packets_remaining % (1 << (i + 1));
2341 /* What largest max packet size should those packets have? */
2342 /* If we've transmitted all packets, don't carry over the
2343 * largest packet size.
2345 if (packets_remaining == 0) {
2348 } else if (packets_transmitted > 0) {
2349 /* Otherwise if we do have remaining packets, and we've
2350 * scheduled some packets in this interval, take the
2351 * largest max packet size from endpoints with this
2354 packet_size = largest_mps;
2355 overhead = interval_overhead;
2357 /* Otherwise carry over packet_size and overhead from the last
2358 * time we had a remainder.
2360 bw_used += bw_added;
2361 if (bw_used > max_bandwidth) {
2362 xhci_warn(xhci, "Not enough bandwidth. "
2363 "Proposed: %u, Max: %u\n",
2364 bw_used, max_bandwidth);
2369 * Ok, we know we have some packets left over after even-handedly
2370 * scheduling interval 15. We don't know which microframes they will
2371 * fit into, so we over-schedule and say they will be scheduled every
2374 if (packets_remaining > 0)
2375 bw_used += overhead + packet_size;
2377 if (!virt_dev->tt_info && virt_dev->udev->speed == USB_SPEED_HIGH) {
2378 unsigned int port_index = virt_dev->real_port - 1;
2380 /* OK, we're manipulating a HS device attached to a
2381 * root port bandwidth domain. Include the number of active TTs
2382 * in the bandwidth used.
2384 bw_used += TT_HS_OVERHEAD *
2385 xhci->rh_bw[port_index].num_active_tts;
2388 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
2389 "Final bandwidth: %u, Limit: %u, Reserved: %u, "
2390 "Available: %u " "percent",
2391 bw_used, max_bandwidth, bw_reserved,
2392 (max_bandwidth - bw_used - bw_reserved) * 100 /
2395 bw_used += bw_reserved;
2396 if (bw_used > max_bandwidth) {
2397 xhci_warn(xhci, "Not enough bandwidth. Proposed: %u, Max: %u\n",
2398 bw_used, max_bandwidth);
2402 bw_table->bw_used = bw_used;
2406 static bool xhci_is_async_ep(unsigned int ep_type)
2408 return (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
2409 ep_type != ISOC_IN_EP &&
2410 ep_type != INT_IN_EP);
2413 static bool xhci_is_sync_in_ep(unsigned int ep_type)
2415 return (ep_type == ISOC_IN_EP || ep_type == INT_IN_EP);
2418 static unsigned int xhci_get_ss_bw_consumed(struct xhci_bw_info *ep_bw)
2420 unsigned int mps = DIV_ROUND_UP(ep_bw->max_packet_size, SS_BLOCK);
2422 if (ep_bw->ep_interval == 0)
2423 return SS_OVERHEAD_BURST +
2424 (ep_bw->mult * ep_bw->num_packets *
2425 (SS_OVERHEAD + mps));
2426 return DIV_ROUND_UP(ep_bw->mult * ep_bw->num_packets *
2427 (SS_OVERHEAD + mps + SS_OVERHEAD_BURST),
2428 1 << ep_bw->ep_interval);
2432 static void xhci_drop_ep_from_interval_table(struct xhci_hcd *xhci,
2433 struct xhci_bw_info *ep_bw,
2434 struct xhci_interval_bw_table *bw_table,
2435 struct usb_device *udev,
2436 struct xhci_virt_ep *virt_ep,
2437 struct xhci_tt_bw_info *tt_info)
2439 struct xhci_interval_bw *interval_bw;
2440 int normalized_interval;
2442 if (xhci_is_async_ep(ep_bw->type))
2445 if (udev->speed >= USB_SPEED_SUPER) {
2446 if (xhci_is_sync_in_ep(ep_bw->type))
2447 xhci->devs[udev->slot_id]->bw_table->ss_bw_in -=
2448 xhci_get_ss_bw_consumed(ep_bw);
2450 xhci->devs[udev->slot_id]->bw_table->ss_bw_out -=
2451 xhci_get_ss_bw_consumed(ep_bw);
2455 /* SuperSpeed endpoints never get added to intervals in the table, so
2456 * this check is only valid for HS/FS/LS devices.
2458 if (list_empty(&virt_ep->bw_endpoint_list))
2460 /* For LS/FS devices, we need to translate the interval expressed in
2461 * microframes to frames.
2463 if (udev->speed == USB_SPEED_HIGH)
2464 normalized_interval = ep_bw->ep_interval;
2466 normalized_interval = ep_bw->ep_interval - 3;
2468 if (normalized_interval == 0)
2469 bw_table->interval0_esit_payload -= ep_bw->max_esit_payload;
2470 interval_bw = &bw_table->interval_bw[normalized_interval];
2471 interval_bw->num_packets -= ep_bw->num_packets;
2472 switch (udev->speed) {
2474 interval_bw->overhead[LS_OVERHEAD_TYPE] -= 1;
2476 case USB_SPEED_FULL:
2477 interval_bw->overhead[FS_OVERHEAD_TYPE] -= 1;
2479 case USB_SPEED_HIGH:
2480 interval_bw->overhead[HS_OVERHEAD_TYPE] -= 1;
2482 case USB_SPEED_SUPER:
2483 case USB_SPEED_SUPER_PLUS:
2484 case USB_SPEED_UNKNOWN:
2485 case USB_SPEED_WIRELESS:
2486 /* Should never happen because only LS/FS/HS endpoints will get
2487 * added to the endpoint list.
2492 tt_info->active_eps -= 1;
2493 list_del_init(&virt_ep->bw_endpoint_list);
2496 static void xhci_add_ep_to_interval_table(struct xhci_hcd *xhci,
2497 struct xhci_bw_info *ep_bw,
2498 struct xhci_interval_bw_table *bw_table,
2499 struct usb_device *udev,
2500 struct xhci_virt_ep *virt_ep,
2501 struct xhci_tt_bw_info *tt_info)
2503 struct xhci_interval_bw *interval_bw;
2504 struct xhci_virt_ep *smaller_ep;
2505 int normalized_interval;
2507 if (xhci_is_async_ep(ep_bw->type))
2510 if (udev->speed == USB_SPEED_SUPER) {
2511 if (xhci_is_sync_in_ep(ep_bw->type))
2512 xhci->devs[udev->slot_id]->bw_table->ss_bw_in +=
2513 xhci_get_ss_bw_consumed(ep_bw);
2515 xhci->devs[udev->slot_id]->bw_table->ss_bw_out +=
2516 xhci_get_ss_bw_consumed(ep_bw);
2520 /* For LS/FS devices, we need to translate the interval expressed in
2521 * microframes to frames.
2523 if (udev->speed == USB_SPEED_HIGH)
2524 normalized_interval = ep_bw->ep_interval;
2526 normalized_interval = ep_bw->ep_interval - 3;
2528 if (normalized_interval == 0)
2529 bw_table->interval0_esit_payload += ep_bw->max_esit_payload;
2530 interval_bw = &bw_table->interval_bw[normalized_interval];
2531 interval_bw->num_packets += ep_bw->num_packets;
2532 switch (udev->speed) {
2534 interval_bw->overhead[LS_OVERHEAD_TYPE] += 1;
2536 case USB_SPEED_FULL:
2537 interval_bw->overhead[FS_OVERHEAD_TYPE] += 1;
2539 case USB_SPEED_HIGH:
2540 interval_bw->overhead[HS_OVERHEAD_TYPE] += 1;
2542 case USB_SPEED_SUPER:
2543 case USB_SPEED_SUPER_PLUS:
2544 case USB_SPEED_UNKNOWN:
2545 case USB_SPEED_WIRELESS:
2546 /* Should never happen because only LS/FS/HS endpoints will get
2547 * added to the endpoint list.
2553 tt_info->active_eps += 1;
2554 /* Insert the endpoint into the list, largest max packet size first. */
2555 list_for_each_entry(smaller_ep, &interval_bw->endpoints,
2557 if (ep_bw->max_packet_size >=
2558 smaller_ep->bw_info.max_packet_size) {
2559 /* Add the new ep before the smaller endpoint */
2560 list_add_tail(&virt_ep->bw_endpoint_list,
2561 &smaller_ep->bw_endpoint_list);
2565 /* Add the new endpoint at the end of the list. */
2566 list_add_tail(&virt_ep->bw_endpoint_list,
2567 &interval_bw->endpoints);
2570 void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2571 struct xhci_virt_device *virt_dev,
2574 struct xhci_root_port_bw_info *rh_bw_info;
2575 if (!virt_dev->tt_info)
2578 rh_bw_info = &xhci->rh_bw[virt_dev->real_port - 1];
2579 if (old_active_eps == 0 &&
2580 virt_dev->tt_info->active_eps != 0) {
2581 rh_bw_info->num_active_tts += 1;
2582 rh_bw_info->bw_table.bw_used += TT_HS_OVERHEAD;
2583 } else if (old_active_eps != 0 &&
2584 virt_dev->tt_info->active_eps == 0) {
2585 rh_bw_info->num_active_tts -= 1;
2586 rh_bw_info->bw_table.bw_used -= TT_HS_OVERHEAD;
2590 static int xhci_reserve_bandwidth(struct xhci_hcd *xhci,
2591 struct xhci_virt_device *virt_dev,
2592 struct xhci_container_ctx *in_ctx)
2594 struct xhci_bw_info ep_bw_info[31];
2596 struct xhci_input_control_ctx *ctrl_ctx;
2597 int old_active_eps = 0;
2599 if (virt_dev->tt_info)
2600 old_active_eps = virt_dev->tt_info->active_eps;
2602 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2604 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2609 for (i = 0; i < 31; i++) {
2610 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2613 /* Make a copy of the BW info in case we need to revert this */
2614 memcpy(&ep_bw_info[i], &virt_dev->eps[i].bw_info,
2615 sizeof(ep_bw_info[i]));
2616 /* Drop the endpoint from the interval table if the endpoint is
2617 * being dropped or changed.
2619 if (EP_IS_DROPPED(ctrl_ctx, i))
2620 xhci_drop_ep_from_interval_table(xhci,
2621 &virt_dev->eps[i].bw_info,
2627 /* Overwrite the information stored in the endpoints' bw_info */
2628 xhci_update_bw_info(xhci, virt_dev->in_ctx, ctrl_ctx, virt_dev);
2629 for (i = 0; i < 31; i++) {
2630 /* Add any changed or added endpoints to the interval table */
2631 if (EP_IS_ADDED(ctrl_ctx, i))
2632 xhci_add_ep_to_interval_table(xhci,
2633 &virt_dev->eps[i].bw_info,
2640 if (!xhci_check_bw_table(xhci, virt_dev, old_active_eps)) {
2641 /* Ok, this fits in the bandwidth we have.
2642 * Update the number of active TTs.
2644 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
2648 /* We don't have enough bandwidth for this, revert the stored info. */
2649 for (i = 0; i < 31; i++) {
2650 if (!EP_IS_ADDED(ctrl_ctx, i) && !EP_IS_DROPPED(ctrl_ctx, i))
2653 /* Drop the new copies of any added or changed endpoints from
2654 * the interval table.
2656 if (EP_IS_ADDED(ctrl_ctx, i)) {
2657 xhci_drop_ep_from_interval_table(xhci,
2658 &virt_dev->eps[i].bw_info,
2664 /* Revert the endpoint back to its old information */
2665 memcpy(&virt_dev->eps[i].bw_info, &ep_bw_info[i],
2666 sizeof(ep_bw_info[i]));
2667 /* Add any changed or dropped endpoints back into the table */
2668 if (EP_IS_DROPPED(ctrl_ctx, i))
2669 xhci_add_ep_to_interval_table(xhci,
2670 &virt_dev->eps[i].bw_info,
2680 /* Issue a configure endpoint command or evaluate context command
2681 * and wait for it to finish.
2683 static int xhci_configure_endpoint(struct xhci_hcd *xhci,
2684 struct usb_device *udev,
2685 struct xhci_command *command,
2686 bool ctx_change, bool must_succeed)
2689 unsigned long flags;
2690 struct xhci_input_control_ctx *ctrl_ctx;
2691 struct xhci_virt_device *virt_dev;
2692 struct xhci_slot_ctx *slot_ctx;
2697 spin_lock_irqsave(&xhci->lock, flags);
2699 if (xhci->xhc_state & XHCI_STATE_DYING) {
2700 spin_unlock_irqrestore(&xhci->lock, flags);
2704 virt_dev = xhci->devs[udev->slot_id];
2706 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2708 spin_unlock_irqrestore(&xhci->lock, flags);
2709 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2714 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK) &&
2715 xhci_reserve_host_resources(xhci, ctrl_ctx)) {
2716 spin_unlock_irqrestore(&xhci->lock, flags);
2717 xhci_warn(xhci, "Not enough host resources, "
2718 "active endpoint contexts = %u\n",
2719 xhci->num_active_eps);
2722 if ((xhci->quirks & XHCI_SW_BW_CHECKING) &&
2723 xhci_reserve_bandwidth(xhci, virt_dev, command->in_ctx)) {
2724 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2725 xhci_free_host_resources(xhci, ctrl_ctx);
2726 spin_unlock_irqrestore(&xhci->lock, flags);
2727 xhci_warn(xhci, "Not enough bandwidth\n");
2731 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
2732 trace_xhci_configure_endpoint(slot_ctx);
2735 ret = xhci_queue_configure_endpoint(xhci, command,
2736 command->in_ctx->dma,
2737 udev->slot_id, must_succeed);
2739 ret = xhci_queue_evaluate_context(xhci, command,
2740 command->in_ctx->dma,
2741 udev->slot_id, must_succeed);
2743 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK))
2744 xhci_free_host_resources(xhci, ctrl_ctx);
2745 spin_unlock_irqrestore(&xhci->lock, flags);
2746 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
2747 "FIXME allocate a new ring segment");
2750 xhci_ring_cmd_db(xhci);
2751 spin_unlock_irqrestore(&xhci->lock, flags);
2753 /* Wait for the configure endpoint command to complete */
2754 wait_for_completion(command->completion);
2757 ret = xhci_configure_endpoint_result(xhci, udev,
2760 ret = xhci_evaluate_context_result(xhci, udev,
2763 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
2764 spin_lock_irqsave(&xhci->lock, flags);
2765 /* If the command failed, remove the reserved resources.
2766 * Otherwise, clean up the estimate to include dropped eps.
2769 xhci_free_host_resources(xhci, ctrl_ctx);
2771 xhci_finish_resource_reservation(xhci, ctrl_ctx);
2772 spin_unlock_irqrestore(&xhci->lock, flags);
2777 static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
2778 struct xhci_virt_device *vdev, int i)
2780 struct xhci_virt_ep *ep = &vdev->eps[i];
2782 if (ep->ep_state & EP_HAS_STREAMS) {
2783 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on set_interface, freeing streams.\n",
2784 xhci_get_endpoint_address(i));
2785 xhci_free_stream_info(xhci, ep->stream_info);
2786 ep->stream_info = NULL;
2787 ep->ep_state &= ~EP_HAS_STREAMS;
2791 /* Called after one or more calls to xhci_add_endpoint() or
2792 * xhci_drop_endpoint(). If this call fails, the USB core is expected
2793 * to call xhci_reset_bandwidth().
2795 * Since we are in the middle of changing either configuration or
2796 * installing a new alt setting, the USB core won't allow URBs to be
2797 * enqueued for any endpoint on the old config or interface. Nothing
2798 * else should be touching the xhci->devs[slot_id] structure, so we
2799 * don't need to take the xhci->lock for manipulating that.
2801 static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2805 struct xhci_hcd *xhci;
2806 struct xhci_virt_device *virt_dev;
2807 struct xhci_input_control_ctx *ctrl_ctx;
2808 struct xhci_slot_ctx *slot_ctx;
2809 struct xhci_command *command;
2811 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2814 xhci = hcd_to_xhci(hcd);
2815 if ((xhci->xhc_state & XHCI_STATE_DYING) ||
2816 (xhci->xhc_state & XHCI_STATE_REMOVING))
2819 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2820 virt_dev = xhci->devs[udev->slot_id];
2822 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
2826 command->in_ctx = virt_dev->in_ctx;
2828 /* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
2829 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
2831 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2834 goto command_cleanup;
2836 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2837 ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
2838 ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
2840 /* Don't issue the command if there's no endpoints to update. */
2841 if (ctrl_ctx->add_flags == cpu_to_le32(SLOT_FLAG) &&
2842 ctrl_ctx->drop_flags == 0) {
2844 goto command_cleanup;
2846 /* Fix up Context Entries field. Minimum value is EP0 == BIT(1). */
2847 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
2848 for (i = 31; i >= 1; i--) {
2849 __le32 le32 = cpu_to_le32(BIT(i));
2851 if ((virt_dev->eps[i-1].ring && !(ctrl_ctx->drop_flags & le32))
2852 || (ctrl_ctx->add_flags & le32) || i == 1) {
2853 slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
2854 slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(i));
2859 ret = xhci_configure_endpoint(xhci, udev, command,
2862 /* Callee should call reset_bandwidth() */
2863 goto command_cleanup;
2865 /* Free any rings that were dropped, but not changed. */
2866 for (i = 1; i < 31; i++) {
2867 if ((le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1))) &&
2868 !(le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))) {
2869 xhci_free_endpoint_ring(xhci, virt_dev, i);
2870 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2873 xhci_zero_in_ctx(xhci, virt_dev);
2875 * Install any rings for completely new endpoints or changed endpoints,
2876 * and free any old rings from changed endpoints.
2878 for (i = 1; i < 31; i++) {
2879 if (!virt_dev->eps[i].new_ring)
2881 /* Only free the old ring if it exists.
2882 * It may not if this is the first add of an endpoint.
2884 if (virt_dev->eps[i].ring) {
2885 xhci_free_endpoint_ring(xhci, virt_dev, i);
2887 xhci_check_bw_drop_ep_streams(xhci, virt_dev, i);
2888 virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
2889 virt_dev->eps[i].new_ring = NULL;
2892 kfree(command->completion);
2898 static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
2900 struct xhci_hcd *xhci;
2901 struct xhci_virt_device *virt_dev;
2904 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
2907 xhci = hcd_to_xhci(hcd);
2909 xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
2910 virt_dev = xhci->devs[udev->slot_id];
2911 /* Free any rings allocated for added endpoints */
2912 for (i = 0; i < 31; i++) {
2913 if (virt_dev->eps[i].new_ring) {
2914 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
2915 xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
2916 virt_dev->eps[i].new_ring = NULL;
2919 xhci_zero_in_ctx(xhci, virt_dev);
2922 static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
2923 struct xhci_container_ctx *in_ctx,
2924 struct xhci_container_ctx *out_ctx,
2925 struct xhci_input_control_ctx *ctrl_ctx,
2926 u32 add_flags, u32 drop_flags)
2928 ctrl_ctx->add_flags = cpu_to_le32(add_flags);
2929 ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
2930 xhci_slot_copy(xhci, in_ctx, out_ctx);
2931 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
2934 static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
2935 unsigned int slot_id, unsigned int ep_index,
2936 struct xhci_dequeue_state *deq_state)
2938 struct xhci_input_control_ctx *ctrl_ctx;
2939 struct xhci_container_ctx *in_ctx;
2940 struct xhci_ep_ctx *ep_ctx;
2944 in_ctx = xhci->devs[slot_id]->in_ctx;
2945 ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
2947 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
2952 xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
2953 xhci->devs[slot_id]->out_ctx, ep_index);
2954 ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
2955 addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
2956 deq_state->new_deq_ptr);
2958 xhci_warn(xhci, "WARN Cannot submit config ep after "
2959 "reset ep command\n");
2960 xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
2961 deq_state->new_deq_seg,
2962 deq_state->new_deq_ptr);
2965 ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
2967 added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
2968 xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
2969 xhci->devs[slot_id]->out_ctx, ctrl_ctx,
2970 added_ctxs, added_ctxs);
2973 void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2974 unsigned int stream_id, struct xhci_td *td)
2976 struct xhci_dequeue_state deq_state;
2977 struct usb_device *udev = td->urb->dev;
2979 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2980 "Cleaning up stalled endpoint ring");
2981 /* We need to move the HW's dequeue pointer past this TD,
2982 * or it will attempt to resend it on the next doorbell ring.
2984 xhci_find_new_dequeue_state(xhci, udev->slot_id,
2985 ep_index, stream_id, td, &deq_state);
2987 if (!deq_state.new_deq_ptr || !deq_state.new_deq_seg)
2990 /* HW with the reset endpoint quirk will use the saved dequeue state to
2991 * issue a configure endpoint command later.
2993 if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
2994 xhci_dbg_trace(xhci, trace_xhci_dbg_reset_ep,
2995 "Queueing new dequeue state");
2996 xhci_queue_new_dequeue_state(xhci, udev->slot_id,
2997 ep_index, &deq_state);
2999 /* Better hope no one uses the input context between now and the
3000 * reset endpoint completion!
3001 * XXX: No idea how this hardware will react when stream rings
3004 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3005 "Setting up input context for "
3006 "configure endpoint command");
3007 xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
3008 ep_index, &deq_state);
3013 * Called after usb core issues a clear halt control message.
3014 * The host side of the halt should already be cleared by a reset endpoint
3015 * command issued when the STALL event was received.
3017 * The reset endpoint command may only be issued to endpoints in the halted
3018 * state. For software that wishes to reset the data toggle or sequence number
3019 * of an endpoint that isn't in the halted state this function will issue a
3020 * configure endpoint command with the Drop and Add bits set for the target
3021 * endpoint. Refer to the additional note in xhci spcification section 4.6.8.
3024 static void xhci_endpoint_reset(struct usb_hcd *hcd,
3025 struct usb_host_endpoint *host_ep)
3027 struct xhci_hcd *xhci;
3028 struct usb_device *udev;
3029 struct xhci_virt_device *vdev;
3030 struct xhci_virt_ep *ep;
3031 struct xhci_input_control_ctx *ctrl_ctx;
3032 struct xhci_command *stop_cmd, *cfg_cmd;
3033 unsigned int ep_index;
3034 unsigned long flags;
3037 xhci = hcd_to_xhci(hcd);
3038 if (!host_ep->hcpriv)
3040 udev = (struct usb_device *) host_ep->hcpriv;
3041 vdev = xhci->devs[udev->slot_id];
3042 ep_index = xhci_get_endpoint_index(&host_ep->desc);
3043 ep = &vdev->eps[ep_index];
3045 /* Bail out if toggle is already being cleared by a endpoint reset */
3046 if (ep->ep_state & EP_HARD_CLEAR_TOGGLE) {
3047 ep->ep_state &= ~EP_HARD_CLEAR_TOGGLE;
3050 /* Only interrupt and bulk ep's use data toggle, USB2 spec 5.5.4-> */
3051 if (usb_endpoint_xfer_control(&host_ep->desc) ||
3052 usb_endpoint_xfer_isoc(&host_ep->desc))
3055 ep_flag = xhci_get_endpoint_flag(&host_ep->desc);
3057 if (ep_flag == SLOT_FLAG || ep_flag == EP0_FLAG)
3060 stop_cmd = xhci_alloc_command(xhci, true, GFP_NOWAIT);
3064 cfg_cmd = xhci_alloc_command_with_ctx(xhci, true, GFP_NOWAIT);
3068 spin_lock_irqsave(&xhci->lock, flags);
3070 /* block queuing new trbs and ringing ep doorbell */
3071 ep->ep_state |= EP_SOFT_CLEAR_TOGGLE;
3074 * Make sure endpoint ring is empty before resetting the toggle/seq.
3075 * Driver is required to synchronously cancel all transfer request.
3076 * Stop the endpoint to force xHC to update the output context
3079 if (!list_empty(&ep->ring->td_list)) {
3080 dev_err(&udev->dev, "EP not empty, refuse reset\n");
3081 spin_unlock_irqrestore(&xhci->lock, flags);
3082 xhci_free_command(xhci, cfg_cmd);
3085 xhci_queue_stop_endpoint(xhci, stop_cmd, udev->slot_id, ep_index, 0);
3086 xhci_ring_cmd_db(xhci);
3087 spin_unlock_irqrestore(&xhci->lock, flags);
3089 wait_for_completion(stop_cmd->completion);
3091 spin_lock_irqsave(&xhci->lock, flags);
3093 /* config ep command clears toggle if add and drop ep flags are set */
3094 ctrl_ctx = xhci_get_input_control_ctx(cfg_cmd->in_ctx);
3095 xhci_setup_input_ctx_for_config_ep(xhci, cfg_cmd->in_ctx, vdev->out_ctx,
3096 ctrl_ctx, ep_flag, ep_flag);
3097 xhci_endpoint_copy(xhci, cfg_cmd->in_ctx, vdev->out_ctx, ep_index);
3099 xhci_queue_configure_endpoint(xhci, cfg_cmd, cfg_cmd->in_ctx->dma,
3100 udev->slot_id, false);
3101 xhci_ring_cmd_db(xhci);
3102 spin_unlock_irqrestore(&xhci->lock, flags);
3104 wait_for_completion(cfg_cmd->completion);
3106 ep->ep_state &= ~EP_SOFT_CLEAR_TOGGLE;
3107 xhci_free_command(xhci, cfg_cmd);
3109 xhci_free_command(xhci, stop_cmd);
3112 static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
3113 struct usb_device *udev, struct usb_host_endpoint *ep,
3114 unsigned int slot_id)
3117 unsigned int ep_index;
3118 unsigned int ep_state;
3122 ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
3125 if (usb_ss_max_streams(&ep->ss_ep_comp) == 0) {
3126 xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
3127 " descriptor for ep 0x%x does not support streams\n",
3128 ep->desc.bEndpointAddress);
3132 ep_index = xhci_get_endpoint_index(&ep->desc);
3133 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3134 if (ep_state & EP_HAS_STREAMS ||
3135 ep_state & EP_GETTING_STREAMS) {
3136 xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
3137 "already has streams set up.\n",
3138 ep->desc.bEndpointAddress);
3139 xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
3140 "dynamic stream context array reallocation.\n");
3143 if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
3144 xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
3145 "endpoint 0x%x; URBs are pending.\n",
3146 ep->desc.bEndpointAddress);
3152 static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
3153 unsigned int *num_streams, unsigned int *num_stream_ctxs)
3155 unsigned int max_streams;
3157 /* The stream context array size must be a power of two */
3158 *num_stream_ctxs = roundup_pow_of_two(*num_streams);
3160 * Find out how many primary stream array entries the host controller
3161 * supports. Later we may use secondary stream arrays (similar to 2nd
3162 * level page entries), but that's an optional feature for xHCI host
3163 * controllers. xHCs must support at least 4 stream IDs.
3165 max_streams = HCC_MAX_PSA(xhci->hcc_params);
3166 if (*num_stream_ctxs > max_streams) {
3167 xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
3169 *num_stream_ctxs = max_streams;
3170 *num_streams = max_streams;
3174 /* Returns an error code if one of the endpoint already has streams.
3175 * This does not change any data structures, it only checks and gathers
3178 static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
3179 struct usb_device *udev,
3180 struct usb_host_endpoint **eps, unsigned int num_eps,
3181 unsigned int *num_streams, u32 *changed_ep_bitmask)
3183 unsigned int max_streams;
3184 unsigned int endpoint_flag;
3188 for (i = 0; i < num_eps; i++) {
3189 ret = xhci_check_streams_endpoint(xhci, udev,
3190 eps[i], udev->slot_id);
3194 max_streams = usb_ss_max_streams(&eps[i]->ss_ep_comp);
3195 if (max_streams < (*num_streams - 1)) {
3196 xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
3197 eps[i]->desc.bEndpointAddress,
3199 *num_streams = max_streams+1;
3202 endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
3203 if (*changed_ep_bitmask & endpoint_flag)
3205 *changed_ep_bitmask |= endpoint_flag;
3210 static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
3211 struct usb_device *udev,
3212 struct usb_host_endpoint **eps, unsigned int num_eps)
3214 u32 changed_ep_bitmask = 0;
3215 unsigned int slot_id;
3216 unsigned int ep_index;
3217 unsigned int ep_state;
3220 slot_id = udev->slot_id;
3221 if (!xhci->devs[slot_id])
3224 for (i = 0; i < num_eps; i++) {
3225 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3226 ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
3227 /* Are streams already being freed for the endpoint? */
3228 if (ep_state & EP_GETTING_NO_STREAMS) {
3229 xhci_warn(xhci, "WARN Can't disable streams for "
3231 "streams are being disabled already\n",
3232 eps[i]->desc.bEndpointAddress);
3235 /* Are there actually any streams to free? */
3236 if (!(ep_state & EP_HAS_STREAMS) &&
3237 !(ep_state & EP_GETTING_STREAMS)) {
3238 xhci_warn(xhci, "WARN Can't disable streams for "
3240 "streams are already disabled!\n",
3241 eps[i]->desc.bEndpointAddress);
3242 xhci_warn(xhci, "WARN xhci_free_streams() called "
3243 "with non-streams endpoint\n");
3246 changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
3248 return changed_ep_bitmask;
3252 * The USB device drivers use this function (through the HCD interface in USB
3253 * core) to prepare a set of bulk endpoints to use streams. Streams are used to
3254 * coordinate mass storage command queueing across multiple endpoints (basically
3255 * a stream ID == a task ID).
3257 * Setting up streams involves allocating the same size stream context array
3258 * for each endpoint and issuing a configure endpoint command for all endpoints.
3260 * Don't allow the call to succeed if one endpoint only supports one stream
3261 * (which means it doesn't support streams at all).
3263 * Drivers may get less stream IDs than they asked for, if the host controller
3264 * hardware or endpoints claim they can't support the number of requested
3267 static int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
3268 struct usb_host_endpoint **eps, unsigned int num_eps,
3269 unsigned int num_streams, gfp_t mem_flags)
3272 struct xhci_hcd *xhci;
3273 struct xhci_virt_device *vdev;
3274 struct xhci_command *config_cmd;
3275 struct xhci_input_control_ctx *ctrl_ctx;
3276 unsigned int ep_index;
3277 unsigned int num_stream_ctxs;
3278 unsigned int max_packet;
3279 unsigned long flags;
3280 u32 changed_ep_bitmask = 0;
3285 /* Add one to the number of streams requested to account for
3286 * stream 0 that is reserved for xHCI usage.
3289 xhci = hcd_to_xhci(hcd);
3290 xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
3293 /* MaxPSASize value 0 (2 streams) means streams are not supported */
3294 if ((xhci->quirks & XHCI_BROKEN_STREAMS) ||
3295 HCC_MAX_PSA(xhci->hcc_params) < 4) {
3296 xhci_dbg(xhci, "xHCI controller does not support streams.\n");
3300 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
3304 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
3306 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3308 xhci_free_command(xhci, config_cmd);
3312 /* Check to make sure all endpoints are not already configured for
3313 * streams. While we're at it, find the maximum number of streams that
3314 * all the endpoints will support and check for duplicate endpoints.
3316 spin_lock_irqsave(&xhci->lock, flags);
3317 ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
3318 num_eps, &num_streams, &changed_ep_bitmask);
3320 xhci_free_command(xhci, config_cmd);
3321 spin_unlock_irqrestore(&xhci->lock, flags);
3324 if (num_streams <= 1) {
3325 xhci_warn(xhci, "WARN: endpoints can't handle "
3326 "more than one stream.\n");
3327 xhci_free_command(xhci, config_cmd);
3328 spin_unlock_irqrestore(&xhci->lock, flags);
3331 vdev = xhci->devs[udev->slot_id];
3332 /* Mark each endpoint as being in transition, so
3333 * xhci_urb_enqueue() will reject all URBs.
3335 for (i = 0; i < num_eps; i++) {
3336 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3337 vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
3339 spin_unlock_irqrestore(&xhci->lock, flags);
3341 /* Setup internal data structures and allocate HW data structures for
3342 * streams (but don't install the HW structures in the input context
3343 * until we're sure all memory allocation succeeded).
3345 xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
3346 xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
3347 num_stream_ctxs, num_streams);
3349 for (i = 0; i < num_eps; i++) {
3350 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3351 max_packet = usb_endpoint_maxp(&eps[i]->desc);
3352 vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
3355 max_packet, mem_flags);
3356 if (!vdev->eps[ep_index].stream_info)
3358 /* Set maxPstreams in endpoint context and update deq ptr to
3359 * point to stream context array. FIXME
3363 /* Set up the input context for a configure endpoint command. */
3364 for (i = 0; i < num_eps; i++) {
3365 struct xhci_ep_ctx *ep_ctx;
3367 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3368 ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
3370 xhci_endpoint_copy(xhci, config_cmd->in_ctx,
3371 vdev->out_ctx, ep_index);
3372 xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
3373 vdev->eps[ep_index].stream_info);
3375 /* Tell the HW to drop its old copy of the endpoint context info
3376 * and add the updated copy from the input context.
3378 xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
3379 vdev->out_ctx, ctrl_ctx,
3380 changed_ep_bitmask, changed_ep_bitmask);
3382 /* Issue and wait for the configure endpoint command */
3383 ret = xhci_configure_endpoint(xhci, udev, config_cmd,
3386 /* xHC rejected the configure endpoint command for some reason, so we
3387 * leave the old ring intact and free our internal streams data
3393 spin_lock_irqsave(&xhci->lock, flags);
3394 for (i = 0; i < num_eps; i++) {
3395 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3396 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3397 xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
3398 udev->slot_id, ep_index);
3399 vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
3401 xhci_free_command(xhci, config_cmd);
3402 spin_unlock_irqrestore(&xhci->lock, flags);
3404 /* Subtract 1 for stream 0, which drivers can't use */
3405 return num_streams - 1;
3408 /* If it didn't work, free the streams! */
3409 for (i = 0; i < num_eps; i++) {
3410 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3411 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3412 vdev->eps[ep_index].stream_info = NULL;
3413 /* FIXME Unset maxPstreams in endpoint context and
3414 * update deq ptr to point to normal string ring.
3416 vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
3417 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3418 xhci_endpoint_zero(xhci, vdev, eps[i]);
3420 xhci_free_command(xhci, config_cmd);
3424 /* Transition the endpoint from using streams to being a "normal" endpoint
3427 * Modify the endpoint context state, submit a configure endpoint command,
3428 * and free all endpoint rings for streams if that completes successfully.
3430 static int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
3431 struct usb_host_endpoint **eps, unsigned int num_eps,
3435 struct xhci_hcd *xhci;
3436 struct xhci_virt_device *vdev;
3437 struct xhci_command *command;
3438 struct xhci_input_control_ctx *ctrl_ctx;
3439 unsigned int ep_index;
3440 unsigned long flags;
3441 u32 changed_ep_bitmask;
3443 xhci = hcd_to_xhci(hcd);
3444 vdev = xhci->devs[udev->slot_id];
3446 /* Set up a configure endpoint command to remove the streams rings */
3447 spin_lock_irqsave(&xhci->lock, flags);
3448 changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
3449 udev, eps, num_eps);
3450 if (changed_ep_bitmask == 0) {
3451 spin_unlock_irqrestore(&xhci->lock, flags);
3455 /* Use the xhci_command structure from the first endpoint. We may have
3456 * allocated too many, but the driver may call xhci_free_streams() for
3457 * each endpoint it grouped into one call to xhci_alloc_streams().
3459 ep_index = xhci_get_endpoint_index(&eps[0]->desc);
3460 command = vdev->eps[ep_index].stream_info->free_streams_command;
3461 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
3463 spin_unlock_irqrestore(&xhci->lock, flags);
3464 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3469 for (i = 0; i < num_eps; i++) {
3470 struct xhci_ep_ctx *ep_ctx;
3472 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3473 ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
3474 xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
3475 EP_GETTING_NO_STREAMS;
3477 xhci_endpoint_copy(xhci, command->in_ctx,
3478 vdev->out_ctx, ep_index);
3479 xhci_setup_no_streams_ep_input_ctx(ep_ctx,
3480 &vdev->eps[ep_index]);
3482 xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
3483 vdev->out_ctx, ctrl_ctx,
3484 changed_ep_bitmask, changed_ep_bitmask);
3485 spin_unlock_irqrestore(&xhci->lock, flags);
3487 /* Issue and wait for the configure endpoint command,
3488 * which must succeed.
3490 ret = xhci_configure_endpoint(xhci, udev, command,
3493 /* xHC rejected the configure endpoint command for some reason, so we
3494 * leave the streams rings intact.
3499 spin_lock_irqsave(&xhci->lock, flags);
3500 for (i = 0; i < num_eps; i++) {
3501 ep_index = xhci_get_endpoint_index(&eps[i]->desc);
3502 xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
3503 vdev->eps[ep_index].stream_info = NULL;
3504 /* FIXME Unset maxPstreams in endpoint context and
3505 * update deq ptr to point to normal string ring.
3507 vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
3508 vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
3510 spin_unlock_irqrestore(&xhci->lock, flags);
3516 * Deletes endpoint resources for endpoints that were active before a Reset
3517 * Device command, or a Disable Slot command. The Reset Device command leaves
3518 * the control endpoint intact, whereas the Disable Slot command deletes it.
3520 * Must be called with xhci->lock held.
3522 void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
3523 struct xhci_virt_device *virt_dev, bool drop_control_ep)
3526 unsigned int num_dropped_eps = 0;
3527 unsigned int drop_flags = 0;
3529 for (i = (drop_control_ep ? 0 : 1); i < 31; i++) {
3530 if (virt_dev->eps[i].ring) {
3531 drop_flags |= 1 << i;
3535 xhci->num_active_eps -= num_dropped_eps;
3536 if (num_dropped_eps)
3537 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3538 "Dropped %u ep ctxs, flags = 0x%x, "
3540 num_dropped_eps, drop_flags,
3541 xhci->num_active_eps);
3545 * This submits a Reset Device Command, which will set the device state to 0,
3546 * set the device address to 0, and disable all the endpoints except the default
3547 * control endpoint. The USB core should come back and call
3548 * xhci_address_device(), and then re-set up the configuration. If this is
3549 * called because of a usb_reset_and_verify_device(), then the old alternate
3550 * settings will be re-installed through the normal bandwidth allocation
3553 * Wait for the Reset Device command to finish. Remove all structures
3554 * associated with the endpoints that were disabled. Clear the input device
3555 * structure? Reset the control endpoint 0 max packet size?
3557 * If the virt_dev to be reset does not exist or does not match the udev,
3558 * it means the device is lost, possibly due to the xHC restore error and
3559 * re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
3560 * re-allocate the device.
3562 static int xhci_discover_or_reset_device(struct usb_hcd *hcd,
3563 struct usb_device *udev)
3566 unsigned long flags;
3567 struct xhci_hcd *xhci;
3568 unsigned int slot_id;
3569 struct xhci_virt_device *virt_dev;
3570 struct xhci_command *reset_device_cmd;
3571 struct xhci_slot_ctx *slot_ctx;
3572 int old_active_eps = 0;
3574 ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
3577 xhci = hcd_to_xhci(hcd);
3578 slot_id = udev->slot_id;
3579 virt_dev = xhci->devs[slot_id];
3581 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3582 "not exist. Re-allocate the device\n", slot_id);
3583 ret = xhci_alloc_dev(hcd, udev);
3590 if (virt_dev->tt_info)
3591 old_active_eps = virt_dev->tt_info->active_eps;
3593 if (virt_dev->udev != udev) {
3594 /* If the virt_dev and the udev does not match, this virt_dev
3595 * may belong to another udev.
3596 * Re-allocate the device.
3598 xhci_dbg(xhci, "The device to be reset with slot ID %u does "
3599 "not match the udev. Re-allocate the device\n",
3601 ret = xhci_alloc_dev(hcd, udev);
3608 /* If device is not setup, there is no point in resetting it */
3609 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3610 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3611 SLOT_STATE_DISABLED)
3614 trace_xhci_discover_or_reset_device(slot_ctx);
3616 xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
3617 /* Allocate the command structure that holds the struct completion.
3618 * Assume we're in process context, since the normal device reset
3619 * process has to wait for the device anyway. Storage devices are
3620 * reset as part of error handling, so use GFP_NOIO instead of
3623 reset_device_cmd = xhci_alloc_command(xhci, true, GFP_NOIO);
3624 if (!reset_device_cmd) {
3625 xhci_dbg(xhci, "Couldn't allocate command structure.\n");
3629 /* Attempt to submit the Reset Device command to the command ring */
3630 spin_lock_irqsave(&xhci->lock, flags);
3632 ret = xhci_queue_reset_device(xhci, reset_device_cmd, slot_id);
3634 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3635 spin_unlock_irqrestore(&xhci->lock, flags);
3636 goto command_cleanup;
3638 xhci_ring_cmd_db(xhci);
3639 spin_unlock_irqrestore(&xhci->lock, flags);
3641 /* Wait for the Reset Device command to finish */
3642 wait_for_completion(reset_device_cmd->completion);
3644 /* The Reset Device command can't fail, according to the 0.95/0.96 spec,
3645 * unless we tried to reset a slot ID that wasn't enabled,
3646 * or the device wasn't in the addressed or configured state.
3648 ret = reset_device_cmd->status;
3650 case COMP_COMMAND_ABORTED:
3651 case COMP_COMMAND_RING_STOPPED:
3652 xhci_warn(xhci, "Timeout waiting for reset device command\n");
3654 goto command_cleanup;
3655 case COMP_SLOT_NOT_ENABLED_ERROR: /* 0.95 completion for bad slot ID */
3656 case COMP_CONTEXT_STATE_ERROR: /* 0.96 completion code for same thing */
3657 xhci_dbg(xhci, "Can't reset device (slot ID %u) in %s state\n",
3659 xhci_get_slot_state(xhci, virt_dev->out_ctx));
3660 xhci_dbg(xhci, "Not freeing device rings.\n");
3661 /* Don't treat this as an error. May change my mind later. */
3663 goto command_cleanup;
3665 xhci_dbg(xhci, "Successful reset device command.\n");
3668 if (xhci_is_vendor_info_code(xhci, ret))
3670 xhci_warn(xhci, "Unknown completion code %u for "
3671 "reset device command.\n", ret);
3673 goto command_cleanup;
3676 /* Free up host controller endpoint resources */
3677 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3678 spin_lock_irqsave(&xhci->lock, flags);
3679 /* Don't delete the default control endpoint resources */
3680 xhci_free_device_endpoint_resources(xhci, virt_dev, false);
3681 spin_unlock_irqrestore(&xhci->lock, flags);
3684 /* Everything but endpoint 0 is disabled, so free the rings. */
3685 for (i = 1; i < 31; i++) {
3686 struct xhci_virt_ep *ep = &virt_dev->eps[i];
3688 if (ep->ep_state & EP_HAS_STREAMS) {
3689 xhci_warn(xhci, "WARN: endpoint 0x%02x has streams on device reset, freeing streams.\n",
3690 xhci_get_endpoint_address(i));
3691 xhci_free_stream_info(xhci, ep->stream_info);
3692 ep->stream_info = NULL;
3693 ep->ep_state &= ~EP_HAS_STREAMS;
3697 xhci_debugfs_remove_endpoint(xhci, virt_dev, i);
3698 xhci_free_endpoint_ring(xhci, virt_dev, i);
3700 if (!list_empty(&virt_dev->eps[i].bw_endpoint_list))
3701 xhci_drop_ep_from_interval_table(xhci,
3702 &virt_dev->eps[i].bw_info,
3707 xhci_clear_endpoint_bw_info(&virt_dev->eps[i].bw_info);
3709 /* If necessary, update the number of active TTs on this root port */
3710 xhci_update_tt_active_eps(xhci, virt_dev, old_active_eps);
3714 xhci_free_command(xhci, reset_device_cmd);
3719 * At this point, the struct usb_device is about to go away, the device has
3720 * disconnected, and all traffic has been stopped and the endpoints have been
3721 * disabled. Free any HC data structures associated with that device.
3723 static void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
3725 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3726 struct xhci_virt_device *virt_dev;
3727 struct xhci_slot_ctx *slot_ctx;
3730 #ifndef CONFIG_USB_DEFAULT_PERSIST
3732 * We called pm_runtime_get_noresume when the device was attached.
3733 * Decrement the counter here to allow controller to runtime suspend
3734 * if no devices remain.
3736 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3737 pm_runtime_put_noidle(hcd->self.controller);
3740 ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
3741 /* If the host is halted due to driver unload, we still need to free the
3744 if (ret <= 0 && ret != -ENODEV)
3747 virt_dev = xhci->devs[udev->slot_id];
3748 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3749 trace_xhci_free_dev(slot_ctx);
3751 /* Stop any wayward timer functions (which may grab the lock) */
3752 for (i = 0; i < 31; i++) {
3753 virt_dev->eps[i].ep_state &= ~EP_STOP_CMD_PENDING;
3754 del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
3756 xhci_debugfs_remove_slot(xhci, udev->slot_id);
3757 virt_dev->udev = NULL;
3758 ret = xhci_disable_slot(xhci, udev->slot_id);
3760 xhci_free_virt_device(xhci, udev->slot_id);
3763 int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id)
3765 struct xhci_command *command;
3766 unsigned long flags;
3770 command = xhci_alloc_command(xhci, false, GFP_KERNEL);
3774 spin_lock_irqsave(&xhci->lock, flags);
3775 /* Don't disable the slot if the host controller is dead. */
3776 state = readl(&xhci->op_regs->status);
3777 if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING) ||
3778 (xhci->xhc_state & XHCI_STATE_HALTED)) {
3779 spin_unlock_irqrestore(&xhci->lock, flags);
3784 ret = xhci_queue_slot_control(xhci, command, TRB_DISABLE_SLOT,
3787 spin_unlock_irqrestore(&xhci->lock, flags);
3791 xhci_ring_cmd_db(xhci);
3792 spin_unlock_irqrestore(&xhci->lock, flags);
3797 * Checks if we have enough host controller resources for the default control
3800 * Must be called with xhci->lock held.
3802 static int xhci_reserve_host_control_ep_resources(struct xhci_hcd *xhci)
3804 if (xhci->num_active_eps + 1 > xhci->limit_active_eps) {
3805 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3806 "Not enough ep ctxs: "
3807 "%u active, need to add 1, limit is %u.",
3808 xhci->num_active_eps, xhci->limit_active_eps);
3811 xhci->num_active_eps += 1;
3812 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
3813 "Adding 1 ep ctx, %u now active.",
3814 xhci->num_active_eps);
3820 * Returns 0 if the xHC ran out of device slots, the Enable Slot command
3821 * timed out, or allocating memory failed. Returns 1 on success.
3823 int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
3825 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3826 struct xhci_virt_device *vdev;
3827 struct xhci_slot_ctx *slot_ctx;
3828 unsigned long flags;
3830 struct xhci_command *command;
3832 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3836 spin_lock_irqsave(&xhci->lock, flags);
3837 ret = xhci_queue_slot_control(xhci, command, TRB_ENABLE_SLOT, 0);
3839 spin_unlock_irqrestore(&xhci->lock, flags);
3840 xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
3841 xhci_free_command(xhci, command);
3844 xhci_ring_cmd_db(xhci);
3845 spin_unlock_irqrestore(&xhci->lock, flags);
3847 wait_for_completion(command->completion);
3848 slot_id = command->slot_id;
3850 if (!slot_id || command->status != COMP_SUCCESS) {
3851 xhci_err(xhci, "Error while assigning device slot ID\n");
3852 xhci_err(xhci, "Max number of devices this xHCI host supports is %u.\n",
3854 readl(&xhci->cap_regs->hcs_params1)));
3855 xhci_free_command(xhci, command);
3859 xhci_free_command(xhci, command);
3861 if ((xhci->quirks & XHCI_EP_LIMIT_QUIRK)) {
3862 spin_lock_irqsave(&xhci->lock, flags);
3863 ret = xhci_reserve_host_control_ep_resources(xhci);
3865 spin_unlock_irqrestore(&xhci->lock, flags);
3866 xhci_warn(xhci, "Not enough host resources, "
3867 "active endpoint contexts = %u\n",
3868 xhci->num_active_eps);
3871 spin_unlock_irqrestore(&xhci->lock, flags);
3873 /* Use GFP_NOIO, since this function can be called from
3874 * xhci_discover_or_reset_device(), which may be called as part of
3875 * mass storage driver error handling.
3877 if (!xhci_alloc_virt_device(xhci, slot_id, udev, GFP_NOIO)) {
3878 xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
3881 vdev = xhci->devs[slot_id];
3882 slot_ctx = xhci_get_slot_ctx(xhci, vdev->out_ctx);
3883 trace_xhci_alloc_dev(slot_ctx);
3885 udev->slot_id = slot_id;
3887 xhci_debugfs_create_slot(xhci, slot_id);
3889 #ifndef CONFIG_USB_DEFAULT_PERSIST
3891 * If resetting upon resume, we can't put the controller into runtime
3892 * suspend if there is a device attached.
3894 if (xhci->quirks & XHCI_RESET_ON_RESUME)
3895 pm_runtime_get_noresume(hcd->self.controller);
3898 /* Is this a LS or FS device under a HS hub? */
3899 /* Hub or peripherial? */
3903 ret = xhci_disable_slot(xhci, udev->slot_id);
3905 xhci_free_virt_device(xhci, udev->slot_id);
3911 * Issue an Address Device command and optionally send a corresponding
3912 * SetAddress request to the device.
3914 static int xhci_setup_device(struct usb_hcd *hcd, struct usb_device *udev,
3915 enum xhci_setup_dev setup)
3917 const char *act = setup == SETUP_CONTEXT_ONLY ? "context" : "address";
3918 unsigned long flags;
3919 struct xhci_virt_device *virt_dev;
3921 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
3922 struct xhci_slot_ctx *slot_ctx;
3923 struct xhci_input_control_ctx *ctrl_ctx;
3925 struct xhci_command *command = NULL;
3927 mutex_lock(&xhci->mutex);
3929 if (xhci->xhc_state) { /* dying, removing or halted */
3934 if (!udev->slot_id) {
3935 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
3936 "Bad Slot ID %d", udev->slot_id);
3941 virt_dev = xhci->devs[udev->slot_id];
3943 if (WARN_ON(!virt_dev)) {
3945 * In plug/unplug torture test with an NEC controller,
3946 * a zero-dereference was observed once due to virt_dev = 0.
3947 * Print useful debug rather than crash if it is observed again!
3949 xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
3954 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
3955 trace_xhci_setup_device_slot(slot_ctx);
3957 if (setup == SETUP_CONTEXT_ONLY) {
3958 if (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state)) ==
3959 SLOT_STATE_DEFAULT) {
3960 xhci_dbg(xhci, "Slot already in default state\n");
3965 command = xhci_alloc_command(xhci, true, GFP_KERNEL);
3971 command->in_ctx = virt_dev->in_ctx;
3973 slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
3974 ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
3976 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
3982 * If this is the first Set Address since device plug-in or
3983 * virt_device realloaction after a resume with an xHCI power loss,
3984 * then set up the slot context.
3986 if (!slot_ctx->dev_info)
3987 xhci_setup_addressable_virt_dev(xhci, udev);
3988 /* Otherwise, update the control endpoint ring enqueue pointer. */
3990 xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
3991 ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
3992 ctrl_ctx->drop_flags = 0;
3994 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
3995 le32_to_cpu(slot_ctx->dev_info) >> 27);
3997 spin_lock_irqsave(&xhci->lock, flags);
3998 trace_xhci_setup_device(virt_dev);
3999 ret = xhci_queue_address_device(xhci, command, virt_dev->in_ctx->dma,
4000 udev->slot_id, setup);
4002 spin_unlock_irqrestore(&xhci->lock, flags);
4003 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4004 "FIXME: allocate a command ring segment");
4007 xhci_ring_cmd_db(xhci);
4008 spin_unlock_irqrestore(&xhci->lock, flags);
4010 /* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
4011 wait_for_completion(command->completion);
4013 /* FIXME: From section 4.3.4: "Software shall be responsible for timing
4014 * the SetAddress() "recovery interval" required by USB and aborting the
4015 * command on a timeout.
4017 switch (command->status) {
4018 case COMP_COMMAND_ABORTED:
4019 case COMP_COMMAND_RING_STOPPED:
4020 xhci_warn(xhci, "Timeout while waiting for setup device command\n");
4023 case COMP_CONTEXT_STATE_ERROR:
4024 case COMP_SLOT_NOT_ENABLED_ERROR:
4025 xhci_err(xhci, "Setup ERROR: setup %s command for slot %d.\n",
4026 act, udev->slot_id);
4029 case COMP_USB_TRANSACTION_ERROR:
4030 dev_warn(&udev->dev, "Device not responding to setup %s.\n", act);
4032 mutex_unlock(&xhci->mutex);
4033 ret = xhci_disable_slot(xhci, udev->slot_id);
4035 xhci_alloc_dev(hcd, udev);
4036 kfree(command->completion);
4039 case COMP_INCOMPATIBLE_DEVICE_ERROR:
4040 dev_warn(&udev->dev,
4041 "ERROR: Incompatible device for setup %s command\n", act);
4045 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4046 "Successful setup %s command", act);
4050 "ERROR: unexpected setup %s command completion code 0x%x.\n",
4051 act, command->status);
4052 trace_xhci_address_ctx(xhci, virt_dev->out_ctx, 1);
4058 temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
4059 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4060 "Op regs DCBAA ptr = %#016llx", temp_64);
4061 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4062 "Slot ID %d dcbaa entry @%p = %#016llx",
4064 &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
4065 (unsigned long long)
4066 le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
4067 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4068 "Output Context DMA address = %#08llx",
4069 (unsigned long long)virt_dev->out_ctx->dma);
4070 trace_xhci_address_ctx(xhci, virt_dev->in_ctx,
4071 le32_to_cpu(slot_ctx->dev_info) >> 27);
4073 * USB core uses address 1 for the roothubs, so we add one to the
4074 * address given back to us by the HC.
4076 trace_xhci_address_ctx(xhci, virt_dev->out_ctx,
4077 le32_to_cpu(slot_ctx->dev_info) >> 27);
4078 /* Zero the input context control for later use */
4079 ctrl_ctx->add_flags = 0;
4080 ctrl_ctx->drop_flags = 0;
4082 xhci_dbg_trace(xhci, trace_xhci_dbg_address,
4083 "Internal device address = %d",
4084 le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
4086 mutex_unlock(&xhci->mutex);
4088 kfree(command->completion);
4094 static int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
4096 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ADDRESS);
4099 static int xhci_enable_device(struct usb_hcd *hcd, struct usb_device *udev)
4101 return xhci_setup_device(hcd, udev, SETUP_CONTEXT_ONLY);
4105 * Transfer the port index into real index in the HW port status
4106 * registers. Caculate offset between the port's PORTSC register
4107 * and port status base. Divide the number of per port register
4108 * to get the real index. The raw port number bases 1.
4110 int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1)
4112 struct xhci_hub *rhub;
4114 rhub = xhci_get_rhub(hcd);
4115 return rhub->ports[port1 - 1]->hw_portnum + 1;
4119 * Issue an Evaluate Context command to change the Maximum Exit Latency in the
4120 * slot context. If that succeeds, store the new MEL in the xhci_virt_device.
4122 static int __maybe_unused xhci_change_max_exit_latency(struct xhci_hcd *xhci,
4123 struct usb_device *udev, u16 max_exit_latency)
4125 struct xhci_virt_device *virt_dev;
4126 struct xhci_command *command;
4127 struct xhci_input_control_ctx *ctrl_ctx;
4128 struct xhci_slot_ctx *slot_ctx;
4129 unsigned long flags;
4132 spin_lock_irqsave(&xhci->lock, flags);
4134 virt_dev = xhci->devs[udev->slot_id];
4137 * virt_dev might not exists yet if xHC resumed from hibernate (S4) and
4138 * xHC was re-initialized. Exit latency will be set later after
4139 * hub_port_finish_reset() is done and xhci->devs[] are re-allocated
4142 if (!virt_dev || max_exit_latency == virt_dev->current_mel) {
4143 spin_unlock_irqrestore(&xhci->lock, flags);
4147 /* Attempt to issue an Evaluate Context command to change the MEL. */
4148 command = xhci->lpm_command;
4149 ctrl_ctx = xhci_get_input_control_ctx(command->in_ctx);
4151 spin_unlock_irqrestore(&xhci->lock, flags);
4152 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4157 xhci_slot_copy(xhci, command->in_ctx, virt_dev->out_ctx);
4158 spin_unlock_irqrestore(&xhci->lock, flags);
4160 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4161 slot_ctx = xhci_get_slot_ctx(xhci, command->in_ctx);
4162 slot_ctx->dev_info2 &= cpu_to_le32(~((u32) MAX_EXIT));
4163 slot_ctx->dev_info2 |= cpu_to_le32(max_exit_latency);
4164 slot_ctx->dev_state = 0;
4166 xhci_dbg_trace(xhci, trace_xhci_dbg_context_change,
4167 "Set up evaluate context for LPM MEL change.");
4169 /* Issue and wait for the evaluate context command. */
4170 ret = xhci_configure_endpoint(xhci, udev, command,
4174 spin_lock_irqsave(&xhci->lock, flags);
4175 virt_dev->current_mel = max_exit_latency;
4176 spin_unlock_irqrestore(&xhci->lock, flags);
4183 /* BESL to HIRD Encoding array for USB2 LPM */
4184 static int xhci_besl_encoding[16] = {125, 150, 200, 300, 400, 500, 1000, 2000,
4185 3000, 4000, 5000, 6000, 7000, 8000, 9000, 10000};
4187 /* Calculate HIRD/BESL for USB2 PORTPMSC*/
4188 static int xhci_calculate_hird_besl(struct xhci_hcd *xhci,
4189 struct usb_device *udev)
4191 int u2del, besl, besl_host;
4192 int besl_device = 0;
4195 u2del = HCS_U2_LATENCY(xhci->hcs_params3);
4196 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4198 if (field & USB_BESL_SUPPORT) {
4199 for (besl_host = 0; besl_host < 16; besl_host++) {
4200 if (xhci_besl_encoding[besl_host] >= u2del)
4203 /* Use baseline BESL value as default */
4204 if (field & USB_BESL_BASELINE_VALID)
4205 besl_device = USB_GET_BESL_BASELINE(field);
4206 else if (field & USB_BESL_DEEP_VALID)
4207 besl_device = USB_GET_BESL_DEEP(field);
4212 besl_host = (u2del - 51) / 75 + 1;
4215 besl = besl_host + besl_device;
4222 /* Calculate BESLD, L1 timeout and HIRDM for USB2 PORTHLPMC */
4223 static int xhci_calculate_usb2_hw_lpm_params(struct usb_device *udev)
4230 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4232 /* xHCI l1 is set in steps of 256us, xHCI 1.0 section 5.4.11.2 */
4233 l1 = udev->l1_params.timeout / 256;
4235 /* device has preferred BESLD */
4236 if (field & USB_BESL_DEEP_VALID) {
4237 besld = USB_GET_BESL_DEEP(field);
4241 return PORT_BESLD(besld) | PORT_L1_TIMEOUT(l1) | PORT_HIRDM(hirdm);
4244 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4245 struct usb_device *udev, int enable)
4247 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4248 struct xhci_port **ports;
4249 __le32 __iomem *pm_addr, *hlpm_addr;
4250 u32 pm_val, hlpm_val, field;
4251 unsigned int port_num;
4252 unsigned long flags;
4253 int hird, exit_latency;
4256 if (hcd->speed >= HCD_USB3 || !xhci->hw_lpm_support ||
4260 if (!udev->parent || udev->parent->parent ||
4261 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4264 if (udev->usb2_hw_lpm_capable != 1)
4267 spin_lock_irqsave(&xhci->lock, flags);
4269 ports = xhci->usb2_rhub.ports;
4270 port_num = udev->portnum - 1;
4271 pm_addr = ports[port_num]->addr + PORTPMSC;
4272 pm_val = readl(pm_addr);
4273 hlpm_addr = ports[port_num]->addr + PORTHLPMC;
4274 field = le32_to_cpu(udev->bos->ext_cap->bmAttributes);
4276 xhci_dbg(xhci, "%s port %d USB2 hardware LPM\n",
4277 enable ? "enable" : "disable", port_num + 1);
4279 if (enable && !(xhci->quirks & XHCI_HW_LPM_DISABLE)) {
4280 /* Host supports BESL timeout instead of HIRD */
4281 if (udev->usb2_hw_lpm_besl_capable) {
4282 /* if device doesn't have a preferred BESL value use a
4283 * default one which works with mixed HIRD and BESL
4284 * systems. See XHCI_DEFAULT_BESL definition in xhci.h
4286 if ((field & USB_BESL_SUPPORT) &&
4287 (field & USB_BESL_BASELINE_VALID))
4288 hird = USB_GET_BESL_BASELINE(field);
4290 hird = udev->l1_params.besl;
4292 exit_latency = xhci_besl_encoding[hird];
4293 spin_unlock_irqrestore(&xhci->lock, flags);
4295 /* USB 3.0 code dedicate one xhci->lpm_command->in_ctx
4296 * input context for link powermanagement evaluate
4297 * context commands. It is protected by hcd->bandwidth
4298 * mutex and is shared by all devices. We need to set
4299 * the max ext latency in USB 2 BESL LPM as well, so
4300 * use the same mutex and xhci_change_max_exit_latency()
4302 mutex_lock(hcd->bandwidth_mutex);
4303 ret = xhci_change_max_exit_latency(xhci, udev,
4305 mutex_unlock(hcd->bandwidth_mutex);
4309 spin_lock_irqsave(&xhci->lock, flags);
4311 hlpm_val = xhci_calculate_usb2_hw_lpm_params(udev);
4312 writel(hlpm_val, hlpm_addr);
4316 hird = xhci_calculate_hird_besl(xhci, udev);
4319 pm_val &= ~PORT_HIRD_MASK;
4320 pm_val |= PORT_HIRD(hird) | PORT_RWE | PORT_L1DS(udev->slot_id);
4321 writel(pm_val, pm_addr);
4322 pm_val = readl(pm_addr);
4324 writel(pm_val, pm_addr);
4328 pm_val &= ~(PORT_HLE | PORT_RWE | PORT_HIRD_MASK | PORT_L1DS_MASK);
4329 writel(pm_val, pm_addr);
4332 if (udev->usb2_hw_lpm_besl_capable) {
4333 spin_unlock_irqrestore(&xhci->lock, flags);
4334 mutex_lock(hcd->bandwidth_mutex);
4335 xhci_change_max_exit_latency(xhci, udev, 0);
4336 mutex_unlock(hcd->bandwidth_mutex);
4341 spin_unlock_irqrestore(&xhci->lock, flags);
4345 /* check if a usb2 port supports a given extened capability protocol
4346 * only USB2 ports extended protocol capability values are cached.
4347 * Return 1 if capability is supported
4349 static int xhci_check_usb2_port_capability(struct xhci_hcd *xhci, int port,
4350 unsigned capability)
4352 u32 port_offset, port_count;
4355 for (i = 0; i < xhci->num_ext_caps; i++) {
4356 if (xhci->ext_caps[i] & capability) {
4357 /* port offsets starts at 1 */
4358 port_offset = XHCI_EXT_PORT_OFF(xhci->ext_caps[i]) - 1;
4359 port_count = XHCI_EXT_PORT_COUNT(xhci->ext_caps[i]);
4360 if (port >= port_offset &&
4361 port < port_offset + port_count)
4368 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4370 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4371 int portnum = udev->portnum - 1;
4373 if (hcd->speed >= HCD_USB3 || !xhci->sw_lpm_support ||
4377 /* we only support lpm for non-hub device connected to root hub yet */
4378 if (!udev->parent || udev->parent->parent ||
4379 udev->descriptor.bDeviceClass == USB_CLASS_HUB)
4382 if (xhci->hw_lpm_support == 1 &&
4383 xhci_check_usb2_port_capability(
4384 xhci, portnum, XHCI_HLC)) {
4385 udev->usb2_hw_lpm_capable = 1;
4386 udev->l1_params.timeout = XHCI_L1_TIMEOUT;
4387 udev->l1_params.besl = XHCI_DEFAULT_BESL;
4388 if (xhci_check_usb2_port_capability(xhci, portnum,
4390 udev->usb2_hw_lpm_besl_capable = 1;
4396 /*---------------------- USB 3.0 Link PM functions ------------------------*/
4398 /* Service interval in nanoseconds = 2^(bInterval - 1) * 125us * 1000ns / 1us */
4399 static unsigned long long xhci_service_interval_to_ns(
4400 struct usb_endpoint_descriptor *desc)
4402 return (1ULL << (desc->bInterval - 1)) * 125 * 1000;
4405 static u16 xhci_get_timeout_no_hub_lpm(struct usb_device *udev,
4406 enum usb3_link_state state)
4408 unsigned long long sel;
4409 unsigned long long pel;
4410 unsigned int max_sel_pel;
4415 /* Convert SEL and PEL stored in nanoseconds to microseconds */
4416 sel = DIV_ROUND_UP(udev->u1_params.sel, 1000);
4417 pel = DIV_ROUND_UP(udev->u1_params.pel, 1000);
4418 max_sel_pel = USB3_LPM_MAX_U1_SEL_PEL;
4422 sel = DIV_ROUND_UP(udev->u2_params.sel, 1000);
4423 pel = DIV_ROUND_UP(udev->u2_params.pel, 1000);
4424 max_sel_pel = USB3_LPM_MAX_U2_SEL_PEL;
4428 dev_warn(&udev->dev, "%s: Can't get timeout for non-U1 or U2 state.\n",
4430 return USB3_LPM_DISABLED;
4433 if (sel <= max_sel_pel && pel <= max_sel_pel)
4434 return USB3_LPM_DEVICE_INITIATED;
4436 if (sel > max_sel_pel)
4437 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4438 "due to long SEL %llu ms\n",
4441 dev_dbg(&udev->dev, "Device-initiated %s disabled "
4442 "due to long PEL %llu ms\n",
4444 return USB3_LPM_DISABLED;
4447 /* The U1 timeout should be the maximum of the following values:
4448 * - For control endpoints, U1 system exit latency (SEL) * 3
4449 * - For bulk endpoints, U1 SEL * 5
4450 * - For interrupt endpoints:
4451 * - Notification EPs, U1 SEL * 3
4452 * - Periodic EPs, max(105% of bInterval, U1 SEL * 2)
4453 * - For isochronous endpoints, max(105% of bInterval, U1 SEL * 2)
4455 static unsigned long long xhci_calculate_intel_u1_timeout(
4456 struct usb_device *udev,
4457 struct usb_endpoint_descriptor *desc)
4459 unsigned long long timeout_ns;
4463 ep_type = usb_endpoint_type(desc);
4465 case USB_ENDPOINT_XFER_CONTROL:
4466 timeout_ns = udev->u1_params.sel * 3;
4468 case USB_ENDPOINT_XFER_BULK:
4469 timeout_ns = udev->u1_params.sel * 5;
4471 case USB_ENDPOINT_XFER_INT:
4472 intr_type = usb_endpoint_interrupt_type(desc);
4473 if (intr_type == USB_ENDPOINT_INTR_NOTIFICATION) {
4474 timeout_ns = udev->u1_params.sel * 3;
4477 /* Otherwise the calculation is the same as isoc eps */
4479 case USB_ENDPOINT_XFER_ISOC:
4480 timeout_ns = xhci_service_interval_to_ns(desc);
4481 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns * 105, 100);
4482 if (timeout_ns < udev->u1_params.sel * 2)
4483 timeout_ns = udev->u1_params.sel * 2;
4492 /* Returns the hub-encoded U1 timeout value. */
4493 static u16 xhci_calculate_u1_timeout(struct xhci_hcd *xhci,
4494 struct usb_device *udev,
4495 struct usb_endpoint_descriptor *desc)
4497 unsigned long long timeout_ns;
4499 if (xhci->quirks & XHCI_INTEL_HOST)
4500 timeout_ns = xhci_calculate_intel_u1_timeout(udev, desc);
4502 timeout_ns = udev->u1_params.sel;
4504 /* The U1 timeout is encoded in 1us intervals.
4505 * Don't return a timeout of zero, because that's USB3_LPM_DISABLED.
4507 if (timeout_ns == USB3_LPM_DISABLED)
4510 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 1000);
4512 /* If the necessary timeout value is bigger than what we can set in the
4513 * USB 3.0 hub, we have to disable hub-initiated U1.
4515 if (timeout_ns <= USB3_LPM_U1_MAX_TIMEOUT)
4517 dev_dbg(&udev->dev, "Hub-initiated U1 disabled "
4518 "due to long timeout %llu ms\n", timeout_ns);
4519 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U1);
4522 /* The U2 timeout should be the maximum of:
4523 * - 10 ms (to avoid the bandwidth impact on the scheduler)
4524 * - largest bInterval of any active periodic endpoint (to avoid going
4525 * into lower power link states between intervals).
4526 * - the U2 Exit Latency of the device
4528 static unsigned long long xhci_calculate_intel_u2_timeout(
4529 struct usb_device *udev,
4530 struct usb_endpoint_descriptor *desc)
4532 unsigned long long timeout_ns;
4533 unsigned long long u2_del_ns;
4535 timeout_ns = 10 * 1000 * 1000;
4537 if ((usb_endpoint_xfer_int(desc) || usb_endpoint_xfer_isoc(desc)) &&
4538 (xhci_service_interval_to_ns(desc) > timeout_ns))
4539 timeout_ns = xhci_service_interval_to_ns(desc);
4541 u2_del_ns = le16_to_cpu(udev->bos->ss_cap->bU2DevExitLat) * 1000ULL;
4542 if (u2_del_ns > timeout_ns)
4543 timeout_ns = u2_del_ns;
4548 /* Returns the hub-encoded U2 timeout value. */
4549 static u16 xhci_calculate_u2_timeout(struct xhci_hcd *xhci,
4550 struct usb_device *udev,
4551 struct usb_endpoint_descriptor *desc)
4553 unsigned long long timeout_ns;
4555 if (xhci->quirks & XHCI_INTEL_HOST)
4556 timeout_ns = xhci_calculate_intel_u2_timeout(udev, desc);
4558 timeout_ns = udev->u2_params.sel;
4560 /* The U2 timeout is encoded in 256us intervals */
4561 timeout_ns = DIV_ROUND_UP_ULL(timeout_ns, 256 * 1000);
4562 /* If the necessary timeout value is bigger than what we can set in the
4563 * USB 3.0 hub, we have to disable hub-initiated U2.
4565 if (timeout_ns <= USB3_LPM_U2_MAX_TIMEOUT)
4567 dev_dbg(&udev->dev, "Hub-initiated U2 disabled "
4568 "due to long timeout %llu ms\n", timeout_ns);
4569 return xhci_get_timeout_no_hub_lpm(udev, USB3_LPM_U2);
4572 static u16 xhci_call_host_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4573 struct usb_device *udev,
4574 struct usb_endpoint_descriptor *desc,
4575 enum usb3_link_state state,
4578 if (state == USB3_LPM_U1)
4579 return xhci_calculate_u1_timeout(xhci, udev, desc);
4580 else if (state == USB3_LPM_U2)
4581 return xhci_calculate_u2_timeout(xhci, udev, desc);
4583 return USB3_LPM_DISABLED;
4586 static int xhci_update_timeout_for_endpoint(struct xhci_hcd *xhci,
4587 struct usb_device *udev,
4588 struct usb_endpoint_descriptor *desc,
4589 enum usb3_link_state state,
4594 alt_timeout = xhci_call_host_update_timeout_for_endpoint(xhci, udev,
4595 desc, state, timeout);
4597 /* If we found we can't enable hub-initiated LPM, or
4598 * the U1 or U2 exit latency was too high to allow
4599 * device-initiated LPM as well, just stop searching.
4601 if (alt_timeout == USB3_LPM_DISABLED ||
4602 alt_timeout == USB3_LPM_DEVICE_INITIATED) {
4603 *timeout = alt_timeout;
4606 if (alt_timeout > *timeout)
4607 *timeout = alt_timeout;
4611 static int xhci_update_timeout_for_interface(struct xhci_hcd *xhci,
4612 struct usb_device *udev,
4613 struct usb_host_interface *alt,
4614 enum usb3_link_state state,
4619 for (j = 0; j < alt->desc.bNumEndpoints; j++) {
4620 if (xhci_update_timeout_for_endpoint(xhci, udev,
4621 &alt->endpoint[j].desc, state, timeout))
4628 static int xhci_check_intel_tier_policy(struct usb_device *udev,
4629 enum usb3_link_state state)
4631 struct usb_device *parent;
4632 unsigned int num_hubs;
4634 if (state == USB3_LPM_U2)
4637 /* Don't enable U1 if the device is on a 2nd tier hub or lower. */
4638 for (parent = udev->parent, num_hubs = 0; parent->parent;
4639 parent = parent->parent)
4645 dev_dbg(&udev->dev, "Disabling U1 link state for device"
4646 " below second-tier hub.\n");
4647 dev_dbg(&udev->dev, "Plug device into first-tier hub "
4648 "to decrease power consumption.\n");
4652 static int xhci_check_tier_policy(struct xhci_hcd *xhci,
4653 struct usb_device *udev,
4654 enum usb3_link_state state)
4656 if (xhci->quirks & XHCI_INTEL_HOST)
4657 return xhci_check_intel_tier_policy(udev, state);
4662 /* Returns the U1 or U2 timeout that should be enabled.
4663 * If the tier check or timeout setting functions return with a non-zero exit
4664 * code, that means the timeout value has been finalized and we shouldn't look
4665 * at any more endpoints.
4667 static u16 xhci_calculate_lpm_timeout(struct usb_hcd *hcd,
4668 struct usb_device *udev, enum usb3_link_state state)
4670 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4671 struct usb_host_config *config;
4674 u16 timeout = USB3_LPM_DISABLED;
4676 if (state == USB3_LPM_U1)
4678 else if (state == USB3_LPM_U2)
4681 dev_warn(&udev->dev, "Can't enable unknown link state %i\n",
4686 if (xhci_check_tier_policy(xhci, udev, state) < 0)
4689 /* Gather some information about the currently installed configuration
4690 * and alternate interface settings.
4692 if (xhci_update_timeout_for_endpoint(xhci, udev, &udev->ep0.desc,
4696 config = udev->actconfig;
4700 for (i = 0; i < config->desc.bNumInterfaces; i++) {
4701 struct usb_driver *driver;
4702 struct usb_interface *intf = config->interface[i];
4707 /* Check if any currently bound drivers want hub-initiated LPM
4710 if (intf->dev.driver) {
4711 driver = to_usb_driver(intf->dev.driver);
4712 if (driver && driver->disable_hub_initiated_lpm) {
4713 dev_dbg(&udev->dev, "Hub-initiated %s disabled "
4714 "at request of driver %s\n",
4715 state_name, driver->name);
4716 return xhci_get_timeout_no_hub_lpm(udev, state);
4720 /* Not sure how this could happen... */
4721 if (!intf->cur_altsetting)
4724 if (xhci_update_timeout_for_interface(xhci, udev,
4725 intf->cur_altsetting,
4732 static int calculate_max_exit_latency(struct usb_device *udev,
4733 enum usb3_link_state state_changed,
4734 u16 hub_encoded_timeout)
4736 unsigned long long u1_mel_us = 0;
4737 unsigned long long u2_mel_us = 0;
4738 unsigned long long mel_us = 0;
4744 disabling_u1 = (state_changed == USB3_LPM_U1 &&
4745 hub_encoded_timeout == USB3_LPM_DISABLED);
4746 disabling_u2 = (state_changed == USB3_LPM_U2 &&
4747 hub_encoded_timeout == USB3_LPM_DISABLED);
4749 enabling_u1 = (state_changed == USB3_LPM_U1 &&
4750 hub_encoded_timeout != USB3_LPM_DISABLED);
4751 enabling_u2 = (state_changed == USB3_LPM_U2 &&
4752 hub_encoded_timeout != USB3_LPM_DISABLED);
4754 /* If U1 was already enabled and we're not disabling it,
4755 * or we're going to enable U1, account for the U1 max exit latency.
4757 if ((udev->u1_params.timeout != USB3_LPM_DISABLED && !disabling_u1) ||
4759 u1_mel_us = DIV_ROUND_UP(udev->u1_params.mel, 1000);
4760 if ((udev->u2_params.timeout != USB3_LPM_DISABLED && !disabling_u2) ||
4762 u2_mel_us = DIV_ROUND_UP(udev->u2_params.mel, 1000);
4764 if (u1_mel_us > u2_mel_us)
4768 /* xHCI host controller max exit latency field is only 16 bits wide. */
4769 if (mel_us > MAX_EXIT) {
4770 dev_warn(&udev->dev, "Link PM max exit latency of %lluus "
4771 "is too big.\n", mel_us);
4777 /* Returns the USB3 hub-encoded value for the U1/U2 timeout. */
4778 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4779 struct usb_device *udev, enum usb3_link_state state)
4781 struct xhci_hcd *xhci;
4782 u16 hub_encoded_timeout;
4786 xhci = hcd_to_xhci(hcd);
4787 /* The LPM timeout values are pretty host-controller specific, so don't
4788 * enable hub-initiated timeouts unless the vendor has provided
4789 * information about their timeout algorithm.
4791 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4792 !xhci->devs[udev->slot_id])
4793 return USB3_LPM_DISABLED;
4795 hub_encoded_timeout = xhci_calculate_lpm_timeout(hcd, udev, state);
4796 mel = calculate_max_exit_latency(udev, state, hub_encoded_timeout);
4798 /* Max Exit Latency is too big, disable LPM. */
4799 hub_encoded_timeout = USB3_LPM_DISABLED;
4803 ret = xhci_change_max_exit_latency(xhci, udev, mel);
4806 return hub_encoded_timeout;
4809 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4810 struct usb_device *udev, enum usb3_link_state state)
4812 struct xhci_hcd *xhci;
4815 xhci = hcd_to_xhci(hcd);
4816 if (!xhci || !(xhci->quirks & XHCI_LPM_SUPPORT) ||
4817 !xhci->devs[udev->slot_id])
4820 mel = calculate_max_exit_latency(udev, state, USB3_LPM_DISABLED);
4821 return xhci_change_max_exit_latency(xhci, udev, mel);
4823 #else /* CONFIG_PM */
4825 static int xhci_set_usb2_hardware_lpm(struct usb_hcd *hcd,
4826 struct usb_device *udev, int enable)
4831 static int xhci_update_device(struct usb_hcd *hcd, struct usb_device *udev)
4836 static int xhci_enable_usb3_lpm_timeout(struct usb_hcd *hcd,
4837 struct usb_device *udev, enum usb3_link_state state)
4839 return USB3_LPM_DISABLED;
4842 static int xhci_disable_usb3_lpm_timeout(struct usb_hcd *hcd,
4843 struct usb_device *udev, enum usb3_link_state state)
4847 #endif /* CONFIG_PM */
4849 /*-------------------------------------------------------------------------*/
4851 /* Once a hub descriptor is fetched for a device, we need to update the xHC's
4852 * internal data structures for the device.
4854 static int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
4855 struct usb_tt *tt, gfp_t mem_flags)
4857 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4858 struct xhci_virt_device *vdev;
4859 struct xhci_command *config_cmd;
4860 struct xhci_input_control_ctx *ctrl_ctx;
4861 struct xhci_slot_ctx *slot_ctx;
4862 unsigned long flags;
4863 unsigned think_time;
4866 /* Ignore root hubs */
4870 vdev = xhci->devs[hdev->slot_id];
4872 xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
4876 config_cmd = xhci_alloc_command_with_ctx(xhci, true, mem_flags);
4880 ctrl_ctx = xhci_get_input_control_ctx(config_cmd->in_ctx);
4882 xhci_warn(xhci, "%s: Could not get input context, bad type.\n",
4884 xhci_free_command(xhci, config_cmd);
4888 spin_lock_irqsave(&xhci->lock, flags);
4889 if (hdev->speed == USB_SPEED_HIGH &&
4890 xhci_alloc_tt_info(xhci, vdev, hdev, tt, GFP_ATOMIC)) {
4891 xhci_dbg(xhci, "Could not allocate xHCI TT structure.\n");
4892 xhci_free_command(xhci, config_cmd);
4893 spin_unlock_irqrestore(&xhci->lock, flags);
4897 xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
4898 ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
4899 slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
4900 slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
4902 * refer to section 6.2.2: MTT should be 0 for full speed hub,
4903 * but it may be already set to 1 when setup an xHCI virtual
4904 * device, so clear it anyway.
4907 slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
4908 else if (hdev->speed == USB_SPEED_FULL)
4909 slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
4911 if (xhci->hci_version > 0x95) {
4912 xhci_dbg(xhci, "xHCI version %x needs hub "
4913 "TT think time and number of ports\n",
4914 (unsigned int) xhci->hci_version);
4915 slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
4916 /* Set TT think time - convert from ns to FS bit times.
4917 * 0 = 8 FS bit times, 1 = 16 FS bit times,
4918 * 2 = 24 FS bit times, 3 = 32 FS bit times.
4920 * xHCI 1.0: this field shall be 0 if the device is not a
4923 think_time = tt->think_time;
4924 if (think_time != 0)
4925 think_time = (think_time / 666) - 1;
4926 if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
4927 slot_ctx->tt_info |=
4928 cpu_to_le32(TT_THINK_TIME(think_time));
4930 xhci_dbg(xhci, "xHCI version %x doesn't need hub "
4931 "TT think time or number of ports\n",
4932 (unsigned int) xhci->hci_version);
4934 slot_ctx->dev_state = 0;
4935 spin_unlock_irqrestore(&xhci->lock, flags);
4937 xhci_dbg(xhci, "Set up %s for hub device.\n",
4938 (xhci->hci_version > 0x95) ?
4939 "configure endpoint" : "evaluate context");
4941 /* Issue and wait for the configure endpoint or
4942 * evaluate context command.
4944 if (xhci->hci_version > 0x95)
4945 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4948 ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
4951 xhci_free_command(xhci, config_cmd);
4955 static int xhci_get_frame(struct usb_hcd *hcd)
4957 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
4958 /* EHCI mods by the periodic size. Why? */
4959 return readl(&xhci->run_regs->microframe_index) >> 3;
4962 int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks)
4964 struct xhci_hcd *xhci;
4966 * TODO: Check with DWC3 clients for sysdev according to
4969 struct device *dev = hcd->self.sysdev;
4970 unsigned int minor_rev;
4973 /* Accept arbitrarily long scatter-gather lists */
4974 hcd->self.sg_tablesize = ~0;
4976 /* support to build packet from discontinuous buffers */
4977 hcd->self.no_sg_constraint = 1;
4979 /* XHCI controllers don't stop the ep queue on short packets :| */
4980 hcd->self.no_stop_on_short = 1;
4982 xhci = hcd_to_xhci(hcd);
4984 if (usb_hcd_is_primary_hcd(hcd)) {
4985 xhci->main_hcd = hcd;
4986 xhci->usb2_rhub.hcd = hcd;
4987 /* Mark the first roothub as being USB 2.0.
4988 * The xHCI driver will register the USB 3.0 roothub.
4990 hcd->speed = HCD_USB2;
4991 hcd->self.root_hub->speed = USB_SPEED_HIGH;
4993 * USB 2.0 roothub under xHCI has an integrated TT,
4994 * (rate matching hub) as opposed to having an OHCI/UHCI
4995 * companion controller.
5000 * Some 3.1 hosts return sbrn 0x30, use xhci supported protocol
5001 * minor revision instead of sbrn
5003 minor_rev = xhci->usb3_rhub.min_rev;
5005 hcd->speed = HCD_USB31;
5006 hcd->self.root_hub->speed = USB_SPEED_SUPER_PLUS;
5008 xhci_info(xhci, "Host supports USB 3.%x %s SuperSpeed\n",
5010 minor_rev ? "Enhanced" : "");
5012 xhci->usb3_rhub.hcd = hcd;
5013 /* xHCI private pointer was set in xhci_pci_probe for the second
5014 * registered roothub.
5019 mutex_init(&xhci->mutex);
5020 xhci->cap_regs = hcd->regs;
5021 xhci->op_regs = hcd->regs +
5022 HC_LENGTH(readl(&xhci->cap_regs->hc_capbase));
5023 xhci->run_regs = hcd->regs +
5024 (readl(&xhci->cap_regs->run_regs_off) & RTSOFF_MASK);
5025 /* Cache read-only capability registers */
5026 xhci->hcs_params1 = readl(&xhci->cap_regs->hcs_params1);
5027 xhci->hcs_params2 = readl(&xhci->cap_regs->hcs_params2);
5028 xhci->hcs_params3 = readl(&xhci->cap_regs->hcs_params3);
5029 xhci->hcc_params = readl(&xhci->cap_regs->hc_capbase);
5030 xhci->hci_version = HC_VERSION(xhci->hcc_params);
5031 xhci->hcc_params = readl(&xhci->cap_regs->hcc_params);
5032 if (xhci->hci_version > 0x100)
5033 xhci->hcc_params2 = readl(&xhci->cap_regs->hcc_params2);
5035 xhci->quirks |= quirks;
5037 get_quirks(dev, xhci);
5039 /* In xhci controllers which follow xhci 1.0 spec gives a spurious
5040 * success event after a short transfer. This quirk will ignore such
5043 if (xhci->hci_version > 0x96)
5044 xhci->quirks |= XHCI_SPURIOUS_SUCCESS;
5046 /* Make sure the HC is halted. */
5047 retval = xhci_halt(xhci);
5051 xhci_zero_64b_regs(xhci);
5053 xhci_dbg(xhci, "Resetting HCD\n");
5054 /* Reset the internal HC memory state and registers. */
5055 retval = xhci_reset(xhci);
5058 xhci_dbg(xhci, "Reset complete\n");
5061 * On some xHCI controllers (e.g. R-Car SoCs), the AC64 bit (bit 0)
5062 * of HCCPARAMS1 is set to 1. However, the xHCs don't support 64-bit
5063 * address memory pointers actually. So, this driver clears the AC64
5064 * bit of xhci->hcc_params to call dma_set_coherent_mask(dev,
5065 * DMA_BIT_MASK(32)) in this xhci_gen_setup().
5067 if (xhci->quirks & XHCI_NO_64BIT_SUPPORT)
5068 xhci->hcc_params &= ~BIT(0);
5070 /* Set dma_mask and coherent_dma_mask to 64-bits,
5071 * if xHC supports 64-bit addressing */
5072 if (HCC_64BIT_ADDR(xhci->hcc_params) &&
5073 !dma_set_mask(dev, DMA_BIT_MASK(64))) {
5074 xhci_dbg(xhci, "Enabling 64-bit DMA addresses.\n");
5075 dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
5078 * This is to avoid error in cases where a 32-bit USB
5079 * controller is used on a 64-bit capable system.
5081 retval = dma_set_mask(dev, DMA_BIT_MASK(32));
5084 xhci_dbg(xhci, "Enabling 32-bit DMA addresses.\n");
5085 dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
5088 xhci_dbg(xhci, "Calling HCD init\n");
5089 /* Initialize HCD and host controller data structures. */
5090 retval = xhci_init(hcd);
5093 xhci_dbg(xhci, "Called HCD init\n");
5095 xhci_info(xhci, "hcc params 0x%08x hci version 0x%x quirks 0x%016llx\n",
5096 xhci->hcc_params, xhci->hci_version, xhci->quirks);
5100 EXPORT_SYMBOL_GPL(xhci_gen_setup);
5102 static const struct hc_driver xhci_hc_driver = {
5103 .description = "xhci-hcd",
5104 .product_desc = "xHCI Host Controller",
5105 .hcd_priv_size = sizeof(struct xhci_hcd),
5108 * generic hardware linkage
5111 .flags = HCD_MEMORY | HCD_USB3 | HCD_SHARED,
5114 * basic lifecycle operations
5116 .reset = NULL, /* set in xhci_init_driver() */
5119 .shutdown = xhci_shutdown,
5122 * managing i/o requests and associated device resources
5124 .urb_enqueue = xhci_urb_enqueue,
5125 .urb_dequeue = xhci_urb_dequeue,
5126 .alloc_dev = xhci_alloc_dev,
5127 .free_dev = xhci_free_dev,
5128 .alloc_streams = xhci_alloc_streams,
5129 .free_streams = xhci_free_streams,
5130 .add_endpoint = xhci_add_endpoint,
5131 .drop_endpoint = xhci_drop_endpoint,
5132 .endpoint_reset = xhci_endpoint_reset,
5133 .check_bandwidth = xhci_check_bandwidth,
5134 .reset_bandwidth = xhci_reset_bandwidth,
5135 .address_device = xhci_address_device,
5136 .enable_device = xhci_enable_device,
5137 .update_hub_device = xhci_update_hub_device,
5138 .reset_device = xhci_discover_or_reset_device,
5141 * scheduling support
5143 .get_frame_number = xhci_get_frame,
5148 .hub_control = xhci_hub_control,
5149 .hub_status_data = xhci_hub_status_data,
5150 .bus_suspend = xhci_bus_suspend,
5151 .bus_resume = xhci_bus_resume,
5152 .get_resuming_ports = xhci_get_resuming_ports,
5155 * call back when device connected and addressed
5157 .update_device = xhci_update_device,
5158 .set_usb2_hw_lpm = xhci_set_usb2_hardware_lpm,
5159 .enable_usb3_lpm_timeout = xhci_enable_usb3_lpm_timeout,
5160 .disable_usb3_lpm_timeout = xhci_disable_usb3_lpm_timeout,
5161 .find_raw_port_number = xhci_find_raw_port_number,
5164 void xhci_init_driver(struct hc_driver *drv,
5165 const struct xhci_driver_overrides *over)
5169 /* Copy the generic table to drv then apply the overrides */
5170 *drv = xhci_hc_driver;
5173 drv->hcd_priv_size += over->extra_priv_size;
5175 drv->reset = over->reset;
5177 drv->start = over->start;
5180 EXPORT_SYMBOL_GPL(xhci_init_driver);
5182 MODULE_DESCRIPTION(DRIVER_DESC);
5183 MODULE_AUTHOR(DRIVER_AUTHOR);
5184 MODULE_LICENSE("GPL");
5186 static int __init xhci_hcd_init(void)
5189 * Check the compiler generated sizes of structures that must be laid
5190 * out in specific ways for hardware access.
5192 BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
5193 BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
5194 BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
5195 /* xhci_device_control has eight fields, and also
5196 * embeds one xhci_slot_ctx and 31 xhci_ep_ctx
5198 BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
5199 BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
5200 BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
5201 BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 8*32/8);
5202 BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
5203 /* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
5204 BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
5209 xhci_debugfs_create_root();
5215 * If an init function is provided, an exit function must also be provided
5216 * to allow module unload.
5218 static void __exit xhci_hcd_fini(void)
5220 xhci_debugfs_remove_root();
5223 module_init(xhci_hcd_init);
5224 module_exit(xhci_hcd_fini);