drivers/usb/phy/phy-tegra-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2010 Google, Inc.
   4  * Copyright (C) 2013 NVIDIA Corporation
   5  *
   6  * Author:
   7  *      Erik Gilling <konkers@google.com>
   8  *      Benoit Goby <benoit@android.com>
   9  *      Venu Byravarasu <vbyravarasu@nvidia.com>
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/err.h>
  14 #include <linux/export.h>
  15 #include <linux/gpio.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/resource.h>
  23 #include <linux/slab.h>
  24 #include <linux/spinlock.h>
  25
  26 #include <linux/regulator/consumer.h>
  27
  28 #include <linux/usb/ehci_def.h>
  29 #include <linux/usb/of.h>
  30 #include <linux/usb/tegra_usb_phy.h>
  31 #include <linux/usb/ulpi.h>
  32
  33 #define ULPI_VIEWPORT                           0x170
  34
  35 /* PORTSC PTS/PHCD bits, Tegra20 only */
  36 #define TEGRA_USB_PORTSC1                       0x184
  37 #define TEGRA_USB_PORTSC1_PTS(x)                (((x) & 0x3) << 30)
  38 #define TEGRA_USB_PORTSC1_PHCD                  BIT(23)
  39
  40 /* HOSTPC1 PTS/PHCD bits, Tegra30 and above */
  41 #define TEGRA_USB_HOSTPC1_DEVLC                 0x1b4
  42 #define TEGRA_USB_HOSTPC1_DEVLC_PTS(x)          (((x) & 0x7) << 29)
  43 #define TEGRA_USB_HOSTPC1_DEVLC_PHCD            BIT(22)
  44
  45 /* Bits of PORTSC1, which will get cleared by writing 1 into them */
  46 #define TEGRA_PORTSC1_RWC_BITS  (PORT_CSC | PORT_PEC | PORT_OCC)
  47
  48 #define USB_SUSP_CTRL                           0x400
  49 #define   USB_WAKE_ON_CNNT_EN_DEV               BIT(3)
  50 #define   USB_WAKE_ON_DISCON_EN_DEV             BIT(4)
  51 #define   USB_SUSP_CLR                          BIT(5)
  52 #define   USB_PHY_CLK_VALID                     BIT(7)
  53 #define   UTMIP_RESET                           BIT(11)
  54 #define   UHSIC_RESET                           BIT(11)
  55 #define   UTMIP_PHY_ENABLE                      BIT(12)
  56 #define   ULPI_PHY_ENABLE                       BIT(13)
  57 #define   USB_SUSP_SET                          BIT(14)
  58 #define   USB_WAKEUP_DEBOUNCE_COUNT(x)          (((x) & 0x7) << 16)
  59
  60 #define USB1_LEGACY_CTRL                        0x410
  61 #define   USB1_NO_LEGACY_MODE                   BIT(0)
  62 #define   USB1_VBUS_SENSE_CTL_MASK              (3 << 1)
  63 #define   USB1_VBUS_SENSE_CTL_VBUS_WAKEUP       (0 << 1)
  64 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP \
  65                                                 (1 << 1)
  66 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD       (2 << 1)
  67 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD        (3 << 1)
  68
  69 #define ULPI_TIMING_CTRL_0                      0x424
  70 #define   ULPI_OUTPUT_PINMUX_BYP                BIT(10)
  71 #define   ULPI_CLKOUT_PINMUX_BYP                BIT(11)
  72
  73 #define ULPI_TIMING_CTRL_1                      0x428
  74 #define   ULPI_DATA_TRIMMER_LOAD                BIT(0)
  75 #define   ULPI_DATA_TRIMMER_SEL(x)              (((x) & 0x7) << 1)
  76 #define   ULPI_STPDIRNXT_TRIMMER_LOAD           BIT(16)
  77 #define   ULPI_STPDIRNXT_TRIMMER_SEL(x)         (((x) & 0x7) << 17)
  78 #define   ULPI_DIR_TRIMMER_LOAD                 BIT(24)
  79 #define   ULPI_DIR_TRIMMER_SEL(x)               (((x) & 0x7) << 25)
  80
  81 #define UTMIP_PLL_CFG1                          0x804
  82 #define   UTMIP_XTAL_FREQ_COUNT(x)              (((x) & 0xfff) << 0)
  83 #define   UTMIP_PLLU_ENABLE_DLY_COUNT(x)        (((x) & 0x1f) << 27)
  84
  85 #define UTMIP_XCVR_CFG0                         0x808
  86 #define   UTMIP_XCVR_SETUP(x)                   (((x) & 0xf) << 0)
  87 #define   UTMIP_XCVR_SETUP_MSB(x)               ((((x) & 0x70) >> 4) << 22)
  88 #define   UTMIP_XCVR_LSRSLEW(x)                 (((x) & 0x3) << 8)
  89 #define   UTMIP_XCVR_LSFSLEW(x)                 (((x) & 0x3) << 10)
  90 #define   UTMIP_FORCE_PD_POWERDOWN              BIT(14)
  91 #define   UTMIP_FORCE_PD2_POWERDOWN             BIT(16)
  92 #define   UTMIP_FORCE_PDZI_POWERDOWN            BIT(18)
  93 #define   UTMIP_XCVR_LSBIAS_SEL                 BIT(21)
  94 #define   UTMIP_XCVR_HSSLEW(x)                  (((x) & 0x3) << 4)
  95 #define   UTMIP_XCVR_HSSLEW_MSB(x)              ((((x) & 0x1fc) >> 2) << 25)
  96
  97 #define UTMIP_BIAS_CFG0                         0x80c
  98 #define   UTMIP_OTGPD                           BIT(11)
  99 #define   UTMIP_BIASPD                          BIT(10)
 100 #define   UTMIP_HSSQUELCH_LEVEL(x)              (((x) & 0x3) << 0)
 101 #define   UTMIP_HSDISCON_LEVEL(x)               (((x) & 0x3) << 2)
 102 #define   UTMIP_HSDISCON_LEVEL_MSB(x)           ((((x) & 0x4) >> 2) << 24)
 103
 104 #define UTMIP_HSRX_CFG0                         0x810
 105 #define   UTMIP_ELASTIC_LIMIT(x)                (((x) & 0x1f) << 10)
 106 #define   UTMIP_IDLE_WAIT(x)                    (((x) & 0x1f) << 15)
 107
 108 #define UTMIP_HSRX_CFG1                         0x814
 109 #define   UTMIP_HS_SYNC_START_DLY(x)            (((x) & 0x1f) << 1)
 110
 111 #define UTMIP_TX_CFG0                           0x820
 112 #define   UTMIP_FS_PREABMLE_J                   BIT(19)
 113 #define   UTMIP_HS_DISCON_DISABLE               BIT(8)
 114
 115 #define UTMIP_MISC_CFG0                         0x824
 116 #define   UTMIP_DPDM_OBSERVE                    BIT(26)
 117 #define   UTMIP_DPDM_OBSERVE_SEL(x)             (((x) & 0xf) << 27)
 118 #define   UTMIP_DPDM_OBSERVE_SEL_FS_J           UTMIP_DPDM_OBSERVE_SEL(0xf)
 119 #define   UTMIP_DPDM_OBSERVE_SEL_FS_K           UTMIP_DPDM_OBSERVE_SEL(0xe)
 120 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE1         UTMIP_DPDM_OBSERVE_SEL(0xd)
 121 #define   UTMIP_DPDM_OBSERVE_SEL_FS_SE0         UTMIP_DPDM_OBSERVE_SEL(0xc)
 122 #define   UTMIP_SUSPEND_EXIT_ON_EDGE            BIT(22)
 123
 124 #define UTMIP_MISC_CFG1                         0x828
 125 #define   UTMIP_PLL_ACTIVE_DLY_COUNT(x)         (((x) & 0x1f) << 18)
 126 #define   UTMIP_PLLU_STABLE_COUNT(x)            (((x) & 0xfff) << 6)
 127
 128 #define UTMIP_DEBOUNCE_CFG0                     0x82c
 129 #define   UTMIP_BIAS_DEBOUNCE_A(x)              (((x) & 0xffff) << 0)
 130
 131 #define UTMIP_BAT_CHRG_CFG0                     0x830
 132 #define   UTMIP_PD_CHRG                         BIT(0)
 133
 134 #define UTMIP_SPARE_CFG0                        0x834
 135 #define   FUSE_SETUP_SEL                        BIT(3)
 136
 137 #define UTMIP_XCVR_CFG1                         0x838
 138 #define   UTMIP_FORCE_PDDISC_POWERDOWN          BIT(0)
 139 #define   UTMIP_FORCE_PDCHRP_POWERDOWN          BIT(2)
 140 #define   UTMIP_FORCE_PDDR_POWERDOWN            BIT(4)
 141 #define   UTMIP_XCVR_TERM_RANGE_ADJ(x)          (((x) & 0xf) << 18)
 142
 143 #define UTMIP_BIAS_CFG1                         0x83c
 144 #define   UTMIP_BIAS_PDTRK_COUNT(x)             (((x) & 0x1f) << 3)
 145
 146 /* For Tegra30 and above only, the address is different in Tegra20 */
 147 #define USB_USBMODE                             0x1f8
 148 #define   USB_USBMODE_MASK                      (3 << 0)
 149 #define   USB_USBMODE_HOST                      (3 << 0)
 150 #define   USB_USBMODE_DEVICE                    (2 << 0)
 151
 152 static DEFINE_SPINLOCK(utmip_pad_lock);
 153 static unsigned int utmip_pad_count;
 154
 155 struct tegra_xtal_freq {
 156         unsigned int freq;
 157         u8 enable_delay;
 158         u8 stable_count;
 159         u8 active_delay;
 160         u8 xtal_freq_count;
 161         u16 debounce;
 162 };
 163
 164 static const struct tegra_xtal_freq tegra_freq_table[] = {
 165         {
 166                 .freq = 12000000,
 167                 .enable_delay = 0x02,
 168                 .stable_count = 0x2F,
 169                 .active_delay = 0x04,
 170                 .xtal_freq_count = 0x76,
 171                 .debounce = 0x7530,
 172         },
 173         {
 174                 .freq = 13000000,
 175                 .enable_delay = 0x02,
 176                 .stable_count = 0x33,
 177                 .active_delay = 0x05,
 178                 .xtal_freq_count = 0x7F,
 179                 .debounce = 0x7EF4,
 180         },
 181         {
 182                 .freq = 19200000,
 183                 .enable_delay = 0x03,
 184                 .stable_count = 0x4B,
 185                 .active_delay = 0x06,
 186                 .xtal_freq_count = 0xBB,
 187                 .debounce = 0xBB80,
 188         },
 189         {
 190                 .freq = 26000000,
 191                 .enable_delay = 0x04,
 192                 .stable_count = 0x66,
 193                 .active_delay = 0x09,
 194                 .xtal_freq_count = 0xFE,
 195                 .debounce = 0xFDE8,
 196         },
 197 };
 198
 199 static inline struct tegra_usb_phy *to_tegra_usb_phy(struct usb_phy *u_phy)
 200 {
 201         return container_of(u_phy, struct tegra_usb_phy, u_phy);
 202 }
 203
 204 static void set_pts(struct tegra_usb_phy *phy, u8 pts_val)
 205 {
 206         void __iomem *base = phy->regs;
 207         u32 val;
 208
 209         if (phy->soc_config->has_hostpc) {
 210                 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
 211                 val &= ~TEGRA_USB_HOSTPC1_DEVLC_PTS(~0);
 212                 val |= TEGRA_USB_HOSTPC1_DEVLC_PTS(pts_val);
 213                 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 214         } else {
 215                 val = readl_relaxed(base + TEGRA_USB_PORTSC1);
 216                 val &= ~TEGRA_PORTSC1_RWC_BITS;
 217                 val &= ~TEGRA_USB_PORTSC1_PTS(~0);
 218                 val |= TEGRA_USB_PORTSC1_PTS(pts_val);
 219                 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
 220         }
 221 }
 222
 223 static void set_phcd(struct tegra_usb_phy *phy, bool enable)
 224 {
 225         void __iomem *base = phy->regs;
 226         u32 val;
 227
 228         if (phy->soc_config->has_hostpc) {
 229                 val = readl_relaxed(base + TEGRA_USB_HOSTPC1_DEVLC);
 230                 if (enable)
 231                         val |= TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 232                 else
 233                         val &= ~TEGRA_USB_HOSTPC1_DEVLC_PHCD;
 234                 writel_relaxed(val, base + TEGRA_USB_HOSTPC1_DEVLC);
 235         } else {
 236                 val = readl_relaxed(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS;
 237                 if (enable)
 238                         val |= TEGRA_USB_PORTSC1_PHCD;
 239                 else
 240                         val &= ~TEGRA_USB_PORTSC1_PHCD;
 241                 writel_relaxed(val, base + TEGRA_USB_PORTSC1);
 242         }
 243 }
 244
 245 static int utmip_pad_open(struct tegra_usb_phy *phy)
 246 {
 247         int ret;
 248
 249         ret = clk_prepare_enable(phy->pad_clk);
 250         if (ret) {
 251                 dev_err(phy->u_phy.dev,
 252                         "Failed to enable UTMI-pads clock: %d\n", ret);
 253                 return ret;
 254         }
 255
 256         spin_lock(&utmip_pad_lock);
 257
 258         ret = reset_control_deassert(phy->pad_rst);
 259         if (ret) {
 260                 dev_err(phy->u_phy.dev,
 261                         "Failed to initialize UTMI-pads reset: %d\n", ret);
 262                 goto unlock;
 263         }
 264
 265         ret = reset_control_assert(phy->pad_rst);
 266         if (ret) {
 267                 dev_err(phy->u_phy.dev,
 268                         "Failed to assert UTMI-pads reset: %d\n", ret);
 269                 goto unlock;
 270         }
 271
 272         udelay(1);
 273
 274         ret = reset_control_deassert(phy->pad_rst);
 275         if (ret)
 276                 dev_err(phy->u_phy.dev,
 277                         "Failed to deassert UTMI-pads reset: %d\n", ret);
 278 unlock:
 279         spin_unlock(&utmip_pad_lock);
 280
 281         clk_disable_unprepare(phy->pad_clk);
 282
 283         return ret;
 284 }
 285
 286 static int utmip_pad_close(struct tegra_usb_phy *phy)
 287 {
 288         int ret;
 289
 290         ret = clk_prepare_enable(phy->pad_clk);
 291         if (ret) {
 292                 dev_err(phy->u_phy.dev,
 293                         "Failed to enable UTMI-pads clock: %d\n", ret);
 294                 return ret;
 295         }
 296
 297         ret = reset_control_assert(phy->pad_rst);
 298         if (ret)
 299                 dev_err(phy->u_phy.dev,
 300                         "Failed to assert UTMI-pads reset: %d\n", ret);
 301
 302         udelay(1);
 303
 304         clk_disable_unprepare(phy->pad_clk);
 305
 306         return ret;
 307 }
 308
 309 static int utmip_pad_power_on(struct tegra_usb_phy *phy)
 310 {
 311         struct tegra_utmip_config *config = phy->config;
 312         void __iomem *base = phy->pad_regs;
 313         u32 val;
 314         int err;
 315
 316         err = clk_prepare_enable(phy->pad_clk);
 317         if (err)
 318                 return err;
 319
 320         spin_lock(&utmip_pad_lock);
 321
 322         if (utmip_pad_count++ == 0) {
 323                 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
 324                 val &= ~(UTMIP_OTGPD | UTMIP_BIASPD);
 325
 326                 if (phy->soc_config->requires_extra_tuning_parameters) {
 327                         val &= ~(UTMIP_HSSQUELCH_LEVEL(~0) |
 328                                 UTMIP_HSDISCON_LEVEL(~0) |
 329                                 UTMIP_HSDISCON_LEVEL_MSB(~0));
 330
 331                         val |= UTMIP_HSSQUELCH_LEVEL(config->hssquelch_level);
 332                         val |= UTMIP_HSDISCON_LEVEL(config->hsdiscon_level);
 333                         val |= UTMIP_HSDISCON_LEVEL_MSB(config->hsdiscon_level);
 334                 }
 335                 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
 336         }
 337
 338         spin_unlock(&utmip_pad_lock);
 339
 340         clk_disable_unprepare(phy->pad_clk);
 341
 342         return 0;
 343 }
 344
 345 static int utmip_pad_power_off(struct tegra_usb_phy *phy)
 346 {
 347         void __iomem *base = phy->pad_regs;
 348         u32 val;
 349         int ret;
 350
 351         ret = clk_prepare_enable(phy->pad_clk);
 352         if (ret)
 353                 return ret;
 354
 355         spin_lock(&utmip_pad_lock);
 356
 357         if (!utmip_pad_count) {
 358                 dev_err(phy->u_phy.dev, "UTMIP pad already powered off\n");
 359                 ret = -EINVAL;
 360                 goto ulock;
 361         }
 362
 363         if (--utmip_pad_count == 0) {
 364                 val = readl_relaxed(base + UTMIP_BIAS_CFG0);
 365                 val |= UTMIP_OTGPD | UTMIP_BIASPD;
 366                 writel_relaxed(val, base + UTMIP_BIAS_CFG0);
 367         }
 368 ulock:
 369         spin_unlock(&utmip_pad_lock);
 370
 371         clk_disable_unprepare(phy->pad_clk);
 372
 373         return ret;
 374 }
 375
 376 static int utmi_wait_register(void __iomem *reg, u32 mask, u32 result)
 377 {
 378         u32 tmp;
 379
 380         return readl_relaxed_poll_timeout(reg, tmp, (tmp & mask) == result,
 381                                           2000, 6000);
 382 }
 383
 384 static void utmi_phy_clk_disable(struct tegra_usb_phy *phy)
 385 {
 386         void __iomem *base = phy->regs;
 387         u32 val;
 388
 389         /*
 390          * The USB driver may have already initiated the phy clock
 391          * disable so wait to see if the clock turns off and if not
 392          * then proceed with gating the clock.
 393          */
 394         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0) == 0)
 395                 return;
 396
 397         if (phy->is_legacy_phy) {
 398                 val = readl_relaxed(base + USB_SUSP_CTRL);
 399                 val |= USB_SUSP_SET;
 400                 writel_relaxed(val, base + USB_SUSP_CTRL);
 401
 402                 usleep_range(10, 100);
 403
 404                 val = readl_relaxed(base + USB_SUSP_CTRL);
 405                 val &= ~USB_SUSP_SET;
 406                 writel_relaxed(val, base + USB_SUSP_CTRL);
 407         } else {
 408                 set_phcd(phy, true);
 409         }
 410
 411         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID, 0))
 412                 dev_err(phy->u_phy.dev,
 413                         "Timeout waiting for PHY to stabilize on disable\n");
 414 }
 415
 416 static void utmi_phy_clk_enable(struct tegra_usb_phy *phy)
 417 {
 418         void __iomem *base = phy->regs;
 419         u32 val;
 420
 421         /*
 422          * The USB driver may have already initiated the phy clock
 423          * enable so wait to see if the clock turns on and if not
 424          * then proceed with ungating the clock.
 425          */
 426         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 427                                USB_PHY_CLK_VALID) == 0)
 428                 return;
 429
 430         if (phy->is_legacy_phy) {
 431                 val = readl_relaxed(base + USB_SUSP_CTRL);
 432                 val |= USB_SUSP_CLR;
 433                 writel_relaxed(val, base + USB_SUSP_CTRL);
 434
 435                 usleep_range(10, 100);
 436
 437                 val = readl_relaxed(base + USB_SUSP_CTRL);
 438                 val &= ~USB_SUSP_CLR;
 439                 writel_relaxed(val, base + USB_SUSP_CTRL);
 440         } else {
 441                 set_phcd(phy, false);
 442         }
 443
 444         if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
 445                                USB_PHY_CLK_VALID))
 446                 dev_err(phy->u_phy.dev,
 447                         "Timeout waiting for PHY to stabilize on enable\n");
 448 }
 449
 450 static int utmi_phy_power_on(struct tegra_usb_phy *phy)
 451 {
 452         struct tegra_utmip_config *config = phy->config;
 453         void __iomem *base = phy->regs;
 454         u32 val;
 455         int err;
 456
 457         val = readl_relaxed(base + USB_SUSP_CTRL);
 458         val |= UTMIP_RESET;
 459         writel_relaxed(val, base + USB_SUSP_CTRL);
 460
 461         if (phy->is_legacy_phy) {
 462                 val = readl_relaxed(base + USB1_LEGACY_CTRL);
 463                 val |= USB1_NO_LEGACY_MODE;
 464                 writel_relaxed(val, base + USB1_LEGACY_CTRL);
 465         }
 466
 467         val = readl_relaxed(base + UTMIP_TX_CFG0);
 468         val |= UTMIP_FS_PREABMLE_J;
 469         writel_relaxed(val, base + UTMIP_TX_CFG0);
 470
 471         val = readl_relaxed(base + UTMIP_HSRX_CFG0);
 472         val &= ~(UTMIP_IDLE_WAIT(~0) | UTMIP_ELASTIC_LIMIT(~0));
 473         val |= UTMIP_IDLE_WAIT(config->idle_wait_delay);
 474         val |= UTMIP_ELASTIC_LIMIT(config->elastic_limit);
 475         writel_relaxed(val, base + UTMIP_HSRX_CFG0);
 476
 477         val = readl_relaxed(base + UTMIP_HSRX_CFG1);
 478         val &= ~UTMIP_HS_SYNC_START_DLY(~0);
 479         val |= UTMIP_HS_SYNC_START_DLY(config->hssync_start_delay);
 480         writel_relaxed(val, base + UTMIP_HSRX_CFG1);
 481
 482         val = readl_relaxed(base + UTMIP_DEBOUNCE_CFG0);
 483         val &= ~UTMIP_BIAS_DEBOUNCE_A(~0);
 484         val |= UTMIP_BIAS_DEBOUNCE_A(phy->freq->debounce);
 485         writel_relaxed(val, base + UTMIP_DEBOUNCE_CFG0);
 486
 487         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 488         val &= ~UTMIP_SUSPEND_EXIT_ON_EDGE;
 489         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 490
 491         if (!phy->soc_config->utmi_pll_config_in_car_module) {
 492                 val = readl_relaxed(base + UTMIP_MISC_CFG1);
 493                 val &= ~(UTMIP_PLL_ACTIVE_DLY_COUNT(~0) |
 494                         UTMIP_PLLU_STABLE_COUNT(~0));
 495                 val |= UTMIP_PLL_ACTIVE_DLY_COUNT(phy->freq->active_delay) |
 496                         UTMIP_PLLU_STABLE_COUNT(phy->freq->stable_count);
 497                 writel_relaxed(val, base + UTMIP_MISC_CFG1);
 498
 499                 val = readl_relaxed(base + UTMIP_PLL_CFG1);
 500                 val &= ~(UTMIP_XTAL_FREQ_COUNT(~0) |
 501                         UTMIP_PLLU_ENABLE_DLY_COUNT(~0));
 502                 val |= UTMIP_XTAL_FREQ_COUNT(phy->freq->xtal_freq_count) |
 503                         UTMIP_PLLU_ENABLE_DLY_COUNT(phy->freq->enable_delay);
 504                 writel_relaxed(val, base + UTMIP_PLL_CFG1);
 505         }
 506
 507         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 508                 val = readl_relaxed(base + USB_SUSP_CTRL);
 509                 val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV);
 510                 writel_relaxed(val, base + USB_SUSP_CTRL);
 511
 512                 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 513                 val &= ~UTMIP_PD_CHRG;
 514                 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 515         } else {
 516                 val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 517                 val |= UTMIP_PD_CHRG;
 518                 writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 519         }
 520
 521         err = utmip_pad_power_on(phy);
 522         if (err)
 523                 return err;
 524
 525         val = readl_relaxed(base + UTMIP_XCVR_CFG0);
 526         val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 527                  UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL |
 528                  UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) |
 529                  UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0));
 530
 531         if (!config->xcvr_setup_use_fuses) {
 532                 val |= UTMIP_XCVR_SETUP(config->xcvr_setup);
 533                 val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup);
 534         }
 535         val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew);
 536         val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew);
 537
 538         if (phy->soc_config->requires_extra_tuning_parameters) {
 539                 val &= ~(UTMIP_XCVR_HSSLEW(~0) | UTMIP_XCVR_HSSLEW_MSB(~0));
 540                 val |= UTMIP_XCVR_HSSLEW(config->xcvr_hsslew);
 541                 val |= UTMIP_XCVR_HSSLEW_MSB(config->xcvr_hsslew);
 542         }
 543         writel_relaxed(val, base + UTMIP_XCVR_CFG0);
 544
 545         val = readl_relaxed(base + UTMIP_XCVR_CFG1);
 546         val &= ~(UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 547                  UTMIP_FORCE_PDDR_POWERDOWN | UTMIP_XCVR_TERM_RANGE_ADJ(~0));
 548         val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj);
 549         writel_relaxed(val, base + UTMIP_XCVR_CFG1);
 550
 551         val = readl_relaxed(base + UTMIP_BIAS_CFG1);
 552         val &= ~UTMIP_BIAS_PDTRK_COUNT(~0);
 553         val |= UTMIP_BIAS_PDTRK_COUNT(0x5);
 554         writel_relaxed(val, base + UTMIP_BIAS_CFG1);
 555
 556         val = readl_relaxed(base + UTMIP_SPARE_CFG0);
 557         if (config->xcvr_setup_use_fuses)
 558                 val |= FUSE_SETUP_SEL;
 559         else
 560                 val &= ~FUSE_SETUP_SEL;
 561         writel_relaxed(val, base + UTMIP_SPARE_CFG0);
 562
 563         if (!phy->is_legacy_phy) {
 564                 val = readl_relaxed(base + USB_SUSP_CTRL);
 565                 val |= UTMIP_PHY_ENABLE;
 566                 writel_relaxed(val, base + USB_SUSP_CTRL);
 567         }
 568
 569         val = readl_relaxed(base + USB_SUSP_CTRL);
 570         val &= ~UTMIP_RESET;
 571         writel_relaxed(val, base + USB_SUSP_CTRL);
 572
 573         if (phy->is_legacy_phy) {
 574                 val = readl_relaxed(base + USB1_LEGACY_CTRL);
 575                 val &= ~USB1_VBUS_SENSE_CTL_MASK;
 576                 val |= USB1_VBUS_SENSE_CTL_A_SESS_VLD;
 577                 writel_relaxed(val, base + USB1_LEGACY_CTRL);
 578
 579                 val = readl_relaxed(base + USB_SUSP_CTRL);
 580                 val &= ~USB_SUSP_SET;
 581                 writel_relaxed(val, base + USB_SUSP_CTRL);
 582         }
 583
 584         utmi_phy_clk_enable(phy);
 585
 586         if (phy->soc_config->requires_usbmode_setup) {
 587                 val = readl_relaxed(base + USB_USBMODE);
 588                 val &= ~USB_USBMODE_MASK;
 589                 if (phy->mode == USB_DR_MODE_HOST)
 590                         val |= USB_USBMODE_HOST;
 591                 else
 592                         val |= USB_USBMODE_DEVICE;
 593                 writel_relaxed(val, base + USB_USBMODE);
 594         }
 595
 596         if (!phy->is_legacy_phy)
 597                 set_pts(phy, 0);
 598
 599         return 0;
 600 }
 601
 602 static int utmi_phy_power_off(struct tegra_usb_phy *phy)
 603 {
 604         void __iomem *base = phy->regs;
 605         u32 val;
 606
 607         utmi_phy_clk_disable(phy);
 608
 609         if (phy->mode == USB_DR_MODE_PERIPHERAL) {
 610                 val = readl_relaxed(base + USB_SUSP_CTRL);
 611                 val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
 612                 val |= USB_WAKE_ON_CNNT_EN_DEV | USB_WAKEUP_DEBOUNCE_COUNT(5);
 613                 writel_relaxed(val, base + USB_SUSP_CTRL);
 614         }
 615
 616         val = readl_relaxed(base + USB_SUSP_CTRL);
 617         val |= UTMIP_RESET;
 618         writel_relaxed(val, base + USB_SUSP_CTRL);
 619
 620         val = readl_relaxed(base + UTMIP_BAT_CHRG_CFG0);
 621         val |= UTMIP_PD_CHRG;
 622         writel_relaxed(val, base + UTMIP_BAT_CHRG_CFG0);
 623
 624         val = readl_relaxed(base + UTMIP_XCVR_CFG0);
 625         val |= UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN |
 626                UTMIP_FORCE_PDZI_POWERDOWN;
 627         writel_relaxed(val, base + UTMIP_XCVR_CFG0);
 628
 629         val = readl_relaxed(base + UTMIP_XCVR_CFG1);
 630         val |= UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN |
 631                UTMIP_FORCE_PDDR_POWERDOWN;
 632         writel_relaxed(val, base + UTMIP_XCVR_CFG1);
 633
 634         return utmip_pad_power_off(phy);
 635 }
 636
 637 static void utmi_phy_preresume(struct tegra_usb_phy *phy)
 638 {
 639         void __iomem *base = phy->regs;
 640         u32 val;
 641
 642         val = readl_relaxed(base + UTMIP_TX_CFG0);
 643         val |= UTMIP_HS_DISCON_DISABLE;
 644         writel_relaxed(val, base + UTMIP_TX_CFG0);
 645 }
 646
 647 static void utmi_phy_postresume(struct tegra_usb_phy *phy)
 648 {
 649         void __iomem *base = phy->regs;
 650         u32 val;
 651
 652         val = readl_relaxed(base + UTMIP_TX_CFG0);
 653         val &= ~UTMIP_HS_DISCON_DISABLE;
 654         writel_relaxed(val, base + UTMIP_TX_CFG0);
 655 }
 656
 657 static void utmi_phy_restore_start(struct tegra_usb_phy *phy,
 658                                    enum tegra_usb_phy_port_speed port_speed)
 659 {
 660         void __iomem *base = phy->regs;
 661         u32 val;
 662
 663         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 664         val &= ~UTMIP_DPDM_OBSERVE_SEL(~0);
 665         if (port_speed == TEGRA_USB_PHY_PORT_SPEED_LOW)
 666                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_K;
 667         else
 668                 val |= UTMIP_DPDM_OBSERVE_SEL_FS_J;
 669         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 670         usleep_range(1, 10);
 671
 672         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 673         val |= UTMIP_DPDM_OBSERVE;
 674         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 675         usleep_range(10, 100);
 676 }
 677
 678 static void utmi_phy_restore_end(struct tegra_usb_phy *phy)
 679 {
 680         void __iomem *base = phy->regs;
 681         u32 val;
 682
 683         val = readl_relaxed(base + UTMIP_MISC_CFG0);
 684         val &= ~UTMIP_DPDM_OBSERVE;
 685         writel_relaxed(val, base + UTMIP_MISC_CFG0);
 686         usleep_range(10, 100);
 687 }
 688
 689 static int ulpi_phy_power_on(struct tegra_usb_phy *phy)
 690 {
 691         void __iomem *base = phy->regs;
 692         u32 val;
 693         int err;
 694
 695         gpiod_set_value_cansleep(phy->reset_gpio, 1);
 696
 697         err = clk_prepare_enable(phy->clk);
 698         if (err)
 699                 return err;
 700
 701         usleep_range(5000, 6000);
 702
 703         gpiod_set_value_cansleep(phy->reset_gpio, 0);
 704
 705         usleep_range(1000, 2000);
 706
 707         val = readl_relaxed(base + USB_SUSP_CTRL);
 708         val |= UHSIC_RESET;
 709         writel_relaxed(val, base + USB_SUSP_CTRL);
 710
 711         val = readl_relaxed(base + ULPI_TIMING_CTRL_0);
 712         val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
 713         writel_relaxed(val, base + ULPI_TIMING_CTRL_0);
 714
 715         val = readl_relaxed(base + USB_SUSP_CTRL);
 716         val |= ULPI_PHY_ENABLE;
 717         writel_relaxed(val, base + USB_SUSP_CTRL);
 718
 719         val = 0;
 720         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 721
 722         val |= ULPI_DATA_TRIMMER_SEL(4);
 723         val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
 724         val |= ULPI_DIR_TRIMMER_SEL(4);
 725         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 726         usleep_range(10, 100);
 727
 728         val |= ULPI_DATA_TRIMMER_LOAD;
 729         val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
 730         val |= ULPI_DIR_TRIMMER_LOAD;
 731         writel_relaxed(val, base + ULPI_TIMING_CTRL_1);
 732
 733         /* Fix VbusInvalid due to floating VBUS */
 734         err = usb_phy_io_write(phy->ulpi, 0x40, 0x08);
 735         if (err) {
 736                 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
 737                 goto disable_clk;
 738         }
 739
 740         err = usb_phy_io_write(phy->ulpi, 0x80, 0x0B);
 741         if (err) {
 742                 dev_err(phy->u_phy.dev, "ULPI write failed: %d\n", err);
 743                 goto disable_clk;
 744         }
 745
 746         val = readl_relaxed(base + USB_SUSP_CTRL);
 747         val |= USB_SUSP_CLR;
 748         writel_relaxed(val, base + USB_SUSP_CTRL);
 749         usleep_range(100, 1000);
 750
 751         val = readl_relaxed(base + USB_SUSP_CTRL);
 752         val &= ~USB_SUSP_CLR;
 753         writel_relaxed(val, base + USB_SUSP_CTRL);
 754
 755         return 0;
 756
 757 disable_clk:
 758         clk_disable_unprepare(phy->clk);
 759
 760         return err;
 761 }
 762
 763 static int ulpi_phy_power_off(struct tegra_usb_phy *phy)
 764 {
 765         gpiod_set_value_cansleep(phy->reset_gpio, 1);
 766         usleep_range(5000, 6000);
 767         clk_disable_unprepare(phy->clk);
 768
 769         return 0;
 770 }
 771
 772 static int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 773 {
 774         int err;
 775
 776         if (phy->powered_on)
 777                 return 0;
 778
 779         if (phy->is_ulpi_phy)
 780                 err = ulpi_phy_power_on(phy);
 781         else
 782                 err = utmi_phy_power_on(phy);
 783         if (err)
 784                 return err;
 785
 786         phy->powered_on = true;
 787
 788         return 0;
 789 }
 790
 791 static int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 792 {
 793         int err;
 794
 795         if (!phy->powered_on)
 796                 return 0;
 797
 798         if (phy->is_ulpi_phy)
 799                 err = ulpi_phy_power_off(phy);
 800         else
 801                 err = utmi_phy_power_off(phy);
 802         if (err)
 803                 return err;
 804
 805         phy->powered_on = false;
 806
 807         return 0;
 808 }
 809
 810 static void tegra_usb_phy_shutdown(struct usb_phy *u_phy)
 811 {
 812         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 813
 814         if (WARN_ON(!phy->freq))
 815                 return;
 816
 817         tegra_usb_phy_power_off(phy);
 818
 819         if (!phy->is_ulpi_phy)
 820                 utmip_pad_close(phy);
 821
 822         regulator_disable(phy->vbus);
 823         clk_disable_unprepare(phy->pll_u);
 824
 825         phy->freq = NULL;
 826 }
 827
 828 static int tegra_usb_phy_set_suspend(struct usb_phy *u_phy, int suspend)
 829 {
 830         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 831
 832         if (WARN_ON(!phy->freq))
 833                 return -EINVAL;
 834
 835         if (suspend)
 836                 return tegra_usb_phy_power_off(phy);
 837         else
 838                 return tegra_usb_phy_power_on(phy);
 839 }
 840
 841 static int tegra_usb_phy_init(struct usb_phy *u_phy)
 842 {
 843         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 844         unsigned long parent_rate;
 845         unsigned int i;
 846         int err;
 847
 848         if (WARN_ON(phy->freq))
 849                 return 0;
 850
 851         err = clk_prepare_enable(phy->pll_u);
 852         if (err)
 853                 return err;
 854
 855         parent_rate = clk_get_rate(clk_get_parent(phy->pll_u));
 856         for (i = 0; i < ARRAY_SIZE(tegra_freq_table); i++) {
 857                 if (tegra_freq_table[i].freq == parent_rate) {
 858                         phy->freq = &tegra_freq_table[i];
 859                         break;
 860                 }
 861         }
 862         if (!phy->freq) {
 863                 dev_err(phy->u_phy.dev, "Invalid pll_u parent rate %ld\n",
 864                         parent_rate);
 865                 err = -EINVAL;
 866                 goto disable_clk;
 867         }
 868
 869         err = regulator_enable(phy->vbus);
 870         if (err) {
 871                 dev_err(phy->u_phy.dev,
 872                         "Failed to enable USB VBUS regulator: %d\n", err);
 873                 goto disable_clk;
 874         }
 875
 876         if (!phy->is_ulpi_phy) {
 877                 err = utmip_pad_open(phy);
 878                 if (err)
 879                         goto disable_vbus;
 880         }
 881
 882         err = tegra_usb_phy_power_on(phy);
 883         if (err)
 884                 goto close_phy;
 885
 886         return 0;
 887
 888 close_phy:
 889         if (!phy->is_ulpi_phy)
 890                 utmip_pad_close(phy);
 891
 892 disable_vbus:
 893         regulator_disable(phy->vbus);
 894
 895 disable_clk:
 896         clk_disable_unprepare(phy->pll_u);
 897
 898         phy->freq = NULL;
 899
 900         return err;
 901 }
 902
 903 void tegra_usb_phy_preresume(struct usb_phy *u_phy)
 904 {
 905         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 906
 907         if (!phy->is_ulpi_phy)
 908                 utmi_phy_preresume(phy);
 909 }
 910 EXPORT_SYMBOL_GPL(tegra_usb_phy_preresume);
 911
 912 void tegra_usb_phy_postresume(struct usb_phy *u_phy)
 913 {
 914         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 915
 916         if (!phy->is_ulpi_phy)
 917                 utmi_phy_postresume(phy);
 918 }
 919 EXPORT_SYMBOL_GPL(tegra_usb_phy_postresume);
 920
 921 void tegra_ehci_phy_restore_start(struct usb_phy *u_phy,
 922                                   enum tegra_usb_phy_port_speed port_speed)
 923 {
 924         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 925
 926         if (!phy->is_ulpi_phy)
 927                 utmi_phy_restore_start(phy, port_speed);
 928 }
 929 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_start);
 930
 931 void tegra_ehci_phy_restore_end(struct usb_phy *u_phy)
 932 {
 933         struct tegra_usb_phy *phy = to_tegra_usb_phy(u_phy);
 934
 935         if (!phy->is_ulpi_phy)
 936                 utmi_phy_restore_end(phy);
 937 }
 938 EXPORT_SYMBOL_GPL(tegra_ehci_phy_restore_end);
 939
 940 static int read_utmi_param(struct platform_device *pdev, const char *param,
 941                            u8 *dest)
 942 {
 943         u32 value;
 944         int err;
 945
 946         err = of_property_read_u32(pdev->dev.of_node, param, &value);
 947         if (err)
 948                 dev_err(&pdev->dev,
 949                         "Failed to read USB UTMI parameter %s: %d\n",
 950                         param, err);
 951         else
 952                 *dest = value;
 953
 954         return err;
 955 }
 956
 957 static int utmi_phy_probe(struct tegra_usb_phy *tegra_phy,
 958                           struct platform_device *pdev)
 959 {
 960         struct tegra_utmip_config *config;
 961         struct resource *res;
 962         int err;
 963
 964         tegra_phy->is_ulpi_phy = false;
 965
 966         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 967         if (!res) {
 968                 dev_err(&pdev->dev, "Failed to get UTMI pad regs\n");
 969                 return  -ENXIO;
 970         }
 971
 972         tegra_phy->pad_regs = devm_ioremap(&pdev->dev, res->start,
 973                                            resource_size(res));
 974         if (!tegra_phy->pad_regs) {
 975                 dev_err(&pdev->dev, "Failed to remap UTMI pad regs\n");
 976                 return -ENOMEM;
 977         }
 978
 979         tegra_phy->config = devm_kzalloc(&pdev->dev, sizeof(*config),
 980                                          GFP_KERNEL);
 981         if (!tegra_phy->config)
 982                 return -ENOMEM;
 983
 984         config = tegra_phy->config;
 985
 986         err = read_utmi_param(pdev, "nvidia,hssync-start-delay",
 987                               &config->hssync_start_delay);
 988         if (err)
 989                 return err;
 990
 991         err = read_utmi_param(pdev, "nvidia,elastic-limit",
 992                               &config->elastic_limit);
 993         if (err)
 994                 return err;
 995
 996         err = read_utmi_param(pdev, "nvidia,idle-wait-delay",
 997                               &config->idle_wait_delay);
 998         if (err)
 999                 return err;
1000
1001         err = read_utmi_param(pdev, "nvidia,term-range-adj",
1002                               &config->term_range_adj);
1003         if (err)
1004                 return err;
1005
1006         err = read_utmi_param(pdev, "nvidia,xcvr-lsfslew",
1007                               &config->xcvr_lsfslew);
1008         if (err)
1009                 return err;
1010
1011         err = read_utmi_param(pdev, "nvidia,xcvr-lsrslew",
1012                               &config->xcvr_lsrslew);
1013         if (err)
1014                 return err;
1015
1016         if (tegra_phy->soc_config->requires_extra_tuning_parameters) {
1017                 err = read_utmi_param(pdev, "nvidia,xcvr-hsslew",
1018                                       &config->xcvr_hsslew);
1019                 if (err)
1020                         return err;
1021
1022                 err = read_utmi_param(pdev, "nvidia,hssquelch-level",
1023                                       &config->hssquelch_level);
1024                 if (err)
1025                         return err;
1026
1027                 err = read_utmi_param(pdev, "nvidia,hsdiscon-level",
1028                                       &config->hsdiscon_level);
1029                 if (err)
1030                         return err;
1031         }
1032
1033         config->xcvr_setup_use_fuses = of_property_read_bool(
1034                 pdev->dev.of_node, "nvidia,xcvr-setup-use-fuses");
1035
1036         if (!config->xcvr_setup_use_fuses) {
1037                 err = read_utmi_param(pdev, "nvidia,xcvr-setup",
1038                                       &config->xcvr_setup);
1039                 if (err)
1040                         return err;
1041         }
1042
1043         return 0;
1044 }
1045
1046 static const struct tegra_phy_soc_config tegra20_soc_config = {
1047         .utmi_pll_config_in_car_module = false,
1048         .has_hostpc = false,
1049         .requires_usbmode_setup = false,
1050         .requires_extra_tuning_parameters = false,
1051 };
1052
1053 static const struct tegra_phy_soc_config tegra30_soc_config = {
1054         .utmi_pll_config_in_car_module = true,
1055         .has_hostpc = true,
1056         .requires_usbmode_setup = true,
1057         .requires_extra_tuning_parameters = true,
1058 };
1059
1060 static const struct of_device_id tegra_usb_phy_id_table[] = {
1061         { .compatible = "nvidia,tegra30-usb-phy", .data = &tegra30_soc_config },
1062         { .compatible = "nvidia,tegra20-usb-phy", .data = &tegra20_soc_config },
1063         { },
1064 };
1065 MODULE_DEVICE_TABLE(of, tegra_usb_phy_id_table);
1066
1067 static int tegra_usb_phy_probe(struct platform_device *pdev)
1068 {
1069         struct device_node *np = pdev->dev.of_node;
1070         struct tegra_usb_phy *tegra_phy;
1071         enum usb_phy_interface phy_type;
1072         struct reset_control *reset;
1073         struct gpio_desc *gpiod;
1074         struct resource *res;
1075         struct usb_phy *phy;
1076         int err;
1077
1078         tegra_phy = devm_kzalloc(&pdev->dev, sizeof(*tegra_phy), GFP_KERNEL);
1079         if (!tegra_phy)
1080                 return -ENOMEM;
1081
1082         tegra_phy->soc_config = of_device_get_match_data(&pdev->dev);
1083
1084         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085         if (!res) {
1086                 dev_err(&pdev->dev, "Failed to get I/O memory\n");
1087                 return  -ENXIO;
1088         }
1089
1090         tegra_phy->regs = devm_ioremap(&pdev->dev, res->start,
1091                                        resource_size(res));
1092         if (!tegra_phy->regs) {
1093                 dev_err(&pdev->dev, "Failed to remap I/O memory\n");
1094                 return -ENOMEM;
1095         }
1096
1097         tegra_phy->is_legacy_phy =
1098                 of_property_read_bool(np, "nvidia,has-legacy-mode");
1099
1100         if (of_find_property(np, "dr_mode", NULL))
1101                 tegra_phy->mode = usb_get_dr_mode(&pdev->dev);
1102         else
1103                 tegra_phy->mode = USB_DR_MODE_HOST;
1104
1105         if (tegra_phy->mode == USB_DR_MODE_UNKNOWN) {
1106                 dev_err(&pdev->dev, "dr_mode is invalid\n");
1107                 return -EINVAL;
1108         }
1109
1110         /* On some boards, the VBUS regulator doesn't need to be controlled */
1111         tegra_phy->vbus = devm_regulator_get(&pdev->dev, "vbus");
1112         if (IS_ERR(tegra_phy->vbus))
1113                 return PTR_ERR(tegra_phy->vbus);
1114
1115         tegra_phy->pll_u = devm_clk_get(&pdev->dev, "pll_u");
1116         err = PTR_ERR_OR_ZERO(tegra_phy->pll_u);
1117         if (err) {
1118                 dev_err(&pdev->dev, "Failed to get pll_u clock: %d\n", err);
1119                 return err;
1120         }
1121
1122         phy_type = of_usb_get_phy_mode(np);
1123         switch (phy_type) {
1124         case USBPHY_INTERFACE_MODE_UTMI:
1125                 err = utmi_phy_probe(tegra_phy, pdev);
1126                 if (err)
1127                         return err;
1128
1129                 tegra_phy->pad_clk = devm_clk_get(&pdev->dev, "utmi-pads");
1130                 err = PTR_ERR_OR_ZERO(tegra_phy->pad_clk);
1131                 if (err) {
1132                         dev_err(&pdev->dev,
1133                                 "Failed to get UTMIP pad clock: %d\n", err);
1134                         return err;
1135                 }
1136
1137                 reset = devm_reset_control_get_optional_shared(&pdev->dev,
1138                                                                "utmi-pads");
1139                 err = PTR_ERR_OR_ZERO(reset);
1140                 if (err) {
1141                         dev_err(&pdev->dev,
1142                                 "Failed to get UTMI-pads reset: %d\n", err);
1143                         return err;
1144                 }
1145                 tegra_phy->pad_rst = reset;
1146                 break;
1147
1148         case USBPHY_INTERFACE_MODE_ULPI:
1149                 tegra_phy->is_ulpi_phy = true;
1150
1151                 tegra_phy->clk = devm_clk_get(&pdev->dev, "ulpi-link");
1152                 err = PTR_ERR_OR_ZERO(tegra_phy->clk);
1153                 if (err) {
1154                         dev_err(&pdev->dev,
1155                                 "Failed to get ULPI clock: %d\n", err);
1156                         return err;
1157                 }
1158
1159                 gpiod = devm_gpiod_get_from_of_node(&pdev->dev, np,
1160                                                     "nvidia,phy-reset-gpio",
1161                                                     0, GPIOD_OUT_HIGH,
1162                                                     "ulpi_phy_reset_b");
1163                 err = PTR_ERR_OR_ZERO(gpiod);
1164                 if (err) {
1165                         dev_err(&pdev->dev,
1166                                 "Request failed for reset GPIO: %d\n", err);
1167                         return err;
1168                 }
1169                 tegra_phy->reset_gpio = gpiod;
1170
1171                 phy = devm_otg_ulpi_create(&pdev->dev,
1172                                            &ulpi_viewport_access_ops, 0);
1173                 if (!phy) {
1174                         dev_err(&pdev->dev, "Failed to create ULPI OTG\n");
1175                         return -ENOMEM;
1176                 }
1177
1178                 tegra_phy->ulpi = phy;
1179                 tegra_phy->ulpi->io_priv = tegra_phy->regs + ULPI_VIEWPORT;
1180                 break;
1181
1182         default:
1183                 dev_err(&pdev->dev, "phy_type %u is invalid or unsupported\n",
1184                         phy_type);
1185                 return -EINVAL;
1186         }
1187
1188         tegra_phy->u_phy.dev = &pdev->dev;
1189         tegra_phy->u_phy.init = tegra_usb_phy_init;
1190         tegra_phy->u_phy.shutdown = tegra_usb_phy_shutdown;
1191         tegra_phy->u_phy.set_suspend = tegra_usb_phy_set_suspend;
1192
1193         platform_set_drvdata(pdev, tegra_phy);
1194
1195         err = usb_add_phy_dev(&tegra_phy->u_phy);
1196         if (err)
1197                 return err;
1198
1199         return 0;
1200 }
1201
1202 static int tegra_usb_phy_remove(struct platform_device *pdev)
1203 {
1204         struct tegra_usb_phy *tegra_phy = platform_get_drvdata(pdev);
1205
1206         usb_remove_phy(&tegra_phy->u_phy);
1207
1208         return 0;
1209 }
1210
1211 static struct platform_driver tegra_usb_phy_driver = {
1212         .probe          = tegra_usb_phy_probe,
1213         .remove         = tegra_usb_phy_remove,
1214         .driver         = {
1215                 .name   = "tegra-phy",
1216                 .of_match_table = tegra_usb_phy_id_table,
1217         },
1218 };
1219 module_platform_driver(tegra_usb_phy_driver);
1220
1221 MODULE_DESCRIPTION("Tegra USB PHY driver");
1222 MODULE_LICENSE("GPL v2");