drivers/usb/typec/ucsi/ucsi_ccg.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * UCSI driver for Cypress CCGx Type-C controller
   4  *
   5  * Copyright (C) 2017-2018 NVIDIA Corporation. All rights reserved.
   6  * Author: Ajay Gupta <ajayg@nvidia.com>
   7  *
   8  * Some code borrowed from drivers/usb/typec/ucsi/ucsi_acpi.c
   9  */
  10 #include <linux/acpi.h>
  11 #include <linux/delay.h>
  12 #include <linux/firmware.h>
  13 #include <linux/i2c.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/usb/typec_dp.h>
  20
  21 #include <asm/unaligned.h>
  22 #include "ucsi.h"
  23
  24 enum enum_fw_mode {
  25         BOOT,   /* bootloader */
  26         FW1,    /* FW partition-1 (contains secondary fw) */
  27         FW2,    /* FW partition-2 (contains primary fw) */
  28         FW_INVALID,
  29 };
  30
  31 #define CCGX_RAB_DEVICE_MODE                    0x0000
  32 #define CCGX_RAB_INTR_REG                       0x0006
  33 #define  DEV_INT                                BIT(0)
  34 #define  PORT0_INT                              BIT(1)
  35 #define  PORT1_INT                              BIT(2)
  36 #define  UCSI_READ_INT                          BIT(7)
  37 #define CCGX_RAB_JUMP_TO_BOOT                   0x0007
  38 #define  TO_BOOT                                'J'
  39 #define  TO_ALT_FW                              'A'
  40 #define CCGX_RAB_RESET_REQ                      0x0008
  41 #define  RESET_SIG                              'R'
  42 #define  CMD_RESET_I2C                          0x0
  43 #define  CMD_RESET_DEV                          0x1
  44 #define CCGX_RAB_ENTER_FLASHING                 0x000A
  45 #define  FLASH_ENTER_SIG                        'P'
  46 #define CCGX_RAB_VALIDATE_FW                    0x000B
  47 #define CCGX_RAB_FLASH_ROW_RW                   0x000C
  48 #define  FLASH_SIG                              'F'
  49 #define  FLASH_RD_CMD                           0x0
  50 #define  FLASH_WR_CMD                           0x1
  51 #define  FLASH_FWCT1_WR_CMD                     0x2
  52 #define  FLASH_FWCT2_WR_CMD                     0x3
  53 #define  FLASH_FWCT_SIG_WR_CMD                  0x4
  54 #define CCGX_RAB_READ_ALL_VER                   0x0010
  55 #define CCGX_RAB_READ_FW2_VER                   0x0020
  56 #define CCGX_RAB_UCSI_CONTROL                   0x0039
  57 #define CCGX_RAB_UCSI_CONTROL_START             BIT(0)
  58 #define CCGX_RAB_UCSI_CONTROL_STOP              BIT(1)
  59 #define CCGX_RAB_UCSI_DATA_BLOCK(offset)        (0xf000 | ((offset) & 0xff))
  60 #define REG_FLASH_RW_MEM        0x0200
  61 #define DEV_REG_IDX                             CCGX_RAB_DEVICE_MODE
  62 #define CCGX_RAB_PDPORT_ENABLE                  0x002C
  63 #define  PDPORT_1               BIT(0)
  64 #define  PDPORT_2               BIT(1)
  65 #define CCGX_RAB_RESPONSE                       0x007E
  66 #define  ASYNC_EVENT                            BIT(7)
  67
  68 /* CCGx events & async msg codes */
  69 #define RESET_COMPLETE          0x80
  70 #define EVENT_INDEX             RESET_COMPLETE
  71 #define PORT_CONNECT_DET        0x84
  72 #define PORT_DISCONNECT_DET     0x85
  73 #define ROLE_SWAP_COMPELETE     0x87
  74
  75 /* ccg firmware */
  76 #define CYACD_LINE_SIZE         527
  77 #define CCG4_ROW_SIZE           256
  78 #define FW1_METADATA_ROW        0x1FF
  79 #define FW2_METADATA_ROW        0x1FE
  80 #define FW_CFG_TABLE_SIG_SIZE   256
  81
  82 static int secondary_fw_min_ver = 41;
  83
  84 enum enum_flash_mode {
  85         SECONDARY_BL,   /* update secondary using bootloader */
  86         PRIMARY,        /* update primary using secondary */
  87         SECONDARY,      /* update secondary using primary */
  88         FLASH_NOT_NEEDED,       /* update not required */
  89         FLASH_INVALID,
  90 };
  91
  92 static const char * const ccg_fw_names[] = {
  93         "ccg_boot.cyacd",
  94         "ccg_primary.cyacd",
  95         "ccg_secondary.cyacd"
  96 };
  97
  98 struct ccg_dev_info {
  99 #define CCG_DEVINFO_FWMODE_SHIFT (0)
 100 #define CCG_DEVINFO_FWMODE_MASK (0x3 << CCG_DEVINFO_FWMODE_SHIFT)
 101 #define CCG_DEVINFO_PDPORTS_SHIFT (2)
 102 #define CCG_DEVINFO_PDPORTS_MASK (0x3 << CCG_DEVINFO_PDPORTS_SHIFT)
 103         u8 mode;
 104         u8 bl_mode;
 105         __le16 silicon_id;
 106         __le16 bl_last_row;
 107 } __packed;
 108
 109 struct version_format {
 110         __le16 build;
 111         u8 patch;
 112         u8 ver;
 113 #define CCG_VERSION_PATCH(x) ((x) << 16)
 114 #define CCG_VERSION(x)  ((x) << 24)
 115 #define CCG_VERSION_MIN_SHIFT (0)
 116 #define CCG_VERSION_MIN_MASK (0xf << CCG_VERSION_MIN_SHIFT)
 117 #define CCG_VERSION_MAJ_SHIFT (4)
 118 #define CCG_VERSION_MAJ_MASK (0xf << CCG_VERSION_MAJ_SHIFT)
 119 } __packed;
 120
 121 /*
 122  * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
 123  * of missing interrupt when a device is connected for runtime resume
 124  */
 125 #define CCG_FW_BUILD_NVIDIA     (('n' << 8) | 'v')
 126 #define CCG_OLD_FW_VERSION      (CCG_VERSION(0x31) | CCG_VERSION_PATCH(10))
 127
 128 struct version_info {
 129         struct version_format base;
 130         struct version_format app;
 131 };
 132
 133 struct fw_config_table {
 134         u32 identity;
 135         u16 table_size;
 136         u8 fwct_version;
 137         u8 is_key_change;
 138         u8 guid[16];
 139         struct version_format base;
 140         struct version_format app;
 141         u8 primary_fw_digest[32];
 142         u32 key_exp_length;
 143         u8 key_modulus[256];
 144         u8 key_exp[4];
 145 };
 146
 147 /* CCGx response codes */
 148 enum ccg_resp_code {
 149         CMD_NO_RESP             = 0x00,
 150         CMD_SUCCESS             = 0x02,
 151         FLASH_DATA_AVAILABLE    = 0x03,
 152         CMD_INVALID             = 0x05,
 153         FLASH_UPDATE_FAIL       = 0x07,
 154         INVALID_FW              = 0x08,
 155         INVALID_ARG             = 0x09,
 156         CMD_NOT_SUPPORT         = 0x0A,
 157         TRANSACTION_FAIL        = 0x0C,
 158         PD_CMD_FAIL             = 0x0D,
 159         UNDEF_ERROR             = 0x0F,
 160         INVALID_RESP            = 0x10,
 161 };
 162
 163 #define CCG_EVENT_MAX   (EVENT_INDEX + 43)
 164
 165 struct ccg_cmd {
 166         u16 reg;
 167         u32 data;
 168         int len;
 169         u32 delay; /* ms delay for cmd timeout  */
 170 };
 171
 172 struct ccg_resp {
 173         u8 code;
 174         u8 length;
 175 };
 176
 177 struct ucsi_ccg_altmode {
 178         u16 svid;
 179         u32 mid;
 180         u8 linked_idx;
 181         u8 active_idx;
 182 #define UCSI_MULTI_DP_INDEX     (0xff)
 183         bool checked;
 184 } __packed;
 185
 186 struct ucsi_ccg {
 187         struct device *dev;
 188         struct ucsi *ucsi;
 189         struct i2c_client *client;
 190
 191         struct ccg_dev_info info;
 192         /* version info for boot, primary and secondary */
 193         struct version_info version[FW2 + 1];
 194         u32 fw_version;
 195         /* CCG HPI communication flags */
 196         unsigned long flags;
 197 #define RESET_PENDING   0
 198 #define DEV_CMD_PENDING 1
 199         struct ccg_resp dev_resp;
 200         u8 cmd_resp;
 201         int port_num;
 202         int irq;
 203         struct work_struct work;
 204         struct mutex lock; /* to sync between user and driver thread */
 205
 206         /* fw build with vendor information */
 207         u16 fw_build;
 208         struct work_struct pm_work;
 209
 210         struct completion complete;
 211
 212         u64 last_cmd_sent;
 213         bool has_multiple_dp;
 214         struct ucsi_ccg_altmode orig[UCSI_MAX_ALTMODES];
 215         struct ucsi_ccg_altmode updated[UCSI_MAX_ALTMODES];
 216 };
 217
 218 static int ccg_read(struct ucsi_ccg *uc, u16 rab, u8 *data, u32 len)
 219 {
 220         struct i2c_client *client = uc->client;
 221         const struct i2c_adapter_quirks *quirks = client->adapter->quirks;
 222         unsigned char buf[2];
 223         struct i2c_msg msgs[] = {
 224                 {
 225                         .addr   = client->addr,
 226                         .flags  = 0x0,
 227                         .len    = sizeof(buf),
 228                         .buf    = buf,
 229                 },
 230                 {
 231                         .addr   = client->addr,
 232                         .flags  = I2C_M_RD,
 233                         .buf    = data,
 234                 },
 235         };
 236         u32 rlen, rem_len = len, max_read_len = len;
 237         int status;
 238
 239         /* check any max_read_len limitation on i2c adapter */
 240         if (quirks && quirks->max_read_len)
 241                 max_read_len = quirks->max_read_len;
 242
 243         pm_runtime_get_sync(uc->dev);
 244         while (rem_len > 0) {
 245                 msgs[1].buf = &data[len - rem_len];
 246                 rlen = min_t(u16, rem_len, max_read_len);
 247                 msgs[1].len = rlen;
 248                 put_unaligned_le16(rab, buf);
 249                 status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 250                 if (status < 0) {
 251                         dev_err(uc->dev, "i2c_transfer failed %d\n", status);
 252                         pm_runtime_put_sync(uc->dev);
 253                         return status;
 254                 }
 255                 rab += rlen;
 256                 rem_len -= rlen;
 257         }
 258
 259         pm_runtime_put_sync(uc->dev);
 260         return 0;
 261 }
 262
 263 static int ccg_write(struct ucsi_ccg *uc, u16 rab, const u8 *data, u32 len)
 264 {
 265         struct i2c_client *client = uc->client;
 266         unsigned char *buf;
 267         struct i2c_msg msgs[] = {
 268                 {
 269                         .addr   = client->addr,
 270                         .flags  = 0x0,
 271                 }
 272         };
 273         int status;
 274
 275         buf = kzalloc(len + sizeof(rab), GFP_KERNEL);
 276         if (!buf)
 277                 return -ENOMEM;
 278
 279         put_unaligned_le16(rab, buf);
 280         memcpy(buf + sizeof(rab), data, len);
 281
 282         msgs[0].len = len + sizeof(rab);
 283         msgs[0].buf = buf;
 284
 285         pm_runtime_get_sync(uc->dev);
 286         status = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 287         if (status < 0) {
 288                 dev_err(uc->dev, "i2c_transfer failed %d\n", status);
 289                 pm_runtime_put_sync(uc->dev);
 290                 kfree(buf);
 291                 return status;
 292         }
 293
 294         pm_runtime_put_sync(uc->dev);
 295         kfree(buf);
 296         return 0;
 297 }
 298
 299 static int ucsi_ccg_init(struct ucsi_ccg *uc)
 300 {
 301         unsigned int count = 10;
 302         u8 data;
 303         int status;
 304
 305         data = CCGX_RAB_UCSI_CONTROL_STOP;
 306         status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
 307         if (status < 0)
 308                 return status;
 309
 310         data = CCGX_RAB_UCSI_CONTROL_START;
 311         status = ccg_write(uc, CCGX_RAB_UCSI_CONTROL, &data, sizeof(data));
 312         if (status < 0)
 313                 return status;
 314
 315         /*
 316          * Flush CCGx RESPONSE queue by acking interrupts. Above ucsi control
 317          * register write will push response which must be cleared.
 318          */
 319         do {
 320                 status = ccg_read(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
 321                 if (status < 0)
 322                         return status;
 323
 324                 if (!data)
 325                         return 0;
 326
 327                 status = ccg_write(uc, CCGX_RAB_INTR_REG, &data, sizeof(data));
 328                 if (status < 0)
 329                         return status;
 330
 331                 usleep_range(10000, 11000);
 332         } while (--count);
 333
 334         return -ETIMEDOUT;
 335 }
 336
 337 static void ucsi_ccg_update_get_current_cam_cmd(struct ucsi_ccg *uc, u8 *data)
 338 {
 339         u8 cam, new_cam;
 340
 341         cam = data[0];
 342         new_cam = uc->orig[cam].linked_idx;
 343         uc->updated[new_cam].active_idx = cam;
 344         data[0] = new_cam;
 345 }
 346
 347 static bool ucsi_ccg_update_altmodes(struct ucsi *ucsi,
 348                                      struct ucsi_altmode *orig,
 349                                      struct ucsi_altmode *updated)
 350 {
 351         struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
 352         struct ucsi_ccg_altmode *alt, *new_alt;
 353         int i, j, k = 0;
 354         bool found = false;
 355
 356         alt = uc->orig;
 357         new_alt = uc->updated;
 358         memset(uc->updated, 0, sizeof(uc->updated));
 359
 360         /*
 361          * Copy original connector altmodes to new structure.
 362          * We need this before second loop since second loop
 363          * checks for duplicate altmodes.
 364          */
 365         for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
 366                 alt[i].svid = orig[i].svid;
 367                 alt[i].mid = orig[i].mid;
 368                 if (!alt[i].svid)
 369                         break;
 370         }
 371
 372         for (i = 0; i < UCSI_MAX_ALTMODES; i++) {
 373                 if (!alt[i].svid)
 374                         break;
 375
 376                 /* already checked and considered */
 377                 if (alt[i].checked)
 378                         continue;
 379
 380                 if (!DP_CONF_GET_PIN_ASSIGN(alt[i].mid)) {
 381                         /* Found Non DP altmode */
 382                         new_alt[k].svid = alt[i].svid;
 383                         new_alt[k].mid |= alt[i].mid;
 384                         new_alt[k].linked_idx = i;
 385                         alt[i].linked_idx = k;
 386                         updated[k].svid = new_alt[k].svid;
 387                         updated[k].mid = new_alt[k].mid;
 388                         k++;
 389                         continue;
 390                 }
 391
 392                 for (j = i + 1; j < UCSI_MAX_ALTMODES; j++) {
 393                         if (alt[i].svid != alt[j].svid ||
 394                             !DP_CONF_GET_PIN_ASSIGN(alt[j].mid)) {
 395                                 continue;
 396                         } else {
 397                                 /* Found duplicate DP mode */
 398                                 new_alt[k].svid = alt[i].svid;
 399                                 new_alt[k].mid |= alt[i].mid | alt[j].mid;
 400                                 new_alt[k].linked_idx = UCSI_MULTI_DP_INDEX;
 401                                 alt[i].linked_idx = k;
 402                                 alt[j].linked_idx = k;
 403                                 alt[j].checked = true;
 404                                 found = true;
 405                         }
 406                 }
 407                 if (found) {
 408                         uc->has_multiple_dp = true;
 409                 } else {
 410                         /* Didn't find any duplicate DP altmode */
 411                         new_alt[k].svid = alt[i].svid;
 412                         new_alt[k].mid |= alt[i].mid;
 413                         new_alt[k].linked_idx = i;
 414                         alt[i].linked_idx = k;
 415                 }
 416                 updated[k].svid = new_alt[k].svid;
 417                 updated[k].mid = new_alt[k].mid;
 418                 k++;
 419         }
 420         return found;
 421 }
 422
 423 static void ucsi_ccg_update_set_new_cam_cmd(struct ucsi_ccg *uc,
 424                                             struct ucsi_connector *con,
 425                                             u64 *cmd)
 426 {
 427         struct ucsi_ccg_altmode *new_port, *port;
 428         struct typec_altmode *alt = NULL;
 429         u8 new_cam, cam, pin;
 430         bool enter_new_mode;
 431         int i, j, k = 0xff;
 432
 433         port = uc->orig;
 434         new_cam = UCSI_SET_NEW_CAM_GET_AM(*cmd);
 435         new_port = &uc->updated[new_cam];
 436         cam = new_port->linked_idx;
 437         enter_new_mode = UCSI_SET_NEW_CAM_ENTER(*cmd);
 438
 439         /*
 440          * If CAM is UCSI_MULTI_DP_INDEX then this is DP altmode
 441          * with multiple DP mode. Find out CAM for best pin assignment
 442          * among all DP mode. Priorite pin E->D->C after making sure
 443          * the partner supports that pin.
 444          */
 445         if (cam == UCSI_MULTI_DP_INDEX) {
 446                 if (enter_new_mode) {
 447                         for (i = 0; con->partner_altmode[i]; i++) {
 448                                 alt = con->partner_altmode[i];
 449                                 if (alt->svid == new_port->svid)
 450                                         break;
 451                         }
 452                         /*
 453                          * alt will always be non NULL since this is
 454                          * UCSI_SET_NEW_CAM command and so there will be
 455                          * at least one con->partner_altmode[i] with svid
 456                          * matching with new_port->svid.
 457                          */
 458                         for (j = 0; port[j].svid; j++) {
 459                                 pin = DP_CONF_GET_PIN_ASSIGN(port[j].mid);
 460                                 if (alt && port[j].svid == alt->svid &&
 461                                     (pin & DP_CONF_GET_PIN_ASSIGN(alt->vdo))) {
 462                                         /* prioritize pin E->D->C */
 463                                         if (k == 0xff || (k != 0xff && pin >
 464                                             DP_CONF_GET_PIN_ASSIGN(port[k].mid))
 465                                             ) {
 466                                                 k = j;
 467                                         }
 468                                 }
 469                         }
 470                         cam = k;
 471                         new_port->active_idx = cam;
 472                 } else {
 473                         cam = new_port->active_idx;
 474                 }
 475         }
 476         *cmd &= ~UCSI_SET_NEW_CAM_AM_MASK;
 477         *cmd |= UCSI_SET_NEW_CAM_SET_AM(cam);
 478 }
 479
 480 static int ucsi_ccg_read(struct ucsi *ucsi, unsigned int offset,
 481                          void *val, size_t val_len)
 482 {
 483         struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
 484         int ret;
 485         u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset);
 486
 487         ret = ccg_read(uc, reg, val, val_len);
 488         if (ret)
 489                 return ret;
 490
 491         if (offset == UCSI_MESSAGE_IN) {
 492                 if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_GET_CURRENT_CAM &&
 493                     uc->has_multiple_dp) {
 494                         ucsi_ccg_update_get_current_cam_cmd(uc, (u8 *)val);
 495                 }
 496                 uc->last_cmd_sent = 0;
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int ucsi_ccg_async_write(struct ucsi *ucsi, unsigned int offset,
 503                                 const void *val, size_t val_len)
 504 {
 505         u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(offset);
 506
 507         return ccg_write(ucsi_get_drvdata(ucsi), reg, val, val_len);
 508 }
 509
 510 static int ucsi_ccg_sync_write(struct ucsi *ucsi, unsigned int offset,
 511                                const void *val, size_t val_len)
 512 {
 513         struct ucsi_ccg *uc = ucsi_get_drvdata(ucsi);
 514         struct ucsi_connector *con;
 515         int con_index;
 516         int ret;
 517
 518         mutex_lock(&uc->lock);
 519         pm_runtime_get_sync(uc->dev);
 520         set_bit(DEV_CMD_PENDING, &uc->flags);
 521
 522         if (offset == UCSI_CONTROL && val_len == sizeof(uc->last_cmd_sent)) {
 523                 uc->last_cmd_sent = *(u64 *)val;
 524
 525                 if (UCSI_COMMAND(uc->last_cmd_sent) == UCSI_SET_NEW_CAM &&
 526                     uc->has_multiple_dp) {
 527                         con_index = (uc->last_cmd_sent >> 16) &
 528                                     UCSI_CMD_CONNECTOR_MASK;
 529                         con = &uc->ucsi->connector[con_index - 1];
 530                         ucsi_ccg_update_set_new_cam_cmd(uc, con, (u64 *)val);
 531                 }
 532         }
 533
 534         ret = ucsi_ccg_async_write(ucsi, offset, val, val_len);
 535         if (ret)
 536                 goto err_clear_bit;
 537
 538         if (!wait_for_completion_timeout(&uc->complete, msecs_to_jiffies(5000)))
 539                 ret = -ETIMEDOUT;
 540
 541 err_clear_bit:
 542         clear_bit(DEV_CMD_PENDING, &uc->flags);
 543         pm_runtime_put_sync(uc->dev);
 544         mutex_unlock(&uc->lock);
 545
 546         return ret;
 547 }
 548
 549 static const struct ucsi_operations ucsi_ccg_ops = {
 550         .read = ucsi_ccg_read,
 551         .sync_write = ucsi_ccg_sync_write,
 552         .async_write = ucsi_ccg_async_write,
 553         .update_altmodes = ucsi_ccg_update_altmodes
 554 };
 555
 556 static irqreturn_t ccg_irq_handler(int irq, void *data)
 557 {
 558         u16 reg = CCGX_RAB_UCSI_DATA_BLOCK(UCSI_CCI);
 559         struct ucsi_ccg *uc = data;
 560         u8 intr_reg;
 561         u32 cci;
 562         int ret;
 563
 564         ret = ccg_read(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
 565         if (ret)
 566                 return ret;
 567
 568         ret = ccg_read(uc, reg, (void *)&cci, sizeof(cci));
 569         if (ret)
 570                 goto err_clear_irq;
 571
 572         if (UCSI_CCI_CONNECTOR(cci))
 573                 ucsi_connector_change(uc->ucsi, UCSI_CCI_CONNECTOR(cci));
 574
 575         if (test_bit(DEV_CMD_PENDING, &uc->flags) &&
 576             cci & (UCSI_CCI_ACK_COMPLETE | UCSI_CCI_COMMAND_COMPLETE))
 577                 complete(&uc->complete);
 578
 579 err_clear_irq:
 580         ccg_write(uc, CCGX_RAB_INTR_REG, &intr_reg, sizeof(intr_reg));
 581
 582         return IRQ_HANDLED;
 583 }
 584
 585 static void ccg_pm_workaround_work(struct work_struct *pm_work)
 586 {
 587         ccg_irq_handler(0, container_of(pm_work, struct ucsi_ccg, pm_work));
 588 }
 589
 590 static int get_fw_info(struct ucsi_ccg *uc)
 591 {
 592         int err;
 593
 594         err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)(&uc->version),
 595                        sizeof(uc->version));
 596         if (err < 0)
 597                 return err;
 598
 599         uc->fw_version = CCG_VERSION(uc->version[FW2].app.ver) |
 600                         CCG_VERSION_PATCH(uc->version[FW2].app.patch);
 601
 602         err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
 603                        sizeof(uc->info));
 604         if (err < 0)
 605                 return err;
 606
 607         return 0;
 608 }
 609
 610 static inline bool invalid_async_evt(int code)
 611 {
 612         return (code >= CCG_EVENT_MAX) || (code < EVENT_INDEX);
 613 }
 614
 615 static void ccg_process_response(struct ucsi_ccg *uc)
 616 {
 617         struct device *dev = uc->dev;
 618
 619         if (uc->dev_resp.code & ASYNC_EVENT) {
 620                 if (uc->dev_resp.code == RESET_COMPLETE) {
 621                         if (test_bit(RESET_PENDING, &uc->flags))
 622                                 uc->cmd_resp = uc->dev_resp.code;
 623                         get_fw_info(uc);
 624                 }
 625                 if (invalid_async_evt(uc->dev_resp.code))
 626                         dev_err(dev, "invalid async evt %d\n",
 627                                 uc->dev_resp.code);
 628         } else {
 629                 if (test_bit(DEV_CMD_PENDING, &uc->flags)) {
 630                         uc->cmd_resp = uc->dev_resp.code;
 631                         clear_bit(DEV_CMD_PENDING, &uc->flags);
 632                 } else {
 633                         dev_err(dev, "dev resp 0x%04x but no cmd pending\n",
 634                                 uc->dev_resp.code);
 635                 }
 636         }
 637 }
 638
 639 static int ccg_read_response(struct ucsi_ccg *uc)
 640 {
 641         unsigned long target = jiffies + msecs_to_jiffies(1000);
 642         struct device *dev = uc->dev;
 643         u8 intval;
 644         int status;
 645
 646         /* wait for interrupt status to get updated */
 647         do {
 648                 status = ccg_read(uc, CCGX_RAB_INTR_REG, &intval,
 649                                   sizeof(intval));
 650                 if (status < 0)
 651                         return status;
 652
 653                 if (intval & DEV_INT)
 654                         break;
 655                 usleep_range(500, 600);
 656         } while (time_is_after_jiffies(target));
 657
 658         if (time_is_before_jiffies(target)) {
 659                 dev_err(dev, "response timeout error\n");
 660                 return -ETIME;
 661         }
 662
 663         status = ccg_read(uc, CCGX_RAB_RESPONSE, (u8 *)&uc->dev_resp,
 664                           sizeof(uc->dev_resp));
 665         if (status < 0)
 666                 return status;
 667
 668         status = ccg_write(uc, CCGX_RAB_INTR_REG, &intval, sizeof(intval));
 669         if (status < 0)
 670                 return status;
 671
 672         return 0;
 673 }
 674
 675 /* Caller must hold uc->lock */
 676 static int ccg_send_command(struct ucsi_ccg *uc, struct ccg_cmd *cmd)
 677 {
 678         struct device *dev = uc->dev;
 679         int ret;
 680
 681         switch (cmd->reg & 0xF000) {
 682         case DEV_REG_IDX:
 683                 set_bit(DEV_CMD_PENDING, &uc->flags);
 684                 break;
 685         default:
 686                 dev_err(dev, "invalid cmd register\n");
 687                 break;
 688         }
 689
 690         ret = ccg_write(uc, cmd->reg, (u8 *)&cmd->data, cmd->len);
 691         if (ret < 0)
 692                 return ret;
 693
 694         msleep(cmd->delay);
 695
 696         ret = ccg_read_response(uc);
 697         if (ret < 0) {
 698                 dev_err(dev, "response read error\n");
 699                 switch (cmd->reg & 0xF000) {
 700                 case DEV_REG_IDX:
 701                         clear_bit(DEV_CMD_PENDING, &uc->flags);
 702                         break;
 703                 default:
 704                         dev_err(dev, "invalid cmd register\n");
 705                         break;
 706                 }
 707                 return -EIO;
 708         }
 709         ccg_process_response(uc);
 710
 711         return uc->cmd_resp;
 712 }
 713
 714 static int ccg_cmd_enter_flashing(struct ucsi_ccg *uc)
 715 {
 716         struct ccg_cmd cmd;
 717         int ret;
 718
 719         cmd.reg = CCGX_RAB_ENTER_FLASHING;
 720         cmd.data = FLASH_ENTER_SIG;
 721         cmd.len = 1;
 722         cmd.delay = 50;
 723
 724         mutex_lock(&uc->lock);
 725
 726         ret = ccg_send_command(uc, &cmd);
 727
 728         mutex_unlock(&uc->lock);
 729
 730         if (ret != CMD_SUCCESS) {
 731                 dev_err(uc->dev, "enter flashing failed ret=%d\n", ret);
 732                 return ret;
 733         }
 734
 735         return 0;
 736 }
 737
 738 static int ccg_cmd_reset(struct ucsi_ccg *uc)
 739 {
 740         struct ccg_cmd cmd;
 741         u8 *p;
 742         int ret;
 743
 744         p = (u8 *)&cmd.data;
 745         cmd.reg = CCGX_RAB_RESET_REQ;
 746         p[0] = RESET_SIG;
 747         p[1] = CMD_RESET_DEV;
 748         cmd.len = 2;
 749         cmd.delay = 5000;
 750
 751         mutex_lock(&uc->lock);
 752
 753         set_bit(RESET_PENDING, &uc->flags);
 754
 755         ret = ccg_send_command(uc, &cmd);
 756         if (ret != RESET_COMPLETE)
 757                 goto err_clear_flag;
 758
 759         ret = 0;
 760
 761 err_clear_flag:
 762         clear_bit(RESET_PENDING, &uc->flags);
 763
 764         mutex_unlock(&uc->lock);
 765
 766         return ret;
 767 }
 768
 769 static int ccg_cmd_port_control(struct ucsi_ccg *uc, bool enable)
 770 {
 771         struct ccg_cmd cmd;
 772         int ret;
 773
 774         cmd.reg = CCGX_RAB_PDPORT_ENABLE;
 775         if (enable)
 776                 cmd.data = (uc->port_num == 1) ?
 777                             PDPORT_1 : (PDPORT_1 | PDPORT_2);
 778         else
 779                 cmd.data = 0x0;
 780         cmd.len = 1;
 781         cmd.delay = 10;
 782
 783         mutex_lock(&uc->lock);
 784
 785         ret = ccg_send_command(uc, &cmd);
 786
 787         mutex_unlock(&uc->lock);
 788
 789         if (ret != CMD_SUCCESS) {
 790                 dev_err(uc->dev, "port control failed ret=%d\n", ret);
 791                 return ret;
 792         }
 793         return 0;
 794 }
 795
 796 static int ccg_cmd_jump_boot_mode(struct ucsi_ccg *uc, int bl_mode)
 797 {
 798         struct ccg_cmd cmd;
 799         int ret;
 800
 801         cmd.reg = CCGX_RAB_JUMP_TO_BOOT;
 802
 803         if (bl_mode)
 804                 cmd.data = TO_BOOT;
 805         else
 806                 cmd.data = TO_ALT_FW;
 807
 808         cmd.len = 1;
 809         cmd.delay = 100;
 810
 811         mutex_lock(&uc->lock);
 812
 813         set_bit(RESET_PENDING, &uc->flags);
 814
 815         ret = ccg_send_command(uc, &cmd);
 816         if (ret != RESET_COMPLETE)
 817                 goto err_clear_flag;
 818
 819         ret = 0;
 820
 821 err_clear_flag:
 822         clear_bit(RESET_PENDING, &uc->flags);
 823
 824         mutex_unlock(&uc->lock);
 825
 826         return ret;
 827 }
 828
 829 static int
 830 ccg_cmd_write_flash_row(struct ucsi_ccg *uc, u16 row,
 831                         const void *data, u8 fcmd)
 832 {
 833         struct i2c_client *client = uc->client;
 834         struct ccg_cmd cmd;
 835         u8 buf[CCG4_ROW_SIZE + 2];
 836         u8 *p;
 837         int ret;
 838
 839         /* Copy the data into the flash read/write memory. */
 840         put_unaligned_le16(REG_FLASH_RW_MEM, buf);
 841
 842         memcpy(buf + 2, data, CCG4_ROW_SIZE);
 843
 844         mutex_lock(&uc->lock);
 845
 846         ret = i2c_master_send(client, buf, CCG4_ROW_SIZE + 2);
 847         if (ret != CCG4_ROW_SIZE + 2) {
 848                 dev_err(uc->dev, "REG_FLASH_RW_MEM write fail %d\n", ret);
 849                 mutex_unlock(&uc->lock);
 850                 return ret < 0 ? ret : -EIO;
 851         }
 852
 853         /* Use the FLASH_ROW_READ_WRITE register to trigger */
 854         /* writing of data to the desired flash row */
 855         p = (u8 *)&cmd.data;
 856         cmd.reg = CCGX_RAB_FLASH_ROW_RW;
 857         p[0] = FLASH_SIG;
 858         p[1] = fcmd;
 859         put_unaligned_le16(row, &p[2]);
 860         cmd.len = 4;
 861         cmd.delay = 50;
 862         if (fcmd == FLASH_FWCT_SIG_WR_CMD)
 863                 cmd.delay += 400;
 864         if (row == 510)
 865                 cmd.delay += 220;
 866         ret = ccg_send_command(uc, &cmd);
 867
 868         mutex_unlock(&uc->lock);
 869
 870         if (ret != CMD_SUCCESS) {
 871                 dev_err(uc->dev, "write flash row failed ret=%d\n", ret);
 872                 return ret;
 873         }
 874
 875         return 0;
 876 }
 877
 878 static int ccg_cmd_validate_fw(struct ucsi_ccg *uc, unsigned int fwid)
 879 {
 880         struct ccg_cmd cmd;
 881         int ret;
 882
 883         cmd.reg = CCGX_RAB_VALIDATE_FW;
 884         cmd.data = fwid;
 885         cmd.len = 1;
 886         cmd.delay = 500;
 887
 888         mutex_lock(&uc->lock);
 889
 890         ret = ccg_send_command(uc, &cmd);
 891
 892         mutex_unlock(&uc->lock);
 893
 894         if (ret != CMD_SUCCESS)
 895                 return ret;
 896
 897         return 0;
 898 }
 899
 900 static bool ccg_check_vendor_version(struct ucsi_ccg *uc,
 901                                      struct version_format *app,
 902                                      struct fw_config_table *fw_cfg)
 903 {
 904         struct device *dev = uc->dev;
 905
 906         /* Check if the fw build is for supported vendors */
 907         if (le16_to_cpu(app->build) != uc->fw_build) {
 908                 dev_info(dev, "current fw is not from supported vendor\n");
 909                 return false;
 910         }
 911
 912         /* Check if the new fw build is for supported vendors */
 913         if (le16_to_cpu(fw_cfg->app.build) != uc->fw_build) {
 914                 dev_info(dev, "new fw is not from supported vendor\n");
 915                 return false;
 916         }
 917         return true;
 918 }
 919
 920 static bool ccg_check_fw_version(struct ucsi_ccg *uc, const char *fw_name,
 921                                  struct version_format *app)
 922 {
 923         const struct firmware *fw = NULL;
 924         struct device *dev = uc->dev;
 925         struct fw_config_table fw_cfg;
 926         u32 cur_version, new_version;
 927         bool is_later = false;
 928
 929         if (request_firmware(&fw, fw_name, dev) != 0) {
 930                 dev_err(dev, "error: Failed to open cyacd file %s\n", fw_name);
 931                 return false;
 932         }
 933
 934         /*
 935          * check if signed fw
 936          * last part of fw image is fw cfg table and signature
 937          */
 938         if (fw->size < sizeof(fw_cfg) + FW_CFG_TABLE_SIG_SIZE)
 939                 goto out_release_firmware;
 940
 941         memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
 942                sizeof(fw_cfg) - FW_CFG_TABLE_SIG_SIZE, sizeof(fw_cfg));
 943
 944         if (fw_cfg.identity != ('F' | 'W' << 8 | 'C' << 16 | 'T' << 24)) {
 945                 dev_info(dev, "not a signed image\n");
 946                 goto out_release_firmware;
 947         }
 948
 949         /* compare input version with FWCT version */
 950         cur_version = le16_to_cpu(app->build) | CCG_VERSION_PATCH(app->patch) |
 951                         CCG_VERSION(app->ver);
 952
 953         new_version = le16_to_cpu(fw_cfg.app.build) |
 954                         CCG_VERSION_PATCH(fw_cfg.app.patch) |
 955                         CCG_VERSION(fw_cfg.app.ver);
 956
 957         if (!ccg_check_vendor_version(uc, app, &fw_cfg))
 958                 goto out_release_firmware;
 959
 960         if (new_version > cur_version)
 961                 is_later = true;
 962
 963 out_release_firmware:
 964         release_firmware(fw);
 965         return is_later;
 966 }
 967
 968 static int ccg_fw_update_needed(struct ucsi_ccg *uc,
 969                                 enum enum_flash_mode *mode)
 970 {
 971         struct device *dev = uc->dev;
 972         int err;
 973         struct version_info version[3];
 974
 975         err = ccg_read(uc, CCGX_RAB_DEVICE_MODE, (u8 *)(&uc->info),
 976                        sizeof(uc->info));
 977         if (err) {
 978                 dev_err(dev, "read device mode failed\n");
 979                 return err;
 980         }
 981
 982         err = ccg_read(uc, CCGX_RAB_READ_ALL_VER, (u8 *)version,
 983                        sizeof(version));
 984         if (err) {
 985                 dev_err(dev, "read device mode failed\n");
 986                 return err;
 987         }
 988
 989         if (memcmp(&version[FW1], "\0\0\0\0\0\0\0\0",
 990                    sizeof(struct version_info)) == 0) {
 991                 dev_info(dev, "secondary fw is not flashed\n");
 992                 *mode = SECONDARY_BL;
 993         } else if (le16_to_cpu(version[FW1].base.build) <
 994                 secondary_fw_min_ver) {
 995                 dev_info(dev, "secondary fw version is too low (< %d)\n",
 996                          secondary_fw_min_ver);
 997                 *mode = SECONDARY;
 998         } else if (memcmp(&version[FW2], "\0\0\0\0\0\0\0\0",
 999                    sizeof(struct version_info)) == 0) {
1000                 dev_info(dev, "primary fw is not flashed\n");
1001                 *mode = PRIMARY;
1002         } else if (ccg_check_fw_version(uc, ccg_fw_names[PRIMARY],
1003                    &version[FW2].app)) {
1004                 dev_info(dev, "found primary fw with later version\n");
1005                 *mode = PRIMARY;
1006         } else {
1007                 dev_info(dev, "secondary and primary fw are the latest\n");
1008                 *mode = FLASH_NOT_NEEDED;
1009         }
1010         return 0;
1011 }
1012
1013 static int do_flash(struct ucsi_ccg *uc, enum enum_flash_mode mode)
1014 {
1015         struct device *dev = uc->dev;
1016         const struct firmware *fw = NULL;
1017         const char *p, *s;
1018         const char *eof;
1019         int err, row, len, line_sz, line_cnt = 0;
1020         unsigned long start_time = jiffies;
1021         struct fw_config_table  fw_cfg;
1022         u8 fw_cfg_sig[FW_CFG_TABLE_SIG_SIZE];
1023         u8 *wr_buf;
1024
1025         err = request_firmware(&fw, ccg_fw_names[mode], dev);
1026         if (err) {
1027                 dev_err(dev, "request %s failed err=%d\n",
1028                         ccg_fw_names[mode], err);
1029                 return err;
1030         }
1031
1032         if (((uc->info.mode & CCG_DEVINFO_FWMODE_MASK) >>
1033                         CCG_DEVINFO_FWMODE_SHIFT) == FW2) {
1034                 err = ccg_cmd_port_control(uc, false);
1035                 if (err < 0)
1036                         goto release_fw;
1037                 err = ccg_cmd_jump_boot_mode(uc, 0);
1038                 if (err < 0)
1039                         goto release_fw;
1040         }
1041
1042         eof = fw->data + fw->size;
1043
1044         /*
1045          * check if signed fw
1046          * last part of fw image is fw cfg table and signature
1047          */
1048         if (fw->size < sizeof(fw_cfg) + sizeof(fw_cfg_sig))
1049                 goto not_signed_fw;
1050
1051         memcpy((uint8_t *)&fw_cfg, fw->data + fw->size -
1052                sizeof(fw_cfg) - sizeof(fw_cfg_sig), sizeof(fw_cfg));
1053
1054         if (fw_cfg.identity != ('F' | ('W' << 8) | ('C' << 16) | ('T' << 24))) {
1055                 dev_info(dev, "not a signed image\n");
1056                 goto not_signed_fw;
1057         }
1058         eof = fw->data + fw->size - sizeof(fw_cfg) - sizeof(fw_cfg_sig);
1059
1060         memcpy((uint8_t *)&fw_cfg_sig,
1061                fw->data + fw->size - sizeof(fw_cfg_sig), sizeof(fw_cfg_sig));
1062
1063         /* flash fw config table and signature first */
1064         err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg,
1065                                       FLASH_FWCT1_WR_CMD);
1066         if (err)
1067                 goto release_fw;
1068
1069         err = ccg_cmd_write_flash_row(uc, 0, (u8 *)&fw_cfg + CCG4_ROW_SIZE,
1070                                       FLASH_FWCT2_WR_CMD);
1071         if (err)
1072                 goto release_fw;
1073
1074         err = ccg_cmd_write_flash_row(uc, 0, &fw_cfg_sig,
1075                                       FLASH_FWCT_SIG_WR_CMD);
1076         if (err)
1077                 goto release_fw;
1078
1079 not_signed_fw:
1080         wr_buf = kzalloc(CCG4_ROW_SIZE + 4, GFP_KERNEL);
1081         if (!wr_buf) {
1082                 err = -ENOMEM;
1083                 goto release_fw;
1084         }
1085
1086         err = ccg_cmd_enter_flashing(uc);
1087         if (err)
1088                 goto release_mem;
1089
1090         /*****************************************************************
1091          * CCG firmware image (.cyacd) file line format
1092          *
1093          * :00rrrrllll[dd....]cc/r/n
1094          *
1095          * :00   header
1096          * rrrr is row number to flash                          (4 char)
1097          * llll is data len to flash                            (4 char)
1098          * dd   is a data field represents one byte of data     (512 char)
1099          * cc   is checksum                                     (2 char)
1100          * \r\n newline
1101          *
1102          * Total length: 3 + 4 + 4 + 512 + 2 + 2 = 527
1103          *
1104          *****************************************************************/
1105
1106         p = strnchr(fw->data, fw->size, ':');
1107         while (p < eof) {
1108                 s = strnchr(p + 1, eof - p - 1, ':');
1109
1110                 if (!s)
1111                         s = eof;
1112
1113                 line_sz = s - p;
1114
1115                 if (line_sz != CYACD_LINE_SIZE) {
1116                         dev_err(dev, "Bad FW format line_sz=%d\n", line_sz);
1117                         err =  -EINVAL;
1118                         goto release_mem;
1119                 }
1120
1121                 if (hex2bin(wr_buf, p + 3, CCG4_ROW_SIZE + 4)) {
1122                         err =  -EINVAL;
1123                         goto release_mem;
1124                 }
1125
1126                 row = get_unaligned_be16(wr_buf);
1127                 len = get_unaligned_be16(&wr_buf[2]);
1128
1129                 if (len != CCG4_ROW_SIZE) {
1130                         err =  -EINVAL;
1131                         goto release_mem;
1132                 }
1133
1134                 err = ccg_cmd_write_flash_row(uc, row, wr_buf + 4,
1135                                               FLASH_WR_CMD);
1136                 if (err)
1137                         goto release_mem;
1138
1139                 line_cnt++;
1140                 p = s;
1141         }
1142
1143         dev_info(dev, "total %d row flashed. time: %dms\n",
1144                  line_cnt, jiffies_to_msecs(jiffies - start_time));
1145
1146         err = ccg_cmd_validate_fw(uc, (mode == PRIMARY) ? FW2 :  FW1);
1147         if (err)
1148                 dev_err(dev, "%s validation failed err=%d\n",
1149                         (mode == PRIMARY) ? "FW2" :  "FW1", err);
1150         else
1151                 dev_info(dev, "%s validated\n",
1152                          (mode == PRIMARY) ? "FW2" :  "FW1");
1153
1154         err = ccg_cmd_port_control(uc, false);
1155         if (err < 0)
1156                 goto release_mem;
1157
1158         err = ccg_cmd_reset(uc);
1159         if (err < 0)
1160                 goto release_mem;
1161
1162         err = ccg_cmd_port_control(uc, true);
1163         if (err < 0)
1164                 goto release_mem;
1165
1166 release_mem:
1167         kfree(wr_buf);
1168
1169 release_fw:
1170         release_firmware(fw);
1171         return err;
1172 }
1173
1174 /*******************************************************************************
1175  * CCG4 has two copies of the firmware in addition to the bootloader.
1176  * If the device is running FW1, FW2 can be updated with the new version.
1177  * Dual firmware mode allows the CCG device to stay in a PD contract and support
1178  * USB PD and Type-C functionality while a firmware update is in progress.
1179  ******************************************************************************/
1180 static int ccg_fw_update(struct ucsi_ccg *uc, enum enum_flash_mode flash_mode)
1181 {
1182         int err = 0;
1183
1184         while (flash_mode != FLASH_NOT_NEEDED) {
1185                 err = do_flash(uc, flash_mode);
1186                 if (err < 0)
1187                         return err;
1188                 err = ccg_fw_update_needed(uc, &flash_mode);
1189                 if (err < 0)
1190                         return err;
1191         }
1192         dev_info(uc->dev, "CCG FW update successful\n");
1193
1194         return err;
1195 }
1196
1197 static int ccg_restart(struct ucsi_ccg *uc)
1198 {
1199         struct device *dev = uc->dev;
1200         int status;
1201
1202         status = ucsi_ccg_init(uc);
1203         if (status < 0) {
1204                 dev_err(dev, "ucsi_ccg_start fail, err=%d\n", status);
1205                 return status;
1206         }
1207
1208         status = request_threaded_irq(uc->irq, NULL, ccg_irq_handler,
1209                                       IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1210                                       dev_name(dev), uc);
1211         if (status < 0) {
1212                 dev_err(dev, "request_threaded_irq failed - %d\n", status);
1213                 return status;
1214         }
1215
1216         status = ucsi_register(uc->ucsi);
1217         if (status) {
1218                 dev_err(uc->dev, "failed to register the interface\n");
1219                 return status;
1220         }
1221
1222         return 0;
1223 }
1224
1225 static void ccg_update_firmware(struct work_struct *work)
1226 {
1227         struct ucsi_ccg *uc = container_of(work, struct ucsi_ccg, work);
1228         enum enum_flash_mode flash_mode;
1229         int status;
1230
1231         status = ccg_fw_update_needed(uc, &flash_mode);
1232         if (status < 0)
1233                 return;
1234
1235         if (flash_mode != FLASH_NOT_NEEDED) {
1236                 ucsi_unregister(uc->ucsi);
1237                 free_irq(uc->irq, uc);
1238
1239                 ccg_fw_update(uc, flash_mode);
1240                 ccg_restart(uc);
1241         }
1242 }
1243
1244 static ssize_t do_flash_store(struct device *dev,
1245                               struct device_attribute *attr,
1246                               const char *buf, size_t n)
1247 {
1248         struct ucsi_ccg *uc = i2c_get_clientdata(to_i2c_client(dev));
1249         bool flash;
1250
1251         if (kstrtobool(buf, &flash))
1252                 return -EINVAL;
1253
1254         if (!flash)
1255                 return n;
1256
1257         if (uc->fw_build == 0x0) {
1258                 dev_err(dev, "fail to flash FW due to missing FW build info\n");
1259                 return -EINVAL;
1260         }
1261
1262         schedule_work(&uc->work);
1263         return n;
1264 }
1265
1266 static DEVICE_ATTR_WO(do_flash);
1267
1268 static struct attribute *ucsi_ccg_attrs[] = {
1269         &dev_attr_do_flash.attr,
1270         NULL,
1271 };
1272 ATTRIBUTE_GROUPS(ucsi_ccg);
1273
1274 static int ucsi_ccg_probe(struct i2c_client *client,
1275                           const struct i2c_device_id *id)
1276 {
1277         struct device *dev = &client->dev;
1278         struct ucsi_ccg *uc;
1279         int status;
1280
1281         uc = devm_kzalloc(dev, sizeof(*uc), GFP_KERNEL);
1282         if (!uc)
1283                 return -ENOMEM;
1284
1285         uc->dev = dev;
1286         uc->client = client;
1287         mutex_init(&uc->lock);
1288         init_completion(&uc->complete);
1289         INIT_WORK(&uc->work, ccg_update_firmware);
1290         INIT_WORK(&uc->pm_work, ccg_pm_workaround_work);
1291
1292         /* Only fail FW flashing when FW build information is not provided */
1293         status = device_property_read_u16(dev, "ccgx,firmware-build",
1294                                           &uc->fw_build);
1295         if (status)
1296                 dev_err(uc->dev, "failed to get FW build information\n");
1297
1298         /* reset ccg device and initialize ucsi */
1299         status = ucsi_ccg_init(uc);
1300         if (status < 0) {
1301                 dev_err(uc->dev, "ucsi_ccg_init failed - %d\n", status);
1302                 return status;
1303         }
1304
1305         status = get_fw_info(uc);
1306         if (status < 0) {
1307                 dev_err(uc->dev, "get_fw_info failed - %d\n", status);
1308                 return status;
1309         }
1310
1311         uc->port_num = 1;
1312
1313         if (uc->info.mode & CCG_DEVINFO_PDPORTS_MASK)
1314                 uc->port_num++;
1315
1316         uc->ucsi = ucsi_create(dev, &ucsi_ccg_ops);
1317         if (IS_ERR(uc->ucsi))
1318                 return PTR_ERR(uc->ucsi);
1319
1320         ucsi_set_drvdata(uc->ucsi, uc);
1321
1322         status = request_threaded_irq(client->irq, NULL, ccg_irq_handler,
1323                                       IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1324                                       dev_name(dev), uc);
1325         if (status < 0) {
1326                 dev_err(uc->dev, "request_threaded_irq failed - %d\n", status);
1327                 goto out_ucsi_destroy;
1328         }
1329
1330         uc->irq = client->irq;
1331
1332         status = ucsi_register(uc->ucsi);
1333         if (status)
1334                 goto out_free_irq;
1335
1336         i2c_set_clientdata(client, uc);
1337
1338         pm_runtime_set_active(uc->dev);
1339         pm_runtime_enable(uc->dev);
1340         pm_runtime_use_autosuspend(uc->dev);
1341         pm_runtime_set_autosuspend_delay(uc->dev, 5000);
1342         pm_runtime_idle(uc->dev);
1343
1344         return 0;
1345
1346 out_free_irq:
1347         free_irq(uc->irq, uc);
1348 out_ucsi_destroy:
1349         ucsi_destroy(uc->ucsi);
1350
1351         return status;
1352 }
1353
1354 static int ucsi_ccg_remove(struct i2c_client *client)
1355 {
1356         struct ucsi_ccg *uc = i2c_get_clientdata(client);
1357
1358         cancel_work_sync(&uc->pm_work);
1359         cancel_work_sync(&uc->work);
1360         pm_runtime_disable(uc->dev);
1361         ucsi_unregister(uc->ucsi);
1362         ucsi_destroy(uc->ucsi);
1363         free_irq(uc->irq, uc);
1364
1365         return 0;
1366 }
1367
1368 static const struct i2c_device_id ucsi_ccg_device_id[] = {
1369         {"ccgx-ucsi", 0},
1370         {}
1371 };
1372 MODULE_DEVICE_TABLE(i2c, ucsi_ccg_device_id);
1373
1374 static int ucsi_ccg_resume(struct device *dev)
1375 {
1376         struct i2c_client *client = to_i2c_client(dev);
1377         struct ucsi_ccg *uc = i2c_get_clientdata(client);
1378
1379         return ucsi_resume(uc->ucsi);
1380 }
1381
1382 static int ucsi_ccg_runtime_suspend(struct device *dev)
1383 {
1384         return 0;
1385 }
1386
1387 static int ucsi_ccg_runtime_resume(struct device *dev)
1388 {
1389         struct i2c_client *client = to_i2c_client(dev);
1390         struct ucsi_ccg *uc = i2c_get_clientdata(client);
1391
1392         /*
1393          * Firmware version 3.1.10 or earlier, built for NVIDIA has known issue
1394          * of missing interrupt when a device is connected for runtime resume.
1395          * Schedule a work to call ISR as a workaround.
1396          */
1397         if (uc->fw_build == CCG_FW_BUILD_NVIDIA &&
1398             uc->fw_version <= CCG_OLD_FW_VERSION)
1399                 schedule_work(&uc->pm_work);
1400
1401         return 0;
1402 }
1403
1404 static const struct dev_pm_ops ucsi_ccg_pm = {
1405         .resume = ucsi_ccg_resume,
1406         .runtime_suspend = ucsi_ccg_runtime_suspend,
1407         .runtime_resume = ucsi_ccg_runtime_resume,
1408 };
1409
1410 static struct i2c_driver ucsi_ccg_driver = {
1411         .driver = {
1412                 .name = "ucsi_ccg",
1413                 .pm = &ucsi_ccg_pm,
1414                 .dev_groups = ucsi_ccg_groups,
1415         },
1416         .probe = ucsi_ccg_probe,
1417         .remove = ucsi_ccg_remove,
1418         .id_table = ucsi_ccg_device_id,
1419 };
1420
1421 module_i2c_driver(ucsi_ccg_driver);
1422
1423 MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
1424 MODULE_DESCRIPTION("UCSI driver for Cypress CCGx Type-C controller");
1425 MODULE_LICENSE("GPL v2");