2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <linux/of_platform.h>
44 #include <video/omapdss.h>
45 #include <video/mipi_display.h>
48 #include "dss_features.h"
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg { u16 module; u16 idx; };
54 #define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx })
56 /* DSI Protocol Engine */
59 #define DSI_PROTO_SZ 0x200
61 #define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000)
62 #define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010)
63 #define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014)
64 #define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018)
65 #define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C)
66 #define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040)
67 #define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044)
68 #define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048)
69 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C)
70 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050)
71 #define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054)
72 #define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058)
73 #define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C)
74 #define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060)
75 #define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064)
76 #define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068)
77 #define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C)
78 #define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070)
79 #define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074)
80 #define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078)
81 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C)
82 #define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080)
83 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084)
84 #define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088)
85 #define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C)
86 #define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090)
87 #define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094)
88 #define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20))
89 #define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20))
90 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20))
91 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20))
92 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20))
93 #define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20))
94 #define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20))
99 #define DSI_PHY_OFFSET 0x200
100 #define DSI_PHY_SZ 0x40
102 #define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000)
103 #define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004)
104 #define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008)
105 #define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014)
106 #define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028)
108 /* DSI_PLL_CTRL_SCP */
111 #define DSI_PLL_OFFSET 0x300
112 #define DSI_PLL_SZ 0x20
114 #define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000)
115 #define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004)
116 #define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008)
117 #define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C)
118 #define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010)
120 #define REG_GET(dsidev, idx, start, end) \
121 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
123 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
124 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
126 /* Global interrupts */
127 #define DSI_IRQ_VC0 (1 << 0)
128 #define DSI_IRQ_VC1 (1 << 1)
129 #define DSI_IRQ_VC2 (1 << 2)
130 #define DSI_IRQ_VC3 (1 << 3)
131 #define DSI_IRQ_WAKEUP (1 << 4)
132 #define DSI_IRQ_RESYNC (1 << 5)
133 #define DSI_IRQ_PLL_LOCK (1 << 7)
134 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
135 #define DSI_IRQ_PLL_RECALL (1 << 9)
136 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
137 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
138 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
139 #define DSI_IRQ_TE_TRIGGER (1 << 16)
140 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
141 #define DSI_IRQ_SYNC_LOST (1 << 18)
142 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
143 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
144 #define DSI_IRQ_ERROR_MASK \
145 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
146 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
147 #define DSI_IRQ_CHANNEL_MASK 0xf
149 /* Virtual channel interrupts */
150 #define DSI_VC_IRQ_CS (1 << 0)
151 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
152 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
153 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
154 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
155 #define DSI_VC_IRQ_BTA (1 << 5)
156 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
157 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
158 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
159 #define DSI_VC_IRQ_ERROR_MASK \
160 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
161 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
162 DSI_VC_IRQ_FIFO_TX_UDF)
164 /* ComplexIO interrupts */
165 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
166 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
167 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
168 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
169 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
170 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
171 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
172 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
173 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
174 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
175 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
176 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
177 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
178 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
179 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
180 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
181 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
182 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
183 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
184 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
185 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
186 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
187 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
188 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
189 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
190 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
191 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
192 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
193 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
194 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
195 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
196 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
197 #define DSI_CIO_IRQ_ERROR_MASK \
198 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
199 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
200 DSI_CIO_IRQ_ERRSYNCESC5 | \
201 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
202 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
203 DSI_CIO_IRQ_ERRESC5 | \
204 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
205 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
206 DSI_CIO_IRQ_ERRCONTROL5 | \
207 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
208 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
209 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
210 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
211 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
213 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
215 static int dsi_display_init_dispc(struct platform_device *dsidev,
216 struct omap_overlay_manager *mgr);
217 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
218 struct omap_overlay_manager *mgr);
220 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
222 #define DSI_MAX_NR_ISRS 2
223 #define DSI_MAX_NR_LANES 5
225 enum dsi_lane_function {
234 struct dsi_lane_config {
235 enum dsi_lane_function function;
239 struct dsi_isr_data {
247 DSI_FIFO_SIZE_32 = 1,
248 DSI_FIFO_SIZE_64 = 2,
249 DSI_FIFO_SIZE_96 = 3,
250 DSI_FIFO_SIZE_128 = 4,
254 DSI_VC_SOURCE_L4 = 0,
258 struct dsi_irq_stats {
259 unsigned long last_reset;
261 unsigned dsi_irqs[32];
262 unsigned vc_irqs[4][32];
263 unsigned cio_irqs[32];
266 struct dsi_isr_tables {
267 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
268 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
269 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
272 struct dsi_clk_calc_ctx {
273 struct platform_device *dsidev;
277 const struct omap_dss_dsi_config *config;
279 unsigned long req_pck_min, req_pck_nom, req_pck_max;
283 struct dsi_clock_info dsi_cinfo;
284 struct dispc_clock_info dispc_cinfo;
286 struct omap_video_timings dispc_vm;
287 struct omap_dss_dsi_videomode_timings dsi_vm;
291 struct platform_device *pdev;
292 void __iomem *proto_base;
293 void __iomem *phy_base;
294 void __iomem *pll_base;
305 struct dispc_clock_info user_dispc_cinfo;
306 struct dsi_clock_info user_dsi_cinfo;
308 struct dsi_clock_info current_cinfo;
310 bool vdds_dsi_enabled;
311 struct regulator *vdds_dsi_reg;
314 enum dsi_vc_source source;
315 struct omap_dss_device *dssdev;
316 enum fifo_size tx_fifo_size;
317 enum fifo_size rx_fifo_size;
322 struct semaphore bus_lock;
327 struct dsi_isr_tables isr_tables;
328 /* space for a copy used by the interrupt handler */
329 struct dsi_isr_tables isr_tables_copy;
332 #ifdef DSI_PERF_MEASURE
333 unsigned update_bytes;
339 void (*framedone_callback)(int, void *);
340 void *framedone_data;
342 struct delayed_work framedone_timeout_work;
344 #ifdef DSI_CATCH_MISSING_TE
345 struct timer_list te_timer;
348 unsigned long cache_req_pck;
349 unsigned long cache_clk_freq;
350 struct dsi_clock_info cache_cinfo;
353 spinlock_t errors_lock;
354 #ifdef DSI_PERF_MEASURE
355 ktime_t perf_setup_time;
356 ktime_t perf_start_time;
361 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
362 spinlock_t irq_stats_lock;
363 struct dsi_irq_stats irq_stats;
365 /* DSI PLL Parameter Ranges */
366 unsigned long regm_max, regn_max;
367 unsigned long regm_dispc_max, regm_dsi_max;
368 unsigned long fint_min, fint_max;
369 unsigned long lpdiv_max;
371 unsigned num_lanes_supported;
372 unsigned line_buffer_size;
374 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
375 unsigned num_lanes_used;
377 unsigned scp_clk_refcount;
379 struct dss_lcd_mgr_config mgr_config;
380 struct omap_video_timings timings;
381 enum omap_dss_dsi_pixel_format pix_fmt;
382 enum omap_dss_dsi_mode mode;
383 struct omap_dss_dsi_videomode_timings vm_timings;
385 struct omap_dss_device output;
388 struct dsi_packet_sent_handler_data {
389 struct platform_device *dsidev;
390 struct completion *completion;
393 struct dsi_module_id_data {
398 static const struct of_device_id dsi_of_match[];
400 #ifdef DSI_PERF_MEASURE
401 static bool dsi_perf;
402 module_param(dsi_perf, bool, 0644);
405 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
407 return dev_get_drvdata(&dsidev->dev);
410 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
412 return to_platform_device(dssdev->dev);
415 struct platform_device *dsi_get_dsidev_from_id(int module)
417 struct omap_dss_device *out;
418 enum omap_dss_output_id id;
422 id = OMAP_DSS_OUTPUT_DSI1;
425 id = OMAP_DSS_OUTPUT_DSI2;
431 out = omap_dss_get_output(id);
433 return out ? to_platform_device(out->dev) : NULL;
436 static inline void dsi_write_reg(struct platform_device *dsidev,
437 const struct dsi_reg idx, u32 val)
439 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
443 case DSI_PROTO: base = dsi->proto_base; break;
444 case DSI_PHY: base = dsi->phy_base; break;
445 case DSI_PLL: base = dsi->pll_base; break;
449 __raw_writel(val, base + idx.idx);
452 static inline u32 dsi_read_reg(struct platform_device *dsidev,
453 const struct dsi_reg idx)
455 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
459 case DSI_PROTO: base = dsi->proto_base; break;
460 case DSI_PHY: base = dsi->phy_base; break;
461 case DSI_PLL: base = dsi->pll_base; break;
465 return __raw_readl(base + idx.idx);
468 static void dsi_bus_lock(struct omap_dss_device *dssdev)
470 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
471 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
473 down(&dsi->bus_lock);
476 static void dsi_bus_unlock(struct omap_dss_device *dssdev)
478 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
479 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
484 static bool dsi_bus_is_locked(struct platform_device *dsidev)
486 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
488 return dsi->bus_lock.count == 0;
491 static void dsi_completion_handler(void *data, u32 mask)
493 complete((struct completion *)data);
496 static inline int wait_for_bit_change(struct platform_device *dsidev,
497 const struct dsi_reg idx, int bitnum, int value)
499 unsigned long timeout;
503 /* first busyloop to see if the bit changes right away */
506 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
510 /* then loop for 500ms, sleeping for 1ms in between */
511 timeout = jiffies + msecs_to_jiffies(500);
512 while (time_before(jiffies, timeout)) {
513 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
516 wait = ns_to_ktime(1000 * 1000);
517 set_current_state(TASK_UNINTERRUPTIBLE);
518 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
524 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
527 case OMAP_DSS_DSI_FMT_RGB888:
528 case OMAP_DSS_DSI_FMT_RGB666:
530 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
532 case OMAP_DSS_DSI_FMT_RGB565:
540 #ifdef DSI_PERF_MEASURE
541 static void dsi_perf_mark_setup(struct platform_device *dsidev)
543 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
544 dsi->perf_setup_time = ktime_get();
547 static void dsi_perf_mark_start(struct platform_device *dsidev)
549 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
550 dsi->perf_start_time = ktime_get();
553 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
556 ktime_t t, setup_time, trans_time;
558 u32 setup_us, trans_us, total_us;
565 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
566 setup_us = (u32)ktime_to_us(setup_time);
570 trans_time = ktime_sub(t, dsi->perf_start_time);
571 trans_us = (u32)ktime_to_us(trans_time);
575 total_us = setup_us + trans_us;
577 total_bytes = dsi->update_bytes;
579 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
580 "%u bytes, %u kbytes/sec\n",
585 1000*1000 / total_us,
587 total_bytes * 1000 / total_us);
590 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
594 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
598 static inline void dsi_perf_show(struct platform_device *dsidev,
604 static int verbose_irq;
606 static void print_irq_status(u32 status)
611 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
614 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
616 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
618 verbose_irq ? PIS(VC0) : "",
619 verbose_irq ? PIS(VC1) : "",
620 verbose_irq ? PIS(VC2) : "",
621 verbose_irq ? PIS(VC3) : "",
638 static void print_irq_status_vc(int channel, u32 status)
643 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
646 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
648 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
654 verbose_irq ? PIS(PACKET_SENT) : "",
659 PIS(PP_BUSY_CHANGE));
663 static void print_irq_status_cio(u32 status)
668 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
670 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
684 PIS(ERRCONTENTIONLP0_1),
685 PIS(ERRCONTENTIONLP1_1),
686 PIS(ERRCONTENTIONLP0_2),
687 PIS(ERRCONTENTIONLP1_2),
688 PIS(ERRCONTENTIONLP0_3),
689 PIS(ERRCONTENTIONLP1_3),
690 PIS(ULPSACTIVENOT_ALL0),
691 PIS(ULPSACTIVENOT_ALL1));
695 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
696 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
697 u32 *vcstatus, u32 ciostatus)
699 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
702 spin_lock(&dsi->irq_stats_lock);
704 dsi->irq_stats.irq_count++;
705 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
707 for (i = 0; i < 4; ++i)
708 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
710 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
712 spin_unlock(&dsi->irq_stats_lock);
715 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
718 static int debug_irq;
720 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
721 u32 *vcstatus, u32 ciostatus)
723 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
726 if (irqstatus & DSI_IRQ_ERROR_MASK) {
727 DSSERR("DSI error, irqstatus %x\n", irqstatus);
728 print_irq_status(irqstatus);
729 spin_lock(&dsi->errors_lock);
730 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
731 spin_unlock(&dsi->errors_lock);
732 } else if (debug_irq) {
733 print_irq_status(irqstatus);
736 for (i = 0; i < 4; ++i) {
737 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
738 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
740 print_irq_status_vc(i, vcstatus[i]);
741 } else if (debug_irq) {
742 print_irq_status_vc(i, vcstatus[i]);
746 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
747 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
748 print_irq_status_cio(ciostatus);
749 } else if (debug_irq) {
750 print_irq_status_cio(ciostatus);
754 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
755 unsigned isr_array_size, u32 irqstatus)
757 struct dsi_isr_data *isr_data;
760 for (i = 0; i < isr_array_size; i++) {
761 isr_data = &isr_array[i];
762 if (isr_data->isr && isr_data->mask & irqstatus)
763 isr_data->isr(isr_data->arg, irqstatus);
767 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
768 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
772 dsi_call_isrs(isr_tables->isr_table,
773 ARRAY_SIZE(isr_tables->isr_table),
776 for (i = 0; i < 4; ++i) {
777 if (vcstatus[i] == 0)
779 dsi_call_isrs(isr_tables->isr_table_vc[i],
780 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
785 dsi_call_isrs(isr_tables->isr_table_cio,
786 ARRAY_SIZE(isr_tables->isr_table_cio),
790 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
792 struct platform_device *dsidev;
793 struct dsi_data *dsi;
794 u32 irqstatus, vcstatus[4], ciostatus;
797 dsidev = (struct platform_device *) arg;
798 dsi = dsi_get_dsidrv_data(dsidev);
800 if (!dsi->is_enabled)
803 spin_lock(&dsi->irq_lock);
805 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
807 /* IRQ is not for us */
809 spin_unlock(&dsi->irq_lock);
813 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
814 /* flush posted write */
815 dsi_read_reg(dsidev, DSI_IRQSTATUS);
817 for (i = 0; i < 4; ++i) {
818 if ((irqstatus & (1 << i)) == 0) {
823 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
825 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
826 /* flush posted write */
827 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
830 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
831 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
833 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
834 /* flush posted write */
835 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
840 #ifdef DSI_CATCH_MISSING_TE
841 if (irqstatus & DSI_IRQ_TE_TRIGGER)
842 del_timer(&dsi->te_timer);
845 /* make a copy and unlock, so that isrs can unregister
847 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
848 sizeof(dsi->isr_tables));
850 spin_unlock(&dsi->irq_lock);
852 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
854 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
856 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
861 /* dsi->irq_lock has to be locked by the caller */
862 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
863 struct dsi_isr_data *isr_array,
864 unsigned isr_array_size, u32 default_mask,
865 const struct dsi_reg enable_reg,
866 const struct dsi_reg status_reg)
868 struct dsi_isr_data *isr_data;
875 for (i = 0; i < isr_array_size; i++) {
876 isr_data = &isr_array[i];
878 if (isr_data->isr == NULL)
881 mask |= isr_data->mask;
884 old_mask = dsi_read_reg(dsidev, enable_reg);
885 /* clear the irqstatus for newly enabled irqs */
886 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
887 dsi_write_reg(dsidev, enable_reg, mask);
889 /* flush posted writes */
890 dsi_read_reg(dsidev, enable_reg);
891 dsi_read_reg(dsidev, status_reg);
894 /* dsi->irq_lock has to be locked by the caller */
895 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
897 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
898 u32 mask = DSI_IRQ_ERROR_MASK;
899 #ifdef DSI_CATCH_MISSING_TE
900 mask |= DSI_IRQ_TE_TRIGGER;
902 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
903 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
904 DSI_IRQENABLE, DSI_IRQSTATUS);
907 /* dsi->irq_lock has to be locked by the caller */
908 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
910 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
912 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
913 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
914 DSI_VC_IRQ_ERROR_MASK,
915 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
918 /* dsi->irq_lock has to be locked by the caller */
919 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
921 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
923 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
924 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
925 DSI_CIO_IRQ_ERROR_MASK,
926 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
929 static void _dsi_initialize_irq(struct platform_device *dsidev)
931 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
935 spin_lock_irqsave(&dsi->irq_lock, flags);
937 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
939 _omap_dsi_set_irqs(dsidev);
940 for (vc = 0; vc < 4; ++vc)
941 _omap_dsi_set_irqs_vc(dsidev, vc);
942 _omap_dsi_set_irqs_cio(dsidev);
944 spin_unlock_irqrestore(&dsi->irq_lock, flags);
947 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
948 struct dsi_isr_data *isr_array, unsigned isr_array_size)
950 struct dsi_isr_data *isr_data;
956 /* check for duplicate entry and find a free slot */
958 for (i = 0; i < isr_array_size; i++) {
959 isr_data = &isr_array[i];
961 if (isr_data->isr == isr && isr_data->arg == arg &&
962 isr_data->mask == mask) {
966 if (isr_data->isr == NULL && free_idx == -1)
973 isr_data = &isr_array[free_idx];
976 isr_data->mask = mask;
981 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
982 struct dsi_isr_data *isr_array, unsigned isr_array_size)
984 struct dsi_isr_data *isr_data;
987 for (i = 0; i < isr_array_size; i++) {
988 isr_data = &isr_array[i];
989 if (isr_data->isr != isr || isr_data->arg != arg ||
990 isr_data->mask != mask)
993 isr_data->isr = NULL;
994 isr_data->arg = NULL;
1003 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
1004 void *arg, u32 mask)
1006 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1007 unsigned long flags;
1010 spin_lock_irqsave(&dsi->irq_lock, flags);
1012 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1013 ARRAY_SIZE(dsi->isr_tables.isr_table));
1016 _omap_dsi_set_irqs(dsidev);
1018 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1023 static int dsi_unregister_isr(struct platform_device *dsidev,
1024 omap_dsi_isr_t isr, void *arg, u32 mask)
1026 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1027 unsigned long flags;
1030 spin_lock_irqsave(&dsi->irq_lock, flags);
1032 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
1033 ARRAY_SIZE(dsi->isr_tables.isr_table));
1036 _omap_dsi_set_irqs(dsidev);
1038 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1043 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1044 omap_dsi_isr_t isr, void *arg, u32 mask)
1046 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1047 unsigned long flags;
1050 spin_lock_irqsave(&dsi->irq_lock, flags);
1052 r = _dsi_register_isr(isr, arg, mask,
1053 dsi->isr_tables.isr_table_vc[channel],
1054 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1057 _omap_dsi_set_irqs_vc(dsidev, channel);
1059 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1064 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1065 omap_dsi_isr_t isr, void *arg, u32 mask)
1067 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1068 unsigned long flags;
1071 spin_lock_irqsave(&dsi->irq_lock, flags);
1073 r = _dsi_unregister_isr(isr, arg, mask,
1074 dsi->isr_tables.isr_table_vc[channel],
1075 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1078 _omap_dsi_set_irqs_vc(dsidev, channel);
1080 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1085 static int dsi_register_isr_cio(struct platform_device *dsidev,
1086 omap_dsi_isr_t isr, void *arg, u32 mask)
1088 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1089 unsigned long flags;
1092 spin_lock_irqsave(&dsi->irq_lock, flags);
1094 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1095 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1098 _omap_dsi_set_irqs_cio(dsidev);
1100 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1105 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1106 omap_dsi_isr_t isr, void *arg, u32 mask)
1108 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1109 unsigned long flags;
1112 spin_lock_irqsave(&dsi->irq_lock, flags);
1114 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1115 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1118 _omap_dsi_set_irqs_cio(dsidev);
1120 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1125 static u32 dsi_get_errors(struct platform_device *dsidev)
1127 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1128 unsigned long flags;
1130 spin_lock_irqsave(&dsi->errors_lock, flags);
1133 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1137 int dsi_runtime_get(struct platform_device *dsidev)
1140 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1142 DSSDBG("dsi_runtime_get\n");
1144 r = pm_runtime_get_sync(&dsi->pdev->dev);
1146 return r < 0 ? r : 0;
1149 void dsi_runtime_put(struct platform_device *dsidev)
1151 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1154 DSSDBG("dsi_runtime_put\n");
1156 r = pm_runtime_put_sync(&dsi->pdev->dev);
1157 WARN_ON(r < 0 && r != -ENOSYS);
1160 static int dsi_regulator_init(struct platform_device *dsidev)
1162 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1163 struct regulator *vdds_dsi;
1166 if (dsi->vdds_dsi_reg != NULL)
1169 vdds_dsi = devm_regulator_get(&dsi->pdev->dev, "vdd");
1171 if (IS_ERR(vdds_dsi)) {
1172 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
1173 DSSERR("can't get DSI VDD regulator\n");
1174 return PTR_ERR(vdds_dsi);
1177 if (regulator_can_change_voltage(vdds_dsi)) {
1178 r = regulator_set_voltage(vdds_dsi, 1800000, 1800000);
1180 devm_regulator_put(vdds_dsi);
1181 DSSERR("can't set the DSI regulator voltage\n");
1186 dsi->vdds_dsi_reg = vdds_dsi;
1191 /* source clock for DSI PLL. this could also be PCLKFREE */
1192 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1195 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1198 clk_prepare_enable(dsi->sys_clk);
1200 clk_disable_unprepare(dsi->sys_clk);
1202 if (enable && dsi->pll_locked) {
1203 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1204 DSSERR("cannot lock PLL when enabling clocks\n");
1208 static void _dsi_print_reset_status(struct platform_device *dsidev)
1213 /* A dummy read using the SCP interface to any DSIPHY register is
1214 * required after DSIPHY reset to complete the reset of the DSI complex
1216 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1218 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1228 #define DSI_FLD_GET(fld, start, end)\
1229 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1231 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1232 DSI_FLD_GET(PLL_STATUS, 0, 0),
1233 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1234 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1235 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1236 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1237 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1238 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1239 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1244 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1246 DSSDBG("dsi_if_enable(%d)\n", enable);
1248 enable = enable ? 1 : 0;
1249 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1251 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1252 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1259 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1261 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1263 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1266 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1268 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1270 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1273 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1275 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1277 return dsi->current_cinfo.clkin4ddr / 16;
1280 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1283 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1285 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1286 /* DSI FCLK source is DSS_CLK_FCK */
1287 r = clk_get_rate(dsi->dss_clk);
1289 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1290 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1296 static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
1297 unsigned long lp_clk_min, unsigned long lp_clk_max)
1299 unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
1300 unsigned lp_clk_div;
1301 unsigned long lp_clk;
1303 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1304 lp_clk = dsi_fclk / 2 / lp_clk_div;
1306 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1309 cinfo->lp_clk_div = lp_clk_div;
1310 cinfo->lp_clk = lp_clk;
1315 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1317 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1318 unsigned long dsi_fclk;
1319 unsigned lp_clk_div;
1320 unsigned long lp_clk;
1322 lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1324 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1327 dsi_fclk = dsi_fclk_rate(dsidev);
1329 lp_clk = dsi_fclk / 2 / lp_clk_div;
1331 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1332 dsi->current_cinfo.lp_clk = lp_clk;
1333 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1335 /* LP_CLK_DIVISOR */
1336 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1338 /* LP_RX_SYNCHRO_ENABLE */
1339 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1344 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1346 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1348 if (dsi->scp_clk_refcount++ == 0)
1349 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1352 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1356 WARN_ON(dsi->scp_clk_refcount == 0);
1357 if (--dsi->scp_clk_refcount == 0)
1358 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1361 enum dsi_pll_power_state {
1362 DSI_PLL_POWER_OFF = 0x0,
1363 DSI_PLL_POWER_ON_HSCLK = 0x1,
1364 DSI_PLL_POWER_ON_ALL = 0x2,
1365 DSI_PLL_POWER_ON_DIV = 0x3,
1368 static int dsi_pll_power(struct platform_device *dsidev,
1369 enum dsi_pll_power_state state)
1373 /* DSI-PLL power command 0x3 is not working */
1374 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1375 state == DSI_PLL_POWER_ON_DIV)
1376 state = DSI_PLL_POWER_ON_ALL;
1379 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1381 /* PLL_PWR_STATUS */
1382 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1384 DSSERR("Failed to set DSI PLL power mode to %d\n",
1394 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
1396 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1397 return clk_get_rate(dsi->sys_clk);
1400 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
1401 unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
1403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1404 int regm, regm_start, regm_stop;
1405 unsigned long out_max;
1408 out_min = out_min ? out_min : 1;
1409 out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1411 regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
1412 regm_stop = min(pll / out_min, dsi->regm_dispc_max);
1414 for (regm = regm_start; regm <= regm_stop; ++regm) {
1417 if (func(regm, out, data))
1424 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
1425 unsigned long pll_min, unsigned long pll_max,
1426 dsi_pll_calc_func func, void *data)
1428 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1429 int regn, regn_start, regn_stop;
1430 int regm, regm_start, regm_stop;
1431 unsigned long fint, pll;
1432 const unsigned long pll_hw_max = 1800000000;
1433 unsigned long fint_hw_min, fint_hw_max;
1435 fint_hw_min = dsi->fint_min;
1436 fint_hw_max = dsi->fint_max;
1438 regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
1439 regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
1441 pll_max = pll_max ? pll_max : ULONG_MAX;
1443 for (regn = regn_start; regn <= regn_stop; ++regn) {
1444 fint = clkin / regn;
1446 regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
1448 regm_stop = min3(pll_max / fint / 2,
1449 pll_hw_max / fint / 2,
1452 for (regm = regm_start; regm <= regm_stop; ++regm) {
1453 pll = 2 * regm * fint;
1455 if (func(regn, regm, fint, pll, data))
1463 /* calculate clock rates using dividers in cinfo */
1464 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1465 struct dsi_clock_info *cinfo)
1467 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1469 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1472 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1475 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1478 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1481 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1482 cinfo->fint = cinfo->clkin / cinfo->regn;
1484 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1487 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1489 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1492 if (cinfo->regm_dispc > 0)
1493 cinfo->dsi_pll_hsdiv_dispc_clk =
1494 cinfo->clkin4ddr / cinfo->regm_dispc;
1496 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1498 if (cinfo->regm_dsi > 0)
1499 cinfo->dsi_pll_hsdiv_dsi_clk =
1500 cinfo->clkin4ddr / cinfo->regm_dsi;
1502 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1507 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1509 unsigned long max_dsi_fck;
1511 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1513 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1514 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1517 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1518 struct dsi_clock_info *cinfo)
1520 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1524 u8 regn_start, regn_end, regm_start, regm_end;
1525 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1527 DSSDBG("DSI PLL clock config starts");
1529 dsi->current_cinfo.clkin = cinfo->clkin;
1530 dsi->current_cinfo.fint = cinfo->fint;
1531 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1532 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1533 cinfo->dsi_pll_hsdiv_dispc_clk;
1534 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1535 cinfo->dsi_pll_hsdiv_dsi_clk;
1537 dsi->current_cinfo.regn = cinfo->regn;
1538 dsi->current_cinfo.regm = cinfo->regm;
1539 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1540 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1542 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1544 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1546 /* DSIPHY == CLKIN4DDR */
1547 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1553 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1554 cinfo->clkin4ddr / 1000 / 1000 / 2);
1556 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1558 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1559 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1560 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1561 cinfo->dsi_pll_hsdiv_dispc_clk);
1562 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1563 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1564 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1565 cinfo->dsi_pll_hsdiv_dsi_clk);
1567 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1568 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1569 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1571 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1574 /* DSI_PLL_AUTOMODE = manual */
1575 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1577 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1578 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1580 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1582 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1584 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1585 regm_dispc_start, regm_dispc_end);
1586 /* DSIPROTO_CLOCK_DIV */
1587 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1588 regm_dsi_start, regm_dsi_end);
1589 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1591 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1593 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1595 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1596 f = cinfo->fint < 1000000 ? 0x3 :
1597 cinfo->fint < 1250000 ? 0x4 :
1598 cinfo->fint < 1500000 ? 0x5 :
1599 cinfo->fint < 1750000 ? 0x6 :
1602 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1603 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1604 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1606 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
1609 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1610 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1611 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1612 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1613 l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
1614 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1616 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1618 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1619 DSSERR("dsi pll go bit not going down.\n");
1624 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1625 DSSERR("cannot lock PLL\n");
1630 dsi->pll_locked = 1;
1632 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1633 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1634 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1635 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1636 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1637 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1638 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1639 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1640 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1641 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1642 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1643 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1644 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1645 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1646 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1647 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1649 DSSDBG("PLL config done\n");
1654 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1657 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1659 enum dsi_pll_power_state pwstate;
1661 DSSDBG("PLL init\n");
1664 * It seems that on many OMAPs we need to enable both to have a
1665 * functional HSDivider.
1667 enable_hsclk = enable_hsdiv = true;
1669 r = dsi_regulator_init(dsidev);
1673 dsi_enable_pll_clock(dsidev, 1);
1675 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1677 dsi_enable_scp_clk(dsidev);
1679 if (!dsi->vdds_dsi_enabled) {
1680 r = regulator_enable(dsi->vdds_dsi_reg);
1683 dsi->vdds_dsi_enabled = true;
1686 /* XXX PLL does not come out of reset without this... */
1687 dispc_pck_free_enable(1);
1689 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1690 DSSERR("PLL not coming out of reset.\n");
1692 dispc_pck_free_enable(0);
1696 /* XXX ... but if left on, we get problems when planes do not
1697 * fill the whole display. No idea about this */
1698 dispc_pck_free_enable(0);
1700 if (enable_hsclk && enable_hsdiv)
1701 pwstate = DSI_PLL_POWER_ON_ALL;
1702 else if (enable_hsclk)
1703 pwstate = DSI_PLL_POWER_ON_HSCLK;
1704 else if (enable_hsdiv)
1705 pwstate = DSI_PLL_POWER_ON_DIV;
1707 pwstate = DSI_PLL_POWER_OFF;
1709 r = dsi_pll_power(dsidev, pwstate);
1714 DSSDBG("PLL init done\n");
1718 if (dsi->vdds_dsi_enabled) {
1719 regulator_disable(dsi->vdds_dsi_reg);
1720 dsi->vdds_dsi_enabled = false;
1723 dsi_disable_scp_clk(dsidev);
1724 dsi_enable_pll_clock(dsidev, 0);
1728 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1730 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1732 dsi->pll_locked = 0;
1733 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1734 if (disconnect_lanes) {
1735 WARN_ON(!dsi->vdds_dsi_enabled);
1736 regulator_disable(dsi->vdds_dsi_reg);
1737 dsi->vdds_dsi_enabled = false;
1740 dsi_disable_scp_clk(dsidev);
1741 dsi_enable_pll_clock(dsidev, 0);
1743 DSSDBG("PLL uninit done\n");
1746 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1749 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1750 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1751 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1752 int dsi_module = dsi->module_id;
1754 dispc_clk_src = dss_get_dispc_clk_source();
1755 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1757 if (dsi_runtime_get(dsidev))
1760 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1762 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1764 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1766 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1767 cinfo->clkin4ddr, cinfo->regm);
1769 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1770 dss_feat_get_clk_source_name(dsi_module == 0 ?
1771 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1772 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1773 cinfo->dsi_pll_hsdiv_dispc_clk,
1775 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1778 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1779 dss_feat_get_clk_source_name(dsi_module == 0 ?
1780 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1781 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1782 cinfo->dsi_pll_hsdiv_dsi_clk,
1784 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1787 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1789 seq_printf(s, "dsi fclk source = %s (%s)\n",
1790 dss_get_generic_clk_source_name(dsi_clk_src),
1791 dss_feat_get_clk_source_name(dsi_clk_src));
1793 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1795 seq_printf(s, "DDR_CLK\t\t%lu\n",
1796 cinfo->clkin4ddr / 4);
1798 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1800 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1802 dsi_runtime_put(dsidev);
1805 void dsi_dump_clocks(struct seq_file *s)
1807 struct platform_device *dsidev;
1810 for (i = 0; i < MAX_NUM_DSI; i++) {
1811 dsidev = dsi_get_dsidev_from_id(i);
1813 dsi_dump_dsidev_clocks(dsidev, s);
1817 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1818 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1821 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1822 unsigned long flags;
1823 struct dsi_irq_stats stats;
1825 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1827 stats = dsi->irq_stats;
1828 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1829 dsi->irq_stats.last_reset = jiffies;
1831 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1833 seq_printf(s, "period %u ms\n",
1834 jiffies_to_msecs(jiffies - stats.last_reset));
1836 seq_printf(s, "irqs %d\n", stats.irq_count);
1838 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1840 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1856 PIS(LDO_POWER_GOOD);
1861 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1862 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1863 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1864 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1865 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1867 seq_printf(s, "-- VC interrupts --\n");
1876 PIS(PP_BUSY_CHANGE);
1880 seq_printf(s, "%-20s %10d\n", #x, \
1881 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1883 seq_printf(s, "-- CIO interrupts --\n");
1896 PIS(ERRCONTENTIONLP0_1);
1897 PIS(ERRCONTENTIONLP1_1);
1898 PIS(ERRCONTENTIONLP0_2);
1899 PIS(ERRCONTENTIONLP1_2);
1900 PIS(ERRCONTENTIONLP0_3);
1901 PIS(ERRCONTENTIONLP1_3);
1902 PIS(ULPSACTIVENOT_ALL0);
1903 PIS(ULPSACTIVENOT_ALL1);
1907 static void dsi1_dump_irqs(struct seq_file *s)
1909 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1911 dsi_dump_dsidev_irqs(dsidev, s);
1914 static void dsi2_dump_irqs(struct seq_file *s)
1916 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1918 dsi_dump_dsidev_irqs(dsidev, s);
1922 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1925 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1927 if (dsi_runtime_get(dsidev))
1929 dsi_enable_scp_clk(dsidev);
1931 DUMPREG(DSI_REVISION);
1932 DUMPREG(DSI_SYSCONFIG);
1933 DUMPREG(DSI_SYSSTATUS);
1934 DUMPREG(DSI_IRQSTATUS);
1935 DUMPREG(DSI_IRQENABLE);
1937 DUMPREG(DSI_COMPLEXIO_CFG1);
1938 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1939 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1940 DUMPREG(DSI_CLK_CTRL);
1941 DUMPREG(DSI_TIMING1);
1942 DUMPREG(DSI_TIMING2);
1943 DUMPREG(DSI_VM_TIMING1);
1944 DUMPREG(DSI_VM_TIMING2);
1945 DUMPREG(DSI_VM_TIMING3);
1946 DUMPREG(DSI_CLK_TIMING);
1947 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1948 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1949 DUMPREG(DSI_COMPLEXIO_CFG2);
1950 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1951 DUMPREG(DSI_VM_TIMING4);
1952 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1953 DUMPREG(DSI_VM_TIMING5);
1954 DUMPREG(DSI_VM_TIMING6);
1955 DUMPREG(DSI_VM_TIMING7);
1956 DUMPREG(DSI_STOPCLK_TIMING);
1958 DUMPREG(DSI_VC_CTRL(0));
1959 DUMPREG(DSI_VC_TE(0));
1960 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1961 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1962 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1963 DUMPREG(DSI_VC_IRQSTATUS(0));
1964 DUMPREG(DSI_VC_IRQENABLE(0));
1966 DUMPREG(DSI_VC_CTRL(1));
1967 DUMPREG(DSI_VC_TE(1));
1968 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1969 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1970 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1971 DUMPREG(DSI_VC_IRQSTATUS(1));
1972 DUMPREG(DSI_VC_IRQENABLE(1));
1974 DUMPREG(DSI_VC_CTRL(2));
1975 DUMPREG(DSI_VC_TE(2));
1976 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1977 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1978 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1979 DUMPREG(DSI_VC_IRQSTATUS(2));
1980 DUMPREG(DSI_VC_IRQENABLE(2));
1982 DUMPREG(DSI_VC_CTRL(3));
1983 DUMPREG(DSI_VC_TE(3));
1984 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1985 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1986 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1987 DUMPREG(DSI_VC_IRQSTATUS(3));
1988 DUMPREG(DSI_VC_IRQENABLE(3));
1990 DUMPREG(DSI_DSIPHY_CFG0);
1991 DUMPREG(DSI_DSIPHY_CFG1);
1992 DUMPREG(DSI_DSIPHY_CFG2);
1993 DUMPREG(DSI_DSIPHY_CFG5);
1995 DUMPREG(DSI_PLL_CONTROL);
1996 DUMPREG(DSI_PLL_STATUS);
1997 DUMPREG(DSI_PLL_GO);
1998 DUMPREG(DSI_PLL_CONFIGURATION1);
1999 DUMPREG(DSI_PLL_CONFIGURATION2);
2001 dsi_disable_scp_clk(dsidev);
2002 dsi_runtime_put(dsidev);
2006 static void dsi1_dump_regs(struct seq_file *s)
2008 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
2010 dsi_dump_dsidev_regs(dsidev, s);
2013 static void dsi2_dump_regs(struct seq_file *s)
2015 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
2017 dsi_dump_dsidev_regs(dsidev, s);
2020 enum dsi_cio_power_state {
2021 DSI_COMPLEXIO_POWER_OFF = 0x0,
2022 DSI_COMPLEXIO_POWER_ON = 0x1,
2023 DSI_COMPLEXIO_POWER_ULPS = 0x2,
2026 static int dsi_cio_power(struct platform_device *dsidev,
2027 enum dsi_cio_power_state state)
2032 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2035 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2038 DSSERR("failed to set complexio power state to "
2048 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2052 /* line buffer on OMAP3 is 1024 x 24bits */
2053 /* XXX: for some reason using full buffer size causes
2054 * considerable TX slowdown with update sizes that fill the
2056 if (!dss_has_feature(FEAT_DSI_GNQ))
2059 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2063 return 512 * 3; /* 512x24 bits */
2065 return 682 * 3; /* 682x24 bits */
2067 return 853 * 3; /* 853x24 bits */
2069 return 1024 * 3; /* 1024x24 bits */
2071 return 1194 * 3; /* 1194x24 bits */
2073 return 1365 * 3; /* 1365x24 bits */
2075 return 1920 * 3; /* 1920x24 bits */
2082 static int dsi_set_lane_config(struct platform_device *dsidev)
2084 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2085 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2086 static const enum dsi_lane_function functions[] = {
2096 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2098 for (i = 0; i < dsi->num_lanes_used; ++i) {
2099 unsigned offset = offsets[i];
2100 unsigned polarity, lane_number;
2103 for (t = 0; t < dsi->num_lanes_supported; ++t)
2104 if (dsi->lanes[t].function == functions[i])
2107 if (t == dsi->num_lanes_supported)
2111 polarity = dsi->lanes[t].polarity;
2113 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2114 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2117 /* clear the unused lanes */
2118 for (; i < dsi->num_lanes_supported; ++i) {
2119 unsigned offset = offsets[i];
2121 r = FLD_MOD(r, 0, offset + 2, offset);
2122 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2125 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2130 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2132 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2134 /* convert time in ns to ddr ticks, rounding up */
2135 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2136 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2139 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2141 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2143 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2144 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2147 static void dsi_cio_timings(struct platform_device *dsidev)
2150 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2151 u32 tlpx_half, tclk_trail, tclk_zero;
2154 /* calculate timings */
2156 /* 1 * DDR_CLK = 2 * UI */
2158 /* min 40ns + 4*UI max 85ns + 6*UI */
2159 ths_prepare = ns2ddr(dsidev, 70) + 2;
2161 /* min 145ns + 10*UI */
2162 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2164 /* min max(8*UI, 60ns+4*UI) */
2165 ths_trail = ns2ddr(dsidev, 60) + 5;
2168 ths_exit = ns2ddr(dsidev, 145);
2171 tlpx_half = ns2ddr(dsidev, 25);
2174 tclk_trail = ns2ddr(dsidev, 60) + 2;
2176 /* min 38ns, max 95ns */
2177 tclk_prepare = ns2ddr(dsidev, 65);
2179 /* min tclk-prepare + tclk-zero = 300ns */
2180 tclk_zero = ns2ddr(dsidev, 260);
2182 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2183 ths_prepare, ddr2ns(dsidev, ths_prepare),
2184 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2185 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2186 ths_trail, ddr2ns(dsidev, ths_trail),
2187 ths_exit, ddr2ns(dsidev, ths_exit));
2189 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2190 "tclk_zero %u (%uns)\n",
2191 tlpx_half, ddr2ns(dsidev, tlpx_half),
2192 tclk_trail, ddr2ns(dsidev, tclk_trail),
2193 tclk_zero, ddr2ns(dsidev, tclk_zero));
2194 DSSDBG("tclk_prepare %u (%uns)\n",
2195 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2197 /* program timings */
2199 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2200 r = FLD_MOD(r, ths_prepare, 31, 24);
2201 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2202 r = FLD_MOD(r, ths_trail, 15, 8);
2203 r = FLD_MOD(r, ths_exit, 7, 0);
2204 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2206 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2207 r = FLD_MOD(r, tlpx_half, 20, 16);
2208 r = FLD_MOD(r, tclk_trail, 15, 8);
2209 r = FLD_MOD(r, tclk_zero, 7, 0);
2211 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2212 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
2213 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2214 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
2217 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2219 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2220 r = FLD_MOD(r, tclk_prepare, 7, 0);
2221 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2224 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2225 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2226 unsigned mask_p, unsigned mask_n)
2228 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2231 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2235 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2236 unsigned p = dsi->lanes[i].polarity;
2238 if (mask_p & (1 << i))
2239 l |= 1 << (i * 2 + (p ? 0 : 1));
2241 if (mask_n & (1 << i))
2242 l |= 1 << (i * 2 + (p ? 1 : 0));
2246 * Bits in REGLPTXSCPDAT4TO0DXDY:
2254 /* Set the lane override configuration */
2256 /* REGLPTXSCPDAT4TO0DXDY */
2257 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2259 /* Enable lane override */
2262 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2265 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2267 /* Disable lane override */
2268 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2269 /* Reset the lane override configuration */
2270 /* REGLPTXSCPDAT4TO0DXDY */
2271 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2274 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2276 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2278 bool in_use[DSI_MAX_NR_LANES];
2279 static const u8 offsets_old[] = { 28, 27, 26 };
2280 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2283 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2284 offsets = offsets_old;
2286 offsets = offsets_new;
2288 for (i = 0; i < dsi->num_lanes_supported; ++i)
2289 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2296 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2299 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2300 if (!in_use[i] || (l & (1 << offsets[i])))
2304 if (ok == dsi->num_lanes_supported)
2308 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2309 if (!in_use[i] || (l & (1 << offsets[i])))
2312 DSSERR("CIO TXCLKESC%d domain not coming " \
2313 "out of reset\n", i);
2322 /* return bitmask of enabled lanes, lane0 being the lsb */
2323 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2325 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2329 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2330 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2337 static int dsi_cio_init(struct platform_device *dsidev)
2339 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2343 DSSDBG("DSI CIO init starts");
2345 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2349 dsi_enable_scp_clk(dsidev);
2351 /* A dummy read using the SCP interface to any DSIPHY register is
2352 * required after DSIPHY reset to complete the reset of the DSI complex
2354 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2356 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2357 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2359 goto err_scp_clk_dom;
2362 r = dsi_set_lane_config(dsidev);
2364 goto err_scp_clk_dom;
2366 /* set TX STOP MODE timer to maximum for this operation */
2367 l = dsi_read_reg(dsidev, DSI_TIMING1);
2368 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2369 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2370 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2371 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2372 dsi_write_reg(dsidev, DSI_TIMING1, l);
2374 if (dsi->ulps_enabled) {
2378 DSSDBG("manual ulps exit\n");
2380 /* ULPS is exited by Mark-1 state for 1ms, followed by
2381 * stop state. DSS HW cannot do this via the normal
2382 * ULPS exit sequence, as after reset the DSS HW thinks
2383 * that we are not in ULPS mode, and refuses to send the
2384 * sequence. So we need to send the ULPS exit sequence
2385 * manually by setting positive lines high and negative lines
2391 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2392 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2397 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2400 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2404 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2405 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2407 goto err_cio_pwr_dom;
2410 dsi_if_enable(dsidev, true);
2411 dsi_if_enable(dsidev, false);
2412 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2414 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2416 goto err_tx_clk_esc_rst;
2418 if (dsi->ulps_enabled) {
2419 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2420 ktime_t wait = ns_to_ktime(1000 * 1000);
2421 set_current_state(TASK_UNINTERRUPTIBLE);
2422 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2424 /* Disable the override. The lanes should be set to Mark-11
2425 * state by the HW */
2426 dsi_cio_disable_lane_override(dsidev);
2429 /* FORCE_TX_STOP_MODE_IO */
2430 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2432 dsi_cio_timings(dsidev);
2434 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2435 /* DDR_CLK_ALWAYS_ON */
2436 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2437 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2440 dsi->ulps_enabled = false;
2442 DSSDBG("CIO init done\n");
2447 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2449 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2451 if (dsi->ulps_enabled)
2452 dsi_cio_disable_lane_override(dsidev);
2454 dsi_disable_scp_clk(dsidev);
2455 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2459 static void dsi_cio_uninit(struct platform_device *dsidev)
2461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2463 /* DDR_CLK_ALWAYS_ON */
2464 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2466 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2467 dsi_disable_scp_clk(dsidev);
2468 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2471 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2472 enum fifo_size size1, enum fifo_size size2,
2473 enum fifo_size size3, enum fifo_size size4)
2475 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2480 dsi->vc[0].tx_fifo_size = size1;
2481 dsi->vc[1].tx_fifo_size = size2;
2482 dsi->vc[2].tx_fifo_size = size3;
2483 dsi->vc[3].tx_fifo_size = size4;
2485 for (i = 0; i < 4; i++) {
2487 int size = dsi->vc[i].tx_fifo_size;
2489 if (add + size > 4) {
2490 DSSERR("Illegal FIFO configuration\n");
2495 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2497 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2501 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2504 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2505 enum fifo_size size1, enum fifo_size size2,
2506 enum fifo_size size3, enum fifo_size size4)
2508 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2513 dsi->vc[0].rx_fifo_size = size1;
2514 dsi->vc[1].rx_fifo_size = size2;
2515 dsi->vc[2].rx_fifo_size = size3;
2516 dsi->vc[3].rx_fifo_size = size4;
2518 for (i = 0; i < 4; i++) {
2520 int size = dsi->vc[i].rx_fifo_size;
2522 if (add + size > 4) {
2523 DSSERR("Illegal FIFO configuration\n");
2528 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2530 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2534 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2537 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2541 r = dsi_read_reg(dsidev, DSI_TIMING1);
2542 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2543 dsi_write_reg(dsidev, DSI_TIMING1, r);
2545 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2546 DSSERR("TX_STOP bit not going down\n");
2553 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2555 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2558 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2560 struct dsi_packet_sent_handler_data *vp_data =
2561 (struct dsi_packet_sent_handler_data *) data;
2562 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2563 const int channel = dsi->update_channel;
2564 u8 bit = dsi->te_enabled ? 30 : 31;
2566 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2567 complete(vp_data->completion);
2570 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2572 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2573 DECLARE_COMPLETION_ONSTACK(completion);
2574 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2578 bit = dsi->te_enabled ? 30 : 31;
2580 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2581 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2585 /* Wait for completion only if TE_EN/TE_START is still set */
2586 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2587 if (wait_for_completion_timeout(&completion,
2588 msecs_to_jiffies(10)) == 0) {
2589 DSSERR("Failed to complete previous frame transfer\n");
2595 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2596 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2600 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2601 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2606 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2608 struct dsi_packet_sent_handler_data *l4_data =
2609 (struct dsi_packet_sent_handler_data *) data;
2610 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2611 const int channel = dsi->update_channel;
2613 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2614 complete(l4_data->completion);
2617 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2619 DECLARE_COMPLETION_ONSTACK(completion);
2620 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2623 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2624 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2628 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2629 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2630 if (wait_for_completion_timeout(&completion,
2631 msecs_to_jiffies(10)) == 0) {
2632 DSSERR("Failed to complete previous l4 transfer\n");
2638 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2639 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2643 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2644 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2649 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2651 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2653 WARN_ON(!dsi_bus_is_locked(dsidev));
2655 WARN_ON(in_interrupt());
2657 if (!dsi_vc_is_enabled(dsidev, channel))
2660 switch (dsi->vc[channel].source) {
2661 case DSI_VC_SOURCE_VP:
2662 return dsi_sync_vc_vp(dsidev, channel);
2663 case DSI_VC_SOURCE_L4:
2664 return dsi_sync_vc_l4(dsidev, channel);
2671 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2674 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2677 enable = enable ? 1 : 0;
2679 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2681 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2682 0, enable) != enable) {
2683 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2690 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2692 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2695 DSSDBG("Initial config of virtual channel %d", channel);
2697 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2699 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2700 DSSERR("VC(%d) busy when trying to configure it!\n",
2703 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2704 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2705 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2706 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2707 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2708 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2709 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2710 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2711 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2713 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2714 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2716 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2718 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2721 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2722 enum dsi_vc_source source)
2724 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2726 if (dsi->vc[channel].source == source)
2729 DSSDBG("Source config of virtual channel %d", channel);
2731 dsi_sync_vc(dsidev, channel);
2733 dsi_vc_enable(dsidev, channel, 0);
2736 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2737 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2741 /* SOURCE, 0 = L4, 1 = video port */
2742 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2744 /* DCS_CMD_ENABLE */
2745 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2746 bool enable = source == DSI_VC_SOURCE_VP;
2747 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2750 dsi_vc_enable(dsidev, channel, 1);
2752 dsi->vc[channel].source = source;
2757 static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2760 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2761 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2763 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2765 WARN_ON(!dsi_bus_is_locked(dsidev));
2767 dsi_vc_enable(dsidev, channel, 0);
2768 dsi_if_enable(dsidev, 0);
2770 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2772 dsi_vc_enable(dsidev, channel, 1);
2773 dsi_if_enable(dsidev, 1);
2775 dsi_force_tx_stop_mode_io(dsidev);
2777 /* start the DDR clock by sending a NULL packet */
2778 if (dsi->vm_timings.ddr_clk_always_on && enable)
2779 dsi_vc_send_null(dssdev, channel);
2782 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2784 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2786 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2787 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2791 (val >> 24) & 0xff);
2795 static void dsi_show_rx_ack_with_err(u16 err)
2797 DSSERR("\tACK with ERROR (%#x):\n", err);
2799 DSSERR("\t\tSoT Error\n");
2801 DSSERR("\t\tSoT Sync Error\n");
2803 DSSERR("\t\tEoT Sync Error\n");
2805 DSSERR("\t\tEscape Mode Entry Command Error\n");
2807 DSSERR("\t\tLP Transmit Sync Error\n");
2809 DSSERR("\t\tHS Receive Timeout Error\n");
2811 DSSERR("\t\tFalse Control Error\n");
2813 DSSERR("\t\t(reserved7)\n");
2815 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2817 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2818 if (err & (1 << 10))
2819 DSSERR("\t\tChecksum Error\n");
2820 if (err & (1 << 11))
2821 DSSERR("\t\tData type not recognized\n");
2822 if (err & (1 << 12))
2823 DSSERR("\t\tInvalid VC ID\n");
2824 if (err & (1 << 13))
2825 DSSERR("\t\tInvalid Transmission Length\n");
2826 if (err & (1 << 14))
2827 DSSERR("\t\t(reserved14)\n");
2828 if (err & (1 << 15))
2829 DSSERR("\t\tDSI Protocol Violation\n");
2832 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2835 /* RX_FIFO_NOT_EMPTY */
2836 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2839 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2840 DSSERR("\trawval %#08x\n", val);
2841 dt = FLD_GET(val, 5, 0);
2842 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2843 u16 err = FLD_GET(val, 23, 8);
2844 dsi_show_rx_ack_with_err(err);
2845 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2846 DSSERR("\tDCS short response, 1 byte: %#x\n",
2847 FLD_GET(val, 23, 8));
2848 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2849 DSSERR("\tDCS short response, 2 byte: %#x\n",
2850 FLD_GET(val, 23, 8));
2851 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2852 DSSERR("\tDCS long response, len %d\n",
2853 FLD_GET(val, 23, 8));
2854 dsi_vc_flush_long_data(dsidev, channel);
2856 DSSERR("\tunknown datatype 0x%02x\n", dt);
2862 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2864 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2866 if (dsi->debug_write || dsi->debug_read)
2867 DSSDBG("dsi_vc_send_bta %d\n", channel);
2869 WARN_ON(!dsi_bus_is_locked(dsidev));
2871 /* RX_FIFO_NOT_EMPTY */
2872 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2873 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2874 dsi_vc_flush_receive_data(dsidev, channel);
2877 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2879 /* flush posted write */
2880 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2885 static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2887 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2888 DECLARE_COMPLETION_ONSTACK(completion);
2892 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2893 &completion, DSI_VC_IRQ_BTA);
2897 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2898 DSI_IRQ_ERROR_MASK);
2902 r = dsi_vc_send_bta(dsidev, channel);
2906 if (wait_for_completion_timeout(&completion,
2907 msecs_to_jiffies(500)) == 0) {
2908 DSSERR("Failed to receive BTA\n");
2913 err = dsi_get_errors(dsidev);
2915 DSSERR("Error while sending BTA: %x\n", err);
2920 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2921 DSI_IRQ_ERROR_MASK);
2923 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2924 &completion, DSI_VC_IRQ_BTA);
2929 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2930 int channel, u8 data_type, u16 len, u8 ecc)
2932 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2936 WARN_ON(!dsi_bus_is_locked(dsidev));
2938 data_id = data_type | dsi->vc[channel].vc_id << 6;
2940 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2941 FLD_VAL(ecc, 31, 24);
2943 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2946 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2947 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2951 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2953 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2954 b1, b2, b3, b4, val); */
2956 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2959 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2960 u8 data_type, u8 *data, u16 len, u8 ecc)
2963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2969 if (dsi->debug_write)
2970 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2973 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) {
2974 DSSERR("unable to send long packet: packet too long.\n");
2978 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2980 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2983 for (i = 0; i < len >> 2; i++) {
2984 if (dsi->debug_write)
2985 DSSDBG("\tsending full packet %d\n", i);
2992 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2997 b1 = 0; b2 = 0; b3 = 0;
2999 if (dsi->debug_write)
3000 DSSDBG("\tsending remainder bytes %d\n", i);
3017 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3023 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3024 u8 data_type, u16 data, u8 ecc)
3026 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3030 WARN_ON(!dsi_bus_is_locked(dsidev));
3032 if (dsi->debug_write)
3033 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3035 data_type, data & 0xff, (data >> 8) & 0xff);
3037 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3039 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3040 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3044 data_id = data_type | dsi->vc[channel].vc_id << 6;
3046 r = (data_id << 0) | (data << 8) | (ecc << 24);
3048 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3053 static int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3055 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3057 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3061 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3062 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3067 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3068 r = dsi_vc_send_short(dsidev, channel,
3069 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3070 } else if (len == 1) {
3071 r = dsi_vc_send_short(dsidev, channel,
3072 type == DSS_DSI_CONTENT_GENERIC ?
3073 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3074 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3075 } else if (len == 2) {
3076 r = dsi_vc_send_short(dsidev, channel,
3077 type == DSS_DSI_CONTENT_GENERIC ?
3078 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3079 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3080 data[0] | (data[1] << 8), 0);
3082 r = dsi_vc_send_long(dsidev, channel,
3083 type == DSS_DSI_CONTENT_GENERIC ?
3084 MIPI_DSI_GENERIC_LONG_WRITE :
3085 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3091 static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3094 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3096 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3097 DSS_DSI_CONTENT_DCS);
3100 static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3103 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3105 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3106 DSS_DSI_CONTENT_GENERIC);
3109 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3110 u8 *data, int len, enum dss_dsi_content_type type)
3112 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3115 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3119 r = dsi_vc_send_bta_sync(dssdev, channel);
3123 /* RX_FIFO_NOT_EMPTY */
3124 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3125 DSSERR("rx fifo not empty after write, dumping data:\n");
3126 dsi_vc_flush_receive_data(dsidev, channel);
3133 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3134 channel, data[0], len);
3138 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3141 return dsi_vc_write_common(dssdev, channel, data, len,
3142 DSS_DSI_CONTENT_DCS);
3145 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3148 return dsi_vc_write_common(dssdev, channel, data, len,
3149 DSS_DSI_CONTENT_GENERIC);
3152 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3153 int channel, u8 dcs_cmd)
3155 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3158 if (dsi->debug_read)
3159 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3162 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3164 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3165 " failed\n", channel, dcs_cmd);
3172 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3173 int channel, u8 *reqdata, int reqlen)
3175 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3180 if (dsi->debug_read)
3181 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3185 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3187 } else if (reqlen == 1) {
3188 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3190 } else if (reqlen == 2) {
3191 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3192 data = reqdata[0] | (reqdata[1] << 8);
3198 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3200 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3201 " failed\n", channel, reqlen);
3208 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3209 u8 *buf, int buflen, enum dss_dsi_content_type type)
3211 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3216 /* RX_FIFO_NOT_EMPTY */
3217 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3218 DSSERR("RX fifo empty when trying to read.\n");
3223 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3224 if (dsi->debug_read)
3225 DSSDBG("\theader: %08x\n", val);
3226 dt = FLD_GET(val, 5, 0);
3227 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3228 u16 err = FLD_GET(val, 23, 8);
3229 dsi_show_rx_ack_with_err(err);
3233 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3234 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3235 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3236 u8 data = FLD_GET(val, 15, 8);
3237 if (dsi->debug_read)
3238 DSSDBG("\t%s short response, 1 byte: %02x\n",
3239 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3250 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3251 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3252 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3253 u16 data = FLD_GET(val, 23, 8);
3254 if (dsi->debug_read)
3255 DSSDBG("\t%s short response, 2 byte: %04x\n",
3256 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3264 buf[0] = data & 0xff;
3265 buf[1] = (data >> 8) & 0xff;
3268 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3269 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3270 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3272 int len = FLD_GET(val, 23, 8);
3273 if (dsi->debug_read)
3274 DSSDBG("\t%s long response, len %d\n",
3275 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3283 /* two byte checksum ends the packet, not included in len */
3284 for (w = 0; w < len + 2;) {
3286 val = dsi_read_reg(dsidev,
3287 DSI_VC_SHORT_PACKET_HEADER(channel));
3288 if (dsi->debug_read)
3289 DSSDBG("\t\t%02x %02x %02x %02x\n",
3293 (val >> 24) & 0xff);
3295 for (b = 0; b < 4; ++b) {
3297 buf[w] = (val >> (b * 8)) & 0xff;
3298 /* we discard the 2 byte checksum */
3305 DSSERR("\tunknown datatype 0x%02x\n", dt);
3311 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3312 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3317 static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3318 u8 *buf, int buflen)
3320 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3323 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3327 r = dsi_vc_send_bta_sync(dssdev, channel);
3331 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3332 DSS_DSI_CONTENT_DCS);
3343 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3347 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3348 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3350 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3353 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3357 r = dsi_vc_send_bta_sync(dssdev, channel);
3361 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3362 DSS_DSI_CONTENT_GENERIC);
3374 static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3377 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3379 return dsi_vc_send_short(dsidev, channel,
3380 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3383 static int dsi_enter_ulps(struct platform_device *dsidev)
3385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3386 DECLARE_COMPLETION_ONSTACK(completion);
3390 DSSDBG("Entering ULPS");
3392 WARN_ON(!dsi_bus_is_locked(dsidev));
3394 WARN_ON(dsi->ulps_enabled);
3396 if (dsi->ulps_enabled)
3399 /* DDR_CLK_ALWAYS_ON */
3400 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3401 dsi_if_enable(dsidev, 0);
3402 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3403 dsi_if_enable(dsidev, 1);
3406 dsi_sync_vc(dsidev, 0);
3407 dsi_sync_vc(dsidev, 1);
3408 dsi_sync_vc(dsidev, 2);
3409 dsi_sync_vc(dsidev, 3);
3411 dsi_force_tx_stop_mode_io(dsidev);
3413 dsi_vc_enable(dsidev, 0, false);
3414 dsi_vc_enable(dsidev, 1, false);
3415 dsi_vc_enable(dsidev, 2, false);
3416 dsi_vc_enable(dsidev, 3, false);
3418 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3419 DSSERR("HS busy when enabling ULPS\n");
3423 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3424 DSSERR("LP busy when enabling ULPS\n");
3428 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3429 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3435 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3436 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3440 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3441 /* LANEx_ULPS_SIG2 */
3442 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3444 /* flush posted write and wait for SCP interface to finish the write */
3445 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3447 if (wait_for_completion_timeout(&completion,
3448 msecs_to_jiffies(1000)) == 0) {
3449 DSSERR("ULPS enable timeout\n");
3454 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3455 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3457 /* Reset LANEx_ULPS_SIG2 */
3458 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3460 /* flush posted write and wait for SCP interface to finish the write */
3461 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3463 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3465 dsi_if_enable(dsidev, false);
3467 dsi->ulps_enabled = true;
3472 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3473 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3477 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3478 unsigned ticks, bool x4, bool x16)
3481 unsigned long total_ticks;
3484 BUG_ON(ticks > 0x1fff);
3486 /* ticks in DSI_FCK */
3487 fck = dsi_fclk_rate(dsidev);
3489 r = dsi_read_reg(dsidev, DSI_TIMING2);
3490 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3491 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3492 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3493 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3494 dsi_write_reg(dsidev, DSI_TIMING2, r);
3496 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3498 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3500 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3501 (total_ticks * 1000) / (fck / 1000 / 1000));
3504 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3508 unsigned long total_ticks;
3511 BUG_ON(ticks > 0x1fff);
3513 /* ticks in DSI_FCK */
3514 fck = dsi_fclk_rate(dsidev);
3516 r = dsi_read_reg(dsidev, DSI_TIMING1);
3517 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3518 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3519 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3520 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3521 dsi_write_reg(dsidev, DSI_TIMING1, r);
3523 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3525 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3527 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3528 (total_ticks * 1000) / (fck / 1000 / 1000));
3531 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3532 unsigned ticks, bool x4, bool x16)
3535 unsigned long total_ticks;
3538 BUG_ON(ticks > 0x1fff);
3540 /* ticks in DSI_FCK */
3541 fck = dsi_fclk_rate(dsidev);
3543 r = dsi_read_reg(dsidev, DSI_TIMING1);
3544 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3545 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3546 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3547 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3548 dsi_write_reg(dsidev, DSI_TIMING1, r);
3550 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3552 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3554 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3555 (total_ticks * 1000) / (fck / 1000 / 1000));
3558 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3559 unsigned ticks, bool x4, bool x16)
3562 unsigned long total_ticks;
3565 BUG_ON(ticks > 0x1fff);
3567 /* ticks in TxByteClkHS */
3568 fck = dsi_get_txbyteclkhs(dsidev);
3570 r = dsi_read_reg(dsidev, DSI_TIMING2);
3571 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3572 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3573 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3574 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3575 dsi_write_reg(dsidev, DSI_TIMING2, r);
3577 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3579 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3581 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3582 (total_ticks * 1000) / (fck / 1000 / 1000));
3585 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3587 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3588 int num_line_buffers;
3590 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3591 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3592 struct omap_video_timings *timings = &dsi->timings;
3594 * Don't use line buffers if width is greater than the video
3595 * port's line buffer size
3597 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3598 num_line_buffers = 0;
3600 num_line_buffers = 2;
3602 /* Use maximum number of line buffers in command mode */
3603 num_line_buffers = 2;
3607 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3610 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3612 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3616 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3621 r = dsi_read_reg(dsidev, DSI_CTRL);
3622 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3623 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3624 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3625 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3626 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3627 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3628 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3629 dsi_write_reg(dsidev, DSI_CTRL, r);
3632 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3634 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3635 int blanking_mode = dsi->vm_timings.blanking_mode;
3636 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3637 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3638 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3642 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3643 * 1 = Long blanking packets are sent in corresponding blanking periods
3645 r = dsi_read_reg(dsidev, DSI_CTRL);
3646 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3647 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3648 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3649 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3650 dsi_write_reg(dsidev, DSI_CTRL, r);
3654 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3655 * results in maximum transition time for data and clock lanes to enter and
3656 * exit HS mode. Hence, this is the scenario where the least amount of command
3657 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3658 * clock cycles that can be used to interleave command mode data in HS so that
3659 * all scenarios are satisfied.
3661 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3662 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3667 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3668 * time of data lanes only, if it isn't set, we need to consider HS
3669 * transition time of both data and clock lanes. HS transition time
3670 * of Scenario 3 is considered.
3673 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3676 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3677 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3679 transition = max(trans1, trans2);
3682 return blank > transition ? blank - transition : 0;
3686 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3687 * results in maximum transition time for data lanes to enter and exit LP mode.
3688 * Hence, this is the scenario where the least amount of command mode data can
3689 * be interleaved. We program the minimum amount of bytes that can be
3690 * interleaved in LP so that all scenarios are satisfied.
3692 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3693 int lp_clk_div, int tdsi_fclk)
3695 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3696 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3697 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3698 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3699 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3701 /* maximum LP transition time according to Scenario 1 */
3702 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3704 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3705 tlp_avail = thsbyte_clk * (blank - trans_lp);
3707 ttxclkesc = tdsi_fclk * lp_clk_div;
3709 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3712 return max(lp_inter, 0);
3715 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3717 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3719 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3720 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3721 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3722 int tclk_trail, ths_exit, exiths_clk;
3724 struct omap_video_timings *timings = &dsi->timings;
3725 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3726 int ndl = dsi->num_lanes_used - 1;
3727 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3728 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3729 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3730 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3731 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3734 r = dsi_read_reg(dsidev, DSI_CTRL);
3735 blanking_mode = FLD_GET(r, 20, 20);
3736 hfp_blanking_mode = FLD_GET(r, 21, 21);
3737 hbp_blanking_mode = FLD_GET(r, 22, 22);
3738 hsa_blanking_mode = FLD_GET(r, 23, 23);
3740 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3741 hbp = FLD_GET(r, 11, 0);
3742 hfp = FLD_GET(r, 23, 12);
3743 hsa = FLD_GET(r, 31, 24);
3745 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3746 ddr_clk_post = FLD_GET(r, 7, 0);
3747 ddr_clk_pre = FLD_GET(r, 15, 8);
3749 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3750 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3751 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3753 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3754 lp_clk_div = FLD_GET(r, 12, 0);
3755 ddr_alwon = FLD_GET(r, 13, 13);
3757 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3758 ths_exit = FLD_GET(r, 7, 0);
3760 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3761 tclk_trail = FLD_GET(r, 15, 8);
3763 exiths_clk = ths_exit + tclk_trail;
3765 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3766 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3768 if (!hsa_blanking_mode) {
3769 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3770 enter_hs_mode_lat, exit_hs_mode_lat,
3771 exiths_clk, ddr_clk_pre, ddr_clk_post);
3772 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3773 enter_hs_mode_lat, exit_hs_mode_lat,
3774 lp_clk_div, dsi_fclk_hsdiv);
3777 if (!hfp_blanking_mode) {
3778 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3779 enter_hs_mode_lat, exit_hs_mode_lat,
3780 exiths_clk, ddr_clk_pre, ddr_clk_post);
3781 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3782 enter_hs_mode_lat, exit_hs_mode_lat,
3783 lp_clk_div, dsi_fclk_hsdiv);
3786 if (!hbp_blanking_mode) {
3787 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3788 enter_hs_mode_lat, exit_hs_mode_lat,
3789 exiths_clk, ddr_clk_pre, ddr_clk_post);
3791 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3792 enter_hs_mode_lat, exit_hs_mode_lat,
3793 lp_clk_div, dsi_fclk_hsdiv);
3796 if (!blanking_mode) {
3797 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3798 enter_hs_mode_lat, exit_hs_mode_lat,
3799 exiths_clk, ddr_clk_pre, ddr_clk_post);
3801 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3802 enter_hs_mode_lat, exit_hs_mode_lat,
3803 lp_clk_div, dsi_fclk_hsdiv);
3806 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3807 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3810 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3811 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3814 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3815 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3816 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3817 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3818 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3820 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3821 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3822 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3823 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3824 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3826 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3827 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3828 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3829 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3832 static int dsi_proto_config(struct platform_device *dsidev)
3834 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3838 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3843 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3848 /* XXX what values for the timeouts? */
3849 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3850 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3851 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3852 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3854 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3869 r = dsi_read_reg(dsidev, DSI_CTRL);
3870 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3871 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3872 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3873 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3874 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3875 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3876 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3877 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3878 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3879 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3880 /* DCS_CMD_CODE, 1=start, 0=continue */
3881 r = FLD_MOD(r, 0, 25, 25);
3884 dsi_write_reg(dsidev, DSI_CTRL, r);
3886 dsi_config_vp_num_line_buffers(dsidev);
3888 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3889 dsi_config_vp_sync_events(dsidev);
3890 dsi_config_blanking_modes(dsidev);
3891 dsi_config_cmd_mode_interleaving(dsidev);
3894 dsi_vc_initial_config(dsidev, 0);
3895 dsi_vc_initial_config(dsidev, 1);
3896 dsi_vc_initial_config(dsidev, 2);
3897 dsi_vc_initial_config(dsidev, 3);
3902 static void dsi_proto_timings(struct platform_device *dsidev)
3904 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3905 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3906 unsigned tclk_pre, tclk_post;
3907 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3908 unsigned ths_trail, ths_exit;
3909 unsigned ddr_clk_pre, ddr_clk_post;
3910 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3912 int ndl = dsi->num_lanes_used - 1;
3915 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3916 ths_prepare = FLD_GET(r, 31, 24);
3917 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3918 ths_zero = ths_prepare_ths_zero - ths_prepare;
3919 ths_trail = FLD_GET(r, 15, 8);
3920 ths_exit = FLD_GET(r, 7, 0);
3922 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3923 tlpx = FLD_GET(r, 20, 16) * 2;
3924 tclk_trail = FLD_GET(r, 15, 8);
3925 tclk_zero = FLD_GET(r, 7, 0);
3927 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3928 tclk_prepare = FLD_GET(r, 7, 0);
3932 /* min 60ns + 52*UI */
3933 tclk_post = ns2ddr(dsidev, 60) + 26;
3935 ths_eot = DIV_ROUND_UP(4, ndl);
3937 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3939 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3941 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3942 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3944 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3945 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3946 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3947 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3949 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3953 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3954 DIV_ROUND_UP(ths_prepare, 4) +
3955 DIV_ROUND_UP(ths_zero + 3, 4);
3957 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3959 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3960 FLD_VAL(exit_hs_mode_lat, 15, 0);
3961 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3963 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3964 enter_hs_mode_lat, exit_hs_mode_lat);
3966 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3967 /* TODO: Implement a video mode check_timings function */
3968 int hsa = dsi->vm_timings.hsa;
3969 int hfp = dsi->vm_timings.hfp;
3970 int hbp = dsi->vm_timings.hbp;
3971 int vsa = dsi->vm_timings.vsa;
3972 int vfp = dsi->vm_timings.vfp;
3973 int vbp = dsi->vm_timings.vbp;
3974 int window_sync = dsi->vm_timings.window_sync;
3976 struct omap_video_timings *timings = &dsi->timings;
3977 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3978 int tl, t_he, width_bytes;
3980 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
3982 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3984 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3986 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3987 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3988 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3990 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3991 hfp, hsync_end ? hsa : 0, tl);
3992 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3993 vsa, timings->y_res);
3995 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3996 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3997 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3998 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3999 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4001 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4002 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
4003 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
4004 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
4005 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
4006 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4008 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4009 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
4010 r = FLD_MOD(r, tl, 31, 16); /* TL */
4011 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4015 static int dsi_configure_pins(struct omap_dss_device *dssdev,
4016 const struct omap_dsi_pin_config *pin_cfg)
4018 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4019 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4022 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4026 static const enum dsi_lane_function functions[] = {
4034 num_pins = pin_cfg->num_pins;
4035 pins = pin_cfg->pins;
4037 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4038 || num_pins % 2 != 0)
4041 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4042 lanes[i].function = DSI_LANE_UNUSED;
4046 for (i = 0; i < num_pins; i += 2) {
4053 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4056 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4071 lanes[lane].function = functions[i / 2];
4072 lanes[lane].polarity = pol;
4076 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4077 dsi->num_lanes_used = num_lanes;
4082 static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4084 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4085 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4086 struct omap_overlay_manager *mgr = dsi->output.manager;
4087 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4088 struct omap_dss_device *out = &dsi->output;
4093 if (out == NULL || out->manager == NULL) {
4094 DSSERR("failed to enable display: no output/manager\n");
4098 r = dsi_display_init_dispc(dsidev, mgr);
4100 goto err_init_dispc;
4102 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4103 switch (dsi->pix_fmt) {
4104 case OMAP_DSS_DSI_FMT_RGB888:
4105 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4107 case OMAP_DSS_DSI_FMT_RGB666:
4108 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4110 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4111 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4113 case OMAP_DSS_DSI_FMT_RGB565:
4114 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4121 dsi_if_enable(dsidev, false);
4122 dsi_vc_enable(dsidev, channel, false);
4124 /* MODE, 1 = video mode */
4125 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4127 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4129 dsi_vc_write_long_header(dsidev, channel, data_type,
4132 dsi_vc_enable(dsidev, channel, true);
4133 dsi_if_enable(dsidev, true);
4136 r = dss_mgr_enable(mgr);
4138 goto err_mgr_enable;
4143 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4144 dsi_if_enable(dsidev, false);
4145 dsi_vc_enable(dsidev, channel, false);
4148 dsi_display_uninit_dispc(dsidev, mgr);
4153 static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4155 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4156 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4157 struct omap_overlay_manager *mgr = dsi->output.manager;
4159 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4160 dsi_if_enable(dsidev, false);
4161 dsi_vc_enable(dsidev, channel, false);
4163 /* MODE, 0 = command mode */
4164 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4166 dsi_vc_enable(dsidev, channel, true);
4167 dsi_if_enable(dsidev, true);
4170 dss_mgr_disable(mgr);
4172 dsi_display_uninit_dispc(dsidev, mgr);
4175 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4177 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4178 struct omap_overlay_manager *mgr = dsi->output.manager;
4183 unsigned packet_payload;
4184 unsigned packet_len;
4187 const unsigned channel = dsi->update_channel;
4188 const unsigned line_buf_size = dsi->line_buffer_size;
4189 u16 w = dsi->timings.x_res;
4190 u16 h = dsi->timings.y_res;
4192 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4194 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4196 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4197 bytespl = w * bytespp;
4198 bytespf = bytespl * h;
4200 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4201 * number of lines in a packet. See errata about VP_CLK_RATIO */
4203 if (bytespf < line_buf_size)
4204 packet_payload = bytespf;
4206 packet_payload = (line_buf_size) / bytespl * bytespl;
4208 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4209 total_len = (bytespf / packet_payload) * packet_len;
4211 if (bytespf % packet_payload)
4212 total_len += (bytespf % packet_payload) + 1;
4214 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4215 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4217 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4220 if (dsi->te_enabled)
4221 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4223 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4224 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4226 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4227 * because DSS interrupts are not capable of waking up the CPU and the
4228 * framedone interrupt could be delayed for quite a long time. I think
4229 * the same goes for any DSS interrupts, but for some reason I have not
4230 * seen the problem anywhere else than here.
4232 dispc_disable_sidle();
4234 dsi_perf_mark_start(dsidev);
4236 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4237 msecs_to_jiffies(250));
4240 dss_mgr_set_timings(mgr, &dsi->timings);
4242 dss_mgr_start_update(mgr);
4244 if (dsi->te_enabled) {
4245 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4246 * for TE is longer than the timer allows */
4247 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4249 dsi_vc_send_bta(dsidev, channel);
4251 #ifdef DSI_CATCH_MISSING_TE
4252 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4257 #ifdef DSI_CATCH_MISSING_TE
4258 static void dsi_te_timeout(unsigned long arg)
4260 DSSERR("TE not received for 250ms!\n");
4264 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4266 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4268 /* SIDLEMODE back to smart-idle */
4269 dispc_enable_sidle();
4271 if (dsi->te_enabled) {
4272 /* enable LP_RX_TO again after the TE */
4273 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4276 dsi->framedone_callback(error, dsi->framedone_data);
4279 dsi_perf_show(dsidev, "DISPC");
4282 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4284 struct dsi_data *dsi = container_of(work, struct dsi_data,
4285 framedone_timeout_work.work);
4286 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4287 * 250ms which would conflict with this timeout work. What should be
4288 * done is first cancel the transfer on the HW, and then cancel the
4289 * possibly scheduled framedone work. However, cancelling the transfer
4290 * on the HW is buggy, and would probably require resetting the whole
4293 DSSERR("Framedone not received for 250ms!\n");
4295 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4298 static void dsi_framedone_irq_callback(void *data)
4300 struct platform_device *dsidev = (struct platform_device *) data;
4301 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4303 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4304 * turns itself off. However, DSI still has the pixels in its buffers,
4305 * and is sending the data.
4308 cancel_delayed_work(&dsi->framedone_timeout_work);
4310 dsi_handle_framedone(dsidev, 0);
4313 static int dsi_update(struct omap_dss_device *dssdev, int channel,
4314 void (*callback)(int, void *), void *data)
4316 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4317 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4320 dsi_perf_mark_setup(dsidev);
4322 dsi->update_channel = channel;
4324 dsi->framedone_callback = callback;
4325 dsi->framedone_data = data;
4327 dw = dsi->timings.x_res;
4328 dh = dsi->timings.y_res;
4330 #ifdef DSI_PERF_MEASURE
4331 dsi->update_bytes = dw * dh *
4332 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4334 dsi_update_screen_dispc(dsidev);
4341 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4343 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4344 struct dispc_clock_info dispc_cinfo;
4348 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4350 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4351 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4353 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4355 DSSERR("Failed to calc dispc clocks\n");
4359 dsi->mgr_config.clock_info = dispc_cinfo;
4364 static int dsi_display_init_dispc(struct platform_device *dsidev,
4365 struct omap_overlay_manager *mgr)
4367 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4370 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4371 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4372 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4374 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4375 r = dss_mgr_register_framedone_handler(mgr,
4376 dsi_framedone_irq_callback, dsidev);
4378 DSSERR("can't register FRAMEDONE handler\n");
4382 dsi->mgr_config.stallmode = true;
4383 dsi->mgr_config.fifohandcheck = true;
4385 dsi->mgr_config.stallmode = false;
4386 dsi->mgr_config.fifohandcheck = false;
4390 * override interlace, logic level and edge related parameters in
4391 * omap_video_timings with default values
4393 dsi->timings.interlace = false;
4394 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4395 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4396 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4397 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4398 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4400 dss_mgr_set_timings(mgr, &dsi->timings);
4402 r = dsi_configure_dispc_clocks(dsidev);
4406 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4407 dsi->mgr_config.video_port_width =
4408 dsi_get_pixel_size(dsi->pix_fmt);
4409 dsi->mgr_config.lcden_sig_polarity = 0;
4411 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4415 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4416 dss_mgr_unregister_framedone_handler(mgr,
4417 dsi_framedone_irq_callback, dsidev);
4419 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4423 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4424 struct omap_overlay_manager *mgr)
4426 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4428 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4429 dss_mgr_unregister_framedone_handler(mgr,
4430 dsi_framedone_irq_callback, dsidev);
4432 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4435 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4437 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4438 struct dsi_clock_info cinfo;
4441 cinfo = dsi->user_dsi_cinfo;
4443 r = dsi_calc_clock_rates(dsidev, &cinfo);
4445 DSSERR("Failed to calc dsi clocks\n");
4449 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4451 DSSERR("Failed to set dsi clocks\n");
4458 static int dsi_display_init_dsi(struct platform_device *dsidev)
4460 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4463 r = dsi_pll_init(dsidev, true, true);
4467 r = dsi_configure_dsi_clocks(dsidev);
4471 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4472 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4473 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4477 r = dsi_cio_init(dsidev);
4481 _dsi_print_reset_status(dsidev);
4483 dsi_proto_timings(dsidev);
4484 dsi_set_lp_clk_divisor(dsidev);
4487 _dsi_print_reset_status(dsidev);
4489 r = dsi_proto_config(dsidev);
4493 /* enable interface */
4494 dsi_vc_enable(dsidev, 0, 1);
4495 dsi_vc_enable(dsidev, 1, 1);
4496 dsi_vc_enable(dsidev, 2, 1);
4497 dsi_vc_enable(dsidev, 3, 1);
4498 dsi_if_enable(dsidev, 1);
4499 dsi_force_tx_stop_mode_io(dsidev);
4503 dsi_cio_uninit(dsidev);
4505 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4507 dsi_pll_uninit(dsidev, true);
4512 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4513 bool disconnect_lanes, bool enter_ulps)
4515 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4517 if (enter_ulps && !dsi->ulps_enabled)
4518 dsi_enter_ulps(dsidev);
4520 /* disable interface */
4521 dsi_if_enable(dsidev, 0);
4522 dsi_vc_enable(dsidev, 0, 0);
4523 dsi_vc_enable(dsidev, 1, 0);
4524 dsi_vc_enable(dsidev, 2, 0);
4525 dsi_vc_enable(dsidev, 3, 0);
4527 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4528 dsi_cio_uninit(dsidev);
4529 dsi_pll_uninit(dsidev, disconnect_lanes);
4532 static int dsi_display_enable(struct omap_dss_device *dssdev)
4534 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4535 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4538 DSSDBG("dsi_display_enable\n");
4540 WARN_ON(!dsi_bus_is_locked(dsidev));
4542 mutex_lock(&dsi->lock);
4544 r = dsi_runtime_get(dsidev);
4548 dsi_enable_pll_clock(dsidev, 1);
4550 _dsi_initialize_irq(dsidev);
4552 r = dsi_display_init_dsi(dsidev);
4556 mutex_unlock(&dsi->lock);
4561 dsi_enable_pll_clock(dsidev, 0);
4562 dsi_runtime_put(dsidev);
4564 mutex_unlock(&dsi->lock);
4565 DSSDBG("dsi_display_enable FAILED\n");
4569 static void dsi_display_disable(struct omap_dss_device *dssdev,
4570 bool disconnect_lanes, bool enter_ulps)
4572 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4573 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4575 DSSDBG("dsi_display_disable\n");
4577 WARN_ON(!dsi_bus_is_locked(dsidev));
4579 mutex_lock(&dsi->lock);
4581 dsi_sync_vc(dsidev, 0);
4582 dsi_sync_vc(dsidev, 1);
4583 dsi_sync_vc(dsidev, 2);
4584 dsi_sync_vc(dsidev, 3);
4586 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4588 dsi_runtime_put(dsidev);
4589 dsi_enable_pll_clock(dsidev, 0);
4591 mutex_unlock(&dsi->lock);
4594 static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4596 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4597 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4599 dsi->te_enabled = enable;
4603 #ifdef PRINT_VERBOSE_VM_TIMINGS
4604 static void print_dsi_vm(const char *str,
4605 const struct omap_dss_dsi_videomode_timings *t)
4607 unsigned long byteclk = t->hsclk / 4;
4608 int bl, wc, pps, tot;
4610 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4611 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4612 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4615 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4617 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4618 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4621 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4637 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4639 unsigned long pck = t->pixelclock;
4643 bl = t->hsw + t->hbp + t->hfp;
4646 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4648 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4649 "%u/%u/%u/%u = %u + %u = %u\n",
4652 t->hsw, t->hbp, hact, t->hfp,
4664 /* note: this is not quite accurate */
4665 static void print_dsi_dispc_vm(const char *str,
4666 const struct omap_dss_dsi_videomode_timings *t)
4668 struct omap_video_timings vm = { 0 };
4669 unsigned long byteclk = t->hsclk / 4;
4672 int dsi_hact, dsi_htot;
4674 dsi_tput = (u64)byteclk * t->ndl * 8;
4675 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4676 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4677 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4679 vm.pixelclock = pck;
4680 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4681 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4682 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4685 print_dispc_vm(str, &vm);
4687 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4689 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4690 unsigned long pck, void *data)
4692 struct dsi_clk_calc_ctx *ctx = data;
4693 struct omap_video_timings *t = &ctx->dispc_vm;
4695 ctx->dispc_cinfo.lck_div = lckd;
4696 ctx->dispc_cinfo.pck_div = pckd;
4697 ctx->dispc_cinfo.lck = lck;
4698 ctx->dispc_cinfo.pck = pck;
4700 *t = *ctx->config->timings;
4701 t->pixelclock = pck;
4702 t->x_res = ctx->config->timings->x_res;
4703 t->y_res = ctx->config->timings->y_res;
4704 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4705 t->vfp = t->vbp = 0;
4710 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4713 struct dsi_clk_calc_ctx *ctx = data;
4715 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4716 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4718 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4719 dsi_cm_calc_dispc_cb, ctx);
4722 static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,
4723 unsigned long pll, void *data)
4725 struct dsi_clk_calc_ctx *ctx = data;
4727 ctx->dsi_cinfo.regn = regn;
4728 ctx->dsi_cinfo.regm = regm;
4729 ctx->dsi_cinfo.fint = fint;
4730 ctx->dsi_cinfo.clkin4ddr = pll;
4732 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4733 dsi_cm_calc_hsdiv_cb, ctx);
4736 static bool dsi_cm_calc(struct dsi_data *dsi,
4737 const struct omap_dss_dsi_config *cfg,
4738 struct dsi_clk_calc_ctx *ctx)
4740 unsigned long clkin;
4742 unsigned long pll_min, pll_max;
4743 unsigned long pck, txbyteclk;
4745 clkin = clk_get_rate(dsi->sys_clk);
4746 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4747 ndl = dsi->num_lanes_used - 1;
4750 * Here we should calculate minimum txbyteclk to be able to send the
4751 * frame in time, and also to handle TE. That's not very simple, though,
4752 * especially as we go to LP between each pixel packet due to HW
4753 * "feature". So let's just estimate very roughly and multiply by 1.5.
4755 pck = cfg->timings->pixelclock;
4757 txbyteclk = pck * bitspp / 8 / ndl;
4759 memset(ctx, 0, sizeof(*ctx));
4760 ctx->dsidev = dsi->pdev;
4762 ctx->req_pck_min = pck;
4763 ctx->req_pck_nom = pck;
4764 ctx->req_pck_max = pck * 3 / 2;
4765 ctx->dsi_cinfo.clkin = clkin;
4767 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4768 pll_max = cfg->hs_clk_max * 4;
4770 return dsi_pll_calc(dsi->pdev, clkin,
4772 dsi_cm_calc_pll_cb, ctx);
4775 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4777 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4778 const struct omap_dss_dsi_config *cfg = ctx->config;
4779 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4780 int ndl = dsi->num_lanes_used - 1;
4781 unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4;
4782 unsigned long byteclk = hsclk / 4;
4784 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4786 int panel_htot, panel_hbl; /* pixels */
4787 int dispc_htot, dispc_hbl; /* pixels */
4788 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4790 const struct omap_video_timings *req_vm;
4791 struct omap_video_timings *dispc_vm;
4792 struct omap_dss_dsi_videomode_timings *dsi_vm;
4793 u64 dsi_tput, dispc_tput;
4795 dsi_tput = (u64)byteclk * ndl * 8;
4797 req_vm = cfg->timings;
4798 req_pck_min = ctx->req_pck_min;
4799 req_pck_max = ctx->req_pck_max;
4800 req_pck_nom = ctx->req_pck_nom;
4802 dispc_pck = ctx->dispc_cinfo.pck;
4803 dispc_tput = (u64)dispc_pck * bitspp;
4805 xres = req_vm->x_res;
4807 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4808 panel_htot = xres + panel_hbl;
4810 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4813 * When there are no line buffers, DISPC and DSI must have the
4814 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4816 if (dsi->line_buffer_size < xres * bitspp / 8) {
4817 if (dispc_tput != dsi_tput)
4820 if (dispc_tput < dsi_tput)
4824 /* DSI tput must be over the min requirement */
4825 if (dsi_tput < (u64)bitspp * req_pck_min)
4828 /* When non-burst mode, DSI tput must be below max requirement. */
4829 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4830 if (dsi_tput > (u64)bitspp * req_pck_max)
4834 hss = DIV_ROUND_UP(4, ndl);
4836 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4837 if (ndl == 3 && req_vm->hsw == 0)
4840 hse = DIV_ROUND_UP(4, ndl);
4845 /* DSI htot to match the panel's nominal pck */
4846 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4848 /* fail if there would be no time for blanking */
4849 if (dsi_htot < hss + hse + dsi_hact)
4852 /* total DSI blanking needed to achieve panel's TL */
4853 dsi_hbl = dsi_htot - dsi_hact;
4855 /* DISPC htot to match the DSI TL */
4856 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4858 /* verify that the DSI and DISPC TLs are the same */
4859 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4862 dispc_hbl = dispc_htot - xres;
4864 /* setup DSI videomode */
4866 dsi_vm = &ctx->dsi_vm;
4867 memset(dsi_vm, 0, sizeof(*dsi_vm));
4869 dsi_vm->hsclk = hsclk;
4872 dsi_vm->bitspp = bitspp;
4874 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4876 } else if (ndl == 3 && req_vm->hsw == 0) {
4879 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4880 hsa = max(hsa - hse, 1);
4883 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4886 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4889 /* we need to take cycles from hbp */
4892 hbp = max(hbp - t, 1);
4893 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4895 if (hfp < 1 && hsa > 0) {
4896 /* we need to take cycles from hsa */
4898 hsa = max(hsa - t, 1);
4899 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4910 dsi_vm->hact = xres;
4913 dsi_vm->vsa = req_vm->vsw;
4914 dsi_vm->vbp = req_vm->vbp;
4915 dsi_vm->vact = req_vm->y_res;
4916 dsi_vm->vfp = req_vm->vfp;
4918 dsi_vm->trans_mode = cfg->trans_mode;
4920 dsi_vm->blanking_mode = 0;
4921 dsi_vm->hsa_blanking_mode = 1;
4922 dsi_vm->hfp_blanking_mode = 1;
4923 dsi_vm->hbp_blanking_mode = 1;
4925 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4926 dsi_vm->window_sync = 4;
4928 /* setup DISPC videomode */
4930 dispc_vm = &ctx->dispc_vm;
4931 *dispc_vm = *req_vm;
4932 dispc_vm->pixelclock = dispc_pck;
4934 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4935 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4942 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4945 hfp = dispc_hbl - hsa - hbp;
4948 /* we need to take cycles from hbp */
4951 hbp = max(hbp - t, 1);
4952 hfp = dispc_hbl - hsa - hbp;
4955 /* we need to take cycles from hsa */
4957 hsa = max(hsa - t, 1);
4958 hfp = dispc_hbl - hsa - hbp;
4965 dispc_vm->hfp = hfp;
4966 dispc_vm->hsw = hsa;
4967 dispc_vm->hbp = hbp;
4973 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4974 unsigned long pck, void *data)
4976 struct dsi_clk_calc_ctx *ctx = data;
4978 ctx->dispc_cinfo.lck_div = lckd;
4979 ctx->dispc_cinfo.pck_div = pckd;
4980 ctx->dispc_cinfo.lck = lck;
4981 ctx->dispc_cinfo.pck = pck;
4983 if (dsi_vm_calc_blanking(ctx) == false)
4986 #ifdef PRINT_VERBOSE_VM_TIMINGS
4987 print_dispc_vm("dispc", &ctx->dispc_vm);
4988 print_dsi_vm("dsi ", &ctx->dsi_vm);
4989 print_dispc_vm("req ", ctx->config->timings);
4990 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
4996 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4999 struct dsi_clk_calc_ctx *ctx = data;
5000 unsigned long pck_max;
5002 ctx->dsi_cinfo.regm_dispc = regm_dispc;
5003 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
5006 * In burst mode we can let the dispc pck be arbitrarily high, but it
5007 * limits our scaling abilities. So for now, don't aim too high.
5010 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
5011 pck_max = ctx->req_pck_max + 10000000;
5013 pck_max = ctx->req_pck_max;
5015 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
5016 dsi_vm_calc_dispc_cb, ctx);
5019 static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,
5020 unsigned long pll, void *data)
5022 struct dsi_clk_calc_ctx *ctx = data;
5024 ctx->dsi_cinfo.regn = regn;
5025 ctx->dsi_cinfo.regm = regm;
5026 ctx->dsi_cinfo.fint = fint;
5027 ctx->dsi_cinfo.clkin4ddr = pll;
5029 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
5030 dsi_vm_calc_hsdiv_cb, ctx);
5033 static bool dsi_vm_calc(struct dsi_data *dsi,
5034 const struct omap_dss_dsi_config *cfg,
5035 struct dsi_clk_calc_ctx *ctx)
5037 const struct omap_video_timings *t = cfg->timings;
5038 unsigned long clkin;
5039 unsigned long pll_min;
5040 unsigned long pll_max;
5041 int ndl = dsi->num_lanes_used - 1;
5042 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
5043 unsigned long byteclk_min;
5045 clkin = clk_get_rate(dsi->sys_clk);
5047 memset(ctx, 0, sizeof(*ctx));
5048 ctx->dsidev = dsi->pdev;
5051 ctx->dsi_cinfo.clkin = clkin;
5053 /* these limits should come from the panel driver */
5054 ctx->req_pck_min = t->pixelclock - 1000;
5055 ctx->req_pck_nom = t->pixelclock;
5056 ctx->req_pck_max = t->pixelclock + 1000;
5058 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5059 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
5061 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
5062 pll_max = cfg->hs_clk_max * 4;
5064 unsigned long byteclk_max;
5065 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
5068 pll_max = byteclk_max * 4 * 4;
5071 return dsi_pll_calc(dsi->pdev, clkin,
5073 dsi_vm_calc_pll_cb, ctx);
5076 static int dsi_set_config(struct omap_dss_device *dssdev,
5077 const struct omap_dss_dsi_config *config)
5079 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5080 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5081 struct dsi_clk_calc_ctx ctx;
5085 mutex_lock(&dsi->lock);
5087 dsi->pix_fmt = config->pixel_format;
5088 dsi->mode = config->mode;
5090 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
5091 ok = dsi_vm_calc(dsi, config, &ctx);
5093 ok = dsi_cm_calc(dsi, config, &ctx);
5096 DSSERR("failed to find suitable DSI clock settings\n");
5101 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
5103 r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
5104 config->lp_clk_max);
5106 DSSERR("failed to find suitable DSI LP clock settings\n");
5110 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
5111 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
5113 dsi->timings = ctx.dispc_vm;
5114 dsi->vm_timings = ctx.dsi_vm;
5116 mutex_unlock(&dsi->lock);
5120 mutex_unlock(&dsi->lock);
5126 * Return a hardcoded channel for the DSI output. This should work for
5127 * current use cases, but this can be later expanded to either resolve
5128 * the channel in some more dynamic manner, or get the channel as a user
5131 static enum omap_channel dsi_get_channel(int module_id)
5133 switch (omapdss_get_version()) {
5134 case OMAPDSS_VER_OMAP24xx:
5135 case OMAPDSS_VER_AM43xx:
5136 DSSWARN("DSI not supported\n");
5137 return OMAP_DSS_CHANNEL_LCD;
5139 case OMAPDSS_VER_OMAP34xx_ES1:
5140 case OMAPDSS_VER_OMAP34xx_ES3:
5141 case OMAPDSS_VER_OMAP3630:
5142 case OMAPDSS_VER_AM35xx:
5143 return OMAP_DSS_CHANNEL_LCD;
5145 case OMAPDSS_VER_OMAP4430_ES1:
5146 case OMAPDSS_VER_OMAP4430_ES2:
5147 case OMAPDSS_VER_OMAP4:
5148 switch (module_id) {
5150 return OMAP_DSS_CHANNEL_LCD;
5152 return OMAP_DSS_CHANNEL_LCD2;
5154 DSSWARN("unsupported module id\n");
5155 return OMAP_DSS_CHANNEL_LCD;
5158 case OMAPDSS_VER_OMAP5:
5159 switch (module_id) {
5161 return OMAP_DSS_CHANNEL_LCD;
5163 return OMAP_DSS_CHANNEL_LCD3;
5165 DSSWARN("unsupported module id\n");
5166 return OMAP_DSS_CHANNEL_LCD;
5170 DSSWARN("unsupported DSS version\n");
5171 return OMAP_DSS_CHANNEL_LCD;
5175 static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5177 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5178 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5181 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5182 if (!dsi->vc[i].dssdev) {
5183 dsi->vc[i].dssdev = dssdev;
5189 DSSERR("cannot get VC for display %s", dssdev->name);
5193 static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5195 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5196 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5198 if (vc_id < 0 || vc_id > 3) {
5199 DSSERR("VC ID out of range\n");
5203 if (channel < 0 || channel > 3) {
5204 DSSERR("Virtual Channel out of range\n");
5208 if (dsi->vc[channel].dssdev != dssdev) {
5209 DSSERR("Virtual Channel not allocated to display %s\n",
5214 dsi->vc[channel].vc_id = vc_id;
5219 static void dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5221 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5222 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5224 if ((channel >= 0 && channel <= 3) &&
5225 dsi->vc[channel].dssdev == dssdev) {
5226 dsi->vc[channel].dssdev = NULL;
5227 dsi->vc[channel].vc_id = 0;
5231 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5233 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5234 DSSERR("%s (%s) not active\n",
5235 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5236 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5239 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5241 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5242 DSSERR("%s (%s) not active\n",
5243 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5244 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5247 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5249 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5251 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5252 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5253 dsi->regm_dispc_max =
5254 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5255 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5256 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5257 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5258 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5261 static int dsi_get_clocks(struct platform_device *dsidev)
5263 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5266 clk = devm_clk_get(&dsidev->dev, "fck");
5268 DSSERR("can't get fck\n");
5269 return PTR_ERR(clk);
5274 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5276 DSSERR("can't get sys_clk\n");
5277 return PTR_ERR(clk);
5285 static int dsi_connect(struct omap_dss_device *dssdev,
5286 struct omap_dss_device *dst)
5288 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5289 struct omap_overlay_manager *mgr;
5292 r = dsi_regulator_init(dsidev);
5296 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
5300 r = dss_mgr_connect(mgr, dssdev);
5304 r = omapdss_output_set_device(dssdev, dst);
5306 DSSERR("failed to connect output to new device: %s\n",
5308 dss_mgr_disconnect(mgr, dssdev);
5315 static void dsi_disconnect(struct omap_dss_device *dssdev,
5316 struct omap_dss_device *dst)
5318 WARN_ON(dst != dssdev->dst);
5320 if (dst != dssdev->dst)
5323 omapdss_output_unset_device(dssdev);
5325 if (dssdev->manager)
5326 dss_mgr_disconnect(dssdev->manager, dssdev);
5329 static const struct omapdss_dsi_ops dsi_ops = {
5330 .connect = dsi_connect,
5331 .disconnect = dsi_disconnect,
5333 .bus_lock = dsi_bus_lock,
5334 .bus_unlock = dsi_bus_unlock,
5336 .enable = dsi_display_enable,
5337 .disable = dsi_display_disable,
5339 .enable_hs = dsi_vc_enable_hs,
5341 .configure_pins = dsi_configure_pins,
5342 .set_config = dsi_set_config,
5344 .enable_video_output = dsi_enable_video_output,
5345 .disable_video_output = dsi_disable_video_output,
5347 .update = dsi_update,
5349 .enable_te = dsi_enable_te,
5351 .request_vc = dsi_request_vc,
5352 .set_vc_id = dsi_set_vc_id,
5353 .release_vc = dsi_release_vc,
5355 .dcs_write = dsi_vc_dcs_write,
5356 .dcs_write_nosync = dsi_vc_dcs_write_nosync,
5357 .dcs_read = dsi_vc_dcs_read,
5359 .gen_write = dsi_vc_generic_write,
5360 .gen_write_nosync = dsi_vc_generic_write_nosync,
5361 .gen_read = dsi_vc_generic_read,
5363 .bta_sync = dsi_vc_send_bta_sync,
5365 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size,
5368 static void dsi_init_output(struct platform_device *dsidev)
5370 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5371 struct omap_dss_device *out = &dsi->output;
5373 out->dev = &dsidev->dev;
5374 out->id = dsi->module_id == 0 ?
5375 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5377 out->output_type = OMAP_DISPLAY_TYPE_DSI;
5378 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5379 out->dispc_channel = dsi_get_channel(dsi->module_id);
5380 out->ops.dsi = &dsi_ops;
5381 out->owner = THIS_MODULE;
5383 omapdss_register_output(out);
5386 static void dsi_uninit_output(struct platform_device *dsidev)
5388 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5389 struct omap_dss_device *out = &dsi->output;
5391 omapdss_unregister_output(out);
5394 static int dsi_probe_of(struct platform_device *pdev)
5396 struct device_node *node = pdev->dev.of_node;
5397 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5398 struct property *prop;
5402 struct device_node *ep;
5403 struct omap_dsi_pin_config pin_cfg;
5405 ep = omapdss_of_get_first_endpoint(node);
5409 prop = of_find_property(ep, "lanes", &len);
5411 dev_err(&pdev->dev, "failed to find lane data\n");
5416 num_pins = len / sizeof(u32);
5418 if (num_pins < 4 || num_pins % 2 != 0 ||
5419 num_pins > dsi->num_lanes_supported * 2) {
5420 dev_err(&pdev->dev, "bad number of lanes\n");
5425 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins);
5427 dev_err(&pdev->dev, "failed to read lane data\n");
5431 pin_cfg.num_pins = num_pins;
5432 for (i = 0; i < num_pins; ++i)
5433 pin_cfg.pins[i] = (int)lane_arr[i];
5435 r = dsi_configure_pins(&dsi->output, &pin_cfg);
5437 dev_err(&pdev->dev, "failed to configure pins");
5450 /* DSI1 HW IP initialisation */
5451 static int omap_dsihw_probe(struct platform_device *dsidev)
5455 struct dsi_data *dsi;
5456 struct resource *dsi_mem;
5457 struct resource *res;
5458 struct resource temp_res;
5460 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5465 dev_set_drvdata(&dsidev->dev, dsi);
5467 spin_lock_init(&dsi->irq_lock);
5468 spin_lock_init(&dsi->errors_lock);
5471 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5472 spin_lock_init(&dsi->irq_stats_lock);
5473 dsi->irq_stats.last_reset = jiffies;
5476 mutex_init(&dsi->lock);
5477 sema_init(&dsi->bus_lock, 1);
5479 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5480 dsi_framedone_timeout_work_callback);
5482 #ifdef DSI_CATCH_MISSING_TE
5483 init_timer(&dsi->te_timer);
5484 dsi->te_timer.function = dsi_te_timeout;
5485 dsi->te_timer.data = 0;
5488 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "proto");
5490 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5492 DSSERR("can't get IORESOURCE_MEM DSI\n");
5496 temp_res.start = res->start;
5497 temp_res.end = temp_res.start + DSI_PROTO_SZ - 1;
5503 dsi->proto_base = devm_ioremap(&dsidev->dev, res->start,
5504 resource_size(res));
5505 if (!dsi->proto_base) {
5506 DSSERR("can't ioremap DSI protocol engine\n");
5510 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "phy");
5512 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5514 DSSERR("can't get IORESOURCE_MEM DSI\n");
5518 temp_res.start = res->start + DSI_PHY_OFFSET;
5519 temp_res.end = temp_res.start + DSI_PHY_SZ - 1;
5523 dsi->phy_base = devm_ioremap(&dsidev->dev, res->start,
5524 resource_size(res));
5525 if (!dsi->proto_base) {
5526 DSSERR("can't ioremap DSI PHY\n");
5530 res = platform_get_resource_byname(dsidev, IORESOURCE_MEM, "pll");
5532 res = platform_get_resource(dsidev, IORESOURCE_MEM, 0);
5534 DSSERR("can't get IORESOURCE_MEM DSI\n");
5538 temp_res.start = res->start + DSI_PLL_OFFSET;
5539 temp_res.end = temp_res.start + DSI_PLL_SZ - 1;
5543 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start,
5544 resource_size(res));
5545 if (!dsi->proto_base) {
5546 DSSERR("can't ioremap DSI PLL\n");
5550 dsi->irq = platform_get_irq(dsi->pdev, 0);
5552 DSSERR("platform_get_irq failed\n");
5556 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5557 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5559 DSSERR("request_irq failed\n");
5563 if (dsidev->dev.of_node) {
5564 const struct of_device_id *match;
5565 const struct dsi_module_id_data *d;
5567 match = of_match_node(dsi_of_match, dsidev->dev.of_node);
5569 DSSERR("unsupported DSI module\n");
5575 while (d->address != 0 && d->address != dsi_mem->start)
5578 if (d->address == 0) {
5579 DSSERR("unsupported DSI module\n");
5583 dsi->module_id = d->id;
5585 dsi->module_id = dsidev->id;
5588 /* DSI VCs initialization */
5589 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5590 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5591 dsi->vc[i].dssdev = NULL;
5592 dsi->vc[i].vc_id = 0;
5595 dsi_calc_clock_param_ranges(dsidev);
5597 r = dsi_get_clocks(dsidev);
5601 pm_runtime_enable(&dsidev->dev);
5603 r = dsi_runtime_get(dsidev);
5605 goto err_runtime_get;
5607 rev = dsi_read_reg(dsidev, DSI_REVISION);
5608 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5609 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5611 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5612 * of data to 3 by default */
5613 if (dss_has_feature(FEAT_DSI_GNQ))
5615 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5617 dsi->num_lanes_supported = 3;
5619 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5621 dsi_init_output(dsidev);
5623 if (dsidev->dev.of_node) {
5624 r = dsi_probe_of(dsidev);
5626 DSSERR("Invalid DSI DT data\n");
5630 r = of_platform_populate(dsidev->dev.of_node, NULL, NULL,
5633 DSSERR("Failed to populate DSI child devices: %d\n", r);
5636 dsi_runtime_put(dsidev);
5638 if (dsi->module_id == 0)
5639 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5640 else if (dsi->module_id == 1)
5641 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5643 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5644 if (dsi->module_id == 0)
5645 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5646 else if (dsi->module_id == 1)
5647 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5653 dsi_uninit_output(dsidev);
5654 dsi_runtime_put(dsidev);
5657 pm_runtime_disable(&dsidev->dev);
5661 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5663 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5665 of_platform_depopulate(&dsidev->dev);
5667 WARN_ON(dsi->scp_clk_refcount > 0);
5669 dsi_uninit_output(dsidev);
5671 pm_runtime_disable(&dsidev->dev);
5673 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) {
5674 regulator_disable(dsi->vdds_dsi_reg);
5675 dsi->vdds_dsi_enabled = false;
5681 static int dsi_runtime_suspend(struct device *dev)
5683 struct platform_device *pdev = to_platform_device(dev);
5684 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5686 dsi->is_enabled = false;
5687 /* ensure the irq handler sees the is_enabled value */
5689 /* wait for current handler to finish before turning the DSI off */
5690 synchronize_irq(dsi->irq);
5692 dispc_runtime_put();
5697 static int dsi_runtime_resume(struct device *dev)
5699 struct platform_device *pdev = to_platform_device(dev);
5700 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5703 r = dispc_runtime_get();
5707 dsi->is_enabled = true;
5708 /* ensure the irq handler sees the is_enabled value */
5714 static const struct dev_pm_ops dsi_pm_ops = {
5715 .runtime_suspend = dsi_runtime_suspend,
5716 .runtime_resume = dsi_runtime_resume,
5719 static const struct dsi_module_id_data dsi_of_data_omap3[] = {
5720 { .address = 0x4804fc00, .id = 0, },
5724 static const struct dsi_module_id_data dsi_of_data_omap4[] = {
5725 { .address = 0x58004000, .id = 0, },
5726 { .address = 0x58005000, .id = 1, },
5730 static const struct dsi_module_id_data dsi_of_data_omap5[] = {
5731 { .address = 0x58004000, .id = 0, },
5732 { .address = 0x58009000, .id = 1, },
5736 static const struct of_device_id dsi_of_match[] = {
5737 { .compatible = "ti,omap3-dsi", .data = dsi_of_data_omap3, },
5738 { .compatible = "ti,omap4-dsi", .data = dsi_of_data_omap4, },
5739 { .compatible = "ti,omap5-dsi", .data = dsi_of_data_omap5, },
5743 static struct platform_driver omap_dsihw_driver = {
5744 .probe = omap_dsihw_probe,
5745 .remove = __exit_p(omap_dsihw_remove),
5747 .name = "omapdss_dsi",
5748 .owner = THIS_MODULE,
5750 .of_match_table = dsi_of_match,
5754 int __init dsi_init_platform_driver(void)
5756 return platform_driver_register(&omap_dsihw_driver);
5759 void __exit dsi_uninit_platform_driver(void)
5761 platform_driver_unregister(&omap_dsihw_driver);