drivers/watchdog/aspeed_wdt.c

   1 /*
   2  * Copyright 2016 IBM Corporation
   3  *
   4  * Joel Stanley <joel@jms.id.au>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/io.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/watchdog.h>
  19
  20 struct aspeed_wdt {
  21         struct watchdog_device  wdd;
  22         void __iomem            *base;
  23         u32                     ctrl;
  24 };
  25
  26 struct aspeed_wdt_config {
  27         u32 ext_pulse_width_mask;
  28 };
  29
  30 static const struct aspeed_wdt_config ast2400_config = {
  31         .ext_pulse_width_mask = 0xff,
  32 };
  33
  34 static const struct aspeed_wdt_config ast2500_config = {
  35         .ext_pulse_width_mask = 0xfffff,
  36 };
  37
  38 static const struct of_device_id aspeed_wdt_of_table[] = {
  39         { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
  40         { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
  41         { },
  42 };
  43 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
  44
  45 #define WDT_STATUS              0x00
  46 #define WDT_RELOAD_VALUE        0x04
  47 #define WDT_RESTART             0x08
  48 #define WDT_CTRL                0x0C
  49 #define   WDT_CTRL_BOOT_SECONDARY       BIT(7)
  50 #define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
  51 #define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
  52 #define   WDT_CTRL_RESET_MODE_ARM_CPU   (0x10 << 5)
  53 #define   WDT_CTRL_1MHZ_CLK             BIT(4)
  54 #define   WDT_CTRL_WDT_EXT              BIT(3)
  55 #define   WDT_CTRL_WDT_INTR             BIT(2)
  56 #define   WDT_CTRL_RESET_SYSTEM         BIT(1)
  57 #define   WDT_CTRL_ENABLE               BIT(0)
  58
  59 /*
  60  * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
  61  * enabled), specifically:
  62  *
  63  * * Pulse duration
  64  * * Drive mode: push-pull vs open-drain
  65  * * Polarity: Active high or active low
  66  *
  67  * Pulse duration configuration is available on both the AST2400 and AST2500,
  68  * though the field changes between SoCs:
  69  *
  70  * AST2400: Bits 7:0
  71  * AST2500: Bits 19:0
  72  *
  73  * This difference is captured in struct aspeed_wdt_config.
  74  *
  75  * The AST2500 exposes the drive mode and polarity options, but not in a
  76  * regular fashion. For read purposes, bit 31 represents active high or low,
  77  * and bit 30 represents push-pull or open-drain. With respect to write, magic
  78  * values need to be written to the top byte to change the state of the drive
  79  * mode and polarity bits. Any other value written to the top byte has no
  80  * effect on the state of the drive mode or polarity bits. However, the pulse
  81  * width value must be preserved (as desired) if written.
  82  */
  83 #define WDT_RESET_WIDTH         0x18
  84 #define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
  85 #define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
  86 #define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
  87 #define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
  88 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
  89 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
  90
  91 #define WDT_RESTART_MAGIC       0x4755
  92
  93 /* 32 bits at 1MHz, in milliseconds */
  94 #define WDT_MAX_TIMEOUT_MS      4294967
  95 #define WDT_DEFAULT_TIMEOUT     30
  96 #define WDT_RATE_1MHZ           1000000
  97
  98 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
  99 {
 100         return container_of(wdd, struct aspeed_wdt, wdd);
 101 }
 102
 103 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
 104 {
 105         wdt->ctrl |= WDT_CTRL_ENABLE;
 106
 107         writel(0, wdt->base + WDT_CTRL);
 108         writel(count, wdt->base + WDT_RELOAD_VALUE);
 109         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 110         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 111 }
 112
 113 static int aspeed_wdt_start(struct watchdog_device *wdd)
 114 {
 115         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 116
 117         aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
 118
 119         return 0;
 120 }
 121
 122 static int aspeed_wdt_stop(struct watchdog_device *wdd)
 123 {
 124         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 125
 126         wdt->ctrl &= ~WDT_CTRL_ENABLE;
 127         writel(wdt->ctrl, wdt->base + WDT_CTRL);
 128
 129         return 0;
 130 }
 131
 132 static int aspeed_wdt_ping(struct watchdog_device *wdd)
 133 {
 134         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 135
 136         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 137
 138         return 0;
 139 }
 140
 141 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
 142                                   unsigned int timeout)
 143 {
 144         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 145         u32 actual;
 146
 147         wdd->timeout = timeout;
 148
 149         actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);
 150
 151         writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
 152         writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
 153
 154         return 0;
 155 }
 156
 157 static int aspeed_wdt_restart(struct watchdog_device *wdd,
 158                               unsigned long action, void *data)
 159 {
 160         struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
 161
 162         wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
 163         aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
 164
 165         mdelay(1000);
 166
 167         return 0;
 168 }
 169
 170 static const struct watchdog_ops aspeed_wdt_ops = {
 171         .start          = aspeed_wdt_start,
 172         .stop           = aspeed_wdt_stop,
 173         .ping           = aspeed_wdt_ping,
 174         .set_timeout    = aspeed_wdt_set_timeout,
 175         .restart        = aspeed_wdt_restart,
 176         .owner          = THIS_MODULE,
 177 };
 178
 179 static const struct watchdog_info aspeed_wdt_info = {
 180         .options        = WDIOF_KEEPALIVEPING
 181                         | WDIOF_MAGICCLOSE
 182                         | WDIOF_SETTIMEOUT,
 183         .identity       = KBUILD_MODNAME,
 184 };
 185
 186 static int aspeed_wdt_probe(struct platform_device *pdev)
 187 {
 188         const struct aspeed_wdt_config *config;
 189         const struct of_device_id *ofdid;
 190         struct aspeed_wdt *wdt;
 191         struct resource *res;
 192         struct device_node *np;
 193         const char *reset_type;
 194         u32 duration;
 195         int ret;
 196
 197         wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
 198         if (!wdt)
 199                 return -ENOMEM;
 200
 201         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 202         wdt->base = devm_ioremap_resource(&pdev->dev, res);
 203         if (IS_ERR(wdt->base))
 204                 return PTR_ERR(wdt->base);
 205
 206         /*
 207          * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only
 208          * runs at 1MHz. We chose to always run at 1MHz, as there's no
 209          * good reason to have a faster watchdog counter.
 210          */
 211         wdt->wdd.info = &aspeed_wdt_info;
 212         wdt->wdd.ops = &aspeed_wdt_ops;
 213         wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
 214         wdt->wdd.parent = &pdev->dev;
 215
 216         wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
 217         watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
 218
 219         np = pdev->dev.of_node;
 220
 221         ofdid = of_match_node(aspeed_wdt_of_table, np);
 222         if (!ofdid)
 223                 return -EINVAL;
 224         config = ofdid->data;
 225
 226         wdt->ctrl = WDT_CTRL_1MHZ_CLK;
 227
 228         /*
 229          * Control reset on a per-device basis to ensure the
 230          * host is not affected by a BMC reboot
 231          */
 232         ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
 233         if (ret) {
 234                 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
 235         } else {
 236                 if (!strcmp(reset_type, "cpu"))
 237                         wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
 238                                      WDT_CTRL_RESET_SYSTEM;
 239                 else if (!strcmp(reset_type, "soc"))
 240                         wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
 241                                      WDT_CTRL_RESET_SYSTEM;
 242                 else if (!strcmp(reset_type, "system"))
 243                         wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
 244                                      WDT_CTRL_RESET_SYSTEM;
 245                 else if (strcmp(reset_type, "none"))
 246                         return -EINVAL;
 247         }
 248         if (of_property_read_bool(np, "aspeed,external-signal"))
 249                 wdt->ctrl |= WDT_CTRL_WDT_EXT;
 250         if (of_property_read_bool(np, "aspeed,alt-boot"))
 251                 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
 252
 253         if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE)  {
 254                 /*
 255                  * The watchdog is running, but invoke aspeed_wdt_start() to
 256                  * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
 257                  * configuration conforms to the driver's expectations.
 258                  * Primarily, ensure we're using the 1MHz clock source.
 259                  */
 260                 aspeed_wdt_start(&wdt->wdd);
 261                 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
 262         }
 263
 264         if (of_device_is_compatible(np, "aspeed,ast2500-wdt")) {
 265                 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
 266
 267                 reg &= config->ext_pulse_width_mask;
 268                 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
 269                         reg |= WDT_PUSH_PULL_MAGIC;
 270                 else
 271                         reg |= WDT_OPEN_DRAIN_MAGIC;
 272
 273                 writel(reg, wdt->base + WDT_RESET_WIDTH);
 274
 275                 reg &= config->ext_pulse_width_mask;
 276                 if (of_property_read_bool(np, "aspeed,ext-active-high"))
 277                         reg |= WDT_ACTIVE_HIGH_MAGIC;
 278                 else
 279                         reg |= WDT_ACTIVE_LOW_MAGIC;
 280
 281                 writel(reg, wdt->base + WDT_RESET_WIDTH);
 282         }
 283
 284         if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
 285                 u32 max_duration = config->ext_pulse_width_mask + 1;
 286
 287                 if (duration == 0 || duration > max_duration) {
 288                         dev_err(&pdev->dev, "Invalid pulse duration: %uus\n",
 289                                         duration);
 290                         duration = max(1U, min(max_duration, duration));
 291                         dev_info(&pdev->dev, "Pulse duration set to %uus\n",
 292                                         duration);
 293                 }
 294
 295                 /*
 296                  * The watchdog is always configured with a 1MHz source, so
 297                  * there is no need to scale the microsecond value. However we
 298                  * need to offset it - from the datasheet:
 299                  *
 300                  * "This register decides the asserting duration of wdt_ext and
 301                  * wdt_rstarm signal. The default value is 0xFF. It means the
 302                  * default asserting duration of wdt_ext and wdt_rstarm is
 303                  * 256us."
 304                  *
 305                  * This implies a value of 0 gives a 1us pulse.
 306                  */
 307                 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
 308         }
 309
 310         ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
 311         if (ret) {
 312                 dev_err(&pdev->dev, "failed to register\n");
 313                 return ret;
 314         }
 315
 316         return 0;
 317 }
 318
 319 static struct platform_driver aspeed_watchdog_driver = {
 320         .probe = aspeed_wdt_probe,
 321         .driver = {
 322                 .name = KBUILD_MODNAME,
 323                 .of_match_table = of_match_ptr(aspeed_wdt_of_table),
 324         },
 325 };
 326
 327 static int __init aspeed_wdt_init(void)
 328 {
 329         return platform_driver_register(&aspeed_watchdog_driver);
 330 }
 331 arch_initcall(aspeed_wdt_init);
 332
 333 static void __exit aspeed_wdt_exit(void)
 334 {
 335         platform_driver_unregister(&aspeed_watchdog_driver);
 336 }
 337 module_exit(aspeed_wdt_exit);
 338
 339 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
 340 MODULE_LICENSE("GPL");