1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2016 IBM Corporation
5 * Joel Stanley <joel@jms.id.au>
8 #include <linux/delay.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/watchdog.h>
17 struct watchdog_device wdd;
22 struct aspeed_wdt_config {
23 u32 ext_pulse_width_mask;
26 static const struct aspeed_wdt_config ast2400_config = {
27 .ext_pulse_width_mask = 0xff,
30 static const struct aspeed_wdt_config ast2500_config = {
31 .ext_pulse_width_mask = 0xfffff,
34 static const struct of_device_id aspeed_wdt_of_table[] = {
35 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
36 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
37 { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
40 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
42 #define WDT_STATUS 0x00
43 #define WDT_RELOAD_VALUE 0x04
44 #define WDT_RESTART 0x08
46 #define WDT_CTRL_BOOT_SECONDARY BIT(7)
47 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
48 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
49 #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
50 #define WDT_CTRL_1MHZ_CLK BIT(4)
51 #define WDT_CTRL_WDT_EXT BIT(3)
52 #define WDT_CTRL_WDT_INTR BIT(2)
53 #define WDT_CTRL_RESET_SYSTEM BIT(1)
54 #define WDT_CTRL_ENABLE BIT(0)
55 #define WDT_TIMEOUT_STATUS 0x10
56 #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
57 #define WDT_CLEAR_TIMEOUT_STATUS 0x14
58 #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
61 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
62 * enabled), specifically:
65 * * Drive mode: push-pull vs open-drain
66 * * Polarity: Active high or active low
68 * Pulse duration configuration is available on both the AST2400 and AST2500,
69 * though the field changes between SoCs:
74 * This difference is captured in struct aspeed_wdt_config.
76 * The AST2500 exposes the drive mode and polarity options, but not in a
77 * regular fashion. For read purposes, bit 31 represents active high or low,
78 * and bit 30 represents push-pull or open-drain. With respect to write, magic
79 * values need to be written to the top byte to change the state of the drive
80 * mode and polarity bits. Any other value written to the top byte has no
81 * effect on the state of the drive mode or polarity bits. However, the pulse
82 * width value must be preserved (as desired) if written.
84 #define WDT_RESET_WIDTH 0x18
85 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
86 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
87 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
88 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
89 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
90 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
92 #define WDT_RESTART_MAGIC 0x4755
94 /* 32 bits at 1MHz, in milliseconds */
95 #define WDT_MAX_TIMEOUT_MS 4294967
96 #define WDT_DEFAULT_TIMEOUT 30
97 #define WDT_RATE_1MHZ 1000000
99 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
101 return container_of(wdd, struct aspeed_wdt, wdd);
104 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
106 wdt->ctrl |= WDT_CTRL_ENABLE;
108 writel(0, wdt->base + WDT_CTRL);
109 writel(count, wdt->base + WDT_RELOAD_VALUE);
110 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
111 writel(wdt->ctrl, wdt->base + WDT_CTRL);
114 static int aspeed_wdt_start(struct watchdog_device *wdd)
116 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
118 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
123 static int aspeed_wdt_stop(struct watchdog_device *wdd)
125 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
127 wdt->ctrl &= ~WDT_CTRL_ENABLE;
128 writel(wdt->ctrl, wdt->base + WDT_CTRL);
133 static int aspeed_wdt_ping(struct watchdog_device *wdd)
135 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
137 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
142 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
143 unsigned int timeout)
145 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
148 wdd->timeout = timeout;
150 actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);
152 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
153 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
158 static int aspeed_wdt_restart(struct watchdog_device *wdd,
159 unsigned long action, void *data)
161 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
163 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
164 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
171 /* access_cs0 shows if cs0 is accessible, hence the reverted bit */
172 static ssize_t access_cs0_show(struct device *dev,
173 struct device_attribute *attr, char *buf)
175 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
176 u32 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
178 return sprintf(buf, "%u\n",
179 !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
182 static ssize_t access_cs0_store(struct device *dev,
183 struct device_attribute *attr, const char *buf,
186 struct aspeed_wdt *wdt = dev_get_drvdata(dev);
189 if (kstrtoul(buf, 10, &val))
193 writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
194 wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
200 * This attribute exists only if the system has booted from the alternate
201 * flash with 'alt-boot' option.
203 * At alternate flash the 'access_cs0' sysfs node provides:
204 * ast2400: a way to get access to the primary SPI flash chip at CS0
205 * after booting from the alternate chip at CS1.
206 * ast2500: a way to restore the normal address mapping from
207 * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
209 * Clearing the boot code selection and timeout counter also resets to the
210 * initial state the chip select line mapping. When the SoC is in normal
211 * mapping state (i.e. booted from CS0), clearing those bits does nothing for
212 * both versions of the SoC. For alternate boot mode (booted from CS1 due to
213 * wdt2 expiration) the behavior differs as described above.
215 * This option can be used with wdt2 (watchdog1) only.
217 static DEVICE_ATTR_RW(access_cs0);
219 static struct attribute *bswitch_attrs[] = {
220 &dev_attr_access_cs0.attr,
223 ATTRIBUTE_GROUPS(bswitch);
225 static const struct watchdog_ops aspeed_wdt_ops = {
226 .start = aspeed_wdt_start,
227 .stop = aspeed_wdt_stop,
228 .ping = aspeed_wdt_ping,
229 .set_timeout = aspeed_wdt_set_timeout,
230 .restart = aspeed_wdt_restart,
231 .owner = THIS_MODULE,
234 static const struct watchdog_info aspeed_wdt_info = {
235 .options = WDIOF_KEEPALIVEPING
238 .identity = KBUILD_MODNAME,
241 static int aspeed_wdt_probe(struct platform_device *pdev)
243 struct device *dev = &pdev->dev;
244 const struct aspeed_wdt_config *config;
245 const struct of_device_id *ofdid;
246 struct aspeed_wdt *wdt;
247 struct device_node *np;
248 const char *reset_type;
253 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
257 wdt->base = devm_platform_ioremap_resource(pdev, 0);
258 if (IS_ERR(wdt->base))
259 return PTR_ERR(wdt->base);
262 * The ast2400 wdt can run at PCLK, or 1MHz. The ast2500 only
263 * runs at 1MHz. We chose to always run at 1MHz, as there's no
264 * good reason to have a faster watchdog counter.
266 wdt->wdd.info = &aspeed_wdt_info;
267 wdt->wdd.ops = &aspeed_wdt_ops;
268 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
269 wdt->wdd.parent = dev;
271 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
272 watchdog_init_timeout(&wdt->wdd, 0, dev);
276 ofdid = of_match_node(aspeed_wdt_of_table, np);
279 config = ofdid->data;
281 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
284 * Control reset on a per-device basis to ensure the
285 * host is not affected by a BMC reboot
287 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
289 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
291 if (!strcmp(reset_type, "cpu"))
292 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
293 WDT_CTRL_RESET_SYSTEM;
294 else if (!strcmp(reset_type, "soc"))
295 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
296 WDT_CTRL_RESET_SYSTEM;
297 else if (!strcmp(reset_type, "system"))
298 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
299 WDT_CTRL_RESET_SYSTEM;
300 else if (strcmp(reset_type, "none"))
303 if (of_property_read_bool(np, "aspeed,external-signal"))
304 wdt->ctrl |= WDT_CTRL_WDT_EXT;
305 if (of_property_read_bool(np, "aspeed,alt-boot"))
306 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
308 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
310 * The watchdog is running, but invoke aspeed_wdt_start() to
311 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
312 * configuration conforms to the driver's expectations.
313 * Primarily, ensure we're using the 1MHz clock source.
315 aspeed_wdt_start(&wdt->wdd);
316 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
319 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
320 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
321 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
323 reg &= config->ext_pulse_width_mask;
324 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
325 reg |= WDT_PUSH_PULL_MAGIC;
327 reg |= WDT_OPEN_DRAIN_MAGIC;
329 writel(reg, wdt->base + WDT_RESET_WIDTH);
331 reg &= config->ext_pulse_width_mask;
332 if (of_property_read_bool(np, "aspeed,ext-active-high"))
333 reg |= WDT_ACTIVE_HIGH_MAGIC;
335 reg |= WDT_ACTIVE_LOW_MAGIC;
337 writel(reg, wdt->base + WDT_RESET_WIDTH);
340 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
341 u32 max_duration = config->ext_pulse_width_mask + 1;
343 if (duration == 0 || duration > max_duration) {
344 dev_err(dev, "Invalid pulse duration: %uus\n",
346 duration = max(1U, min(max_duration, duration));
347 dev_info(dev, "Pulse duration set to %uus\n",
352 * The watchdog is always configured with a 1MHz source, so
353 * there is no need to scale the microsecond value. However we
354 * need to offset it - from the datasheet:
356 * "This register decides the asserting duration of wdt_ext and
357 * wdt_rstarm signal. The default value is 0xFF. It means the
358 * default asserting duration of wdt_ext and wdt_rstarm is
361 * This implies a value of 0 gives a 1us pulse.
363 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
366 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
367 if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
368 wdt->wdd.bootstatus = WDIOF_CARDRESET;
370 if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
371 of_device_is_compatible(np, "aspeed,ast2500-wdt"))
372 wdt->wdd.groups = bswitch_groups;
375 dev_set_drvdata(dev, wdt);
377 return devm_watchdog_register_device(dev, &wdt->wdd);
380 static struct platform_driver aspeed_watchdog_driver = {
381 .probe = aspeed_wdt_probe,
383 .name = KBUILD_MODNAME,
384 .of_match_table = of_match_ptr(aspeed_wdt_of_table),
388 static int __init aspeed_wdt_init(void)
390 return platform_driver_register(&aspeed_watchdog_driver);
392 arch_initcall(aspeed_wdt_init);
394 static void __exit aspeed_wdt_exit(void)
396 platform_driver_unregister(&aspeed_watchdog_driver);
398 module_exit(aspeed_wdt_exit);
400 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
401 MODULE_LICENSE("GPL");