drivers/watchdog/dw_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2010-2011 Picochip Ltd., Jamie Iles
   4  * http://www.picochip.com
   5  *
   6  * This file implements a driver for the Synopsys DesignWare watchdog device
   7  * in the many subsystems. The watchdog has 16 different timeout periods
   8  * and these are a function of the input clock frequency.
   9  *
  10  * The DesignWare watchdog cannot be stopped once it has been started so we
  11  * do not implement a stop function. The watchdog core will continue to send
  12  * heartbeat requests after the watchdog device has been closed.
  13  */
  14
  15 #include <linux/bitops.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/io.h>
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/of.h>
  24 #include <linux/pm.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/reset.h>
  27 #include <linux/watchdog.h>
  28
  29 #define WDOG_CONTROL_REG_OFFSET             0x00
  30 #define WDOG_CONTROL_REG_WDT_EN_MASK        0x01
  31 #define WDOG_CONTROL_REG_RESP_MODE_MASK     0x02
  32 #define WDOG_TIMEOUT_RANGE_REG_OFFSET       0x04
  33 #define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT    4
  34 #define WDOG_CURRENT_COUNT_REG_OFFSET       0x08
  35 #define WDOG_COUNTER_RESTART_REG_OFFSET     0x0c
  36 #define WDOG_COUNTER_RESTART_KICK_VALUE     0x76
  37
  38 /* The maximum TOP (timeout period) value that can be set in the watchdog. */
  39 #define DW_WDT_MAX_TOP          15
  40
  41 #define DW_WDT_DEFAULT_SECONDS  30
  42
  43 static bool nowayout = WATCHDOG_NOWAYOUT;
  44 module_param(nowayout, bool, 0);
  45 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
  46                  "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  47
  48 struct dw_wdt {
  49         void __iomem            *regs;
  50         struct clk              *clk;
  51         unsigned long           rate;
  52         struct watchdog_device  wdd;
  53         struct reset_control    *rst;
  54         /* Save/restore */
  55         u32                     control;
  56         u32                     timeout;
  57 };
  58
  59 #define to_dw_wdt(wdd)  container_of(wdd, struct dw_wdt, wdd)
  60
  61 static inline int dw_wdt_is_enabled(struct dw_wdt *dw_wdt)
  62 {
  63         return readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET) &
  64                 WDOG_CONTROL_REG_WDT_EN_MASK;
  65 }
  66
  67 static inline int dw_wdt_top_in_seconds(struct dw_wdt *dw_wdt, unsigned top)
  68 {
  69         /*
  70          * There are 16 possible timeout values in 0..15 where the number of
  71          * cycles is 2 ^ (16 + i) and the watchdog counts down.
  72          */
  73         return (1U << (16 + top)) / dw_wdt->rate;
  74 }
  75
  76 static int dw_wdt_get_top(struct dw_wdt *dw_wdt)
  77 {
  78         int top = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET) & 0xF;
  79
  80         return dw_wdt_top_in_seconds(dw_wdt, top);
  81 }
  82
  83 static int dw_wdt_ping(struct watchdog_device *wdd)
  84 {
  85         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  86
  87         writel(WDOG_COUNTER_RESTART_KICK_VALUE, dw_wdt->regs +
  88                WDOG_COUNTER_RESTART_REG_OFFSET);
  89
  90         return 0;
  91 }
  92
  93 static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
  94 {
  95         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
  96         int i, top_val = DW_WDT_MAX_TOP;
  97
  98         /*
  99          * Iterate over the timeout values until we find the closest match. We
 100          * always look for >=.
 101          */
 102         for (i = 0; i <= DW_WDT_MAX_TOP; ++i)
 103                 if (dw_wdt_top_in_seconds(dw_wdt, i) >= top_s) {
 104                         top_val = i;
 105                         break;
 106                 }
 107
 108         /*
 109          * Set the new value in the watchdog.  Some versions of dw_wdt
 110          * have have TOPINIT in the TIMEOUT_RANGE register (as per
 111          * CP_WDT_DUAL_TOP in WDT_COMP_PARAMS_1).  On those we
 112          * effectively get a pat of the watchdog right here.
 113          */
 114         writel(top_val | top_val << WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT,
 115                dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 116
 117         /*
 118          * In case users set bigger timeout value than HW can support,
 119          * kernel(watchdog_dev.c) helps to feed watchdog before
 120          * wdd->max_hw_heartbeat_ms
 121          */
 122         if (top_s * 1000 <= wdd->max_hw_heartbeat_ms)
 123                 wdd->timeout = dw_wdt_top_in_seconds(dw_wdt, top_val);
 124         else
 125                 wdd->timeout = top_s;
 126
 127         return 0;
 128 }
 129
 130 static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
 131 {
 132         u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
 133
 134         /* Disable interrupt mode; always perform system reset. */
 135         val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
 136         /* Enable watchdog. */
 137         val |= WDOG_CONTROL_REG_WDT_EN_MASK;
 138         writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
 139 }
 140
 141 static int dw_wdt_start(struct watchdog_device *wdd)
 142 {
 143         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 144
 145         dw_wdt_set_timeout(wdd, wdd->timeout);
 146         dw_wdt_arm_system_reset(dw_wdt);
 147
 148         return 0;
 149 }
 150
 151 static int dw_wdt_stop(struct watchdog_device *wdd)
 152 {
 153         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 154
 155         if (!dw_wdt->rst) {
 156                 set_bit(WDOG_HW_RUNNING, &wdd->status);
 157                 return 0;
 158         }
 159
 160         reset_control_assert(dw_wdt->rst);
 161         reset_control_deassert(dw_wdt->rst);
 162
 163         return 0;
 164 }
 165
 166 static int dw_wdt_restart(struct watchdog_device *wdd,
 167                           unsigned long action, void *data)
 168 {
 169         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 170
 171         writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 172         if (dw_wdt_is_enabled(dw_wdt))
 173                 writel(WDOG_COUNTER_RESTART_KICK_VALUE,
 174                        dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
 175         else
 176                 dw_wdt_arm_system_reset(dw_wdt);
 177
 178         /* wait for reset to assert... */
 179         mdelay(500);
 180
 181         return 0;
 182 }
 183
 184 static unsigned int dw_wdt_get_timeleft(struct watchdog_device *wdd)
 185 {
 186         struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
 187
 188         return readl(dw_wdt->regs + WDOG_CURRENT_COUNT_REG_OFFSET) /
 189                 dw_wdt->rate;
 190 }
 191
 192 static const struct watchdog_info dw_wdt_ident = {
 193         .options        = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
 194                           WDIOF_MAGICCLOSE,
 195         .identity       = "Synopsys DesignWare Watchdog",
 196 };
 197
 198 static const struct watchdog_ops dw_wdt_ops = {
 199         .owner          = THIS_MODULE,
 200         .start          = dw_wdt_start,
 201         .stop           = dw_wdt_stop,
 202         .ping           = dw_wdt_ping,
 203         .set_timeout    = dw_wdt_set_timeout,
 204         .get_timeleft   = dw_wdt_get_timeleft,
 205         .restart        = dw_wdt_restart,
 206 };
 207
 208 #ifdef CONFIG_PM_SLEEP
 209 static int dw_wdt_suspend(struct device *dev)
 210 {
 211         struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
 212
 213         dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
 214         dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 215
 216         clk_disable_unprepare(dw_wdt->clk);
 217
 218         return 0;
 219 }
 220
 221 static int dw_wdt_resume(struct device *dev)
 222 {
 223         struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
 224         int err = clk_prepare_enable(dw_wdt->clk);
 225
 226         if (err)
 227                 return err;
 228
 229         writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
 230         writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
 231
 232         dw_wdt_ping(&dw_wdt->wdd);
 233
 234         return 0;
 235 }
 236 #endif /* CONFIG_PM_SLEEP */
 237
 238 static SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume);
 239
 240 static int dw_wdt_drv_probe(struct platform_device *pdev)
 241 {
 242         struct device *dev = &pdev->dev;
 243         struct watchdog_device *wdd;
 244         struct dw_wdt *dw_wdt;
 245         int ret;
 246
 247         dw_wdt = devm_kzalloc(dev, sizeof(*dw_wdt), GFP_KERNEL);
 248         if (!dw_wdt)
 249                 return -ENOMEM;
 250
 251         dw_wdt->regs = devm_platform_ioremap_resource(pdev, 0);
 252         if (IS_ERR(dw_wdt->regs))
 253                 return PTR_ERR(dw_wdt->regs);
 254
 255         dw_wdt->clk = devm_clk_get(dev, NULL);
 256         if (IS_ERR(dw_wdt->clk))
 257                 return PTR_ERR(dw_wdt->clk);
 258
 259         ret = clk_prepare_enable(dw_wdt->clk);
 260         if (ret)
 261                 return ret;
 262
 263         dw_wdt->rate = clk_get_rate(dw_wdt->clk);
 264         if (dw_wdt->rate == 0) {
 265                 ret = -EINVAL;
 266                 goto out_disable_clk;
 267         }
 268
 269         dw_wdt->rst = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
 270         if (IS_ERR(dw_wdt->rst)) {
 271                 ret = PTR_ERR(dw_wdt->rst);
 272                 goto out_disable_clk;
 273         }
 274
 275         reset_control_deassert(dw_wdt->rst);
 276
 277         wdd = &dw_wdt->wdd;
 278         wdd->info = &dw_wdt_ident;
 279         wdd->ops = &dw_wdt_ops;
 280         wdd->min_timeout = 1;
 281         wdd->max_hw_heartbeat_ms =
 282                 dw_wdt_top_in_seconds(dw_wdt, DW_WDT_MAX_TOP) * 1000;
 283         wdd->parent = dev;
 284
 285         watchdog_set_drvdata(wdd, dw_wdt);
 286         watchdog_set_nowayout(wdd, nowayout);
 287         watchdog_init_timeout(wdd, 0, dev);
 288
 289         /*
 290          * If the watchdog is already running, use its already configured
 291          * timeout. Otherwise use the default or the value provided through
 292          * devicetree.
 293          */
 294         if (dw_wdt_is_enabled(dw_wdt)) {
 295                 wdd->timeout = dw_wdt_get_top(dw_wdt);
 296                 set_bit(WDOG_HW_RUNNING, &wdd->status);
 297         } else {
 298                 wdd->timeout = DW_WDT_DEFAULT_SECONDS;
 299                 watchdog_init_timeout(wdd, 0, dev);
 300         }
 301
 302         platform_set_drvdata(pdev, dw_wdt);
 303
 304         watchdog_set_restart_priority(wdd, 128);
 305
 306         ret = watchdog_register_device(wdd);
 307         if (ret)
 308                 goto out_disable_clk;
 309
 310         return 0;
 311
 312 out_disable_clk:
 313         clk_disable_unprepare(dw_wdt->clk);
 314         return ret;
 315 }
 316
 317 static int dw_wdt_drv_remove(struct platform_device *pdev)
 318 {
 319         struct dw_wdt *dw_wdt = platform_get_drvdata(pdev);
 320
 321         watchdog_unregister_device(&dw_wdt->wdd);
 322         reset_control_assert(dw_wdt->rst);
 323         clk_disable_unprepare(dw_wdt->clk);
 324
 325         return 0;
 326 }
 327
 328 #ifdef CONFIG_OF
 329 static const struct of_device_id dw_wdt_of_match[] = {
 330         { .compatible = "snps,dw-wdt", },
 331         { /* sentinel */ }
 332 };
 333 MODULE_DEVICE_TABLE(of, dw_wdt_of_match);
 334 #endif
 335
 336 static struct platform_driver dw_wdt_driver = {
 337         .probe          = dw_wdt_drv_probe,
 338         .remove         = dw_wdt_drv_remove,
 339         .driver         = {
 340                 .name   = "dw_wdt",
 341                 .of_match_table = of_match_ptr(dw_wdt_of_match),
 342                 .pm     = &dw_wdt_pm_ops,
 343         },
 344 };
 345
 346 module_platform_driver(dw_wdt_driver);
 347
 348 MODULE_AUTHOR("Jamie Iles");
 349 MODULE_DESCRIPTION("Synopsys DesignWare Watchdog Driver");
 350 MODULE_LICENSE("GPL");