2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #ifndef __ASM_ARM_KVM_VGIC_H
20 #define __ASM_ARM_KVM_VGIC_H
22 #include <linux/kernel.h>
23 #include <linux/kvm.h>
24 #include <linux/irqreturn.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
28 #define VGIC_NR_IRQS_LEGACY 256
29 #define VGIC_NR_SGIS 16
30 #define VGIC_NR_PPIS 16
31 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33 #define VGIC_V2_MAX_LRS (1 << 6)
34 #define VGIC_V3_MAX_LRS 16
35 #define VGIC_MAX_IRQS 1024
36 #define VGIC_V2_MAX_CPUS 8
38 /* Sanity checks... */
39 #if (KVM_MAX_VCPUS > 255)
40 #error Too many KVM VCPUs, the VGIC only supports up to 255 VCPUs for now
43 #if (VGIC_NR_IRQS_LEGACY & 31)
44 #error "VGIC_NR_IRQS must be a multiple of 32"
47 #if (VGIC_NR_IRQS_LEGACY > VGIC_MAX_IRQS)
48 #error "VGIC_NR_IRQS must be <= 1024"
52 * The GIC distributor registers describing interrupts have two parts:
53 * - 32 per-CPU interrupts (SGI + PPI)
54 * - a bunch of shared interrupts (SPI)
58 * - One UL per VCPU for private interrupts (assumes UL is at
60 * - As many UL as necessary for shared interrupts.
62 * The private interrupts are accessed via the "private"
63 * field, one UL per vcpu (the state for vcpu n is in
64 * private[n]). The shared interrupts are accessed via the
65 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
67 unsigned long *private;
68 unsigned long *shared;
73 * - 8 u32 per VCPU for private interrupts
74 * - As many u32 as necessary for shared interrupts.
76 * The private interrupts are accessed via the "private"
77 * field, (the state for vcpu n is in private[n*8] to
78 * private[n*8 + 7]). The shared interrupts are accessed via
79 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
80 * shared[(n-32)/4] word).
89 VGIC_V2, /* Good ol' GICv2 */
90 VGIC_V3, /* New fancy GICv3 */
93 #define LR_STATE_PENDING (1 << 0)
94 #define LR_STATE_ACTIVE (1 << 1)
95 #define LR_STATE_MASK (3 << 0)
96 #define LR_EOI_INT (1 << 2)
112 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
113 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
114 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
115 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
116 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
117 void (*clear_eisr)(struct kvm_vcpu *vcpu);
118 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
119 void (*enable_underflow)(struct kvm_vcpu *vcpu);
120 void (*disable_underflow)(struct kvm_vcpu *vcpu);
121 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
122 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
123 void (*enable)(struct kvm_vcpu *vcpu);
129 /* Physical address of vgic virtual cpu interface */
130 phys_addr_t vcpu_base;
131 /* Number of list registers */
133 /* Interrupt number */
134 unsigned int maint_irq;
135 /* Virtual control interface base address */
136 void __iomem *vctrl_base;
138 /* Only needed for the legacy KVM_CREATE_IRQCHIP */
139 bool can_emulate_gicv2;
143 bool (*handle_mmio)(struct kvm_vcpu *, struct kvm_run *,
144 struct kvm_exit_mmio *);
145 bool (*queue_sgi)(struct kvm_vcpu *, int irq);
146 void (*add_sgi_source)(struct kvm_vcpu *, int irq, int source);
147 int (*init_model)(struct kvm *);
148 int (*map_resources)(struct kvm *, const struct vgic_params *);
152 #ifdef CONFIG_KVM_ARM_VGIC
157 /* vGIC model the kernel emulates for the guest (GICv2 or GICv3) */
163 /* Virtual control interface mapping */
164 void __iomem *vctrl_base;
166 /* Distributor and vcpu interface mapping in the guest */
167 phys_addr_t vgic_dist_base;
168 /* GICv2 and GICv3 use different mapped register blocks */
170 phys_addr_t vgic_cpu_base;
171 phys_addr_t vgic_redist_base;
174 /* Distributor enabled */
177 /* Interrupt enabled (one bit per IRQ) */
178 struct vgic_bitmap irq_enabled;
180 /* Level-triggered interrupt external input is asserted */
181 struct vgic_bitmap irq_level;
184 * Interrupt state is pending on the distributor
186 struct vgic_bitmap irq_pending;
189 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
190 * interrupts. Essentially holds the state of the flip-flop in
191 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
192 * Once set, it is only cleared for level-triggered interrupts on
193 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
195 struct vgic_bitmap irq_soft_pend;
197 /* Level-triggered interrupt queued on VCPU interface */
198 struct vgic_bitmap irq_queued;
200 /* Interrupt priority. Not used yet. */
201 struct vgic_bytemap irq_priority;
203 /* Level/edge triggered */
204 struct vgic_bitmap irq_cfg;
207 * Source CPU per SGI and target CPU:
209 * Each byte represent a SGI observable on a VCPU, each bit of
210 * this byte indicating if the corresponding VCPU has
211 * generated this interrupt. This is a GICv2 feature only.
213 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
214 * the SGIs observable on VCPUn.
219 * Target CPU for each SPI:
221 * Array of available SPI, each byte indicating the target
222 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
227 * Reverse lookup of irq_spi_cpu for faster compute pending:
229 * Array of bitmaps, one per VCPU, describing if IRQn is
230 * routed to a particular VCPU.
232 struct vgic_bitmap *irq_spi_target;
234 /* Target MPIDR for each IRQ (needed for GICv3 IROUTERn) only */
237 /* Bitmap indicating which CPU has something pending */
238 unsigned long *irq_pending_on_cpu;
240 struct vgic_vm_ops vm_ops;
244 struct vgic_v2_cpu_if {
247 u32 vgic_misr; /* Saved only */
248 u64 vgic_eisr; /* Saved only */
249 u64 vgic_elrsr; /* Saved only */
251 u32 vgic_lr[VGIC_V2_MAX_LRS];
254 struct vgic_v3_cpu_if {
255 #ifdef CONFIG_ARM_GIC_V3
258 u32 vgic_sre; /* Restored only, change ignored */
259 u32 vgic_misr; /* Saved only */
260 u32 vgic_eisr; /* Saved only */
261 u32 vgic_elrsr; /* Saved only */
264 u64 vgic_lr[VGIC_V3_MAX_LRS];
269 #ifdef CONFIG_KVM_ARM_VGIC
270 /* per IRQ to LR mapping */
273 /* Pending interrupts on this VCPU */
274 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
275 unsigned long *pending_shared;
277 /* Bitmap of used/free list registers */
278 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
280 /* Number of list registers on this CPU */
283 /* CPU vif control registers for world switch */
285 struct vgic_v2_cpu_if vgic_v2;
286 struct vgic_v3_cpu_if vgic_v3;
291 #define LR_EMPTY 0xff
293 #define INT_STATUS_EOI (1 << 0)
294 #define INT_STATUS_UNDERFLOW (1 << 1)
299 struct kvm_exit_mmio;
301 #ifdef CONFIG_KVM_ARM_VGIC
302 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
303 int kvm_vgic_hyp_init(void);
304 int kvm_vgic_map_resources(struct kvm *kvm);
305 int kvm_vgic_get_max_vcpus(void);
306 int kvm_vgic_create(struct kvm *kvm, u32 type);
307 void kvm_vgic_destroy(struct kvm *kvm);
308 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
309 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
310 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
311 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
313 void vgic_v3_dispatch_sgi(struct kvm_vcpu *vcpu, u64 reg);
314 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
315 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
316 struct kvm_exit_mmio *mmio);
318 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
319 #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
320 #define vgic_ready(k) ((k)->arch.vgic.ready)
322 int vgic_v2_probe(struct device_node *vgic_node,
323 const struct vgic_ops **ops,
324 const struct vgic_params **params);
325 #ifdef CONFIG_ARM_GIC_V3
326 int vgic_v3_probe(struct device_node *vgic_node,
327 const struct vgic_ops **ops,
328 const struct vgic_params **params);
330 static inline int vgic_v3_probe(struct device_node *vgic_node,
331 const struct vgic_ops **ops,
332 const struct vgic_params **params)
339 static inline int kvm_vgic_hyp_init(void)
344 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
349 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
354 static inline int kvm_vgic_map_resources(struct kvm *kvm)
359 static inline int kvm_vgic_create(struct kvm *kvm, u32 type)
364 static inline void kvm_vgic_destroy(struct kvm *kvm)
368 static inline void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
372 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
377 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
378 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
380 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
381 unsigned int irq_num, bool level)
386 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
391 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
392 struct kvm_exit_mmio *mmio)
397 static inline int irqchip_in_kernel(struct kvm *kvm)
402 static inline bool vgic_initialized(struct kvm *kvm)
407 static inline bool vgic_ready(struct kvm *kvm)
412 static inline int kvm_vgic_get_max_vcpus(void)
414 return KVM_MAX_VCPUS;