1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
6 #ifndef __LINUX_CLK_PROVIDER_H
7 #define __LINUX_CLK_PROVIDER_H
10 #include <linux/of_clk.h>
13 * flags used across common struct clk. these flags should only affect the
14 * top-level framework. custom flags for dealing with hardware specifics
15 * belong in struct clk_foo
17 * Please update clk_flags[] in drivers/clk/clk.c when making changes here!
19 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
20 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
21 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
22 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
25 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
27 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
28 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
29 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
30 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
31 /* parents need enable during gate/ungate, set rate and re-parent */
32 #define CLK_OPS_PARENT_ENABLE BIT(12)
33 /* duty cycle call may be forwarded to the parent clock */
34 #define CLK_DUTY_CYCLE_PARENT BIT(13)
42 * struct clk_rate_request - Structure encoding the clk constraints that
43 * a clock user might require.
45 * @rate: Requested clock rate. This field will be adjusted by
46 * clock drivers according to hardware capabilities.
47 * @min_rate: Minimum rate imposed by clk users.
48 * @max_rate: Maximum rate imposed by clk users.
49 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
50 * requested constraints.
51 * @best_parent_hw: The most appropriate parent clock that fulfills the
52 * requested constraints.
55 struct clk_rate_request {
57 unsigned long min_rate;
58 unsigned long max_rate;
59 unsigned long best_parent_rate;
60 struct clk_hw *best_parent_hw;
64 * struct clk_duty - Struture encoding the duty cycle ratio of a clock
66 * @num: Numerator of the duty cycle ratio
67 * @den: Denominator of the duty cycle ratio
75 * struct clk_ops - Callback operations for hardware clocks; these are to
76 * be provided by the clock implementation, and will be called by drivers
77 * through the clk_* api.
79 * @prepare: Prepare the clock for enabling. This must not return until
80 * the clock is fully prepared, and it's safe to call clk_enable.
81 * This callback is intended to allow clock implementations to
82 * do any initialisation that may sleep. Called with
85 * @unprepare: Release the clock from its prepared state. This will typically
86 * undo any work done in the @prepare callback. Called with
89 * @is_prepared: Queries the hardware to determine if the clock is prepared.
90 * This function is allowed to sleep. Optional, if this op is not
91 * set then the prepare count will be used.
93 * @unprepare_unused: Unprepare the clock atomically. Only called from
94 * clk_disable_unused for prepare clocks with special needs.
95 * Called with prepare mutex held. This function may sleep.
97 * @enable: Enable the clock atomically. This must not return until the
98 * clock is generating a valid clock signal, usable by consumer
99 * devices. Called with enable_lock held. This function must not
102 * @disable: Disable the clock atomically. Called with enable_lock held.
103 * This function must not sleep.
105 * @is_enabled: Queries the hardware to determine if the clock is enabled.
106 * This function must not sleep. Optional, if this op is not
107 * set then the enable count will be used.
109 * @disable_unused: Disable the clock atomically. Only called from
110 * clk_disable_unused for gate clocks with special needs.
111 * Called with enable_lock held. This function must not
114 * @save_context: Save the context of the clock in prepration for poweroff.
116 * @restore_context: Restore the context of the clock after a restoration
119 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
120 * parent rate is an input parameter. It is up to the caller to
121 * ensure that the prepare_mutex is held across this call.
122 * Returns the calculated rate. Optional, but recommended - if
123 * this op is not set then clock rate will be initialized to 0.
125 * @round_rate: Given a target rate as input, returns the closest rate actually
126 * supported by the clock. The parent rate is an input/output
129 * @determine_rate: Given a target rate as input, returns the closest rate
130 * actually supported by the clock, and optionally the parent clock
131 * that should be used to provide the clock rate.
133 * @set_parent: Change the input source of this clock; for clocks with multiple
134 * possible parents specify a new parent by passing in the index
135 * as a u8 corresponding to the parent in either the .parent_names
136 * or .parents arrays. This function in affect translates an
137 * array index into the value programmed into the hardware.
138 * Returns 0 on success, -EERROR otherwise.
140 * @get_parent: Queries the hardware to determine the parent of a clock. The
141 * return value is a u8 which specifies the index corresponding to
142 * the parent clock. This index can be applied to either the
143 * .parent_names or .parents arrays. In short, this function
144 * translates the parent value read from hardware into an array
145 * index. Currently only called when the clock is initialized by
146 * __clk_init. This callback is mandatory for clocks with
147 * multiple parents. It is optional (and unnecessary) for clocks
148 * with 0 or 1 parents.
150 * @set_rate: Change the rate of this clock. The requested rate is specified
151 * by the second argument, which should typically be the return
152 * of .round_rate call. The third argument gives the parent rate
153 * which is likely helpful for most .set_rate implementation.
154 * Returns 0 on success, -EERROR otherwise.
156 * @set_rate_and_parent: Change the rate and the parent of this clock. The
157 * requested rate is specified by the second argument, which
158 * should typically be the return of .round_rate call. The
159 * third argument gives the parent rate which is likely helpful
160 * for most .set_rate_and_parent implementation. The fourth
161 * argument gives the parent index. This callback is optional (and
162 * unnecessary) for clocks with 0 or 1 parents as well as
163 * for clocks that can tolerate switching the rate and the parent
164 * separately via calls to .set_parent and .set_rate.
165 * Returns 0 on success, -EERROR otherwise.
167 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
168 * is expressed in ppb (parts per billion). The parent accuracy is
169 * an input parameter.
170 * Returns the calculated accuracy. Optional - if this op is not
171 * set then clock accuracy will be initialized to parent accuracy
172 * or 0 (perfect clock) if clock has no parent.
174 * @get_phase: Queries the hardware to get the current phase of a clock.
175 * Returned values are 0-359 degrees on success, negative
176 * error codes on failure.
178 * @set_phase: Shift the phase this clock signal in degrees specified
179 * by the second argument. Valid values for degrees are
180 * 0-359. Return 0 on success, otherwise -EERROR.
182 * @get_duty_cycle: Queries the hardware to get the current duty cycle ratio
183 * of a clock. Returned values denominator cannot be 0 and must be
184 * superior or equal to the numerator.
186 * @set_duty_cycle: Apply the duty cycle ratio to this clock signal specified by
187 * the numerator (2nd argurment) and denominator (3rd argument).
188 * Argument must be a valid ratio (denominator > 0
189 * and >= numerator) Return 0 on success, otherwise -EERROR.
191 * @init: Perform platform-specific initialization magic.
192 * This is not not used by any of the basic clock types.
193 * Please consider other ways of solving initialization problems
194 * before using this callback, as its use is discouraged.
196 * @debug_init: Set up type-specific debugfs entries for this clock. This
197 * is called once, after the debugfs directory entry for this
198 * clock has been created. The dentry pointer representing that
199 * directory is provided as an argument. Called with
200 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
203 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
204 * implementations to split any work between atomic (enable) and sleepable
205 * (prepare) contexts. If enabling a clock requires code that might sleep,
206 * this must be done in clk_prepare. Clock enable code that will never be
207 * called in a sleepable context may be implemented in clk_enable.
209 * Typically, drivers will call clk_prepare when a clock may be needed later
210 * (eg. when a device is opened), and clk_enable when the clock is actually
211 * required (eg. from an interrupt). Note that clk_prepare MUST have been
212 * called before clk_enable.
215 int (*prepare)(struct clk_hw *hw);
216 void (*unprepare)(struct clk_hw *hw);
217 int (*is_prepared)(struct clk_hw *hw);
218 void (*unprepare_unused)(struct clk_hw *hw);
219 int (*enable)(struct clk_hw *hw);
220 void (*disable)(struct clk_hw *hw);
221 int (*is_enabled)(struct clk_hw *hw);
222 void (*disable_unused)(struct clk_hw *hw);
223 int (*save_context)(struct clk_hw *hw);
224 void (*restore_context)(struct clk_hw *hw);
225 unsigned long (*recalc_rate)(struct clk_hw *hw,
226 unsigned long parent_rate);
227 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
228 unsigned long *parent_rate);
229 int (*determine_rate)(struct clk_hw *hw,
230 struct clk_rate_request *req);
231 int (*set_parent)(struct clk_hw *hw, u8 index);
232 u8 (*get_parent)(struct clk_hw *hw);
233 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
234 unsigned long parent_rate);
235 int (*set_rate_and_parent)(struct clk_hw *hw,
237 unsigned long parent_rate, u8 index);
238 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
239 unsigned long parent_accuracy);
240 int (*get_phase)(struct clk_hw *hw);
241 int (*set_phase)(struct clk_hw *hw, int degrees);
242 int (*get_duty_cycle)(struct clk_hw *hw,
243 struct clk_duty *duty);
244 int (*set_duty_cycle)(struct clk_hw *hw,
245 struct clk_duty *duty);
246 void (*init)(struct clk_hw *hw);
247 void (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
251 * struct clk_parent_data - clk parent information
252 * @hw: parent clk_hw pointer (used for clk providers with internal clks)
253 * @fw_name: parent name local to provider registering clk
254 * @name: globally unique parent name (used as a fallback)
255 * @index: parent index local to provider registering clk (if @fw_name absent)
257 struct clk_parent_data {
258 const struct clk_hw *hw;
265 * struct clk_init_data - holds init data that's common to all clocks and is
266 * shared between the clock provider and the common clock framework.
269 * @ops: operations this clock supports
270 * @parent_names: array of string names for all possible parents
271 * @parent_data: array of parent data for all possible parents (when some
272 * parents are external to the clk controller)
273 * @parent_hws: array of pointers to all possible parents (when all parents
274 * are internal to the clk controller)
275 * @num_parents: number of possible parents
276 * @flags: framework-level hints and quirks
278 struct clk_init_data {
280 const struct clk_ops *ops;
281 /* Only one of the following three should be assigned */
282 const char * const *parent_names;
283 const struct clk_parent_data *parent_data;
284 const struct clk_hw **parent_hws;
290 * struct clk_hw - handle for traversing from a struct clk to its corresponding
291 * hardware-specific structure. struct clk_hw should be declared within struct
292 * clk_foo and then referenced by the struct clk instance that uses struct
295 * @core: pointer to the struct clk_core instance that points back to this
296 * struct clk_hw instance
298 * @clk: pointer to the per-user struct clk instance that can be used to call
301 * @init: pointer to struct clk_init_data that contains the init data shared
302 * with the common clock framework.
305 struct clk_core *core;
307 const struct clk_init_data *init;
311 * DOC: Basic clock implementations common to many platforms
313 * Each basic clock hardware type is comprised of a structure describing the
314 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
315 * unique flags for that hardware type, a registration function and an
316 * alternative macro for static initialization
320 * struct clk_fixed_rate - fixed-rate clock
321 * @hw: handle between common and hardware-specific interfaces
322 * @fixed_rate: constant frequency of clock
324 struct clk_fixed_rate {
326 unsigned long fixed_rate;
327 unsigned long fixed_accuracy;
330 #define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
332 extern const struct clk_ops clk_fixed_rate_ops;
333 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
334 const char *parent_name, unsigned long flags,
335 unsigned long fixed_rate);
336 struct clk_hw *clk_hw_register_fixed_rate(struct device *dev, const char *name,
337 const char *parent_name, unsigned long flags,
338 unsigned long fixed_rate);
339 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
340 const char *name, const char *parent_name, unsigned long flags,
341 unsigned long fixed_rate, unsigned long fixed_accuracy);
342 void clk_unregister_fixed_rate(struct clk *clk);
343 struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
344 const char *name, const char *parent_name, unsigned long flags,
345 unsigned long fixed_rate, unsigned long fixed_accuracy);
346 void clk_hw_unregister_fixed_rate(struct clk_hw *hw);
348 void of_fixed_clk_setup(struct device_node *np);
351 * struct clk_gate - gating clock
353 * @hw: handle between common and hardware-specific interfaces
354 * @reg: register controlling gate
355 * @bit_idx: single bit controlling gate
356 * @flags: hardware-specific flags
357 * @lock: register lock
359 * Clock which can gate its output. Implements .enable & .disable
362 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
363 * enable the clock. Setting this flag does the opposite: setting the bit
364 * disable the clock and clearing it enables the clock
365 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
366 * of this register, and mask of gate bits are in higher 16-bit of this
367 * register. While setting the gate bits, higher 16-bit should also be
368 * updated to indicate changing gate bits.
369 * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
370 * the gate register. Setting this flag makes the register accesses big
381 #define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
383 #define CLK_GATE_SET_TO_DISABLE BIT(0)
384 #define CLK_GATE_HIWORD_MASK BIT(1)
385 #define CLK_GATE_BIG_ENDIAN BIT(2)
387 extern const struct clk_ops clk_gate_ops;
388 struct clk *clk_register_gate(struct device *dev, const char *name,
389 const char *parent_name, unsigned long flags,
390 void __iomem *reg, u8 bit_idx,
391 u8 clk_gate_flags, spinlock_t *lock);
392 struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
393 const char *parent_name, unsigned long flags,
394 void __iomem *reg, u8 bit_idx,
395 u8 clk_gate_flags, spinlock_t *lock);
396 void clk_unregister_gate(struct clk *clk);
397 void clk_hw_unregister_gate(struct clk_hw *hw);
398 int clk_gate_is_enabled(struct clk_hw *hw);
400 struct clk_div_table {
406 * struct clk_divider - adjustable divider clock
408 * @hw: handle between common and hardware-specific interfaces
409 * @reg: register containing the divider
410 * @shift: shift to the divider bit field
411 * @width: width of the divider bit field
412 * @table: array of value/divider pairs, last entry should have div = 0
413 * @lock: register lock
415 * Clock with an adjustable divider affecting its output frequency. Implements
416 * .recalc_rate, .set_rate and .round_rate
419 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
420 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
421 * the raw value read from the register, with the value of zero considered
422 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
423 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
424 * the hardware register
425 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
426 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
427 * Some hardware implementations gracefully handle this case and allow a
428 * zero divisor by not modifying their input clock
429 * (divide by one / bypass).
430 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
431 * of this register, and mask of divider bits are in higher 16-bit of this
432 * register. While setting the divider bits, higher 16-bit should also be
433 * updated to indicate changing divider bits.
434 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
435 * to the closest integer instead of the up one.
436 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
437 * not be changed by the clock framework.
438 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
439 * except when the value read from the register is zero, the divisor is
440 * 2^width of the field.
441 * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
442 * for the divider register. Setting this flag makes the register accesses
451 const struct clk_div_table *table;
455 #define clk_div_mask(width) ((1 << (width)) - 1)
456 #define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
458 #define CLK_DIVIDER_ONE_BASED BIT(0)
459 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
460 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
461 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
462 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
463 #define CLK_DIVIDER_READ_ONLY BIT(5)
464 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
465 #define CLK_DIVIDER_BIG_ENDIAN BIT(7)
467 extern const struct clk_ops clk_divider_ops;
468 extern const struct clk_ops clk_divider_ro_ops;
470 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
471 unsigned int val, const struct clk_div_table *table,
472 unsigned long flags, unsigned long width);
473 long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
474 unsigned long rate, unsigned long *prate,
475 const struct clk_div_table *table,
476 u8 width, unsigned long flags);
477 long divider_ro_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
478 unsigned long rate, unsigned long *prate,
479 const struct clk_div_table *table, u8 width,
480 unsigned long flags, unsigned int val);
481 int divider_get_val(unsigned long rate, unsigned long parent_rate,
482 const struct clk_div_table *table, u8 width,
483 unsigned long flags);
485 struct clk *clk_register_divider(struct device *dev, const char *name,
486 const char *parent_name, unsigned long flags,
487 void __iomem *reg, u8 shift, u8 width,
488 u8 clk_divider_flags, spinlock_t *lock);
489 struct clk_hw *clk_hw_register_divider(struct device *dev, const char *name,
490 const char *parent_name, unsigned long flags,
491 void __iomem *reg, u8 shift, u8 width,
492 u8 clk_divider_flags, spinlock_t *lock);
493 struct clk *clk_register_divider_table(struct device *dev, const char *name,
494 const char *parent_name, unsigned long flags,
495 void __iomem *reg, u8 shift, u8 width,
496 u8 clk_divider_flags, const struct clk_div_table *table,
498 struct clk_hw *clk_hw_register_divider_table(struct device *dev,
499 const char *name, const char *parent_name, unsigned long flags,
500 void __iomem *reg, u8 shift, u8 width,
501 u8 clk_divider_flags, const struct clk_div_table *table,
503 void clk_unregister_divider(struct clk *clk);
504 void clk_hw_unregister_divider(struct clk_hw *hw);
507 * struct clk_mux - multiplexer clock
509 * @hw: handle between common and hardware-specific interfaces
510 * @reg: register controlling multiplexer
511 * @table: array of register values corresponding to the parent index
512 * @shift: shift to multiplexer bit field
513 * @mask: mask of mutliplexer bit field
514 * @flags: hardware-specific flags
515 * @lock: register lock
517 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
521 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
522 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
523 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
524 * register, and mask of mux bits are in higher 16-bit of this register.
525 * While setting the mux bits, higher 16-bit should also be updated to
526 * indicate changing mux bits.
527 * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
528 * .get_parent clk_op.
529 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
531 * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
532 * the mux register. Setting this flag makes the register accesses big
545 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
547 #define CLK_MUX_INDEX_ONE BIT(0)
548 #define CLK_MUX_INDEX_BIT BIT(1)
549 #define CLK_MUX_HIWORD_MASK BIT(2)
550 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
551 #define CLK_MUX_ROUND_CLOSEST BIT(4)
552 #define CLK_MUX_BIG_ENDIAN BIT(5)
554 extern const struct clk_ops clk_mux_ops;
555 extern const struct clk_ops clk_mux_ro_ops;
557 struct clk *clk_register_mux(struct device *dev, const char *name,
558 const char * const *parent_names, u8 num_parents,
560 void __iomem *reg, u8 shift, u8 width,
561 u8 clk_mux_flags, spinlock_t *lock);
562 struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
563 const char * const *parent_names, u8 num_parents,
565 void __iomem *reg, u8 shift, u8 width,
566 u8 clk_mux_flags, spinlock_t *lock);
568 struct clk *clk_register_mux_table(struct device *dev, const char *name,
569 const char * const *parent_names, u8 num_parents,
571 void __iomem *reg, u8 shift, u32 mask,
572 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
573 struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
574 const char * const *parent_names, u8 num_parents,
576 void __iomem *reg, u8 shift, u32 mask,
577 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
579 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
581 unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index);
583 void clk_unregister_mux(struct clk *clk);
584 void clk_hw_unregister_mux(struct clk_hw *hw);
586 void of_fixed_factor_clk_setup(struct device_node *node);
589 * struct clk_fixed_factor - fixed multiplier and divider clock
591 * @hw: handle between common and hardware-specific interfaces
595 * Clock with a fixed multiplier and divider. The output frequency is the
596 * parent clock rate divided by div and multiplied by mult.
597 * Implements .recalc_rate, .set_rate and .round_rate
600 struct clk_fixed_factor {
606 #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
608 extern const struct clk_ops clk_fixed_factor_ops;
609 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
610 const char *parent_name, unsigned long flags,
611 unsigned int mult, unsigned int div);
612 void clk_unregister_fixed_factor(struct clk *clk);
613 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
614 const char *name, const char *parent_name, unsigned long flags,
615 unsigned int mult, unsigned int div);
616 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
619 * struct clk_fractional_divider - adjustable fractional divider clock
621 * @hw: handle between common and hardware-specific interfaces
622 * @reg: register containing the divider
623 * @mshift: shift to the numerator bit field
624 * @mwidth: width of the numerator bit field
625 * @nshift: shift to the denominator bit field
626 * @nwidth: width of the denominator bit field
627 * @lock: register lock
629 * Clock with adjustable fractional divider affecting its output frequency.
632 * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
633 * is the value read from the register. If CLK_FRAC_DIVIDER_ZERO_BASED
634 * is set then the numerator and denominator are both the value read
636 * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
637 * used for the divider register. Setting this flag makes the register
638 * accesses big endian.
640 struct clk_fractional_divider {
650 void (*approximation)(struct clk_hw *hw,
651 unsigned long rate, unsigned long *parent_rate,
652 unsigned long *m, unsigned long *n);
656 #define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
658 #define CLK_FRAC_DIVIDER_ZERO_BASED BIT(0)
659 #define CLK_FRAC_DIVIDER_BIG_ENDIAN BIT(1)
661 extern const struct clk_ops clk_fractional_divider_ops;
662 struct clk *clk_register_fractional_divider(struct device *dev,
663 const char *name, const char *parent_name, unsigned long flags,
664 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
665 u8 clk_divider_flags, spinlock_t *lock);
666 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
667 const char *name, const char *parent_name, unsigned long flags,
668 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
669 u8 clk_divider_flags, spinlock_t *lock);
670 void clk_hw_unregister_fractional_divider(struct clk_hw *hw);
673 * struct clk_multiplier - adjustable multiplier clock
675 * @hw: handle between common and hardware-specific interfaces
676 * @reg: register containing the multiplier
677 * @shift: shift to the multiplier bit field
678 * @width: width of the multiplier bit field
679 * @lock: register lock
681 * Clock with an adjustable multiplier affecting its output frequency.
682 * Implements .recalc_rate, .set_rate and .round_rate
685 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
686 * from the register, with 0 being a valid value effectively
687 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
688 * set, then a null multiplier will be considered as a bypass,
689 * leaving the parent rate unmodified.
690 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
691 * rounded to the closest integer instead of the down one.
692 * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
693 * used for the multiplier register. Setting this flag makes the register
694 * accesses big endian.
696 struct clk_multiplier {
705 #define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
707 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
708 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
709 #define CLK_MULTIPLIER_BIG_ENDIAN BIT(2)
711 extern const struct clk_ops clk_multiplier_ops;
714 * struct clk_composite - aggregate clock of mux, divider and gate clocks
716 * @hw: handle between common and hardware-specific interfaces
717 * @mux_hw: handle between composite and hardware-specific mux clock
718 * @rate_hw: handle between composite and hardware-specific rate clock
719 * @gate_hw: handle between composite and hardware-specific gate clock
720 * @mux_ops: clock ops for mux
721 * @rate_ops: clock ops for rate
722 * @gate_ops: clock ops for gate
724 struct clk_composite {
728 struct clk_hw *mux_hw;
729 struct clk_hw *rate_hw;
730 struct clk_hw *gate_hw;
732 const struct clk_ops *mux_ops;
733 const struct clk_ops *rate_ops;
734 const struct clk_ops *gate_ops;
737 #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
739 struct clk *clk_register_composite(struct device *dev, const char *name,
740 const char * const *parent_names, int num_parents,
741 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
742 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
743 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
744 unsigned long flags);
745 void clk_unregister_composite(struct clk *clk);
746 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
747 const char * const *parent_names, int num_parents,
748 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
749 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
750 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
751 unsigned long flags);
752 void clk_hw_unregister_composite(struct clk_hw *hw);
755 * struct clk_gpio - gpio gated clock
757 * @hw: handle between common and hardware-specific interfaces
758 * @gpiod: gpio descriptor
760 * Clock with a gpio control for enabling and disabling the parent clock
761 * or switching between two parents by asserting or deasserting the gpio.
763 * Implements .enable, .disable and .is_enabled or
764 * .get_parent, .set_parent and .determine_rate depending on which clk_ops
769 struct gpio_desc *gpiod;
772 #define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
774 extern const struct clk_ops clk_gpio_gate_ops;
775 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
776 const char *parent_name, struct gpio_desc *gpiod,
777 unsigned long flags);
778 struct clk_hw *clk_hw_register_gpio_gate(struct device *dev, const char *name,
779 const char *parent_name, struct gpio_desc *gpiod,
780 unsigned long flags);
781 void clk_hw_unregister_gpio_gate(struct clk_hw *hw);
783 extern const struct clk_ops clk_gpio_mux_ops;
784 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
785 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
786 unsigned long flags);
787 struct clk_hw *clk_hw_register_gpio_mux(struct device *dev, const char *name,
788 const char * const *parent_names, u8 num_parents, struct gpio_desc *gpiod,
789 unsigned long flags);
790 void clk_hw_unregister_gpio_mux(struct clk_hw *hw);
792 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
793 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
795 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
796 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
797 int __must_check of_clk_hw_register(struct device_node *node, struct clk_hw *hw);
799 void clk_unregister(struct clk *clk);
800 void devm_clk_unregister(struct device *dev, struct clk *clk);
802 void clk_hw_unregister(struct clk_hw *hw);
803 void devm_clk_hw_unregister(struct device *dev, struct clk_hw *hw);
805 /* helper functions */
806 const char *__clk_get_name(const struct clk *clk);
807 const char *clk_hw_get_name(const struct clk_hw *hw);
808 #ifdef CONFIG_COMMON_CLK
809 struct clk_hw *__clk_get_hw(struct clk *clk);
811 static inline struct clk_hw *__clk_get_hw(struct clk *clk)
813 return (struct clk_hw *)clk;
816 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
817 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
818 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
820 unsigned int __clk_get_enable_count(struct clk *clk);
821 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
822 unsigned long __clk_get_flags(struct clk *clk);
823 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
824 #define clk_hw_can_set_rate_parent(hw) \
825 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
827 bool clk_hw_is_prepared(const struct clk_hw *hw);
828 bool clk_hw_rate_is_protected(const struct clk_hw *hw);
829 bool clk_hw_is_enabled(const struct clk_hw *hw);
830 bool __clk_is_enabled(struct clk *clk);
831 struct clk *__clk_lookup(const char *name);
832 int __clk_mux_determine_rate(struct clk_hw *hw,
833 struct clk_rate_request *req);
834 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
835 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
836 struct clk_rate_request *req);
837 int clk_mux_determine_rate_flags(struct clk_hw *hw,
838 struct clk_rate_request *req,
839 unsigned long flags);
840 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
841 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
842 unsigned long max_rate);
844 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
847 dst->core = src->core;
850 static inline long divider_round_rate(struct clk_hw *hw, unsigned long rate,
851 unsigned long *prate,
852 const struct clk_div_table *table,
853 u8 width, unsigned long flags)
855 return divider_round_rate_parent(hw, clk_hw_get_parent(hw),
856 rate, prate, table, width, flags);
859 static inline long divider_ro_round_rate(struct clk_hw *hw, unsigned long rate,
860 unsigned long *prate,
861 const struct clk_div_table *table,
862 u8 width, unsigned long flags,
865 return divider_ro_round_rate_parent(hw, clk_hw_get_parent(hw),
866 rate, prate, table, width, flags,
871 * FIXME clock api without lock protection
873 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
875 struct clk_onecell_data {
877 unsigned int clk_num;
880 struct clk_hw_onecell_data {
882 struct clk_hw *hws[];
885 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
888 * Use this macro when you have a driver that requires two initialization
889 * routines, one at of_clk_init(), and one at platform device probe
891 #define CLK_OF_DECLARE_DRIVER(name, compat, fn) \
892 static void __init name##_of_clk_init_driver(struct device_node *np) \
894 of_node_clear_flag(np, OF_POPULATED); \
897 OF_DECLARE_1(clk, name, compat, name##_of_clk_init_driver)
899 #define CLK_HW_INIT(_name, _parent, _ops, _flags) \
900 (&(struct clk_init_data) { \
903 .parent_names = (const char *[]) { _parent }, \
908 #define CLK_HW_INIT_HW(_name, _parent, _ops, _flags) \
909 (&(struct clk_init_data) { \
912 .parent_hws = (const struct clk_hw*[]) { _parent }, \
918 * This macro is intended for drivers to be able to share the otherwise
919 * individual struct clk_hw[] compound literals created by the compiler
920 * when using CLK_HW_INIT_HW. It does NOT support multiple parents.
922 #define CLK_HW_INIT_HWS(_name, _parent, _ops, _flags) \
923 (&(struct clk_init_data) { \
926 .parent_hws = _parent, \
931 #define CLK_HW_INIT_FW_NAME(_name, _parent, _ops, _flags) \
932 (&(struct clk_init_data) { \
935 .parent_data = (const struct clk_parent_data[]) { \
936 { .fw_name = _parent }, \
942 #define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
943 (&(struct clk_init_data) { \
946 .parent_names = _parents, \
947 .num_parents = ARRAY_SIZE(_parents), \
951 #define CLK_HW_INIT_PARENTS_HW(_name, _parents, _ops, _flags) \
952 (&(struct clk_init_data) { \
955 .parent_hws = _parents, \
956 .num_parents = ARRAY_SIZE(_parents), \
960 #define CLK_HW_INIT_PARENTS_DATA(_name, _parents, _ops, _flags) \
961 (&(struct clk_init_data) { \
964 .parent_data = _parents, \
965 .num_parents = ARRAY_SIZE(_parents), \
969 #define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
970 (&(struct clk_init_data) { \
973 .parent_names = NULL, \
978 #define CLK_FIXED_FACTOR(_struct, _name, _parent, \
979 _div, _mult, _flags) \
980 struct clk_fixed_factor _struct = { \
983 .hw.init = CLK_HW_INIT(_name, \
985 &clk_fixed_factor_ops, \
989 #define CLK_FIXED_FACTOR_HW(_struct, _name, _parent, \
990 _div, _mult, _flags) \
991 struct clk_fixed_factor _struct = { \
994 .hw.init = CLK_HW_INIT_HW(_name, \
996 &clk_fixed_factor_ops, \
1001 * This macro allows the driver to reuse the _parent array for multiple
1002 * fixed factor clk declarations.
1004 #define CLK_FIXED_FACTOR_HWS(_struct, _name, _parent, \
1005 _div, _mult, _flags) \
1006 struct clk_fixed_factor _struct = { \
1009 .hw.init = CLK_HW_INIT_HWS(_name, \
1011 &clk_fixed_factor_ops, \
1015 #define CLK_FIXED_FACTOR_FW_NAME(_struct, _name, _parent, \
1016 _div, _mult, _flags) \
1017 struct clk_fixed_factor _struct = { \
1020 .hw.init = CLK_HW_INIT_FW_NAME(_name, \
1022 &clk_fixed_factor_ops, \
1027 int of_clk_add_provider(struct device_node *np,
1028 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1031 int of_clk_add_hw_provider(struct device_node *np,
1032 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1035 int devm_of_clk_add_hw_provider(struct device *dev,
1036 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1039 void of_clk_del_provider(struct device_node *np);
1040 void devm_of_clk_del_provider(struct device *dev);
1041 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
1043 struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec,
1045 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
1046 struct clk_hw *of_clk_hw_onecell_get(struct of_phandle_args *clkspec,
1048 int of_clk_parent_fill(struct device_node *np, const char **parents,
1050 int of_clk_detect_critical(struct device_node *np, int index,
1051 unsigned long *flags);
1053 #else /* !CONFIG_OF */
1055 static inline int of_clk_add_provider(struct device_node *np,
1056 struct clk *(*clk_src_get)(struct of_phandle_args *args,
1062 static inline int of_clk_add_hw_provider(struct device_node *np,
1063 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1069 static inline int devm_of_clk_add_hw_provider(struct device *dev,
1070 struct clk_hw *(*get)(struct of_phandle_args *clkspec,
1076 static inline void of_clk_del_provider(struct device_node *np) {}
1077 static inline void devm_of_clk_del_provider(struct device *dev) {}
1078 static inline struct clk *of_clk_src_simple_get(
1079 struct of_phandle_args *clkspec, void *data)
1081 return ERR_PTR(-ENOENT);
1083 static inline struct clk_hw *
1084 of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
1086 return ERR_PTR(-ENOENT);
1088 static inline struct clk *of_clk_src_onecell_get(
1089 struct of_phandle_args *clkspec, void *data)
1091 return ERR_PTR(-ENOENT);
1093 static inline struct clk_hw *
1094 of_clk_hw_onecell_get(struct of_phandle_args *clkspec, void *data)
1096 return ERR_PTR(-ENOENT);
1098 static inline int of_clk_parent_fill(struct device_node *np,
1099 const char **parents, unsigned int size)
1103 static inline int of_clk_detect_critical(struct device_node *np, int index,
1104 unsigned long *flags)
1108 #endif /* CONFIG_OF */
1110 void clk_gate_restore_context(struct clk_hw *hw);
1112 #endif /* CLK_PROVIDER_H */