2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
244 struct mlx5_ifc_flow_table_fields_supported_bits {
247 u8 outer_ether_type[0x1];
248 u8 outer_ip_version[0x1];
249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
252 u8 outer_ipv4_ttl[0x1];
253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
256 u8 reserved_at_b[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
271 u8 reserved_at_1a[0x5];
272 u8 source_eswitch_port[0x1];
276 u8 inner_ether_type[0x1];
277 u8 inner_ip_version[0x1];
278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
281 u8 reserved_at_27[0x1];
282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
285 u8 reserved_at_2b[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
297 u8 reserved_at_37[0x9];
298 u8 reserved_at_40[0x1a];
301 u8 reserved_at_5b[0x25];
304 struct mlx5_ifc_flow_table_prop_layout_bits {
306 u8 reserved_at_1[0x1];
307 u8 flow_counter[0x1];
308 u8 flow_modify_en[0x1];
310 u8 identified_miss_table_mode[0x1];
311 u8 flow_table_modify[0x1];
314 u8 reserved_at_9[0x17];
316 u8 reserved_at_20[0x2];
317 u8 log_max_ft_size[0x6];
318 u8 log_max_modify_header_context[0x8];
319 u8 max_modify_header_actions[0x8];
320 u8 max_ft_level[0x8];
322 u8 reserved_at_40[0x20];
324 u8 reserved_at_60[0x18];
325 u8 log_max_ft_num[0x8];
327 u8 reserved_at_80[0x18];
328 u8 log_max_destination[0x8];
330 u8 log_max_flow_counter[0x8];
331 u8 reserved_at_a8[0x10];
332 u8 log_max_flow[0x8];
334 u8 reserved_at_c0[0x40];
336 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
341 struct mlx5_ifc_odp_per_transport_service_cap_bits {
348 u8 reserved_at_6[0x1a];
351 struct mlx5_ifc_ipv4_layout_bits {
352 u8 reserved_at_0[0x60];
357 struct mlx5_ifc_ipv6_layout_bits {
361 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
362 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
363 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
364 u8 reserved_at_0[0x80];
367 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
392 u8 reserved_at_c0[0x18];
393 u8 ttl_hoplimit[0x8];
398 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
403 struct mlx5_ifc_fte_match_set_misc_bits {
404 u8 reserved_at_0[0x8];
407 u8 reserved_at_20[0x10];
408 u8 source_port[0x10];
410 u8 outer_second_prio[0x3];
411 u8 outer_second_cfi[0x1];
412 u8 outer_second_vid[0xc];
413 u8 inner_second_prio[0x3];
414 u8 inner_second_cfi[0x1];
415 u8 inner_second_vid[0xc];
417 u8 outer_second_cvlan_tag[0x1];
418 u8 inner_second_cvlan_tag[0x1];
419 u8 outer_second_svlan_tag[0x1];
420 u8 inner_second_svlan_tag[0x1];
421 u8 reserved_at_64[0xc];
422 u8 gre_protocol[0x10];
428 u8 reserved_at_b8[0x8];
430 u8 reserved_at_c0[0x20];
432 u8 reserved_at_e0[0xc];
433 u8 outer_ipv6_flow_label[0x14];
435 u8 reserved_at_100[0xc];
436 u8 inner_ipv6_flow_label[0x14];
438 u8 reserved_at_120[0x28];
440 u8 reserved_at_160[0xa0];
443 struct mlx5_ifc_cmd_pas_bits {
447 u8 reserved_at_34[0xc];
450 struct mlx5_ifc_uint64_bits {
457 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
458 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
459 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
460 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
461 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
462 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
463 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
464 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
465 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
466 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
469 struct mlx5_ifc_ads_bits {
472 u8 reserved_at_2[0xe];
475 u8 reserved_at_20[0x8];
481 u8 reserved_at_45[0x3];
482 u8 src_addr_index[0x8];
483 u8 reserved_at_50[0x4];
487 u8 reserved_at_60[0x4];
491 u8 rgid_rip[16][0x8];
493 u8 reserved_at_100[0x4];
496 u8 reserved_at_106[0x1];
511 struct mlx5_ifc_flow_table_nic_cap_bits {
512 u8 nic_rx_multi_path_tirs[0x1];
513 u8 nic_rx_multi_path_tirs_fts[0x1];
514 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
515 u8 reserved_at_3[0x1fd];
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
519 u8 reserved_at_400[0x200];
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
525 u8 reserved_at_a00[0x200];
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
529 u8 reserved_at_e00[0x7200];
532 struct mlx5_ifc_flow_table_eswitch_cap_bits {
533 u8 reserved_at_0[0x200];
535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
541 u8 reserved_at_800[0x7800];
544 struct mlx5_ifc_e_switch_cap_bits {
545 u8 vport_svlan_strip[0x1];
546 u8 vport_cvlan_strip[0x1];
547 u8 vport_svlan_insert[0x1];
548 u8 vport_cvlan_insert_if_not_exist[0x1];
549 u8 vport_cvlan_insert_overwrite[0x1];
550 u8 reserved_at_5[0x19];
551 u8 nic_vport_node_guid_modify[0x1];
552 u8 nic_vport_port_guid_modify[0x1];
554 u8 vxlan_encap_decap[0x1];
555 u8 nvgre_encap_decap[0x1];
556 u8 reserved_at_22[0x9];
557 u8 log_max_encap_headers[0x5];
559 u8 max_encap_header_size[0xa];
561 u8 reserved_40[0x7c0];
565 struct mlx5_ifc_qos_cap_bits {
566 u8 packet_pacing[0x1];
567 u8 esw_scheduling[0x1];
568 u8 esw_bw_share[0x1];
569 u8 esw_rate_limit[0x1];
570 u8 reserved_at_4[0x1c];
572 u8 reserved_at_20[0x20];
574 u8 packet_pacing_max_rate[0x20];
576 u8 packet_pacing_min_rate[0x20];
578 u8 reserved_at_80[0x10];
579 u8 packet_pacing_rate_table_size[0x10];
581 u8 esw_element_type[0x10];
582 u8 esw_tsar_type[0x10];
584 u8 reserved_at_c0[0x10];
585 u8 max_qos_para_vport[0x10];
587 u8 max_tsar_bw_share[0x20];
589 u8 reserved_at_100[0x700];
592 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
596 u8 lro_psh_flag[0x1];
597 u8 lro_time_stamp[0x1];
598 u8 reserved_at_5[0x2];
599 u8 wqe_vlan_insert[0x1];
600 u8 self_lb_en_modifiable[0x1];
601 u8 reserved_at_9[0x2];
603 u8 multi_pkt_send_wqe[0x2];
604 u8 wqe_inline_mode[0x2];
605 u8 rss_ind_tbl_cap[0x4];
608 u8 enhanced_multi_pkt_send_wqe[0x1];
609 u8 tunnel_lso_const_out_ip_id[0x1];
610 u8 reserved_at_1c[0x2];
611 u8 tunnel_stateless_gre[0x1];
612 u8 tunnel_stateless_vxlan[0x1];
617 u8 reserved_at_23[0x1b];
618 u8 max_geneve_opt_len[0x1];
619 u8 tunnel_stateless_geneve_rx[0x1];
621 u8 reserved_at_40[0x10];
622 u8 lro_min_mss_size[0x10];
624 u8 reserved_at_60[0x120];
626 u8 lro_timer_supported_periods[4][0x20];
628 u8 reserved_at_200[0x600];
631 struct mlx5_ifc_roce_cap_bits {
633 u8 reserved_at_1[0x1f];
635 u8 reserved_at_20[0x60];
637 u8 reserved_at_80[0xc];
639 u8 reserved_at_90[0x8];
640 u8 roce_version[0x8];
642 u8 reserved_at_a0[0x10];
643 u8 r_roce_dest_udp_port[0x10];
645 u8 r_roce_max_src_udp_port[0x10];
646 u8 r_roce_min_src_udp_port[0x10];
648 u8 reserved_at_e0[0x10];
649 u8 roce_address_table_size[0x10];
651 u8 reserved_at_100[0x700];
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
662 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
663 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
674 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
675 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
678 struct mlx5_ifc_atomic_caps_bits {
679 u8 reserved_at_0[0x40];
681 u8 atomic_req_8B_endianness_mode[0x2];
682 u8 reserved_at_42[0x4];
683 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
685 u8 reserved_at_47[0x19];
687 u8 reserved_at_60[0x20];
689 u8 reserved_at_80[0x10];
690 u8 atomic_operations[0x10];
692 u8 reserved_at_a0[0x10];
693 u8 atomic_size_qp[0x10];
695 u8 reserved_at_c0[0x10];
696 u8 atomic_size_dc[0x10];
698 u8 reserved_at_e0[0x720];
701 struct mlx5_ifc_odp_cap_bits {
702 u8 reserved_at_0[0x40];
705 u8 reserved_at_41[0x1f];
707 u8 reserved_at_60[0x20];
709 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
711 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
713 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
715 u8 reserved_at_e0[0x720];
718 struct mlx5_ifc_calc_op {
719 u8 reserved_at_0[0x10];
720 u8 reserved_at_10[0x9];
721 u8 op_swap_endianness[0x1];
730 struct mlx5_ifc_vector_calc_cap_bits {
732 u8 reserved_at_1[0x1f];
733 u8 reserved_at_20[0x8];
734 u8 max_vec_count[0x8];
735 u8 reserved_at_30[0xd];
736 u8 max_chunk_size[0x3];
737 struct mlx5_ifc_calc_op calc0;
738 struct mlx5_ifc_calc_op calc1;
739 struct mlx5_ifc_calc_op calc2;
740 struct mlx5_ifc_calc_op calc3;
742 u8 reserved_at_e0[0x720];
746 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
747 MLX5_WQ_TYPE_CYCLIC = 0x1,
748 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
749 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
753 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
754 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
758 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
759 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
760 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
761 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
762 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
766 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
768 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
769 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
770 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
771 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
775 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
776 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
780 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
781 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
782 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
786 MLX5_CAP_PORT_TYPE_IB = 0x0,
787 MLX5_CAP_PORT_TYPE_ETH = 0x1,
791 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
792 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
793 MLX5_CAP_UMR_FENCE_NONE = 0x2,
796 struct mlx5_ifc_cmd_hca_cap_bits {
797 u8 reserved_at_0[0x80];
799 u8 log_max_srq_sz[0x8];
800 u8 log_max_qp_sz[0x8];
801 u8 reserved_at_90[0xb];
804 u8 reserved_at_a0[0xb];
806 u8 reserved_at_b0[0x10];
808 u8 reserved_at_c0[0x8];
809 u8 log_max_cq_sz[0x8];
810 u8 reserved_at_d0[0xb];
813 u8 log_max_eq_sz[0x8];
814 u8 reserved_at_e8[0x2];
815 u8 log_max_mkey[0x6];
816 u8 reserved_at_f0[0xc];
819 u8 max_indirection[0x8];
820 u8 fixed_buffer_size[0x1];
821 u8 log_max_mrw_sz[0x7];
822 u8 force_teardown[0x1];
823 u8 reserved_at_111[0x1];
824 u8 log_max_bsf_list_size[0x6];
825 u8 umr_extended_translation_offset[0x1];
827 u8 log_max_klm_list_size[0x6];
829 u8 reserved_at_120[0xa];
830 u8 log_max_ra_req_dc[0x6];
831 u8 reserved_at_130[0xa];
832 u8 log_max_ra_res_dc[0x6];
834 u8 reserved_at_140[0xa];
835 u8 log_max_ra_req_qp[0x6];
836 u8 reserved_at_150[0xa];
837 u8 log_max_ra_res_qp[0x6];
840 u8 cc_query_allowed[0x1];
841 u8 cc_modify_allowed[0x1];
843 u8 cache_line_128byte[0x1];
844 u8 reserved_at_165[0xa];
846 u8 gid_table_size[0x10];
848 u8 out_of_seq_cnt[0x1];
849 u8 vport_counters[0x1];
850 u8 retransmission_q_counters[0x1];
851 u8 reserved_at_183[0x1];
852 u8 modify_rq_counter_set_id[0x1];
853 u8 rq_delay_drop[0x1];
855 u8 pkey_table_size[0x10];
857 u8 vport_group_manager[0x1];
858 u8 vhca_group_manager[0x1];
861 u8 reserved_at_1a4[0x1];
863 u8 nic_flow_table[0x1];
864 u8 eswitch_flow_table[0x1];
865 u8 early_vf_enable[0x1];
868 u8 local_ca_ack_delay[0x5];
869 u8 port_module_event[0x1];
870 u8 enhanced_error_q_counters[0x1];
872 u8 reserved_at_1b3[0x1];
873 u8 disable_link_up[0x1];
878 u8 reserved_at_1c0[0x1];
882 u8 reserved_at_1c8[0x4];
884 u8 reserved_at_1d0[0x1];
886 u8 general_notification_event[0x1];
887 u8 reserved_at_1d3[0x2];
891 u8 reserved_at_1d8[0x1];
900 u8 stat_rate_support[0x10];
901 u8 reserved_at_1f0[0xc];
904 u8 compact_address_vector[0x1];
906 u8 reserved_at_202[0x1];
907 u8 ipoib_enhanced_offloads[0x1];
908 u8 ipoib_basic_offloads[0x1];
909 u8 reserved_at_205[0x5];
911 u8 reserved_at_20c[0x3];
912 u8 drain_sigerr[0x1];
913 u8 cmdif_checksum[0x2];
915 u8 reserved_at_213[0x1];
916 u8 wq_signature[0x1];
917 u8 sctr_data_cqe[0x1];
918 u8 reserved_at_216[0x1];
924 u8 eth_net_offloads[0x1];
927 u8 reserved_at_21f[0x1];
931 u8 cq_moderation[0x1];
932 u8 reserved_at_223[0x3];
936 u8 reserved_at_229[0x1];
937 u8 scqe_break_moderation[0x1];
938 u8 cq_period_start_from_cqe[0x1];
940 u8 reserved_at_22d[0x1];
943 u8 umr_ptr_rlky[0x1];
945 u8 reserved_at_232[0x4];
948 u8 set_deth_sqpn[0x1];
949 u8 reserved_at_239[0x3];
956 u8 reserved_at_241[0x9];
958 u8 reserved_at_250[0x8];
962 u8 driver_version[0x1];
963 u8 pad_tx_eth_packet[0x1];
964 u8 reserved_at_263[0x8];
965 u8 log_bf_reg_size[0x5];
967 u8 reserved_at_270[0xb];
969 u8 num_lag_ports[0x4];
971 u8 reserved_at_280[0x10];
972 u8 max_wqe_sz_sq[0x10];
974 u8 reserved_at_2a0[0x10];
975 u8 max_wqe_sz_rq[0x10];
977 u8 max_flow_counter_31_16[0x10];
978 u8 max_wqe_sz_sq_dc[0x10];
980 u8 reserved_at_2e0[0x7];
983 u8 reserved_at_300[0x18];
986 u8 reserved_at_320[0x3];
987 u8 log_max_transport_domain[0x5];
988 u8 reserved_at_328[0x3];
990 u8 reserved_at_330[0xb];
991 u8 log_max_xrcd[0x5];
993 u8 reserved_at_340[0x8];
994 u8 log_max_flow_counter_bulk[0x8];
995 u8 max_flow_counter_15_0[0x10];
998 u8 reserved_at_360[0x3];
1000 u8 reserved_at_368[0x3];
1002 u8 reserved_at_370[0x3];
1003 u8 log_max_tir[0x5];
1004 u8 reserved_at_378[0x3];
1005 u8 log_max_tis[0x5];
1007 u8 basic_cyclic_rcv_wqe[0x1];
1008 u8 reserved_at_381[0x2];
1009 u8 log_max_rmp[0x5];
1010 u8 reserved_at_388[0x3];
1011 u8 log_max_rqt[0x5];
1012 u8 reserved_at_390[0x3];
1013 u8 log_max_rqt_size[0x5];
1014 u8 reserved_at_398[0x3];
1015 u8 log_max_tis_per_sq[0x5];
1017 u8 reserved_at_3a0[0x3];
1018 u8 log_max_stride_sz_rq[0x5];
1019 u8 reserved_at_3a8[0x3];
1020 u8 log_min_stride_sz_rq[0x5];
1021 u8 reserved_at_3b0[0x3];
1022 u8 log_max_stride_sz_sq[0x5];
1023 u8 reserved_at_3b8[0x3];
1024 u8 log_min_stride_sz_sq[0x5];
1026 u8 reserved_at_3c0[0x1b];
1027 u8 log_max_wq_sz[0x5];
1029 u8 nic_vport_change_event[0x1];
1030 u8 disable_local_lb[0x1];
1031 u8 reserved_at_3e2[0x9];
1032 u8 log_max_vlan_list[0x5];
1033 u8 reserved_at_3f0[0x3];
1034 u8 log_max_current_mc_list[0x5];
1035 u8 reserved_at_3f8[0x3];
1036 u8 log_max_current_uc_list[0x5];
1038 u8 reserved_at_400[0x80];
1040 u8 reserved_at_480[0x3];
1041 u8 log_max_l2_table[0x5];
1042 u8 reserved_at_488[0x8];
1043 u8 log_uar_page_sz[0x10];
1045 u8 reserved_at_4a0[0x20];
1046 u8 device_frequency_mhz[0x20];
1047 u8 device_frequency_khz[0x20];
1049 u8 reserved_at_500[0x20];
1050 u8 num_of_uars_per_page[0x20];
1051 u8 reserved_at_540[0x40];
1053 u8 reserved_at_580[0x3d];
1054 u8 cqe_128_always[0x1];
1055 u8 cqe_compression_128[0x1];
1056 u8 cqe_compression[0x1];
1058 u8 cqe_compression_timeout[0x10];
1059 u8 cqe_compression_max_num[0x10];
1061 u8 reserved_at_5e0[0x10];
1062 u8 tag_matching[0x1];
1063 u8 rndv_offload_rc[0x1];
1064 u8 rndv_offload_dc[0x1];
1065 u8 log_tag_matching_list_sz[0x5];
1066 u8 reserved_at_5f8[0x3];
1067 u8 log_max_xrq[0x5];
1069 u8 reserved_at_600[0x200];
1072 enum mlx5_flow_destination_type {
1073 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1074 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1075 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1077 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1080 struct mlx5_ifc_dest_format_struct_bits {
1081 u8 destination_type[0x8];
1082 u8 destination_id[0x18];
1084 u8 reserved_at_20[0x20];
1087 struct mlx5_ifc_flow_counter_list_bits {
1088 u8 flow_counter_id[0x20];
1090 u8 reserved_at_20[0x20];
1093 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1094 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1095 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1096 u8 reserved_at_0[0x40];
1099 struct mlx5_ifc_fte_match_param_bits {
1100 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1102 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1104 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1106 u8 reserved_at_600[0xa00];
1110 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1111 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1112 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1113 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1114 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1117 struct mlx5_ifc_rx_hash_field_select_bits {
1118 u8 l3_prot_type[0x1];
1119 u8 l4_prot_type[0x1];
1120 u8 selected_fields[0x1e];
1124 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1125 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1129 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1130 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1133 struct mlx5_ifc_wq_bits {
1135 u8 wq_signature[0x1];
1136 u8 end_padding_mode[0x2];
1138 u8 reserved_at_8[0x18];
1140 u8 hds_skip_first_sge[0x1];
1141 u8 log2_hds_buf_size[0x3];
1142 u8 reserved_at_24[0x7];
1143 u8 page_offset[0x5];
1146 u8 reserved_at_40[0x8];
1149 u8 reserved_at_60[0x8];
1154 u8 hw_counter[0x20];
1156 u8 sw_counter[0x20];
1158 u8 reserved_at_100[0xc];
1159 u8 log_wq_stride[0x4];
1160 u8 reserved_at_110[0x3];
1161 u8 log_wq_pg_sz[0x5];
1162 u8 reserved_at_118[0x3];
1165 u8 reserved_at_120[0x15];
1166 u8 log_wqe_num_of_strides[0x3];
1167 u8 two_byte_shift_en[0x1];
1168 u8 reserved_at_139[0x4];
1169 u8 log_wqe_stride_size[0x3];
1171 u8 reserved_at_140[0x4c0];
1173 struct mlx5_ifc_cmd_pas_bits pas[0];
1176 struct mlx5_ifc_rq_num_bits {
1177 u8 reserved_at_0[0x8];
1181 struct mlx5_ifc_mac_address_layout_bits {
1182 u8 reserved_at_0[0x10];
1183 u8 mac_addr_47_32[0x10];
1185 u8 mac_addr_31_0[0x20];
1188 struct mlx5_ifc_vlan_layout_bits {
1189 u8 reserved_at_0[0x14];
1192 u8 reserved_at_20[0x20];
1195 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1196 u8 reserved_at_0[0xa0];
1198 u8 min_time_between_cnps[0x20];
1200 u8 reserved_at_c0[0x12];
1202 u8 reserved_at_d8[0x4];
1203 u8 cnp_prio_mode[0x1];
1204 u8 cnp_802p_prio[0x3];
1206 u8 reserved_at_e0[0x720];
1209 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1210 u8 reserved_at_0[0x60];
1212 u8 reserved_at_60[0x4];
1213 u8 clamp_tgt_rate[0x1];
1214 u8 reserved_at_65[0x3];
1215 u8 clamp_tgt_rate_after_time_inc[0x1];
1216 u8 reserved_at_69[0x17];
1218 u8 reserved_at_80[0x20];
1220 u8 rpg_time_reset[0x20];
1222 u8 rpg_byte_reset[0x20];
1224 u8 rpg_threshold[0x20];
1226 u8 rpg_max_rate[0x20];
1228 u8 rpg_ai_rate[0x20];
1230 u8 rpg_hai_rate[0x20];
1234 u8 rpg_min_dec_fac[0x20];
1236 u8 rpg_min_rate[0x20];
1238 u8 reserved_at_1c0[0xe0];
1240 u8 rate_to_set_on_first_cnp[0x20];
1244 u8 dce_tcp_rtt[0x20];
1246 u8 rate_reduce_monitor_period[0x20];
1248 u8 reserved_at_320[0x20];
1250 u8 initial_alpha_value[0x20];
1252 u8 reserved_at_360[0x4a0];
1255 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1256 u8 reserved_at_0[0x80];
1258 u8 rppp_max_rps[0x20];
1260 u8 rpg_time_reset[0x20];
1262 u8 rpg_byte_reset[0x20];
1264 u8 rpg_threshold[0x20];
1266 u8 rpg_max_rate[0x20];
1268 u8 rpg_ai_rate[0x20];
1270 u8 rpg_hai_rate[0x20];
1274 u8 rpg_min_dec_fac[0x20];
1276 u8 rpg_min_rate[0x20];
1278 u8 reserved_at_1c0[0x640];
1282 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1283 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1284 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1287 struct mlx5_ifc_resize_field_select_bits {
1288 u8 resize_field_select[0x20];
1292 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1293 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1294 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1295 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1298 struct mlx5_ifc_modify_field_select_bits {
1299 u8 modify_field_select[0x20];
1302 struct mlx5_ifc_field_select_r_roce_np_bits {
1303 u8 field_select_r_roce_np[0x20];
1306 struct mlx5_ifc_field_select_r_roce_rp_bits {
1307 u8 field_select_r_roce_rp[0x20];
1311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1323 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1324 u8 field_select_8021qaurp[0x20];
1327 struct mlx5_ifc_phys_layer_cntrs_bits {
1328 u8 time_since_last_clear_high[0x20];
1330 u8 time_since_last_clear_low[0x20];
1332 u8 symbol_errors_high[0x20];
1334 u8 symbol_errors_low[0x20];
1336 u8 sync_headers_errors_high[0x20];
1338 u8 sync_headers_errors_low[0x20];
1340 u8 edpl_bip_errors_lane0_high[0x20];
1342 u8 edpl_bip_errors_lane0_low[0x20];
1344 u8 edpl_bip_errors_lane1_high[0x20];
1346 u8 edpl_bip_errors_lane1_low[0x20];
1348 u8 edpl_bip_errors_lane2_high[0x20];
1350 u8 edpl_bip_errors_lane2_low[0x20];
1352 u8 edpl_bip_errors_lane3_high[0x20];
1354 u8 edpl_bip_errors_lane3_low[0x20];
1356 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1358 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1360 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1362 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1364 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1366 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1368 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1370 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1372 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1374 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1376 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1378 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1380 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1382 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1384 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1386 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1388 u8 rs_fec_corrected_blocks_high[0x20];
1390 u8 rs_fec_corrected_blocks_low[0x20];
1392 u8 rs_fec_uncorrectable_blocks_high[0x20];
1394 u8 rs_fec_uncorrectable_blocks_low[0x20];
1396 u8 rs_fec_no_errors_blocks_high[0x20];
1398 u8 rs_fec_no_errors_blocks_low[0x20];
1400 u8 rs_fec_single_error_blocks_high[0x20];
1402 u8 rs_fec_single_error_blocks_low[0x20];
1404 u8 rs_fec_corrected_symbols_total_high[0x20];
1406 u8 rs_fec_corrected_symbols_total_low[0x20];
1408 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1410 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1412 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1414 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1416 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1418 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1420 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1422 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1424 u8 link_down_events[0x20];
1426 u8 successful_recovery_events[0x20];
1428 u8 reserved_at_640[0x180];
1431 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1432 u8 time_since_last_clear_high[0x20];
1434 u8 time_since_last_clear_low[0x20];
1436 u8 phy_received_bits_high[0x20];
1438 u8 phy_received_bits_low[0x20];
1440 u8 phy_symbol_errors_high[0x20];
1442 u8 phy_symbol_errors_low[0x20];
1444 u8 phy_corrected_bits_high[0x20];
1446 u8 phy_corrected_bits_low[0x20];
1448 u8 phy_corrected_bits_lane0_high[0x20];
1450 u8 phy_corrected_bits_lane0_low[0x20];
1452 u8 phy_corrected_bits_lane1_high[0x20];
1454 u8 phy_corrected_bits_lane1_low[0x20];
1456 u8 phy_corrected_bits_lane2_high[0x20];
1458 u8 phy_corrected_bits_lane2_low[0x20];
1460 u8 phy_corrected_bits_lane3_high[0x20];
1462 u8 phy_corrected_bits_lane3_low[0x20];
1464 u8 reserved_at_200[0x5c0];
1467 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1468 u8 symbol_error_counter[0x10];
1470 u8 link_error_recovery_counter[0x8];
1472 u8 link_downed_counter[0x8];
1474 u8 port_rcv_errors[0x10];
1476 u8 port_rcv_remote_physical_errors[0x10];
1478 u8 port_rcv_switch_relay_errors[0x10];
1480 u8 port_xmit_discards[0x10];
1482 u8 port_xmit_constraint_errors[0x8];
1484 u8 port_rcv_constraint_errors[0x8];
1486 u8 reserved_at_70[0x8];
1488 u8 link_overrun_errors[0x8];
1490 u8 reserved_at_80[0x10];
1492 u8 vl_15_dropped[0x10];
1494 u8 reserved_at_a0[0x80];
1496 u8 port_xmit_wait[0x20];
1499 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1500 u8 transmit_queue_high[0x20];
1502 u8 transmit_queue_low[0x20];
1504 u8 reserved_at_40[0x780];
1507 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1508 u8 rx_octets_high[0x20];
1510 u8 rx_octets_low[0x20];
1512 u8 reserved_at_40[0xc0];
1514 u8 rx_frames_high[0x20];
1516 u8 rx_frames_low[0x20];
1518 u8 tx_octets_high[0x20];
1520 u8 tx_octets_low[0x20];
1522 u8 reserved_at_180[0xc0];
1524 u8 tx_frames_high[0x20];
1526 u8 tx_frames_low[0x20];
1528 u8 rx_pause_high[0x20];
1530 u8 rx_pause_low[0x20];
1532 u8 rx_pause_duration_high[0x20];
1534 u8 rx_pause_duration_low[0x20];
1536 u8 tx_pause_high[0x20];
1538 u8 tx_pause_low[0x20];
1540 u8 tx_pause_duration_high[0x20];
1542 u8 tx_pause_duration_low[0x20];
1544 u8 rx_pause_transition_high[0x20];
1546 u8 rx_pause_transition_low[0x20];
1548 u8 reserved_at_3c0[0x400];
1551 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1552 u8 port_transmit_wait_high[0x20];
1554 u8 port_transmit_wait_low[0x20];
1556 u8 reserved_at_40[0x100];
1558 u8 rx_buffer_almost_full_high[0x20];
1560 u8 rx_buffer_almost_full_low[0x20];
1562 u8 rx_buffer_full_high[0x20];
1564 u8 rx_buffer_full_low[0x20];
1566 u8 reserved_at_1c0[0x600];
1569 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1570 u8 dot3stats_alignment_errors_high[0x20];
1572 u8 dot3stats_alignment_errors_low[0x20];
1574 u8 dot3stats_fcs_errors_high[0x20];
1576 u8 dot3stats_fcs_errors_low[0x20];
1578 u8 dot3stats_single_collision_frames_high[0x20];
1580 u8 dot3stats_single_collision_frames_low[0x20];
1582 u8 dot3stats_multiple_collision_frames_high[0x20];
1584 u8 dot3stats_multiple_collision_frames_low[0x20];
1586 u8 dot3stats_sqe_test_errors_high[0x20];
1588 u8 dot3stats_sqe_test_errors_low[0x20];
1590 u8 dot3stats_deferred_transmissions_high[0x20];
1592 u8 dot3stats_deferred_transmissions_low[0x20];
1594 u8 dot3stats_late_collisions_high[0x20];
1596 u8 dot3stats_late_collisions_low[0x20];
1598 u8 dot3stats_excessive_collisions_high[0x20];
1600 u8 dot3stats_excessive_collisions_low[0x20];
1602 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1604 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1606 u8 dot3stats_carrier_sense_errors_high[0x20];
1608 u8 dot3stats_carrier_sense_errors_low[0x20];
1610 u8 dot3stats_frame_too_longs_high[0x20];
1612 u8 dot3stats_frame_too_longs_low[0x20];
1614 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1616 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1618 u8 dot3stats_symbol_errors_high[0x20];
1620 u8 dot3stats_symbol_errors_low[0x20];
1622 u8 dot3control_in_unknown_opcodes_high[0x20];
1624 u8 dot3control_in_unknown_opcodes_low[0x20];
1626 u8 dot3in_pause_frames_high[0x20];
1628 u8 dot3in_pause_frames_low[0x20];
1630 u8 dot3out_pause_frames_high[0x20];
1632 u8 dot3out_pause_frames_low[0x20];
1634 u8 reserved_at_400[0x3c0];
1637 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1638 u8 ether_stats_drop_events_high[0x20];
1640 u8 ether_stats_drop_events_low[0x20];
1642 u8 ether_stats_octets_high[0x20];
1644 u8 ether_stats_octets_low[0x20];
1646 u8 ether_stats_pkts_high[0x20];
1648 u8 ether_stats_pkts_low[0x20];
1650 u8 ether_stats_broadcast_pkts_high[0x20];
1652 u8 ether_stats_broadcast_pkts_low[0x20];
1654 u8 ether_stats_multicast_pkts_high[0x20];
1656 u8 ether_stats_multicast_pkts_low[0x20];
1658 u8 ether_stats_crc_align_errors_high[0x20];
1660 u8 ether_stats_crc_align_errors_low[0x20];
1662 u8 ether_stats_undersize_pkts_high[0x20];
1664 u8 ether_stats_undersize_pkts_low[0x20];
1666 u8 ether_stats_oversize_pkts_high[0x20];
1668 u8 ether_stats_oversize_pkts_low[0x20];
1670 u8 ether_stats_fragments_high[0x20];
1672 u8 ether_stats_fragments_low[0x20];
1674 u8 ether_stats_jabbers_high[0x20];
1676 u8 ether_stats_jabbers_low[0x20];
1678 u8 ether_stats_collisions_high[0x20];
1680 u8 ether_stats_collisions_low[0x20];
1682 u8 ether_stats_pkts64octets_high[0x20];
1684 u8 ether_stats_pkts64octets_low[0x20];
1686 u8 ether_stats_pkts65to127octets_high[0x20];
1688 u8 ether_stats_pkts65to127octets_low[0x20];
1690 u8 ether_stats_pkts128to255octets_high[0x20];
1692 u8 ether_stats_pkts128to255octets_low[0x20];
1694 u8 ether_stats_pkts256to511octets_high[0x20];
1696 u8 ether_stats_pkts256to511octets_low[0x20];
1698 u8 ether_stats_pkts512to1023octets_high[0x20];
1700 u8 ether_stats_pkts512to1023octets_low[0x20];
1702 u8 ether_stats_pkts1024to1518octets_high[0x20];
1704 u8 ether_stats_pkts1024to1518octets_low[0x20];
1706 u8 ether_stats_pkts1519to2047octets_high[0x20];
1708 u8 ether_stats_pkts1519to2047octets_low[0x20];
1710 u8 ether_stats_pkts2048to4095octets_high[0x20];
1712 u8 ether_stats_pkts2048to4095octets_low[0x20];
1714 u8 ether_stats_pkts4096to8191octets_high[0x20];
1716 u8 ether_stats_pkts4096to8191octets_low[0x20];
1718 u8 ether_stats_pkts8192to10239octets_high[0x20];
1720 u8 ether_stats_pkts8192to10239octets_low[0x20];
1722 u8 reserved_at_540[0x280];
1725 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1726 u8 if_in_octets_high[0x20];
1728 u8 if_in_octets_low[0x20];
1730 u8 if_in_ucast_pkts_high[0x20];
1732 u8 if_in_ucast_pkts_low[0x20];
1734 u8 if_in_discards_high[0x20];
1736 u8 if_in_discards_low[0x20];
1738 u8 if_in_errors_high[0x20];
1740 u8 if_in_errors_low[0x20];
1742 u8 if_in_unknown_protos_high[0x20];
1744 u8 if_in_unknown_protos_low[0x20];
1746 u8 if_out_octets_high[0x20];
1748 u8 if_out_octets_low[0x20];
1750 u8 if_out_ucast_pkts_high[0x20];
1752 u8 if_out_ucast_pkts_low[0x20];
1754 u8 if_out_discards_high[0x20];
1756 u8 if_out_discards_low[0x20];
1758 u8 if_out_errors_high[0x20];
1760 u8 if_out_errors_low[0x20];
1762 u8 if_in_multicast_pkts_high[0x20];
1764 u8 if_in_multicast_pkts_low[0x20];
1766 u8 if_in_broadcast_pkts_high[0x20];
1768 u8 if_in_broadcast_pkts_low[0x20];
1770 u8 if_out_multicast_pkts_high[0x20];
1772 u8 if_out_multicast_pkts_low[0x20];
1774 u8 if_out_broadcast_pkts_high[0x20];
1776 u8 if_out_broadcast_pkts_low[0x20];
1778 u8 reserved_at_340[0x480];
1781 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1782 u8 a_frames_transmitted_ok_high[0x20];
1784 u8 a_frames_transmitted_ok_low[0x20];
1786 u8 a_frames_received_ok_high[0x20];
1788 u8 a_frames_received_ok_low[0x20];
1790 u8 a_frame_check_sequence_errors_high[0x20];
1792 u8 a_frame_check_sequence_errors_low[0x20];
1794 u8 a_alignment_errors_high[0x20];
1796 u8 a_alignment_errors_low[0x20];
1798 u8 a_octets_transmitted_ok_high[0x20];
1800 u8 a_octets_transmitted_ok_low[0x20];
1802 u8 a_octets_received_ok_high[0x20];
1804 u8 a_octets_received_ok_low[0x20];
1806 u8 a_multicast_frames_xmitted_ok_high[0x20];
1808 u8 a_multicast_frames_xmitted_ok_low[0x20];
1810 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1812 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1814 u8 a_multicast_frames_received_ok_high[0x20];
1816 u8 a_multicast_frames_received_ok_low[0x20];
1818 u8 a_broadcast_frames_received_ok_high[0x20];
1820 u8 a_broadcast_frames_received_ok_low[0x20];
1822 u8 a_in_range_length_errors_high[0x20];
1824 u8 a_in_range_length_errors_low[0x20];
1826 u8 a_out_of_range_length_field_high[0x20];
1828 u8 a_out_of_range_length_field_low[0x20];
1830 u8 a_frame_too_long_errors_high[0x20];
1832 u8 a_frame_too_long_errors_low[0x20];
1834 u8 a_symbol_error_during_carrier_high[0x20];
1836 u8 a_symbol_error_during_carrier_low[0x20];
1838 u8 a_mac_control_frames_transmitted_high[0x20];
1840 u8 a_mac_control_frames_transmitted_low[0x20];
1842 u8 a_mac_control_frames_received_high[0x20];
1844 u8 a_mac_control_frames_received_low[0x20];
1846 u8 a_unsupported_opcodes_received_high[0x20];
1848 u8 a_unsupported_opcodes_received_low[0x20];
1850 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1852 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1854 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1856 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1858 u8 reserved_at_4c0[0x300];
1861 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1862 u8 life_time_counter_high[0x20];
1864 u8 life_time_counter_low[0x20];
1870 u8 l0_to_recovery_eieos[0x20];
1872 u8 l0_to_recovery_ts[0x20];
1874 u8 l0_to_recovery_framing[0x20];
1876 u8 l0_to_recovery_retrain[0x20];
1878 u8 crc_error_dllp[0x20];
1880 u8 crc_error_tlp[0x20];
1882 u8 tx_overflow_buffer_pkt_high[0x20];
1884 u8 tx_overflow_buffer_pkt_low[0x20];
1886 u8 outbound_stalled_reads[0x20];
1888 u8 outbound_stalled_writes[0x20];
1890 u8 outbound_stalled_reads_events[0x20];
1892 u8 outbound_stalled_writes_events[0x20];
1894 u8 reserved_at_200[0x5c0];
1897 struct mlx5_ifc_cmd_inter_comp_event_bits {
1898 u8 command_completion_vector[0x20];
1900 u8 reserved_at_20[0xc0];
1903 struct mlx5_ifc_stall_vl_event_bits {
1904 u8 reserved_at_0[0x18];
1906 u8 reserved_at_19[0x3];
1909 u8 reserved_at_20[0xa0];
1912 struct mlx5_ifc_db_bf_congestion_event_bits {
1913 u8 event_subtype[0x8];
1914 u8 reserved_at_8[0x8];
1915 u8 congestion_level[0x8];
1916 u8 reserved_at_18[0x8];
1918 u8 reserved_at_20[0xa0];
1921 struct mlx5_ifc_gpio_event_bits {
1922 u8 reserved_at_0[0x60];
1924 u8 gpio_event_hi[0x20];
1926 u8 gpio_event_lo[0x20];
1928 u8 reserved_at_a0[0x40];
1931 struct mlx5_ifc_port_state_change_event_bits {
1932 u8 reserved_at_0[0x40];
1935 u8 reserved_at_44[0x1c];
1937 u8 reserved_at_60[0x80];
1940 struct mlx5_ifc_dropped_packet_logged_bits {
1941 u8 reserved_at_0[0xe0];
1945 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1946 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1949 struct mlx5_ifc_cq_error_bits {
1950 u8 reserved_at_0[0x8];
1953 u8 reserved_at_20[0x20];
1955 u8 reserved_at_40[0x18];
1958 u8 reserved_at_60[0x80];
1961 struct mlx5_ifc_rdma_page_fault_event_bits {
1962 u8 bytes_committed[0x20];
1966 u8 reserved_at_40[0x10];
1967 u8 packet_len[0x10];
1969 u8 rdma_op_len[0x20];
1973 u8 reserved_at_c0[0x5];
1980 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1981 u8 bytes_committed[0x20];
1983 u8 reserved_at_20[0x10];
1986 u8 reserved_at_40[0x10];
1989 u8 reserved_at_60[0x60];
1991 u8 reserved_at_c0[0x5];
1998 struct mlx5_ifc_qp_events_bits {
1999 u8 reserved_at_0[0xa0];
2002 u8 reserved_at_a8[0x18];
2004 u8 reserved_at_c0[0x8];
2005 u8 qpn_rqn_sqn[0x18];
2008 struct mlx5_ifc_dct_events_bits {
2009 u8 reserved_at_0[0xc0];
2011 u8 reserved_at_c0[0x8];
2012 u8 dct_number[0x18];
2015 struct mlx5_ifc_comp_event_bits {
2016 u8 reserved_at_0[0xc0];
2018 u8 reserved_at_c0[0x8];
2023 MLX5_QPC_STATE_RST = 0x0,
2024 MLX5_QPC_STATE_INIT = 0x1,
2025 MLX5_QPC_STATE_RTR = 0x2,
2026 MLX5_QPC_STATE_RTS = 0x3,
2027 MLX5_QPC_STATE_SQER = 0x4,
2028 MLX5_QPC_STATE_ERR = 0x6,
2029 MLX5_QPC_STATE_SQD = 0x7,
2030 MLX5_QPC_STATE_SUSPENDED = 0x9,
2034 MLX5_QPC_ST_RC = 0x0,
2035 MLX5_QPC_ST_UC = 0x1,
2036 MLX5_QPC_ST_UD = 0x2,
2037 MLX5_QPC_ST_XRC = 0x3,
2038 MLX5_QPC_ST_DCI = 0x5,
2039 MLX5_QPC_ST_QP0 = 0x7,
2040 MLX5_QPC_ST_QP1 = 0x8,
2041 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2042 MLX5_QPC_ST_REG_UMR = 0xc,
2046 MLX5_QPC_PM_STATE_ARMED = 0x0,
2047 MLX5_QPC_PM_STATE_REARM = 0x1,
2048 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2049 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2053 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2057 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2058 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2062 MLX5_QPC_MTU_256_BYTES = 0x1,
2063 MLX5_QPC_MTU_512_BYTES = 0x2,
2064 MLX5_QPC_MTU_1K_BYTES = 0x3,
2065 MLX5_QPC_MTU_2K_BYTES = 0x4,
2066 MLX5_QPC_MTU_4K_BYTES = 0x5,
2067 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2071 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2072 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2073 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2074 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2075 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2076 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2077 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2078 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2082 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2083 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2084 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2088 MLX5_QPC_CS_RES_DISABLE = 0x0,
2089 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2090 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2093 struct mlx5_ifc_qpc_bits {
2095 u8 lag_tx_port_affinity[0x4];
2097 u8 reserved_at_10[0x3];
2099 u8 reserved_at_15[0x3];
2100 u8 offload_type[0x4];
2101 u8 end_padding_mode[0x2];
2102 u8 reserved_at_1e[0x2];
2104 u8 wq_signature[0x1];
2105 u8 block_lb_mc[0x1];
2106 u8 atomic_like_write_en[0x1];
2107 u8 latency_sensitive[0x1];
2108 u8 reserved_at_24[0x1];
2109 u8 drain_sigerr[0x1];
2110 u8 reserved_at_26[0x2];
2114 u8 log_msg_max[0x5];
2115 u8 reserved_at_48[0x1];
2116 u8 log_rq_size[0x4];
2117 u8 log_rq_stride[0x3];
2119 u8 log_sq_size[0x4];
2120 u8 reserved_at_55[0x6];
2122 u8 ulp_stateless_offload_mode[0x4];
2124 u8 counter_set_id[0x8];
2127 u8 reserved_at_80[0x8];
2128 u8 user_index[0x18];
2130 u8 reserved_at_a0[0x3];
2131 u8 log_page_size[0x5];
2132 u8 remote_qpn[0x18];
2134 struct mlx5_ifc_ads_bits primary_address_path;
2136 struct mlx5_ifc_ads_bits secondary_address_path;
2138 u8 log_ack_req_freq[0x4];
2139 u8 reserved_at_384[0x4];
2140 u8 log_sra_max[0x3];
2141 u8 reserved_at_38b[0x2];
2142 u8 retry_count[0x3];
2144 u8 reserved_at_393[0x1];
2146 u8 cur_rnr_retry[0x3];
2147 u8 cur_retry_count[0x3];
2148 u8 reserved_at_39b[0x5];
2150 u8 reserved_at_3a0[0x20];
2152 u8 reserved_at_3c0[0x8];
2153 u8 next_send_psn[0x18];
2155 u8 reserved_at_3e0[0x8];
2158 u8 reserved_at_400[0x8];
2161 u8 reserved_at_420[0x20];
2163 u8 reserved_at_440[0x8];
2164 u8 last_acked_psn[0x18];
2166 u8 reserved_at_460[0x8];
2169 u8 reserved_at_480[0x8];
2170 u8 log_rra_max[0x3];
2171 u8 reserved_at_48b[0x1];
2172 u8 atomic_mode[0x4];
2176 u8 reserved_at_493[0x1];
2177 u8 page_offset[0x6];
2178 u8 reserved_at_49a[0x3];
2179 u8 cd_slave_receive[0x1];
2180 u8 cd_slave_send[0x1];
2183 u8 reserved_at_4a0[0x3];
2184 u8 min_rnr_nak[0x5];
2185 u8 next_rcv_psn[0x18];
2187 u8 reserved_at_4c0[0x8];
2190 u8 reserved_at_4e0[0x8];
2197 u8 reserved_at_560[0x5];
2199 u8 srqn_rmpn_xrqn[0x18];
2201 u8 reserved_at_580[0x8];
2204 u8 hw_sq_wqebb_counter[0x10];
2205 u8 sw_sq_wqebb_counter[0x10];
2207 u8 hw_rq_counter[0x20];
2209 u8 sw_rq_counter[0x20];
2211 u8 reserved_at_600[0x20];
2213 u8 reserved_at_620[0xf];
2218 u8 dc_access_key[0x40];
2220 u8 reserved_at_680[0xc0];
2223 struct mlx5_ifc_roce_addr_layout_bits {
2224 u8 source_l3_address[16][0x8];
2226 u8 reserved_at_80[0x3];
2229 u8 source_mac_47_32[0x10];
2231 u8 source_mac_31_0[0x20];
2233 u8 reserved_at_c0[0x14];
2234 u8 roce_l3_type[0x4];
2235 u8 roce_version[0x8];
2237 u8 reserved_at_e0[0x20];
2240 union mlx5_ifc_hca_cap_union_bits {
2241 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2242 struct mlx5_ifc_odp_cap_bits odp_cap;
2243 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2244 struct mlx5_ifc_roce_cap_bits roce_cap;
2245 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2246 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2247 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2248 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2249 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2250 struct mlx5_ifc_qos_cap_bits qos_cap;
2251 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2252 u8 reserved_at_0[0x8000];
2256 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2257 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2258 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2259 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2260 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2261 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2262 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2265 struct mlx5_ifc_flow_context_bits {
2266 u8 reserved_at_0[0x20];
2270 u8 reserved_at_40[0x8];
2273 u8 reserved_at_60[0x10];
2276 u8 reserved_at_80[0x8];
2277 u8 destination_list_size[0x18];
2279 u8 reserved_at_a0[0x8];
2280 u8 flow_counter_list_size[0x18];
2284 u8 modify_header_id[0x20];
2286 u8 reserved_at_100[0x100];
2288 struct mlx5_ifc_fte_match_param_bits match_value;
2290 u8 reserved_at_1200[0x600];
2292 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2296 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2297 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2300 struct mlx5_ifc_xrc_srqc_bits {
2302 u8 log_xrc_srq_size[0x4];
2303 u8 reserved_at_8[0x18];
2305 u8 wq_signature[0x1];
2307 u8 reserved_at_22[0x1];
2309 u8 basic_cyclic_rcv_wqe[0x1];
2310 u8 log_rq_stride[0x3];
2313 u8 page_offset[0x6];
2314 u8 reserved_at_46[0x2];
2317 u8 reserved_at_60[0x20];
2319 u8 user_index_equal_xrc_srqn[0x1];
2320 u8 reserved_at_81[0x1];
2321 u8 log_page_size[0x6];
2322 u8 user_index[0x18];
2324 u8 reserved_at_a0[0x20];
2326 u8 reserved_at_c0[0x8];
2332 u8 reserved_at_100[0x40];
2334 u8 db_record_addr_h[0x20];
2336 u8 db_record_addr_l[0x1e];
2337 u8 reserved_at_17e[0x2];
2339 u8 reserved_at_180[0x80];
2342 struct mlx5_ifc_traffic_counter_bits {
2348 struct mlx5_ifc_tisc_bits {
2349 u8 strict_lag_tx_port_affinity[0x1];
2350 u8 reserved_at_1[0x3];
2351 u8 lag_tx_port_affinity[0x04];
2353 u8 reserved_at_8[0x4];
2355 u8 reserved_at_10[0x10];
2357 u8 reserved_at_20[0x100];
2359 u8 reserved_at_120[0x8];
2360 u8 transport_domain[0x18];
2362 u8 reserved_at_140[0x8];
2363 u8 underlay_qpn[0x18];
2364 u8 reserved_at_160[0x3a0];
2368 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2369 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2373 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2374 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2378 MLX5_RX_HASH_FN_NONE = 0x0,
2379 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2380 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2384 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2385 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2388 struct mlx5_ifc_tirc_bits {
2389 u8 reserved_at_0[0x20];
2392 u8 reserved_at_24[0x1c];
2394 u8 reserved_at_40[0x40];
2396 u8 reserved_at_80[0x4];
2397 u8 lro_timeout_period_usecs[0x10];
2398 u8 lro_enable_mask[0x4];
2399 u8 lro_max_ip_payload_size[0x8];
2401 u8 reserved_at_a0[0x40];
2403 u8 reserved_at_e0[0x8];
2404 u8 inline_rqn[0x18];
2406 u8 rx_hash_symmetric[0x1];
2407 u8 reserved_at_101[0x1];
2408 u8 tunneled_offload_en[0x1];
2409 u8 reserved_at_103[0x5];
2410 u8 indirect_table[0x18];
2413 u8 reserved_at_124[0x2];
2414 u8 self_lb_block[0x2];
2415 u8 transport_domain[0x18];
2417 u8 rx_hash_toeplitz_key[10][0x20];
2419 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2421 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2423 u8 reserved_at_2c0[0x4c0];
2427 MLX5_SRQC_STATE_GOOD = 0x0,
2428 MLX5_SRQC_STATE_ERROR = 0x1,
2431 struct mlx5_ifc_srqc_bits {
2433 u8 log_srq_size[0x4];
2434 u8 reserved_at_8[0x18];
2436 u8 wq_signature[0x1];
2438 u8 reserved_at_22[0x1];
2440 u8 reserved_at_24[0x1];
2441 u8 log_rq_stride[0x3];
2444 u8 page_offset[0x6];
2445 u8 reserved_at_46[0x2];
2448 u8 reserved_at_60[0x20];
2450 u8 reserved_at_80[0x2];
2451 u8 log_page_size[0x6];
2452 u8 reserved_at_88[0x18];
2454 u8 reserved_at_a0[0x20];
2456 u8 reserved_at_c0[0x8];
2462 u8 reserved_at_100[0x40];
2466 u8 reserved_at_180[0x80];
2470 MLX5_SQC_STATE_RST = 0x0,
2471 MLX5_SQC_STATE_RDY = 0x1,
2472 MLX5_SQC_STATE_ERR = 0x3,
2475 struct mlx5_ifc_sqc_bits {
2479 u8 flush_in_error_en[0x1];
2480 u8 allow_multi_pkt_send_wqe[0x1];
2481 u8 min_wqe_inline_mode[0x3];
2485 u8 reserved_at_e[0x12];
2487 u8 reserved_at_20[0x8];
2488 u8 user_index[0x18];
2490 u8 reserved_at_40[0x8];
2493 u8 reserved_at_60[0x90];
2495 u8 packet_pacing_rate_limit_index[0x10];
2496 u8 tis_lst_sz[0x10];
2497 u8 reserved_at_110[0x10];
2499 u8 reserved_at_120[0x40];
2501 u8 reserved_at_160[0x8];
2504 struct mlx5_ifc_wq_bits wq;
2508 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2509 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2510 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2511 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2514 struct mlx5_ifc_scheduling_context_bits {
2515 u8 element_type[0x8];
2516 u8 reserved_at_8[0x18];
2518 u8 element_attributes[0x20];
2520 u8 parent_element_id[0x20];
2522 u8 reserved_at_60[0x40];
2526 u8 max_average_bw[0x20];
2528 u8 reserved_at_e0[0x120];
2531 struct mlx5_ifc_rqtc_bits {
2532 u8 reserved_at_0[0xa0];
2534 u8 reserved_at_a0[0x10];
2535 u8 rqt_max_size[0x10];
2537 u8 reserved_at_c0[0x10];
2538 u8 rqt_actual_size[0x10];
2540 u8 reserved_at_e0[0x6a0];
2542 struct mlx5_ifc_rq_num_bits rq_num[0];
2546 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2547 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2551 MLX5_RQC_STATE_RST = 0x0,
2552 MLX5_RQC_STATE_RDY = 0x1,
2553 MLX5_RQC_STATE_ERR = 0x3,
2556 struct mlx5_ifc_rqc_bits {
2558 u8 delay_drop_en[0x1];
2559 u8 scatter_fcs[0x1];
2561 u8 mem_rq_type[0x4];
2563 u8 reserved_at_c[0x1];
2564 u8 flush_in_error_en[0x1];
2565 u8 reserved_at_e[0x12];
2567 u8 reserved_at_20[0x8];
2568 u8 user_index[0x18];
2570 u8 reserved_at_40[0x8];
2573 u8 counter_set_id[0x8];
2574 u8 reserved_at_68[0x18];
2576 u8 reserved_at_80[0x8];
2579 u8 reserved_at_a0[0xe0];
2581 struct mlx5_ifc_wq_bits wq;
2585 MLX5_RMPC_STATE_RDY = 0x1,
2586 MLX5_RMPC_STATE_ERR = 0x3,
2589 struct mlx5_ifc_rmpc_bits {
2590 u8 reserved_at_0[0x8];
2592 u8 reserved_at_c[0x14];
2594 u8 basic_cyclic_rcv_wqe[0x1];
2595 u8 reserved_at_21[0x1f];
2597 u8 reserved_at_40[0x140];
2599 struct mlx5_ifc_wq_bits wq;
2602 struct mlx5_ifc_nic_vport_context_bits {
2603 u8 reserved_at_0[0x5];
2604 u8 min_wqe_inline_mode[0x3];
2605 u8 reserved_at_8[0x15];
2606 u8 disable_mc_local_lb[0x1];
2607 u8 disable_uc_local_lb[0x1];
2610 u8 arm_change_event[0x1];
2611 u8 reserved_at_21[0x1a];
2612 u8 event_on_mtu[0x1];
2613 u8 event_on_promisc_change[0x1];
2614 u8 event_on_vlan_change[0x1];
2615 u8 event_on_mc_address_change[0x1];
2616 u8 event_on_uc_address_change[0x1];
2618 u8 reserved_at_40[0xf0];
2622 u8 system_image_guid[0x40];
2626 u8 reserved_at_200[0x140];
2627 u8 qkey_violation_counter[0x10];
2628 u8 reserved_at_350[0x430];
2632 u8 promisc_all[0x1];
2633 u8 reserved_at_783[0x2];
2634 u8 allowed_list_type[0x3];
2635 u8 reserved_at_788[0xc];
2636 u8 allowed_list_size[0xc];
2638 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2640 u8 reserved_at_7e0[0x20];
2642 u8 current_uc_mac_address[0][0x40];
2646 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2647 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2648 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2649 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
2652 struct mlx5_ifc_mkc_bits {
2653 u8 reserved_at_0[0x1];
2655 u8 reserved_at_2[0xd];
2656 u8 small_fence_on_rdma_read_response[0x1];
2663 u8 access_mode[0x2];
2664 u8 reserved_at_18[0x8];
2669 u8 reserved_at_40[0x20];
2674 u8 reserved_at_63[0x2];
2675 u8 expected_sigerr_count[0x1];
2676 u8 reserved_at_66[0x1];
2680 u8 start_addr[0x40];
2684 u8 bsf_octword_size[0x20];
2686 u8 reserved_at_120[0x80];
2688 u8 translations_octword_size[0x20];
2690 u8 reserved_at_1c0[0x1b];
2691 u8 log_page_size[0x5];
2693 u8 reserved_at_1e0[0x20];
2696 struct mlx5_ifc_pkey_bits {
2697 u8 reserved_at_0[0x10];
2701 struct mlx5_ifc_array128_auto_bits {
2702 u8 array128_auto[16][0x8];
2705 struct mlx5_ifc_hca_vport_context_bits {
2706 u8 field_select[0x20];
2708 u8 reserved_at_20[0xe0];
2710 u8 sm_virt_aware[0x1];
2713 u8 grh_required[0x1];
2714 u8 reserved_at_104[0xc];
2715 u8 port_physical_state[0x4];
2716 u8 vport_state_policy[0x4];
2718 u8 vport_state[0x4];
2720 u8 reserved_at_120[0x20];
2722 u8 system_image_guid[0x40];
2730 u8 cap_mask1_field_select[0x20];
2734 u8 cap_mask2_field_select[0x20];
2736 u8 reserved_at_280[0x80];
2739 u8 reserved_at_310[0x4];
2740 u8 init_type_reply[0x4];
2742 u8 subnet_timeout[0x5];
2746 u8 reserved_at_334[0xc];
2748 u8 qkey_violation_counter[0x10];
2749 u8 pkey_violation_counter[0x10];
2751 u8 reserved_at_360[0xca0];
2754 struct mlx5_ifc_esw_vport_context_bits {
2755 u8 reserved_at_0[0x3];
2756 u8 vport_svlan_strip[0x1];
2757 u8 vport_cvlan_strip[0x1];
2758 u8 vport_svlan_insert[0x1];
2759 u8 vport_cvlan_insert[0x2];
2760 u8 reserved_at_8[0x18];
2762 u8 reserved_at_20[0x20];
2771 u8 reserved_at_60[0x7a0];
2775 MLX5_EQC_STATUS_OK = 0x0,
2776 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2780 MLX5_EQC_ST_ARMED = 0x9,
2781 MLX5_EQC_ST_FIRED = 0xa,
2784 struct mlx5_ifc_eqc_bits {
2786 u8 reserved_at_4[0x9];
2789 u8 reserved_at_f[0x5];
2791 u8 reserved_at_18[0x8];
2793 u8 reserved_at_20[0x20];
2795 u8 reserved_at_40[0x14];
2796 u8 page_offset[0x6];
2797 u8 reserved_at_5a[0x6];
2799 u8 reserved_at_60[0x3];
2800 u8 log_eq_size[0x5];
2803 u8 reserved_at_80[0x20];
2805 u8 reserved_at_a0[0x18];
2808 u8 reserved_at_c0[0x3];
2809 u8 log_page_size[0x5];
2810 u8 reserved_at_c8[0x18];
2812 u8 reserved_at_e0[0x60];
2814 u8 reserved_at_140[0x8];
2815 u8 consumer_counter[0x18];
2817 u8 reserved_at_160[0x8];
2818 u8 producer_counter[0x18];
2820 u8 reserved_at_180[0x80];
2824 MLX5_DCTC_STATE_ACTIVE = 0x0,
2825 MLX5_DCTC_STATE_DRAINING = 0x1,
2826 MLX5_DCTC_STATE_DRAINED = 0x2,
2830 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2831 MLX5_DCTC_CS_RES_NA = 0x1,
2832 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2836 MLX5_DCTC_MTU_256_BYTES = 0x1,
2837 MLX5_DCTC_MTU_512_BYTES = 0x2,
2838 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2839 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2840 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2843 struct mlx5_ifc_dctc_bits {
2844 u8 reserved_at_0[0x4];
2846 u8 reserved_at_8[0x18];
2848 u8 reserved_at_20[0x8];
2849 u8 user_index[0x18];
2851 u8 reserved_at_40[0x8];
2854 u8 counter_set_id[0x8];
2855 u8 atomic_mode[0x4];
2859 u8 atomic_like_write_en[0x1];
2860 u8 latency_sensitive[0x1];
2863 u8 reserved_at_73[0xd];
2865 u8 reserved_at_80[0x8];
2867 u8 reserved_at_90[0x3];
2868 u8 min_rnr_nak[0x5];
2869 u8 reserved_at_98[0x8];
2871 u8 reserved_at_a0[0x8];
2874 u8 reserved_at_c0[0x8];
2878 u8 reserved_at_e8[0x4];
2879 u8 flow_label[0x14];
2881 u8 dc_access_key[0x40];
2883 u8 reserved_at_140[0x5];
2886 u8 pkey_index[0x10];
2888 u8 reserved_at_160[0x8];
2889 u8 my_addr_index[0x8];
2890 u8 reserved_at_170[0x8];
2893 u8 dc_access_key_violation_count[0x20];
2895 u8 reserved_at_1a0[0x14];
2901 u8 reserved_at_1c0[0x40];
2905 MLX5_CQC_STATUS_OK = 0x0,
2906 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2907 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2911 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2912 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2916 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2917 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2918 MLX5_CQC_ST_FIRED = 0xa,
2922 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2923 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2924 MLX5_CQ_PERIOD_NUM_MODES
2927 struct mlx5_ifc_cqc_bits {
2929 u8 reserved_at_4[0x4];
2932 u8 reserved_at_c[0x1];
2933 u8 scqe_break_moderation_en[0x1];
2935 u8 cq_period_mode[0x2];
2936 u8 cqe_comp_en[0x1];
2937 u8 mini_cqe_res_format[0x2];
2939 u8 reserved_at_18[0x8];
2941 u8 reserved_at_20[0x20];
2943 u8 reserved_at_40[0x14];
2944 u8 page_offset[0x6];
2945 u8 reserved_at_5a[0x6];
2947 u8 reserved_at_60[0x3];
2948 u8 log_cq_size[0x5];
2951 u8 reserved_at_80[0x4];
2953 u8 cq_max_count[0x10];
2955 u8 reserved_at_a0[0x18];
2958 u8 reserved_at_c0[0x3];
2959 u8 log_page_size[0x5];
2960 u8 reserved_at_c8[0x18];
2962 u8 reserved_at_e0[0x20];
2964 u8 reserved_at_100[0x8];
2965 u8 last_notified_index[0x18];
2967 u8 reserved_at_120[0x8];
2968 u8 last_solicit_index[0x18];
2970 u8 reserved_at_140[0x8];
2971 u8 consumer_counter[0x18];
2973 u8 reserved_at_160[0x8];
2974 u8 producer_counter[0x18];
2976 u8 reserved_at_180[0x40];
2981 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2982 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2983 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2984 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2985 u8 reserved_at_0[0x800];
2988 struct mlx5_ifc_query_adapter_param_block_bits {
2989 u8 reserved_at_0[0xc0];
2991 u8 reserved_at_c0[0x8];
2992 u8 ieee_vendor_id[0x18];
2994 u8 reserved_at_e0[0x10];
2995 u8 vsd_vendor_id[0x10];
2999 u8 vsd_contd_psid[16][0x8];
3003 MLX5_XRQC_STATE_GOOD = 0x0,
3004 MLX5_XRQC_STATE_ERROR = 0x1,
3008 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3009 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3013 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3016 struct mlx5_ifc_tag_matching_topology_context_bits {
3017 u8 log_matching_list_sz[0x4];
3018 u8 reserved_at_4[0xc];
3019 u8 append_next_index[0x10];
3021 u8 sw_phase_cnt[0x10];
3022 u8 hw_phase_cnt[0x10];
3024 u8 reserved_at_40[0x40];
3027 struct mlx5_ifc_xrqc_bits {
3030 u8 reserved_at_5[0xf];
3032 u8 reserved_at_18[0x4];
3035 u8 reserved_at_20[0x8];
3036 u8 user_index[0x18];
3038 u8 reserved_at_40[0x8];
3041 u8 reserved_at_60[0xa0];
3043 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3045 u8 reserved_at_180[0x280];
3047 struct mlx5_ifc_wq_bits wq;
3050 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3051 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3052 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3053 u8 reserved_at_0[0x20];
3056 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3057 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3058 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3059 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3060 u8 reserved_at_0[0x20];
3063 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3064 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3065 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3066 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3067 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3068 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3069 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3070 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3071 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3072 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3073 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3074 u8 reserved_at_0[0x7c0];
3077 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3078 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3079 u8 reserved_at_0[0x7c0];
3082 union mlx5_ifc_event_auto_bits {
3083 struct mlx5_ifc_comp_event_bits comp_event;
3084 struct mlx5_ifc_dct_events_bits dct_events;
3085 struct mlx5_ifc_qp_events_bits qp_events;
3086 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3087 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3088 struct mlx5_ifc_cq_error_bits cq_error;
3089 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3090 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3091 struct mlx5_ifc_gpio_event_bits gpio_event;
3092 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3093 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3094 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3095 u8 reserved_at_0[0xe0];
3098 struct mlx5_ifc_health_buffer_bits {
3099 u8 reserved_at_0[0x100];
3101 u8 assert_existptr[0x20];
3103 u8 assert_callra[0x20];
3105 u8 reserved_at_140[0x40];
3107 u8 fw_version[0x20];
3111 u8 reserved_at_1c0[0x20];
3113 u8 irisc_index[0x8];
3118 struct mlx5_ifc_register_loopback_control_bits {
3120 u8 reserved_at_1[0x7];
3122 u8 reserved_at_10[0x10];
3124 u8 reserved_at_20[0x60];
3127 struct mlx5_ifc_vport_tc_element_bits {
3128 u8 traffic_class[0x4];
3129 u8 reserved_at_4[0xc];
3130 u8 vport_number[0x10];
3133 struct mlx5_ifc_vport_element_bits {
3134 u8 reserved_at_0[0x10];
3135 u8 vport_number[0x10];
3139 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3140 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3141 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3144 struct mlx5_ifc_tsar_element_bits {
3145 u8 reserved_at_0[0x8];
3147 u8 reserved_at_10[0x10];
3151 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3152 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3155 struct mlx5_ifc_teardown_hca_out_bits {
3157 u8 reserved_at_8[0x18];
3161 u8 reserved_at_40[0x3f];
3163 u8 force_state[0x1];
3167 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3168 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3171 struct mlx5_ifc_teardown_hca_in_bits {
3173 u8 reserved_at_10[0x10];
3175 u8 reserved_at_20[0x10];
3178 u8 reserved_at_40[0x10];
3181 u8 reserved_at_60[0x20];
3184 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3186 u8 reserved_at_8[0x18];
3190 u8 reserved_at_40[0x40];
3193 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3195 u8 reserved_at_10[0x10];
3197 u8 reserved_at_20[0x10];
3200 u8 reserved_at_40[0x8];
3203 u8 reserved_at_60[0x20];
3205 u8 opt_param_mask[0x20];
3207 u8 reserved_at_a0[0x20];
3209 struct mlx5_ifc_qpc_bits qpc;
3211 u8 reserved_at_800[0x80];
3214 struct mlx5_ifc_sqd2rts_qp_out_bits {
3216 u8 reserved_at_8[0x18];
3220 u8 reserved_at_40[0x40];
3223 struct mlx5_ifc_sqd2rts_qp_in_bits {
3225 u8 reserved_at_10[0x10];
3227 u8 reserved_at_20[0x10];
3230 u8 reserved_at_40[0x8];
3233 u8 reserved_at_60[0x20];
3235 u8 opt_param_mask[0x20];
3237 u8 reserved_at_a0[0x20];
3239 struct mlx5_ifc_qpc_bits qpc;
3241 u8 reserved_at_800[0x80];
3244 struct mlx5_ifc_set_roce_address_out_bits {
3246 u8 reserved_at_8[0x18];
3250 u8 reserved_at_40[0x40];
3253 struct mlx5_ifc_set_roce_address_in_bits {
3255 u8 reserved_at_10[0x10];
3257 u8 reserved_at_20[0x10];
3260 u8 roce_address_index[0x10];
3261 u8 reserved_at_50[0x10];
3263 u8 reserved_at_60[0x20];
3265 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3268 struct mlx5_ifc_set_mad_demux_out_bits {
3270 u8 reserved_at_8[0x18];
3274 u8 reserved_at_40[0x40];
3278 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3279 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3282 struct mlx5_ifc_set_mad_demux_in_bits {
3284 u8 reserved_at_10[0x10];
3286 u8 reserved_at_20[0x10];
3289 u8 reserved_at_40[0x20];
3291 u8 reserved_at_60[0x6];
3293 u8 reserved_at_68[0x18];
3296 struct mlx5_ifc_set_l2_table_entry_out_bits {
3298 u8 reserved_at_8[0x18];
3302 u8 reserved_at_40[0x40];
3305 struct mlx5_ifc_set_l2_table_entry_in_bits {
3307 u8 reserved_at_10[0x10];
3309 u8 reserved_at_20[0x10];
3312 u8 reserved_at_40[0x60];
3314 u8 reserved_at_a0[0x8];
3315 u8 table_index[0x18];
3317 u8 reserved_at_c0[0x20];
3319 u8 reserved_at_e0[0x13];
3323 struct mlx5_ifc_mac_address_layout_bits mac_address;
3325 u8 reserved_at_140[0xc0];
3328 struct mlx5_ifc_set_issi_out_bits {
3330 u8 reserved_at_8[0x18];
3334 u8 reserved_at_40[0x40];
3337 struct mlx5_ifc_set_issi_in_bits {
3339 u8 reserved_at_10[0x10];
3341 u8 reserved_at_20[0x10];
3344 u8 reserved_at_40[0x10];
3345 u8 current_issi[0x10];
3347 u8 reserved_at_60[0x20];
3350 struct mlx5_ifc_set_hca_cap_out_bits {
3352 u8 reserved_at_8[0x18];
3356 u8 reserved_at_40[0x40];
3359 struct mlx5_ifc_set_hca_cap_in_bits {
3361 u8 reserved_at_10[0x10];
3363 u8 reserved_at_20[0x10];
3366 u8 reserved_at_40[0x40];
3368 union mlx5_ifc_hca_cap_union_bits capability;
3372 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3373 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3374 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3375 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3378 struct mlx5_ifc_set_fte_out_bits {
3380 u8 reserved_at_8[0x18];
3384 u8 reserved_at_40[0x40];
3387 struct mlx5_ifc_set_fte_in_bits {
3389 u8 reserved_at_10[0x10];
3391 u8 reserved_at_20[0x10];
3394 u8 other_vport[0x1];
3395 u8 reserved_at_41[0xf];
3396 u8 vport_number[0x10];
3398 u8 reserved_at_60[0x20];
3401 u8 reserved_at_88[0x18];
3403 u8 reserved_at_a0[0x8];
3406 u8 reserved_at_c0[0x18];
3407 u8 modify_enable_mask[0x8];
3409 u8 reserved_at_e0[0x20];
3411 u8 flow_index[0x20];
3413 u8 reserved_at_120[0xe0];
3415 struct mlx5_ifc_flow_context_bits flow_context;
3418 struct mlx5_ifc_rts2rts_qp_out_bits {
3420 u8 reserved_at_8[0x18];
3424 u8 reserved_at_40[0x40];
3427 struct mlx5_ifc_rts2rts_qp_in_bits {
3429 u8 reserved_at_10[0x10];
3431 u8 reserved_at_20[0x10];
3434 u8 reserved_at_40[0x8];
3437 u8 reserved_at_60[0x20];
3439 u8 opt_param_mask[0x20];
3441 u8 reserved_at_a0[0x20];
3443 struct mlx5_ifc_qpc_bits qpc;
3445 u8 reserved_at_800[0x80];
3448 struct mlx5_ifc_rtr2rts_qp_out_bits {
3450 u8 reserved_at_8[0x18];
3454 u8 reserved_at_40[0x40];
3457 struct mlx5_ifc_rtr2rts_qp_in_bits {
3459 u8 reserved_at_10[0x10];
3461 u8 reserved_at_20[0x10];
3464 u8 reserved_at_40[0x8];
3467 u8 reserved_at_60[0x20];
3469 u8 opt_param_mask[0x20];
3471 u8 reserved_at_a0[0x20];
3473 struct mlx5_ifc_qpc_bits qpc;
3475 u8 reserved_at_800[0x80];
3478 struct mlx5_ifc_rst2init_qp_out_bits {
3480 u8 reserved_at_8[0x18];
3484 u8 reserved_at_40[0x40];
3487 struct mlx5_ifc_rst2init_qp_in_bits {
3489 u8 reserved_at_10[0x10];
3491 u8 reserved_at_20[0x10];
3494 u8 reserved_at_40[0x8];
3497 u8 reserved_at_60[0x20];
3499 u8 opt_param_mask[0x20];
3501 u8 reserved_at_a0[0x20];
3503 struct mlx5_ifc_qpc_bits qpc;
3505 u8 reserved_at_800[0x80];
3508 struct mlx5_ifc_query_xrq_out_bits {
3510 u8 reserved_at_8[0x18];
3514 u8 reserved_at_40[0x40];
3516 struct mlx5_ifc_xrqc_bits xrq_context;
3519 struct mlx5_ifc_query_xrq_in_bits {
3521 u8 reserved_at_10[0x10];
3523 u8 reserved_at_20[0x10];
3526 u8 reserved_at_40[0x8];
3529 u8 reserved_at_60[0x20];
3532 struct mlx5_ifc_query_xrc_srq_out_bits {
3534 u8 reserved_at_8[0x18];
3538 u8 reserved_at_40[0x40];
3540 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3542 u8 reserved_at_280[0x600];
3547 struct mlx5_ifc_query_xrc_srq_in_bits {
3549 u8 reserved_at_10[0x10];
3551 u8 reserved_at_20[0x10];
3554 u8 reserved_at_40[0x8];
3557 u8 reserved_at_60[0x20];
3561 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3562 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3565 struct mlx5_ifc_query_vport_state_out_bits {
3567 u8 reserved_at_8[0x18];
3571 u8 reserved_at_40[0x20];
3573 u8 reserved_at_60[0x18];
3574 u8 admin_state[0x4];
3579 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3580 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3583 struct mlx5_ifc_query_vport_state_in_bits {
3585 u8 reserved_at_10[0x10];
3587 u8 reserved_at_20[0x10];
3590 u8 other_vport[0x1];
3591 u8 reserved_at_41[0xf];
3592 u8 vport_number[0x10];
3594 u8 reserved_at_60[0x20];
3597 struct mlx5_ifc_query_vport_counter_out_bits {
3599 u8 reserved_at_8[0x18];
3603 u8 reserved_at_40[0x40];
3605 struct mlx5_ifc_traffic_counter_bits received_errors;
3607 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3609 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3611 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3613 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3615 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3617 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3619 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3621 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3623 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3625 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3627 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3629 u8 reserved_at_680[0xa00];
3633 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3636 struct mlx5_ifc_query_vport_counter_in_bits {
3638 u8 reserved_at_10[0x10];
3640 u8 reserved_at_20[0x10];
3643 u8 other_vport[0x1];
3644 u8 reserved_at_41[0xb];
3646 u8 vport_number[0x10];
3648 u8 reserved_at_60[0x60];
3651 u8 reserved_at_c1[0x1f];
3653 u8 reserved_at_e0[0x20];
3656 struct mlx5_ifc_query_tis_out_bits {
3658 u8 reserved_at_8[0x18];
3662 u8 reserved_at_40[0x40];
3664 struct mlx5_ifc_tisc_bits tis_context;
3667 struct mlx5_ifc_query_tis_in_bits {
3669 u8 reserved_at_10[0x10];
3671 u8 reserved_at_20[0x10];
3674 u8 reserved_at_40[0x8];
3677 u8 reserved_at_60[0x20];
3680 struct mlx5_ifc_query_tir_out_bits {
3682 u8 reserved_at_8[0x18];
3686 u8 reserved_at_40[0xc0];
3688 struct mlx5_ifc_tirc_bits tir_context;
3691 struct mlx5_ifc_query_tir_in_bits {
3693 u8 reserved_at_10[0x10];
3695 u8 reserved_at_20[0x10];
3698 u8 reserved_at_40[0x8];
3701 u8 reserved_at_60[0x20];
3704 struct mlx5_ifc_query_srq_out_bits {
3706 u8 reserved_at_8[0x18];
3710 u8 reserved_at_40[0x40];
3712 struct mlx5_ifc_srqc_bits srq_context_entry;
3714 u8 reserved_at_280[0x600];
3719 struct mlx5_ifc_query_srq_in_bits {
3721 u8 reserved_at_10[0x10];
3723 u8 reserved_at_20[0x10];
3726 u8 reserved_at_40[0x8];
3729 u8 reserved_at_60[0x20];
3732 struct mlx5_ifc_query_sq_out_bits {
3734 u8 reserved_at_8[0x18];
3738 u8 reserved_at_40[0xc0];
3740 struct mlx5_ifc_sqc_bits sq_context;
3743 struct mlx5_ifc_query_sq_in_bits {
3745 u8 reserved_at_10[0x10];
3747 u8 reserved_at_20[0x10];
3750 u8 reserved_at_40[0x8];
3753 u8 reserved_at_60[0x20];
3756 struct mlx5_ifc_query_special_contexts_out_bits {
3758 u8 reserved_at_8[0x18];
3762 u8 dump_fill_mkey[0x20];
3768 u8 reserved_at_a0[0x60];
3771 struct mlx5_ifc_query_special_contexts_in_bits {
3773 u8 reserved_at_10[0x10];
3775 u8 reserved_at_20[0x10];
3778 u8 reserved_at_40[0x40];
3781 struct mlx5_ifc_query_scheduling_element_out_bits {
3783 u8 reserved_at_10[0x10];
3785 u8 reserved_at_20[0x10];
3788 u8 reserved_at_40[0xc0];
3790 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3792 u8 reserved_at_300[0x100];
3796 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3799 struct mlx5_ifc_query_scheduling_element_in_bits {
3801 u8 reserved_at_10[0x10];
3803 u8 reserved_at_20[0x10];
3806 u8 scheduling_hierarchy[0x8];
3807 u8 reserved_at_48[0x18];
3809 u8 scheduling_element_id[0x20];
3811 u8 reserved_at_80[0x180];
3814 struct mlx5_ifc_query_rqt_out_bits {
3816 u8 reserved_at_8[0x18];
3820 u8 reserved_at_40[0xc0];
3822 struct mlx5_ifc_rqtc_bits rqt_context;
3825 struct mlx5_ifc_query_rqt_in_bits {
3827 u8 reserved_at_10[0x10];
3829 u8 reserved_at_20[0x10];
3832 u8 reserved_at_40[0x8];
3835 u8 reserved_at_60[0x20];
3838 struct mlx5_ifc_query_rq_out_bits {
3840 u8 reserved_at_8[0x18];
3844 u8 reserved_at_40[0xc0];
3846 struct mlx5_ifc_rqc_bits rq_context;
3849 struct mlx5_ifc_query_rq_in_bits {
3851 u8 reserved_at_10[0x10];
3853 u8 reserved_at_20[0x10];
3856 u8 reserved_at_40[0x8];
3859 u8 reserved_at_60[0x20];
3862 struct mlx5_ifc_query_roce_address_out_bits {
3864 u8 reserved_at_8[0x18];
3868 u8 reserved_at_40[0x40];
3870 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3873 struct mlx5_ifc_query_roce_address_in_bits {
3875 u8 reserved_at_10[0x10];
3877 u8 reserved_at_20[0x10];
3880 u8 roce_address_index[0x10];
3881 u8 reserved_at_50[0x10];
3883 u8 reserved_at_60[0x20];
3886 struct mlx5_ifc_query_rmp_out_bits {
3888 u8 reserved_at_8[0x18];
3892 u8 reserved_at_40[0xc0];
3894 struct mlx5_ifc_rmpc_bits rmp_context;
3897 struct mlx5_ifc_query_rmp_in_bits {
3899 u8 reserved_at_10[0x10];
3901 u8 reserved_at_20[0x10];
3904 u8 reserved_at_40[0x8];
3907 u8 reserved_at_60[0x20];
3910 struct mlx5_ifc_query_qp_out_bits {
3912 u8 reserved_at_8[0x18];
3916 u8 reserved_at_40[0x40];
3918 u8 opt_param_mask[0x20];
3920 u8 reserved_at_a0[0x20];
3922 struct mlx5_ifc_qpc_bits qpc;
3924 u8 reserved_at_800[0x80];
3929 struct mlx5_ifc_query_qp_in_bits {
3931 u8 reserved_at_10[0x10];
3933 u8 reserved_at_20[0x10];
3936 u8 reserved_at_40[0x8];
3939 u8 reserved_at_60[0x20];
3942 struct mlx5_ifc_query_q_counter_out_bits {
3944 u8 reserved_at_8[0x18];
3948 u8 reserved_at_40[0x40];
3950 u8 rx_write_requests[0x20];
3952 u8 reserved_at_a0[0x20];
3954 u8 rx_read_requests[0x20];
3956 u8 reserved_at_e0[0x20];
3958 u8 rx_atomic_requests[0x20];
3960 u8 reserved_at_120[0x20];
3962 u8 rx_dct_connect[0x20];
3964 u8 reserved_at_160[0x20];
3966 u8 out_of_buffer[0x20];
3968 u8 reserved_at_1a0[0x20];
3970 u8 out_of_sequence[0x20];
3972 u8 reserved_at_1e0[0x20];
3974 u8 duplicate_request[0x20];
3976 u8 reserved_at_220[0x20];
3978 u8 rnr_nak_retry_err[0x20];
3980 u8 reserved_at_260[0x20];
3982 u8 packet_seq_err[0x20];
3984 u8 reserved_at_2a0[0x20];
3986 u8 implied_nak_seq_err[0x20];
3988 u8 reserved_at_2e0[0x20];
3990 u8 local_ack_timeout_err[0x20];
3992 u8 reserved_at_320[0xa0];
3994 u8 resp_local_length_error[0x20];
3996 u8 req_local_length_error[0x20];
3998 u8 resp_local_qp_error[0x20];
4000 u8 local_operation_error[0x20];
4002 u8 resp_local_protection[0x20];
4004 u8 req_local_protection[0x20];
4006 u8 resp_cqe_error[0x20];
4008 u8 req_cqe_error[0x20];
4010 u8 req_mw_binding[0x20];
4012 u8 req_bad_response[0x20];
4014 u8 req_remote_invalid_request[0x20];
4016 u8 resp_remote_invalid_request[0x20];
4018 u8 req_remote_access_errors[0x20];
4020 u8 resp_remote_access_errors[0x20];
4022 u8 req_remote_operation_errors[0x20];
4024 u8 req_transport_retries_exceeded[0x20];
4026 u8 cq_overflow[0x20];
4028 u8 resp_cqe_flush_error[0x20];
4030 u8 req_cqe_flush_error[0x20];
4032 u8 reserved_at_620[0x1e0];
4035 struct mlx5_ifc_query_q_counter_in_bits {
4037 u8 reserved_at_10[0x10];
4039 u8 reserved_at_20[0x10];
4042 u8 reserved_at_40[0x80];
4045 u8 reserved_at_c1[0x1f];
4047 u8 reserved_at_e0[0x18];
4048 u8 counter_set_id[0x8];
4051 struct mlx5_ifc_query_pages_out_bits {
4053 u8 reserved_at_8[0x18];
4057 u8 reserved_at_40[0x10];
4058 u8 function_id[0x10];
4064 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4065 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4066 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4069 struct mlx5_ifc_query_pages_in_bits {
4071 u8 reserved_at_10[0x10];
4073 u8 reserved_at_20[0x10];
4076 u8 reserved_at_40[0x10];
4077 u8 function_id[0x10];
4079 u8 reserved_at_60[0x20];
4082 struct mlx5_ifc_query_nic_vport_context_out_bits {
4084 u8 reserved_at_8[0x18];
4088 u8 reserved_at_40[0x40];
4090 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4093 struct mlx5_ifc_query_nic_vport_context_in_bits {
4095 u8 reserved_at_10[0x10];
4097 u8 reserved_at_20[0x10];
4100 u8 other_vport[0x1];
4101 u8 reserved_at_41[0xf];
4102 u8 vport_number[0x10];
4104 u8 reserved_at_60[0x5];
4105 u8 allowed_list_type[0x3];
4106 u8 reserved_at_68[0x18];
4109 struct mlx5_ifc_query_mkey_out_bits {
4111 u8 reserved_at_8[0x18];
4115 u8 reserved_at_40[0x40];
4117 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4119 u8 reserved_at_280[0x600];
4121 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4123 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4126 struct mlx5_ifc_query_mkey_in_bits {
4128 u8 reserved_at_10[0x10];
4130 u8 reserved_at_20[0x10];
4133 u8 reserved_at_40[0x8];
4134 u8 mkey_index[0x18];
4137 u8 reserved_at_61[0x1f];
4140 struct mlx5_ifc_query_mad_demux_out_bits {
4142 u8 reserved_at_8[0x18];
4146 u8 reserved_at_40[0x40];
4148 u8 mad_dumux_parameters_block[0x20];
4151 struct mlx5_ifc_query_mad_demux_in_bits {
4153 u8 reserved_at_10[0x10];
4155 u8 reserved_at_20[0x10];
4158 u8 reserved_at_40[0x40];
4161 struct mlx5_ifc_query_l2_table_entry_out_bits {
4163 u8 reserved_at_8[0x18];
4167 u8 reserved_at_40[0xa0];
4169 u8 reserved_at_e0[0x13];
4173 struct mlx5_ifc_mac_address_layout_bits mac_address;
4175 u8 reserved_at_140[0xc0];
4178 struct mlx5_ifc_query_l2_table_entry_in_bits {
4180 u8 reserved_at_10[0x10];
4182 u8 reserved_at_20[0x10];
4185 u8 reserved_at_40[0x60];
4187 u8 reserved_at_a0[0x8];
4188 u8 table_index[0x18];
4190 u8 reserved_at_c0[0x140];
4193 struct mlx5_ifc_query_issi_out_bits {
4195 u8 reserved_at_8[0x18];
4199 u8 reserved_at_40[0x10];
4200 u8 current_issi[0x10];
4202 u8 reserved_at_60[0xa0];
4204 u8 reserved_at_100[76][0x8];
4205 u8 supported_issi_dw0[0x20];
4208 struct mlx5_ifc_query_issi_in_bits {
4210 u8 reserved_at_10[0x10];
4212 u8 reserved_at_20[0x10];
4215 u8 reserved_at_40[0x40];
4218 struct mlx5_ifc_set_driver_version_out_bits {
4220 u8 reserved_0[0x18];
4223 u8 reserved_1[0x40];
4226 struct mlx5_ifc_set_driver_version_in_bits {
4228 u8 reserved_0[0x10];
4230 u8 reserved_1[0x10];
4233 u8 reserved_2[0x40];
4234 u8 driver_version[64][0x8];
4237 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4239 u8 reserved_at_8[0x18];
4243 u8 reserved_at_40[0x40];
4245 struct mlx5_ifc_pkey_bits pkey[0];
4248 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4250 u8 reserved_at_10[0x10];
4252 u8 reserved_at_20[0x10];
4255 u8 other_vport[0x1];
4256 u8 reserved_at_41[0xb];
4258 u8 vport_number[0x10];
4260 u8 reserved_at_60[0x10];
4261 u8 pkey_index[0x10];
4265 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4266 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4267 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4270 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4272 u8 reserved_at_8[0x18];
4276 u8 reserved_at_40[0x20];
4279 u8 reserved_at_70[0x10];
4281 struct mlx5_ifc_array128_auto_bits gid[0];
4284 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4286 u8 reserved_at_10[0x10];
4288 u8 reserved_at_20[0x10];
4291 u8 other_vport[0x1];
4292 u8 reserved_at_41[0xb];
4294 u8 vport_number[0x10];
4296 u8 reserved_at_60[0x10];
4300 struct mlx5_ifc_query_hca_vport_context_out_bits {
4302 u8 reserved_at_8[0x18];
4306 u8 reserved_at_40[0x40];
4308 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4311 struct mlx5_ifc_query_hca_vport_context_in_bits {
4313 u8 reserved_at_10[0x10];
4315 u8 reserved_at_20[0x10];
4318 u8 other_vport[0x1];
4319 u8 reserved_at_41[0xb];
4321 u8 vport_number[0x10];
4323 u8 reserved_at_60[0x20];
4326 struct mlx5_ifc_query_hca_cap_out_bits {
4328 u8 reserved_at_8[0x18];
4332 u8 reserved_at_40[0x40];
4334 union mlx5_ifc_hca_cap_union_bits capability;
4337 struct mlx5_ifc_query_hca_cap_in_bits {
4339 u8 reserved_at_10[0x10];
4341 u8 reserved_at_20[0x10];
4344 u8 reserved_at_40[0x40];
4347 struct mlx5_ifc_query_flow_table_out_bits {
4349 u8 reserved_at_8[0x18];
4353 u8 reserved_at_40[0x80];
4355 u8 reserved_at_c0[0x8];
4357 u8 reserved_at_d0[0x8];
4360 u8 reserved_at_e0[0x120];
4363 struct mlx5_ifc_query_flow_table_in_bits {
4365 u8 reserved_at_10[0x10];
4367 u8 reserved_at_20[0x10];
4370 u8 reserved_at_40[0x40];
4373 u8 reserved_at_88[0x18];
4375 u8 reserved_at_a0[0x8];
4378 u8 reserved_at_c0[0x140];
4381 struct mlx5_ifc_query_fte_out_bits {
4383 u8 reserved_at_8[0x18];
4387 u8 reserved_at_40[0x1c0];
4389 struct mlx5_ifc_flow_context_bits flow_context;
4392 struct mlx5_ifc_query_fte_in_bits {
4394 u8 reserved_at_10[0x10];
4396 u8 reserved_at_20[0x10];
4399 u8 reserved_at_40[0x40];
4402 u8 reserved_at_88[0x18];
4404 u8 reserved_at_a0[0x8];
4407 u8 reserved_at_c0[0x40];
4409 u8 flow_index[0x20];
4411 u8 reserved_at_120[0xe0];
4415 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4416 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4417 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4420 struct mlx5_ifc_query_flow_group_out_bits {
4422 u8 reserved_at_8[0x18];
4426 u8 reserved_at_40[0xa0];
4428 u8 start_flow_index[0x20];
4430 u8 reserved_at_100[0x20];
4432 u8 end_flow_index[0x20];
4434 u8 reserved_at_140[0xa0];
4436 u8 reserved_at_1e0[0x18];
4437 u8 match_criteria_enable[0x8];
4439 struct mlx5_ifc_fte_match_param_bits match_criteria;
4441 u8 reserved_at_1200[0xe00];
4444 struct mlx5_ifc_query_flow_group_in_bits {
4446 u8 reserved_at_10[0x10];
4448 u8 reserved_at_20[0x10];
4451 u8 reserved_at_40[0x40];
4454 u8 reserved_at_88[0x18];
4456 u8 reserved_at_a0[0x8];
4461 u8 reserved_at_e0[0x120];
4464 struct mlx5_ifc_query_flow_counter_out_bits {
4466 u8 reserved_at_8[0x18];
4470 u8 reserved_at_40[0x40];
4472 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4475 struct mlx5_ifc_query_flow_counter_in_bits {
4477 u8 reserved_at_10[0x10];
4479 u8 reserved_at_20[0x10];
4482 u8 reserved_at_40[0x80];
4485 u8 reserved_at_c1[0xf];
4486 u8 num_of_counters[0x10];
4488 u8 flow_counter_id[0x20];
4491 struct mlx5_ifc_query_esw_vport_context_out_bits {
4493 u8 reserved_at_8[0x18];
4497 u8 reserved_at_40[0x40];
4499 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4502 struct mlx5_ifc_query_esw_vport_context_in_bits {
4504 u8 reserved_at_10[0x10];
4506 u8 reserved_at_20[0x10];
4509 u8 other_vport[0x1];
4510 u8 reserved_at_41[0xf];
4511 u8 vport_number[0x10];
4513 u8 reserved_at_60[0x20];
4516 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4518 u8 reserved_at_8[0x18];
4522 u8 reserved_at_40[0x40];
4525 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4526 u8 reserved_at_0[0x1c];
4527 u8 vport_cvlan_insert[0x1];
4528 u8 vport_svlan_insert[0x1];
4529 u8 vport_cvlan_strip[0x1];
4530 u8 vport_svlan_strip[0x1];
4533 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4535 u8 reserved_at_10[0x10];
4537 u8 reserved_at_20[0x10];
4540 u8 other_vport[0x1];
4541 u8 reserved_at_41[0xf];
4542 u8 vport_number[0x10];
4544 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4546 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4549 struct mlx5_ifc_query_eq_out_bits {
4551 u8 reserved_at_8[0x18];
4555 u8 reserved_at_40[0x40];
4557 struct mlx5_ifc_eqc_bits eq_context_entry;
4559 u8 reserved_at_280[0x40];
4561 u8 event_bitmask[0x40];
4563 u8 reserved_at_300[0x580];
4568 struct mlx5_ifc_query_eq_in_bits {
4570 u8 reserved_at_10[0x10];
4572 u8 reserved_at_20[0x10];
4575 u8 reserved_at_40[0x18];
4578 u8 reserved_at_60[0x20];
4581 struct mlx5_ifc_encap_header_in_bits {
4582 u8 reserved_at_0[0x5];
4583 u8 header_type[0x3];
4584 u8 reserved_at_8[0xe];
4585 u8 encap_header_size[0xa];
4587 u8 reserved_at_20[0x10];
4588 u8 encap_header[2][0x8];
4590 u8 more_encap_header[0][0x8];
4593 struct mlx5_ifc_query_encap_header_out_bits {
4595 u8 reserved_at_8[0x18];
4599 u8 reserved_at_40[0xa0];
4601 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4604 struct mlx5_ifc_query_encap_header_in_bits {
4606 u8 reserved_at_10[0x10];
4608 u8 reserved_at_20[0x10];
4613 u8 reserved_at_60[0xa0];
4616 struct mlx5_ifc_alloc_encap_header_out_bits {
4618 u8 reserved_at_8[0x18];
4624 u8 reserved_at_60[0x20];
4627 struct mlx5_ifc_alloc_encap_header_in_bits {
4629 u8 reserved_at_10[0x10];
4631 u8 reserved_at_20[0x10];
4634 u8 reserved_at_40[0xa0];
4636 struct mlx5_ifc_encap_header_in_bits encap_header;
4639 struct mlx5_ifc_dealloc_encap_header_out_bits {
4641 u8 reserved_at_8[0x18];
4645 u8 reserved_at_40[0x40];
4648 struct mlx5_ifc_dealloc_encap_header_in_bits {
4650 u8 reserved_at_10[0x10];
4652 u8 reserved_20[0x10];
4657 u8 reserved_60[0x20];
4660 struct mlx5_ifc_set_action_in_bits {
4661 u8 action_type[0x4];
4663 u8 reserved_at_10[0x3];
4665 u8 reserved_at_18[0x3];
4671 struct mlx5_ifc_add_action_in_bits {
4672 u8 action_type[0x4];
4674 u8 reserved_at_10[0x10];
4679 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4680 struct mlx5_ifc_set_action_in_bits set_action_in;
4681 struct mlx5_ifc_add_action_in_bits add_action_in;
4682 u8 reserved_at_0[0x40];
4686 MLX5_ACTION_TYPE_SET = 0x1,
4687 MLX5_ACTION_TYPE_ADD = 0x2,
4691 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4692 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4693 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4694 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4695 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4696 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4697 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4698 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4699 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4700 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4701 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4702 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4703 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4704 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4705 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4706 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4707 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4708 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4709 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4710 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4711 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4712 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4713 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
4716 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4718 u8 reserved_at_8[0x18];
4722 u8 modify_header_id[0x20];
4724 u8 reserved_at_60[0x20];
4727 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4729 u8 reserved_at_10[0x10];
4731 u8 reserved_at_20[0x10];
4734 u8 reserved_at_40[0x20];
4737 u8 reserved_at_68[0x10];
4738 u8 num_of_actions[0x8];
4740 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4743 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4745 u8 reserved_at_8[0x18];
4749 u8 reserved_at_40[0x40];
4752 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4754 u8 reserved_at_10[0x10];
4756 u8 reserved_at_20[0x10];
4759 u8 modify_header_id[0x20];
4761 u8 reserved_at_60[0x20];
4764 struct mlx5_ifc_query_dct_out_bits {
4766 u8 reserved_at_8[0x18];
4770 u8 reserved_at_40[0x40];
4772 struct mlx5_ifc_dctc_bits dct_context_entry;
4774 u8 reserved_at_280[0x180];
4777 struct mlx5_ifc_query_dct_in_bits {
4779 u8 reserved_at_10[0x10];
4781 u8 reserved_at_20[0x10];
4784 u8 reserved_at_40[0x8];
4787 u8 reserved_at_60[0x20];
4790 struct mlx5_ifc_query_cq_out_bits {
4792 u8 reserved_at_8[0x18];
4796 u8 reserved_at_40[0x40];
4798 struct mlx5_ifc_cqc_bits cq_context;
4800 u8 reserved_at_280[0x600];
4805 struct mlx5_ifc_query_cq_in_bits {
4807 u8 reserved_at_10[0x10];
4809 u8 reserved_at_20[0x10];
4812 u8 reserved_at_40[0x8];
4815 u8 reserved_at_60[0x20];
4818 struct mlx5_ifc_query_cong_status_out_bits {
4820 u8 reserved_at_8[0x18];
4824 u8 reserved_at_40[0x20];
4828 u8 reserved_at_62[0x1e];
4831 struct mlx5_ifc_query_cong_status_in_bits {
4833 u8 reserved_at_10[0x10];
4835 u8 reserved_at_20[0x10];
4838 u8 reserved_at_40[0x18];
4840 u8 cong_protocol[0x4];
4842 u8 reserved_at_60[0x20];
4845 struct mlx5_ifc_query_cong_statistics_out_bits {
4847 u8 reserved_at_8[0x18];
4851 u8 reserved_at_40[0x40];
4853 u8 rp_cur_flows[0x20];
4857 u8 rp_cnp_ignored_high[0x20];
4859 u8 rp_cnp_ignored_low[0x20];
4861 u8 rp_cnp_handled_high[0x20];
4863 u8 rp_cnp_handled_low[0x20];
4865 u8 reserved_at_140[0x100];
4867 u8 time_stamp_high[0x20];
4869 u8 time_stamp_low[0x20];
4871 u8 accumulators_period[0x20];
4873 u8 np_ecn_marked_roce_packets_high[0x20];
4875 u8 np_ecn_marked_roce_packets_low[0x20];
4877 u8 np_cnp_sent_high[0x20];
4879 u8 np_cnp_sent_low[0x20];
4881 u8 reserved_at_320[0x560];
4884 struct mlx5_ifc_query_cong_statistics_in_bits {
4886 u8 reserved_at_10[0x10];
4888 u8 reserved_at_20[0x10];
4892 u8 reserved_at_41[0x1f];
4894 u8 reserved_at_60[0x20];
4897 struct mlx5_ifc_query_cong_params_out_bits {
4899 u8 reserved_at_8[0x18];
4903 u8 reserved_at_40[0x40];
4905 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4908 struct mlx5_ifc_query_cong_params_in_bits {
4910 u8 reserved_at_10[0x10];
4912 u8 reserved_at_20[0x10];
4915 u8 reserved_at_40[0x1c];
4916 u8 cong_protocol[0x4];
4918 u8 reserved_at_60[0x20];
4921 struct mlx5_ifc_query_adapter_out_bits {
4923 u8 reserved_at_8[0x18];
4927 u8 reserved_at_40[0x40];
4929 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4932 struct mlx5_ifc_query_adapter_in_bits {
4934 u8 reserved_at_10[0x10];
4936 u8 reserved_at_20[0x10];
4939 u8 reserved_at_40[0x40];
4942 struct mlx5_ifc_qp_2rst_out_bits {
4944 u8 reserved_at_8[0x18];
4948 u8 reserved_at_40[0x40];
4951 struct mlx5_ifc_qp_2rst_in_bits {
4953 u8 reserved_at_10[0x10];
4955 u8 reserved_at_20[0x10];
4958 u8 reserved_at_40[0x8];
4961 u8 reserved_at_60[0x20];
4964 struct mlx5_ifc_qp_2err_out_bits {
4966 u8 reserved_at_8[0x18];
4970 u8 reserved_at_40[0x40];
4973 struct mlx5_ifc_qp_2err_in_bits {
4975 u8 reserved_at_10[0x10];
4977 u8 reserved_at_20[0x10];
4980 u8 reserved_at_40[0x8];
4983 u8 reserved_at_60[0x20];
4986 struct mlx5_ifc_page_fault_resume_out_bits {
4988 u8 reserved_at_8[0x18];
4992 u8 reserved_at_40[0x40];
4995 struct mlx5_ifc_page_fault_resume_in_bits {
4997 u8 reserved_at_10[0x10];
4999 u8 reserved_at_20[0x10];
5003 u8 reserved_at_41[0x4];
5004 u8 page_fault_type[0x3];
5007 u8 reserved_at_60[0x8];
5011 struct mlx5_ifc_nop_out_bits {
5013 u8 reserved_at_8[0x18];
5017 u8 reserved_at_40[0x40];
5020 struct mlx5_ifc_nop_in_bits {
5022 u8 reserved_at_10[0x10];
5024 u8 reserved_at_20[0x10];
5027 u8 reserved_at_40[0x40];
5030 struct mlx5_ifc_modify_vport_state_out_bits {
5032 u8 reserved_at_8[0x18];
5036 u8 reserved_at_40[0x40];
5039 struct mlx5_ifc_modify_vport_state_in_bits {
5041 u8 reserved_at_10[0x10];
5043 u8 reserved_at_20[0x10];
5046 u8 other_vport[0x1];
5047 u8 reserved_at_41[0xf];
5048 u8 vport_number[0x10];
5050 u8 reserved_at_60[0x18];
5051 u8 admin_state[0x4];
5052 u8 reserved_at_7c[0x4];
5055 struct mlx5_ifc_modify_tis_out_bits {
5057 u8 reserved_at_8[0x18];
5061 u8 reserved_at_40[0x40];
5064 struct mlx5_ifc_modify_tis_bitmask_bits {
5065 u8 reserved_at_0[0x20];
5067 u8 reserved_at_20[0x1d];
5068 u8 lag_tx_port_affinity[0x1];
5069 u8 strict_lag_tx_port_affinity[0x1];
5073 struct mlx5_ifc_modify_tis_in_bits {
5075 u8 reserved_at_10[0x10];
5077 u8 reserved_at_20[0x10];
5080 u8 reserved_at_40[0x8];
5083 u8 reserved_at_60[0x20];
5085 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5087 u8 reserved_at_c0[0x40];
5089 struct mlx5_ifc_tisc_bits ctx;
5092 struct mlx5_ifc_modify_tir_bitmask_bits {
5093 u8 reserved_at_0[0x20];
5095 u8 reserved_at_20[0x1b];
5097 u8 reserved_at_3c[0x1];
5099 u8 reserved_at_3e[0x1];
5103 struct mlx5_ifc_modify_tir_out_bits {
5105 u8 reserved_at_8[0x18];
5109 u8 reserved_at_40[0x40];
5112 struct mlx5_ifc_modify_tir_in_bits {
5114 u8 reserved_at_10[0x10];
5116 u8 reserved_at_20[0x10];
5119 u8 reserved_at_40[0x8];
5122 u8 reserved_at_60[0x20];
5124 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5126 u8 reserved_at_c0[0x40];
5128 struct mlx5_ifc_tirc_bits ctx;
5131 struct mlx5_ifc_modify_sq_out_bits {
5133 u8 reserved_at_8[0x18];
5137 u8 reserved_at_40[0x40];
5140 struct mlx5_ifc_modify_sq_in_bits {
5142 u8 reserved_at_10[0x10];
5144 u8 reserved_at_20[0x10];
5148 u8 reserved_at_44[0x4];
5151 u8 reserved_at_60[0x20];
5153 u8 modify_bitmask[0x40];
5155 u8 reserved_at_c0[0x40];
5157 struct mlx5_ifc_sqc_bits ctx;
5160 struct mlx5_ifc_modify_scheduling_element_out_bits {
5162 u8 reserved_at_8[0x18];
5166 u8 reserved_at_40[0x1c0];
5170 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5171 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5174 struct mlx5_ifc_modify_scheduling_element_in_bits {
5176 u8 reserved_at_10[0x10];
5178 u8 reserved_at_20[0x10];
5181 u8 scheduling_hierarchy[0x8];
5182 u8 reserved_at_48[0x18];
5184 u8 scheduling_element_id[0x20];
5186 u8 reserved_at_80[0x20];
5188 u8 modify_bitmask[0x20];
5190 u8 reserved_at_c0[0x40];
5192 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5194 u8 reserved_at_300[0x100];
5197 struct mlx5_ifc_modify_rqt_out_bits {
5199 u8 reserved_at_8[0x18];
5203 u8 reserved_at_40[0x40];
5206 struct mlx5_ifc_rqt_bitmask_bits {
5207 u8 reserved_at_0[0x20];
5209 u8 reserved_at_20[0x1f];
5213 struct mlx5_ifc_modify_rqt_in_bits {
5215 u8 reserved_at_10[0x10];
5217 u8 reserved_at_20[0x10];
5220 u8 reserved_at_40[0x8];
5223 u8 reserved_at_60[0x20];
5225 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5227 u8 reserved_at_c0[0x40];
5229 struct mlx5_ifc_rqtc_bits ctx;
5232 struct mlx5_ifc_modify_rq_out_bits {
5234 u8 reserved_at_8[0x18];
5238 u8 reserved_at_40[0x40];
5242 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5243 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5244 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5247 struct mlx5_ifc_modify_rq_in_bits {
5249 u8 reserved_at_10[0x10];
5251 u8 reserved_at_20[0x10];
5255 u8 reserved_at_44[0x4];
5258 u8 reserved_at_60[0x20];
5260 u8 modify_bitmask[0x40];
5262 u8 reserved_at_c0[0x40];
5264 struct mlx5_ifc_rqc_bits ctx;
5267 struct mlx5_ifc_modify_rmp_out_bits {
5269 u8 reserved_at_8[0x18];
5273 u8 reserved_at_40[0x40];
5276 struct mlx5_ifc_rmp_bitmask_bits {
5277 u8 reserved_at_0[0x20];
5279 u8 reserved_at_20[0x1f];
5283 struct mlx5_ifc_modify_rmp_in_bits {
5285 u8 reserved_at_10[0x10];
5287 u8 reserved_at_20[0x10];
5291 u8 reserved_at_44[0x4];
5294 u8 reserved_at_60[0x20];
5296 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5298 u8 reserved_at_c0[0x40];
5300 struct mlx5_ifc_rmpc_bits ctx;
5303 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5305 u8 reserved_at_8[0x18];
5309 u8 reserved_at_40[0x40];
5312 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5313 u8 reserved_at_0[0x14];
5314 u8 disable_uc_local_lb[0x1];
5315 u8 disable_mc_local_lb[0x1];
5320 u8 change_event[0x1];
5322 u8 permanent_address[0x1];
5323 u8 addresses_list[0x1];
5325 u8 reserved_at_1f[0x1];
5328 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5330 u8 reserved_at_10[0x10];
5332 u8 reserved_at_20[0x10];
5335 u8 other_vport[0x1];
5336 u8 reserved_at_41[0xf];
5337 u8 vport_number[0x10];
5339 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5341 u8 reserved_at_80[0x780];
5343 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5346 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5348 u8 reserved_at_8[0x18];
5352 u8 reserved_at_40[0x40];
5355 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5357 u8 reserved_at_10[0x10];
5359 u8 reserved_at_20[0x10];
5362 u8 other_vport[0x1];
5363 u8 reserved_at_41[0xb];
5365 u8 vport_number[0x10];
5367 u8 reserved_at_60[0x20];
5369 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5372 struct mlx5_ifc_modify_cq_out_bits {
5374 u8 reserved_at_8[0x18];
5378 u8 reserved_at_40[0x40];
5382 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5383 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5386 struct mlx5_ifc_modify_cq_in_bits {
5388 u8 reserved_at_10[0x10];
5390 u8 reserved_at_20[0x10];
5393 u8 reserved_at_40[0x8];
5396 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5398 struct mlx5_ifc_cqc_bits cq_context;
5400 u8 reserved_at_280[0x600];
5405 struct mlx5_ifc_modify_cong_status_out_bits {
5407 u8 reserved_at_8[0x18];
5411 u8 reserved_at_40[0x40];
5414 struct mlx5_ifc_modify_cong_status_in_bits {
5416 u8 reserved_at_10[0x10];
5418 u8 reserved_at_20[0x10];
5421 u8 reserved_at_40[0x18];
5423 u8 cong_protocol[0x4];
5427 u8 reserved_at_62[0x1e];
5430 struct mlx5_ifc_modify_cong_params_out_bits {
5432 u8 reserved_at_8[0x18];
5436 u8 reserved_at_40[0x40];
5439 struct mlx5_ifc_modify_cong_params_in_bits {
5441 u8 reserved_at_10[0x10];
5443 u8 reserved_at_20[0x10];
5446 u8 reserved_at_40[0x1c];
5447 u8 cong_protocol[0x4];
5449 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5451 u8 reserved_at_80[0x80];
5453 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5456 struct mlx5_ifc_manage_pages_out_bits {
5458 u8 reserved_at_8[0x18];
5462 u8 output_num_entries[0x20];
5464 u8 reserved_at_60[0x20];
5470 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5471 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5472 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5475 struct mlx5_ifc_manage_pages_in_bits {
5477 u8 reserved_at_10[0x10];
5479 u8 reserved_at_20[0x10];
5482 u8 reserved_at_40[0x10];
5483 u8 function_id[0x10];
5485 u8 input_num_entries[0x20];
5490 struct mlx5_ifc_mad_ifc_out_bits {
5492 u8 reserved_at_8[0x18];
5496 u8 reserved_at_40[0x40];
5498 u8 response_mad_packet[256][0x8];
5501 struct mlx5_ifc_mad_ifc_in_bits {
5503 u8 reserved_at_10[0x10];
5505 u8 reserved_at_20[0x10];
5508 u8 remote_lid[0x10];
5509 u8 reserved_at_50[0x8];
5512 u8 reserved_at_60[0x20];
5517 struct mlx5_ifc_init_hca_out_bits {
5519 u8 reserved_at_8[0x18];
5523 u8 reserved_at_40[0x40];
5526 struct mlx5_ifc_init_hca_in_bits {
5528 u8 reserved_at_10[0x10];
5530 u8 reserved_at_20[0x10];
5533 u8 reserved_at_40[0x40];
5536 struct mlx5_ifc_init2rtr_qp_out_bits {
5538 u8 reserved_at_8[0x18];
5542 u8 reserved_at_40[0x40];
5545 struct mlx5_ifc_init2rtr_qp_in_bits {
5547 u8 reserved_at_10[0x10];
5549 u8 reserved_at_20[0x10];
5552 u8 reserved_at_40[0x8];
5555 u8 reserved_at_60[0x20];
5557 u8 opt_param_mask[0x20];
5559 u8 reserved_at_a0[0x20];
5561 struct mlx5_ifc_qpc_bits qpc;
5563 u8 reserved_at_800[0x80];
5566 struct mlx5_ifc_init2init_qp_out_bits {
5568 u8 reserved_at_8[0x18];
5572 u8 reserved_at_40[0x40];
5575 struct mlx5_ifc_init2init_qp_in_bits {
5577 u8 reserved_at_10[0x10];
5579 u8 reserved_at_20[0x10];
5582 u8 reserved_at_40[0x8];
5585 u8 reserved_at_60[0x20];
5587 u8 opt_param_mask[0x20];
5589 u8 reserved_at_a0[0x20];
5591 struct mlx5_ifc_qpc_bits qpc;
5593 u8 reserved_at_800[0x80];
5596 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5598 u8 reserved_at_8[0x18];
5602 u8 reserved_at_40[0x40];
5604 u8 packet_headers_log[128][0x8];
5606 u8 packet_syndrome[64][0x8];
5609 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5611 u8 reserved_at_10[0x10];
5613 u8 reserved_at_20[0x10];
5616 u8 reserved_at_40[0x40];
5619 struct mlx5_ifc_gen_eqe_in_bits {
5621 u8 reserved_at_10[0x10];
5623 u8 reserved_at_20[0x10];
5626 u8 reserved_at_40[0x18];
5629 u8 reserved_at_60[0x20];
5634 struct mlx5_ifc_gen_eq_out_bits {
5636 u8 reserved_at_8[0x18];
5640 u8 reserved_at_40[0x40];
5643 struct mlx5_ifc_enable_hca_out_bits {
5645 u8 reserved_at_8[0x18];
5649 u8 reserved_at_40[0x20];
5652 struct mlx5_ifc_enable_hca_in_bits {
5654 u8 reserved_at_10[0x10];
5656 u8 reserved_at_20[0x10];
5659 u8 reserved_at_40[0x10];
5660 u8 function_id[0x10];
5662 u8 reserved_at_60[0x20];
5665 struct mlx5_ifc_drain_dct_out_bits {
5667 u8 reserved_at_8[0x18];
5671 u8 reserved_at_40[0x40];
5674 struct mlx5_ifc_drain_dct_in_bits {
5676 u8 reserved_at_10[0x10];
5678 u8 reserved_at_20[0x10];
5681 u8 reserved_at_40[0x8];
5684 u8 reserved_at_60[0x20];
5687 struct mlx5_ifc_disable_hca_out_bits {
5689 u8 reserved_at_8[0x18];
5693 u8 reserved_at_40[0x20];
5696 struct mlx5_ifc_disable_hca_in_bits {
5698 u8 reserved_at_10[0x10];
5700 u8 reserved_at_20[0x10];
5703 u8 reserved_at_40[0x10];
5704 u8 function_id[0x10];
5706 u8 reserved_at_60[0x20];
5709 struct mlx5_ifc_detach_from_mcg_out_bits {
5711 u8 reserved_at_8[0x18];
5715 u8 reserved_at_40[0x40];
5718 struct mlx5_ifc_detach_from_mcg_in_bits {
5720 u8 reserved_at_10[0x10];
5722 u8 reserved_at_20[0x10];
5725 u8 reserved_at_40[0x8];
5728 u8 reserved_at_60[0x20];
5730 u8 multicast_gid[16][0x8];
5733 struct mlx5_ifc_destroy_xrq_out_bits {
5735 u8 reserved_at_8[0x18];
5739 u8 reserved_at_40[0x40];
5742 struct mlx5_ifc_destroy_xrq_in_bits {
5744 u8 reserved_at_10[0x10];
5746 u8 reserved_at_20[0x10];
5749 u8 reserved_at_40[0x8];
5752 u8 reserved_at_60[0x20];
5755 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5757 u8 reserved_at_8[0x18];
5761 u8 reserved_at_40[0x40];
5764 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5766 u8 reserved_at_10[0x10];
5768 u8 reserved_at_20[0x10];
5771 u8 reserved_at_40[0x8];
5774 u8 reserved_at_60[0x20];
5777 struct mlx5_ifc_destroy_tis_out_bits {
5779 u8 reserved_at_8[0x18];
5783 u8 reserved_at_40[0x40];
5786 struct mlx5_ifc_destroy_tis_in_bits {
5788 u8 reserved_at_10[0x10];
5790 u8 reserved_at_20[0x10];
5793 u8 reserved_at_40[0x8];
5796 u8 reserved_at_60[0x20];
5799 struct mlx5_ifc_destroy_tir_out_bits {
5801 u8 reserved_at_8[0x18];
5805 u8 reserved_at_40[0x40];
5808 struct mlx5_ifc_destroy_tir_in_bits {
5810 u8 reserved_at_10[0x10];
5812 u8 reserved_at_20[0x10];
5815 u8 reserved_at_40[0x8];
5818 u8 reserved_at_60[0x20];
5821 struct mlx5_ifc_destroy_srq_out_bits {
5823 u8 reserved_at_8[0x18];
5827 u8 reserved_at_40[0x40];
5830 struct mlx5_ifc_destroy_srq_in_bits {
5832 u8 reserved_at_10[0x10];
5834 u8 reserved_at_20[0x10];
5837 u8 reserved_at_40[0x8];
5840 u8 reserved_at_60[0x20];
5843 struct mlx5_ifc_destroy_sq_out_bits {
5845 u8 reserved_at_8[0x18];
5849 u8 reserved_at_40[0x40];
5852 struct mlx5_ifc_destroy_sq_in_bits {
5854 u8 reserved_at_10[0x10];
5856 u8 reserved_at_20[0x10];
5859 u8 reserved_at_40[0x8];
5862 u8 reserved_at_60[0x20];
5865 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5867 u8 reserved_at_8[0x18];
5871 u8 reserved_at_40[0x1c0];
5874 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5876 u8 reserved_at_10[0x10];
5878 u8 reserved_at_20[0x10];
5881 u8 scheduling_hierarchy[0x8];
5882 u8 reserved_at_48[0x18];
5884 u8 scheduling_element_id[0x20];
5886 u8 reserved_at_80[0x180];
5889 struct mlx5_ifc_destroy_rqt_out_bits {
5891 u8 reserved_at_8[0x18];
5895 u8 reserved_at_40[0x40];
5898 struct mlx5_ifc_destroy_rqt_in_bits {
5900 u8 reserved_at_10[0x10];
5902 u8 reserved_at_20[0x10];
5905 u8 reserved_at_40[0x8];
5908 u8 reserved_at_60[0x20];
5911 struct mlx5_ifc_destroy_rq_out_bits {
5913 u8 reserved_at_8[0x18];
5917 u8 reserved_at_40[0x40];
5920 struct mlx5_ifc_destroy_rq_in_bits {
5922 u8 reserved_at_10[0x10];
5924 u8 reserved_at_20[0x10];
5927 u8 reserved_at_40[0x8];
5930 u8 reserved_at_60[0x20];
5933 struct mlx5_ifc_set_delay_drop_params_in_bits {
5935 u8 reserved_at_10[0x10];
5937 u8 reserved_at_20[0x10];
5940 u8 reserved_at_40[0x20];
5942 u8 reserved_at_60[0x10];
5943 u8 delay_drop_timeout[0x10];
5946 struct mlx5_ifc_set_delay_drop_params_out_bits {
5948 u8 reserved_at_8[0x18];
5952 u8 reserved_at_40[0x40];
5955 struct mlx5_ifc_destroy_rmp_out_bits {
5957 u8 reserved_at_8[0x18];
5961 u8 reserved_at_40[0x40];
5964 struct mlx5_ifc_destroy_rmp_in_bits {
5966 u8 reserved_at_10[0x10];
5968 u8 reserved_at_20[0x10];
5971 u8 reserved_at_40[0x8];
5974 u8 reserved_at_60[0x20];
5977 struct mlx5_ifc_destroy_qp_out_bits {
5979 u8 reserved_at_8[0x18];
5983 u8 reserved_at_40[0x40];
5986 struct mlx5_ifc_destroy_qp_in_bits {
5988 u8 reserved_at_10[0x10];
5990 u8 reserved_at_20[0x10];
5993 u8 reserved_at_40[0x8];
5996 u8 reserved_at_60[0x20];
5999 struct mlx5_ifc_destroy_psv_out_bits {
6001 u8 reserved_at_8[0x18];
6005 u8 reserved_at_40[0x40];
6008 struct mlx5_ifc_destroy_psv_in_bits {
6010 u8 reserved_at_10[0x10];
6012 u8 reserved_at_20[0x10];
6015 u8 reserved_at_40[0x8];
6018 u8 reserved_at_60[0x20];
6021 struct mlx5_ifc_destroy_mkey_out_bits {
6023 u8 reserved_at_8[0x18];
6027 u8 reserved_at_40[0x40];
6030 struct mlx5_ifc_destroy_mkey_in_bits {
6032 u8 reserved_at_10[0x10];
6034 u8 reserved_at_20[0x10];
6037 u8 reserved_at_40[0x8];
6038 u8 mkey_index[0x18];
6040 u8 reserved_at_60[0x20];
6043 struct mlx5_ifc_destroy_flow_table_out_bits {
6045 u8 reserved_at_8[0x18];
6049 u8 reserved_at_40[0x40];
6052 struct mlx5_ifc_destroy_flow_table_in_bits {
6054 u8 reserved_at_10[0x10];
6056 u8 reserved_at_20[0x10];
6059 u8 other_vport[0x1];
6060 u8 reserved_at_41[0xf];
6061 u8 vport_number[0x10];
6063 u8 reserved_at_60[0x20];
6066 u8 reserved_at_88[0x18];
6068 u8 reserved_at_a0[0x8];
6071 u8 reserved_at_c0[0x140];
6074 struct mlx5_ifc_destroy_flow_group_out_bits {
6076 u8 reserved_at_8[0x18];
6080 u8 reserved_at_40[0x40];
6083 struct mlx5_ifc_destroy_flow_group_in_bits {
6085 u8 reserved_at_10[0x10];
6087 u8 reserved_at_20[0x10];
6090 u8 other_vport[0x1];
6091 u8 reserved_at_41[0xf];
6092 u8 vport_number[0x10];
6094 u8 reserved_at_60[0x20];
6097 u8 reserved_at_88[0x18];
6099 u8 reserved_at_a0[0x8];
6104 u8 reserved_at_e0[0x120];
6107 struct mlx5_ifc_destroy_eq_out_bits {
6109 u8 reserved_at_8[0x18];
6113 u8 reserved_at_40[0x40];
6116 struct mlx5_ifc_destroy_eq_in_bits {
6118 u8 reserved_at_10[0x10];
6120 u8 reserved_at_20[0x10];
6123 u8 reserved_at_40[0x18];
6126 u8 reserved_at_60[0x20];
6129 struct mlx5_ifc_destroy_dct_out_bits {
6131 u8 reserved_at_8[0x18];
6135 u8 reserved_at_40[0x40];
6138 struct mlx5_ifc_destroy_dct_in_bits {
6140 u8 reserved_at_10[0x10];
6142 u8 reserved_at_20[0x10];
6145 u8 reserved_at_40[0x8];
6148 u8 reserved_at_60[0x20];
6151 struct mlx5_ifc_destroy_cq_out_bits {
6153 u8 reserved_at_8[0x18];
6157 u8 reserved_at_40[0x40];
6160 struct mlx5_ifc_destroy_cq_in_bits {
6162 u8 reserved_at_10[0x10];
6164 u8 reserved_at_20[0x10];
6167 u8 reserved_at_40[0x8];
6170 u8 reserved_at_60[0x20];
6173 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6175 u8 reserved_at_8[0x18];
6179 u8 reserved_at_40[0x40];
6182 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6184 u8 reserved_at_10[0x10];
6186 u8 reserved_at_20[0x10];
6189 u8 reserved_at_40[0x20];
6191 u8 reserved_at_60[0x10];
6192 u8 vxlan_udp_port[0x10];
6195 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6197 u8 reserved_at_8[0x18];
6201 u8 reserved_at_40[0x40];
6204 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6206 u8 reserved_at_10[0x10];
6208 u8 reserved_at_20[0x10];
6211 u8 reserved_at_40[0x60];
6213 u8 reserved_at_a0[0x8];
6214 u8 table_index[0x18];
6216 u8 reserved_at_c0[0x140];
6219 struct mlx5_ifc_delete_fte_out_bits {
6221 u8 reserved_at_8[0x18];
6225 u8 reserved_at_40[0x40];
6228 struct mlx5_ifc_delete_fte_in_bits {
6230 u8 reserved_at_10[0x10];
6232 u8 reserved_at_20[0x10];
6235 u8 other_vport[0x1];
6236 u8 reserved_at_41[0xf];
6237 u8 vport_number[0x10];
6239 u8 reserved_at_60[0x20];
6242 u8 reserved_at_88[0x18];
6244 u8 reserved_at_a0[0x8];
6247 u8 reserved_at_c0[0x40];
6249 u8 flow_index[0x20];
6251 u8 reserved_at_120[0xe0];
6254 struct mlx5_ifc_dealloc_xrcd_out_bits {
6256 u8 reserved_at_8[0x18];
6260 u8 reserved_at_40[0x40];
6263 struct mlx5_ifc_dealloc_xrcd_in_bits {
6265 u8 reserved_at_10[0x10];
6267 u8 reserved_at_20[0x10];
6270 u8 reserved_at_40[0x8];
6273 u8 reserved_at_60[0x20];
6276 struct mlx5_ifc_dealloc_uar_out_bits {
6278 u8 reserved_at_8[0x18];
6282 u8 reserved_at_40[0x40];
6285 struct mlx5_ifc_dealloc_uar_in_bits {
6287 u8 reserved_at_10[0x10];
6289 u8 reserved_at_20[0x10];
6292 u8 reserved_at_40[0x8];
6295 u8 reserved_at_60[0x20];
6298 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6300 u8 reserved_at_8[0x18];
6304 u8 reserved_at_40[0x40];
6307 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6309 u8 reserved_at_10[0x10];
6311 u8 reserved_at_20[0x10];
6314 u8 reserved_at_40[0x8];
6315 u8 transport_domain[0x18];
6317 u8 reserved_at_60[0x20];
6320 struct mlx5_ifc_dealloc_q_counter_out_bits {
6322 u8 reserved_at_8[0x18];
6326 u8 reserved_at_40[0x40];
6329 struct mlx5_ifc_dealloc_q_counter_in_bits {
6331 u8 reserved_at_10[0x10];
6333 u8 reserved_at_20[0x10];
6336 u8 reserved_at_40[0x18];
6337 u8 counter_set_id[0x8];
6339 u8 reserved_at_60[0x20];
6342 struct mlx5_ifc_dealloc_pd_out_bits {
6344 u8 reserved_at_8[0x18];
6348 u8 reserved_at_40[0x40];
6351 struct mlx5_ifc_dealloc_pd_in_bits {
6353 u8 reserved_at_10[0x10];
6355 u8 reserved_at_20[0x10];
6358 u8 reserved_at_40[0x8];
6361 u8 reserved_at_60[0x20];
6364 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6366 u8 reserved_at_8[0x18];
6370 u8 reserved_at_40[0x40];
6373 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6375 u8 reserved_at_10[0x10];
6377 u8 reserved_at_20[0x10];
6380 u8 flow_counter_id[0x20];
6382 u8 reserved_at_60[0x20];
6385 struct mlx5_ifc_create_xrq_out_bits {
6387 u8 reserved_at_8[0x18];
6391 u8 reserved_at_40[0x8];
6394 u8 reserved_at_60[0x20];
6397 struct mlx5_ifc_create_xrq_in_bits {
6399 u8 reserved_at_10[0x10];
6401 u8 reserved_at_20[0x10];
6404 u8 reserved_at_40[0x40];
6406 struct mlx5_ifc_xrqc_bits xrq_context;
6409 struct mlx5_ifc_create_xrc_srq_out_bits {
6411 u8 reserved_at_8[0x18];
6415 u8 reserved_at_40[0x8];
6418 u8 reserved_at_60[0x20];
6421 struct mlx5_ifc_create_xrc_srq_in_bits {
6423 u8 reserved_at_10[0x10];
6425 u8 reserved_at_20[0x10];
6428 u8 reserved_at_40[0x40];
6430 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6432 u8 reserved_at_280[0x600];
6437 struct mlx5_ifc_create_tis_out_bits {
6439 u8 reserved_at_8[0x18];
6443 u8 reserved_at_40[0x8];
6446 u8 reserved_at_60[0x20];
6449 struct mlx5_ifc_create_tis_in_bits {
6451 u8 reserved_at_10[0x10];
6453 u8 reserved_at_20[0x10];
6456 u8 reserved_at_40[0xc0];
6458 struct mlx5_ifc_tisc_bits ctx;
6461 struct mlx5_ifc_create_tir_out_bits {
6463 u8 reserved_at_8[0x18];
6467 u8 reserved_at_40[0x8];
6470 u8 reserved_at_60[0x20];
6473 struct mlx5_ifc_create_tir_in_bits {
6475 u8 reserved_at_10[0x10];
6477 u8 reserved_at_20[0x10];
6480 u8 reserved_at_40[0xc0];
6482 struct mlx5_ifc_tirc_bits ctx;
6485 struct mlx5_ifc_create_srq_out_bits {
6487 u8 reserved_at_8[0x18];
6491 u8 reserved_at_40[0x8];
6494 u8 reserved_at_60[0x20];
6497 struct mlx5_ifc_create_srq_in_bits {
6499 u8 reserved_at_10[0x10];
6501 u8 reserved_at_20[0x10];
6504 u8 reserved_at_40[0x40];
6506 struct mlx5_ifc_srqc_bits srq_context_entry;
6508 u8 reserved_at_280[0x600];
6513 struct mlx5_ifc_create_sq_out_bits {
6515 u8 reserved_at_8[0x18];
6519 u8 reserved_at_40[0x8];
6522 u8 reserved_at_60[0x20];
6525 struct mlx5_ifc_create_sq_in_bits {
6527 u8 reserved_at_10[0x10];
6529 u8 reserved_at_20[0x10];
6532 u8 reserved_at_40[0xc0];
6534 struct mlx5_ifc_sqc_bits ctx;
6537 struct mlx5_ifc_create_scheduling_element_out_bits {
6539 u8 reserved_at_8[0x18];
6543 u8 reserved_at_40[0x40];
6545 u8 scheduling_element_id[0x20];
6547 u8 reserved_at_a0[0x160];
6550 struct mlx5_ifc_create_scheduling_element_in_bits {
6552 u8 reserved_at_10[0x10];
6554 u8 reserved_at_20[0x10];
6557 u8 scheduling_hierarchy[0x8];
6558 u8 reserved_at_48[0x18];
6560 u8 reserved_at_60[0xa0];
6562 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6564 u8 reserved_at_300[0x100];
6567 struct mlx5_ifc_create_rqt_out_bits {
6569 u8 reserved_at_8[0x18];
6573 u8 reserved_at_40[0x8];
6576 u8 reserved_at_60[0x20];
6579 struct mlx5_ifc_create_rqt_in_bits {
6581 u8 reserved_at_10[0x10];
6583 u8 reserved_at_20[0x10];
6586 u8 reserved_at_40[0xc0];
6588 struct mlx5_ifc_rqtc_bits rqt_context;
6591 struct mlx5_ifc_create_rq_out_bits {
6593 u8 reserved_at_8[0x18];
6597 u8 reserved_at_40[0x8];
6600 u8 reserved_at_60[0x20];
6603 struct mlx5_ifc_create_rq_in_bits {
6605 u8 reserved_at_10[0x10];
6607 u8 reserved_at_20[0x10];
6610 u8 reserved_at_40[0xc0];
6612 struct mlx5_ifc_rqc_bits ctx;
6615 struct mlx5_ifc_create_rmp_out_bits {
6617 u8 reserved_at_8[0x18];
6621 u8 reserved_at_40[0x8];
6624 u8 reserved_at_60[0x20];
6627 struct mlx5_ifc_create_rmp_in_bits {
6629 u8 reserved_at_10[0x10];
6631 u8 reserved_at_20[0x10];
6634 u8 reserved_at_40[0xc0];
6636 struct mlx5_ifc_rmpc_bits ctx;
6639 struct mlx5_ifc_create_qp_out_bits {
6641 u8 reserved_at_8[0x18];
6645 u8 reserved_at_40[0x8];
6648 u8 reserved_at_60[0x20];
6651 struct mlx5_ifc_create_qp_in_bits {
6653 u8 reserved_at_10[0x10];
6655 u8 reserved_at_20[0x10];
6658 u8 reserved_at_40[0x40];
6660 u8 opt_param_mask[0x20];
6662 u8 reserved_at_a0[0x20];
6664 struct mlx5_ifc_qpc_bits qpc;
6666 u8 reserved_at_800[0x80];
6671 struct mlx5_ifc_create_psv_out_bits {
6673 u8 reserved_at_8[0x18];
6677 u8 reserved_at_40[0x40];
6679 u8 reserved_at_80[0x8];
6680 u8 psv0_index[0x18];
6682 u8 reserved_at_a0[0x8];
6683 u8 psv1_index[0x18];
6685 u8 reserved_at_c0[0x8];
6686 u8 psv2_index[0x18];
6688 u8 reserved_at_e0[0x8];
6689 u8 psv3_index[0x18];
6692 struct mlx5_ifc_create_psv_in_bits {
6694 u8 reserved_at_10[0x10];
6696 u8 reserved_at_20[0x10];
6700 u8 reserved_at_44[0x4];
6703 u8 reserved_at_60[0x20];
6706 struct mlx5_ifc_create_mkey_out_bits {
6708 u8 reserved_at_8[0x18];
6712 u8 reserved_at_40[0x8];
6713 u8 mkey_index[0x18];
6715 u8 reserved_at_60[0x20];
6718 struct mlx5_ifc_create_mkey_in_bits {
6720 u8 reserved_at_10[0x10];
6722 u8 reserved_at_20[0x10];
6725 u8 reserved_at_40[0x20];
6728 u8 reserved_at_61[0x1f];
6730 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6732 u8 reserved_at_280[0x80];
6734 u8 translations_octword_actual_size[0x20];
6736 u8 reserved_at_320[0x560];
6738 u8 klm_pas_mtt[0][0x20];
6741 struct mlx5_ifc_create_flow_table_out_bits {
6743 u8 reserved_at_8[0x18];
6747 u8 reserved_at_40[0x8];
6750 u8 reserved_at_60[0x20];
6753 struct mlx5_ifc_flow_table_context_bits {
6756 u8 reserved_at_2[0x2];
6757 u8 table_miss_action[0x4];
6759 u8 reserved_at_10[0x8];
6762 u8 reserved_at_20[0x8];
6763 u8 table_miss_id[0x18];
6765 u8 reserved_at_40[0x8];
6766 u8 lag_master_next_table_id[0x18];
6768 u8 reserved_at_60[0xe0];
6771 struct mlx5_ifc_create_flow_table_in_bits {
6773 u8 reserved_at_10[0x10];
6775 u8 reserved_at_20[0x10];
6778 u8 other_vport[0x1];
6779 u8 reserved_at_41[0xf];
6780 u8 vport_number[0x10];
6782 u8 reserved_at_60[0x20];
6785 u8 reserved_at_88[0x18];
6787 u8 reserved_at_a0[0x20];
6789 struct mlx5_ifc_flow_table_context_bits flow_table_context;
6792 struct mlx5_ifc_create_flow_group_out_bits {
6794 u8 reserved_at_8[0x18];
6798 u8 reserved_at_40[0x8];
6801 u8 reserved_at_60[0x20];
6805 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6806 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6807 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6810 struct mlx5_ifc_create_flow_group_in_bits {
6812 u8 reserved_at_10[0x10];
6814 u8 reserved_at_20[0x10];
6817 u8 other_vport[0x1];
6818 u8 reserved_at_41[0xf];
6819 u8 vport_number[0x10];
6821 u8 reserved_at_60[0x20];
6824 u8 reserved_at_88[0x18];
6826 u8 reserved_at_a0[0x8];
6829 u8 reserved_at_c0[0x20];
6831 u8 start_flow_index[0x20];
6833 u8 reserved_at_100[0x20];
6835 u8 end_flow_index[0x20];
6837 u8 reserved_at_140[0xa0];
6839 u8 reserved_at_1e0[0x18];
6840 u8 match_criteria_enable[0x8];
6842 struct mlx5_ifc_fte_match_param_bits match_criteria;
6844 u8 reserved_at_1200[0xe00];
6847 struct mlx5_ifc_create_eq_out_bits {
6849 u8 reserved_at_8[0x18];
6853 u8 reserved_at_40[0x18];
6856 u8 reserved_at_60[0x20];
6859 struct mlx5_ifc_create_eq_in_bits {
6861 u8 reserved_at_10[0x10];
6863 u8 reserved_at_20[0x10];
6866 u8 reserved_at_40[0x40];
6868 struct mlx5_ifc_eqc_bits eq_context_entry;
6870 u8 reserved_at_280[0x40];
6872 u8 event_bitmask[0x40];
6874 u8 reserved_at_300[0x580];
6879 struct mlx5_ifc_create_dct_out_bits {
6881 u8 reserved_at_8[0x18];
6885 u8 reserved_at_40[0x8];
6888 u8 reserved_at_60[0x20];
6891 struct mlx5_ifc_create_dct_in_bits {
6893 u8 reserved_at_10[0x10];
6895 u8 reserved_at_20[0x10];
6898 u8 reserved_at_40[0x40];
6900 struct mlx5_ifc_dctc_bits dct_context_entry;
6902 u8 reserved_at_280[0x180];
6905 struct mlx5_ifc_create_cq_out_bits {
6907 u8 reserved_at_8[0x18];
6911 u8 reserved_at_40[0x8];
6914 u8 reserved_at_60[0x20];
6917 struct mlx5_ifc_create_cq_in_bits {
6919 u8 reserved_at_10[0x10];
6921 u8 reserved_at_20[0x10];
6924 u8 reserved_at_40[0x40];
6926 struct mlx5_ifc_cqc_bits cq_context;
6928 u8 reserved_at_280[0x600];
6933 struct mlx5_ifc_config_int_moderation_out_bits {
6935 u8 reserved_at_8[0x18];
6939 u8 reserved_at_40[0x4];
6941 u8 int_vector[0x10];
6943 u8 reserved_at_60[0x20];
6947 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6948 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6951 struct mlx5_ifc_config_int_moderation_in_bits {
6953 u8 reserved_at_10[0x10];
6955 u8 reserved_at_20[0x10];
6958 u8 reserved_at_40[0x4];
6960 u8 int_vector[0x10];
6962 u8 reserved_at_60[0x20];
6965 struct mlx5_ifc_attach_to_mcg_out_bits {
6967 u8 reserved_at_8[0x18];
6971 u8 reserved_at_40[0x40];
6974 struct mlx5_ifc_attach_to_mcg_in_bits {
6976 u8 reserved_at_10[0x10];
6978 u8 reserved_at_20[0x10];
6981 u8 reserved_at_40[0x8];
6984 u8 reserved_at_60[0x20];
6986 u8 multicast_gid[16][0x8];
6989 struct mlx5_ifc_arm_xrq_out_bits {
6991 u8 reserved_at_8[0x18];
6995 u8 reserved_at_40[0x40];
6998 struct mlx5_ifc_arm_xrq_in_bits {
7000 u8 reserved_at_10[0x10];
7002 u8 reserved_at_20[0x10];
7005 u8 reserved_at_40[0x8];
7008 u8 reserved_at_60[0x10];
7012 struct mlx5_ifc_arm_xrc_srq_out_bits {
7014 u8 reserved_at_8[0x18];
7018 u8 reserved_at_40[0x40];
7022 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7025 struct mlx5_ifc_arm_xrc_srq_in_bits {
7027 u8 reserved_at_10[0x10];
7029 u8 reserved_at_20[0x10];
7032 u8 reserved_at_40[0x8];
7035 u8 reserved_at_60[0x10];
7039 struct mlx5_ifc_arm_rq_out_bits {
7041 u8 reserved_at_8[0x18];
7045 u8 reserved_at_40[0x40];
7049 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7050 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7053 struct mlx5_ifc_arm_rq_in_bits {
7055 u8 reserved_at_10[0x10];
7057 u8 reserved_at_20[0x10];
7060 u8 reserved_at_40[0x8];
7061 u8 srq_number[0x18];
7063 u8 reserved_at_60[0x10];
7067 struct mlx5_ifc_arm_dct_out_bits {
7069 u8 reserved_at_8[0x18];
7073 u8 reserved_at_40[0x40];
7076 struct mlx5_ifc_arm_dct_in_bits {
7078 u8 reserved_at_10[0x10];
7080 u8 reserved_at_20[0x10];
7083 u8 reserved_at_40[0x8];
7084 u8 dct_number[0x18];
7086 u8 reserved_at_60[0x20];
7089 struct mlx5_ifc_alloc_xrcd_out_bits {
7091 u8 reserved_at_8[0x18];
7095 u8 reserved_at_40[0x8];
7098 u8 reserved_at_60[0x20];
7101 struct mlx5_ifc_alloc_xrcd_in_bits {
7103 u8 reserved_at_10[0x10];
7105 u8 reserved_at_20[0x10];
7108 u8 reserved_at_40[0x40];
7111 struct mlx5_ifc_alloc_uar_out_bits {
7113 u8 reserved_at_8[0x18];
7117 u8 reserved_at_40[0x8];
7120 u8 reserved_at_60[0x20];
7123 struct mlx5_ifc_alloc_uar_in_bits {
7125 u8 reserved_at_10[0x10];
7127 u8 reserved_at_20[0x10];
7130 u8 reserved_at_40[0x40];
7133 struct mlx5_ifc_alloc_transport_domain_out_bits {
7135 u8 reserved_at_8[0x18];
7139 u8 reserved_at_40[0x8];
7140 u8 transport_domain[0x18];
7142 u8 reserved_at_60[0x20];
7145 struct mlx5_ifc_alloc_transport_domain_in_bits {
7147 u8 reserved_at_10[0x10];
7149 u8 reserved_at_20[0x10];
7152 u8 reserved_at_40[0x40];
7155 struct mlx5_ifc_alloc_q_counter_out_bits {
7157 u8 reserved_at_8[0x18];
7161 u8 reserved_at_40[0x18];
7162 u8 counter_set_id[0x8];
7164 u8 reserved_at_60[0x20];
7167 struct mlx5_ifc_alloc_q_counter_in_bits {
7169 u8 reserved_at_10[0x10];
7171 u8 reserved_at_20[0x10];
7174 u8 reserved_at_40[0x40];
7177 struct mlx5_ifc_alloc_pd_out_bits {
7179 u8 reserved_at_8[0x18];
7183 u8 reserved_at_40[0x8];
7186 u8 reserved_at_60[0x20];
7189 struct mlx5_ifc_alloc_pd_in_bits {
7191 u8 reserved_at_10[0x10];
7193 u8 reserved_at_20[0x10];
7196 u8 reserved_at_40[0x40];
7199 struct mlx5_ifc_alloc_flow_counter_out_bits {
7201 u8 reserved_at_8[0x18];
7205 u8 flow_counter_id[0x20];
7207 u8 reserved_at_60[0x20];
7210 struct mlx5_ifc_alloc_flow_counter_in_bits {
7212 u8 reserved_at_10[0x10];
7214 u8 reserved_at_20[0x10];
7217 u8 reserved_at_40[0x40];
7220 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7222 u8 reserved_at_8[0x18];
7226 u8 reserved_at_40[0x40];
7229 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7231 u8 reserved_at_10[0x10];
7233 u8 reserved_at_20[0x10];
7236 u8 reserved_at_40[0x20];
7238 u8 reserved_at_60[0x10];
7239 u8 vxlan_udp_port[0x10];
7242 struct mlx5_ifc_set_rate_limit_out_bits {
7244 u8 reserved_at_8[0x18];
7248 u8 reserved_at_40[0x40];
7251 struct mlx5_ifc_set_rate_limit_in_bits {
7253 u8 reserved_at_10[0x10];
7255 u8 reserved_at_20[0x10];
7258 u8 reserved_at_40[0x10];
7259 u8 rate_limit_index[0x10];
7261 u8 reserved_at_60[0x20];
7263 u8 rate_limit[0x20];
7266 struct mlx5_ifc_access_register_out_bits {
7268 u8 reserved_at_8[0x18];
7272 u8 reserved_at_40[0x40];
7274 u8 register_data[0][0x20];
7278 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7279 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7282 struct mlx5_ifc_access_register_in_bits {
7284 u8 reserved_at_10[0x10];
7286 u8 reserved_at_20[0x10];
7289 u8 reserved_at_40[0x10];
7290 u8 register_id[0x10];
7294 u8 register_data[0][0x20];
7297 struct mlx5_ifc_sltp_reg_bits {
7302 u8 reserved_at_12[0x2];
7304 u8 reserved_at_18[0x8];
7306 u8 reserved_at_20[0x20];
7308 u8 reserved_at_40[0x7];
7314 u8 reserved_at_60[0xc];
7315 u8 ob_preemp_mode[0x4];
7319 u8 reserved_at_80[0x20];
7322 struct mlx5_ifc_slrg_reg_bits {
7327 u8 reserved_at_12[0x2];
7329 u8 reserved_at_18[0x8];
7331 u8 time_to_link_up[0x10];
7332 u8 reserved_at_30[0xc];
7333 u8 grade_lane_speed[0x4];
7335 u8 grade_version[0x8];
7338 u8 reserved_at_60[0x4];
7339 u8 height_grade_type[0x4];
7340 u8 height_grade[0x18];
7345 u8 reserved_at_a0[0x10];
7346 u8 height_sigma[0x10];
7348 u8 reserved_at_c0[0x20];
7350 u8 reserved_at_e0[0x4];
7351 u8 phase_grade_type[0x4];
7352 u8 phase_grade[0x18];
7354 u8 reserved_at_100[0x8];
7355 u8 phase_eo_pos[0x8];
7356 u8 reserved_at_110[0x8];
7357 u8 phase_eo_neg[0x8];
7359 u8 ffe_set_tested[0x10];
7360 u8 test_errors_per_lane[0x10];
7363 struct mlx5_ifc_pvlc_reg_bits {
7364 u8 reserved_at_0[0x8];
7366 u8 reserved_at_10[0x10];
7368 u8 reserved_at_20[0x1c];
7371 u8 reserved_at_40[0x1c];
7374 u8 reserved_at_60[0x1c];
7375 u8 vl_operational[0x4];
7378 struct mlx5_ifc_pude_reg_bits {
7381 u8 reserved_at_10[0x4];
7382 u8 admin_status[0x4];
7383 u8 reserved_at_18[0x4];
7384 u8 oper_status[0x4];
7386 u8 reserved_at_20[0x60];
7389 struct mlx5_ifc_ptys_reg_bits {
7390 u8 reserved_at_0[0x1];
7391 u8 an_disable_admin[0x1];
7392 u8 an_disable_cap[0x1];
7393 u8 reserved_at_3[0x5];
7395 u8 reserved_at_10[0xd];
7399 u8 reserved_at_24[0x3c];
7401 u8 eth_proto_capability[0x20];
7403 u8 ib_link_width_capability[0x10];
7404 u8 ib_proto_capability[0x10];
7406 u8 reserved_at_a0[0x20];
7408 u8 eth_proto_admin[0x20];
7410 u8 ib_link_width_admin[0x10];
7411 u8 ib_proto_admin[0x10];
7413 u8 reserved_at_100[0x20];
7415 u8 eth_proto_oper[0x20];
7417 u8 ib_link_width_oper[0x10];
7418 u8 ib_proto_oper[0x10];
7420 u8 reserved_at_160[0x1c];
7421 u8 connector_type[0x4];
7423 u8 eth_proto_lp_advertise[0x20];
7425 u8 reserved_at_1a0[0x60];
7428 struct mlx5_ifc_mlcr_reg_bits {
7429 u8 reserved_at_0[0x8];
7431 u8 reserved_at_10[0x20];
7433 u8 beacon_duration[0x10];
7434 u8 reserved_at_40[0x10];
7436 u8 beacon_remain[0x10];
7439 struct mlx5_ifc_ptas_reg_bits {
7440 u8 reserved_at_0[0x20];
7442 u8 algorithm_options[0x10];
7443 u8 reserved_at_30[0x4];
7444 u8 repetitions_mode[0x4];
7445 u8 num_of_repetitions[0x8];
7447 u8 grade_version[0x8];
7448 u8 height_grade_type[0x4];
7449 u8 phase_grade_type[0x4];
7450 u8 height_grade_weight[0x8];
7451 u8 phase_grade_weight[0x8];
7453 u8 gisim_measure_bits[0x10];
7454 u8 adaptive_tap_measure_bits[0x10];
7456 u8 ber_bath_high_error_threshold[0x10];
7457 u8 ber_bath_mid_error_threshold[0x10];
7459 u8 ber_bath_low_error_threshold[0x10];
7460 u8 one_ratio_high_threshold[0x10];
7462 u8 one_ratio_high_mid_threshold[0x10];
7463 u8 one_ratio_low_mid_threshold[0x10];
7465 u8 one_ratio_low_threshold[0x10];
7466 u8 ndeo_error_threshold[0x10];
7468 u8 mixer_offset_step_size[0x10];
7469 u8 reserved_at_110[0x8];
7470 u8 mix90_phase_for_voltage_bath[0x8];
7472 u8 mixer_offset_start[0x10];
7473 u8 mixer_offset_end[0x10];
7475 u8 reserved_at_140[0x15];
7476 u8 ber_test_time[0xb];
7479 struct mlx5_ifc_pspa_reg_bits {
7483 u8 reserved_at_18[0x8];
7485 u8 reserved_at_20[0x20];
7488 struct mlx5_ifc_pqdr_reg_bits {
7489 u8 reserved_at_0[0x8];
7491 u8 reserved_at_10[0x5];
7493 u8 reserved_at_18[0x6];
7496 u8 reserved_at_20[0x20];
7498 u8 reserved_at_40[0x10];
7499 u8 min_threshold[0x10];
7501 u8 reserved_at_60[0x10];
7502 u8 max_threshold[0x10];
7504 u8 reserved_at_80[0x10];
7505 u8 mark_probability_denominator[0x10];
7507 u8 reserved_at_a0[0x60];
7510 struct mlx5_ifc_ppsc_reg_bits {
7511 u8 reserved_at_0[0x8];
7513 u8 reserved_at_10[0x10];
7515 u8 reserved_at_20[0x60];
7517 u8 reserved_at_80[0x1c];
7520 u8 reserved_at_a0[0x1c];
7521 u8 wrps_status[0x4];
7523 u8 reserved_at_c0[0x8];
7524 u8 up_threshold[0x8];
7525 u8 reserved_at_d0[0x8];
7526 u8 down_threshold[0x8];
7528 u8 reserved_at_e0[0x20];
7530 u8 reserved_at_100[0x1c];
7533 u8 reserved_at_120[0x1c];
7534 u8 srps_status[0x4];
7536 u8 reserved_at_140[0x40];
7539 struct mlx5_ifc_pplr_reg_bits {
7540 u8 reserved_at_0[0x8];
7542 u8 reserved_at_10[0x10];
7544 u8 reserved_at_20[0x8];
7546 u8 reserved_at_30[0x8];
7550 struct mlx5_ifc_pplm_reg_bits {
7551 u8 reserved_at_0[0x8];
7553 u8 reserved_at_10[0x10];
7555 u8 reserved_at_20[0x20];
7557 u8 port_profile_mode[0x8];
7558 u8 static_port_profile[0x8];
7559 u8 active_port_profile[0x8];
7560 u8 reserved_at_58[0x8];
7562 u8 retransmission_active[0x8];
7563 u8 fec_mode_active[0x18];
7565 u8 reserved_at_80[0x20];
7568 struct mlx5_ifc_ppcnt_reg_bits {
7572 u8 reserved_at_12[0x8];
7576 u8 reserved_at_21[0x1c];
7579 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7582 struct mlx5_ifc_mpcnt_reg_bits {
7583 u8 reserved_at_0[0x8];
7585 u8 reserved_at_10[0xa];
7589 u8 reserved_at_21[0x1f];
7591 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7594 struct mlx5_ifc_ppad_reg_bits {
7595 u8 reserved_at_0[0x3];
7597 u8 reserved_at_4[0x4];
7603 u8 reserved_at_40[0x40];
7606 struct mlx5_ifc_pmtu_reg_bits {
7607 u8 reserved_at_0[0x8];
7609 u8 reserved_at_10[0x10];
7612 u8 reserved_at_30[0x10];
7615 u8 reserved_at_50[0x10];
7618 u8 reserved_at_70[0x10];
7621 struct mlx5_ifc_pmpr_reg_bits {
7622 u8 reserved_at_0[0x8];
7624 u8 reserved_at_10[0x10];
7626 u8 reserved_at_20[0x18];
7627 u8 attenuation_5g[0x8];
7629 u8 reserved_at_40[0x18];
7630 u8 attenuation_7g[0x8];
7632 u8 reserved_at_60[0x18];
7633 u8 attenuation_12g[0x8];
7636 struct mlx5_ifc_pmpe_reg_bits {
7637 u8 reserved_at_0[0x8];
7639 u8 reserved_at_10[0xc];
7640 u8 module_status[0x4];
7642 u8 reserved_at_20[0x60];
7645 struct mlx5_ifc_pmpc_reg_bits {
7646 u8 module_state_updated[32][0x8];
7649 struct mlx5_ifc_pmlpn_reg_bits {
7650 u8 reserved_at_0[0x4];
7651 u8 mlpn_status[0x4];
7653 u8 reserved_at_10[0x10];
7656 u8 reserved_at_21[0x1f];
7659 struct mlx5_ifc_pmlp_reg_bits {
7661 u8 reserved_at_1[0x7];
7663 u8 reserved_at_10[0x8];
7666 u8 lane0_module_mapping[0x20];
7668 u8 lane1_module_mapping[0x20];
7670 u8 lane2_module_mapping[0x20];
7672 u8 lane3_module_mapping[0x20];
7674 u8 reserved_at_a0[0x160];
7677 struct mlx5_ifc_pmaos_reg_bits {
7678 u8 reserved_at_0[0x8];
7680 u8 reserved_at_10[0x4];
7681 u8 admin_status[0x4];
7682 u8 reserved_at_18[0x4];
7683 u8 oper_status[0x4];
7687 u8 reserved_at_22[0x1c];
7690 u8 reserved_at_40[0x40];
7693 struct mlx5_ifc_plpc_reg_bits {
7694 u8 reserved_at_0[0x4];
7696 u8 reserved_at_10[0x4];
7698 u8 reserved_at_18[0x8];
7700 u8 reserved_at_20[0x10];
7701 u8 lane_speed[0x10];
7703 u8 reserved_at_40[0x17];
7705 u8 fec_mode_policy[0x8];
7707 u8 retransmission_capability[0x8];
7708 u8 fec_mode_capability[0x18];
7710 u8 retransmission_support_admin[0x8];
7711 u8 fec_mode_support_admin[0x18];
7713 u8 retransmission_request_admin[0x8];
7714 u8 fec_mode_request_admin[0x18];
7716 u8 reserved_at_c0[0x80];
7719 struct mlx5_ifc_plib_reg_bits {
7720 u8 reserved_at_0[0x8];
7722 u8 reserved_at_10[0x8];
7725 u8 reserved_at_20[0x60];
7728 struct mlx5_ifc_plbf_reg_bits {
7729 u8 reserved_at_0[0x8];
7731 u8 reserved_at_10[0xd];
7734 u8 reserved_at_20[0x20];
7737 struct mlx5_ifc_pipg_reg_bits {
7738 u8 reserved_at_0[0x8];
7740 u8 reserved_at_10[0x10];
7743 u8 reserved_at_21[0x19];
7745 u8 reserved_at_3e[0x2];
7748 struct mlx5_ifc_pifr_reg_bits {
7749 u8 reserved_at_0[0x8];
7751 u8 reserved_at_10[0x10];
7753 u8 reserved_at_20[0xe0];
7755 u8 port_filter[8][0x20];
7757 u8 port_filter_update_en[8][0x20];
7760 struct mlx5_ifc_pfcc_reg_bits {
7761 u8 reserved_at_0[0x8];
7763 u8 reserved_at_10[0x10];
7766 u8 reserved_at_24[0x4];
7767 u8 prio_mask_tx[0x8];
7768 u8 reserved_at_30[0x8];
7769 u8 prio_mask_rx[0x8];
7773 u8 reserved_at_42[0x6];
7775 u8 reserved_at_50[0x10];
7779 u8 reserved_at_62[0x6];
7781 u8 reserved_at_70[0x10];
7783 u8 reserved_at_80[0x80];
7786 struct mlx5_ifc_pelc_reg_bits {
7788 u8 reserved_at_4[0x4];
7790 u8 reserved_at_10[0x10];
7793 u8 op_capability[0x8];
7799 u8 capability[0x40];
7805 u8 reserved_at_140[0x80];
7808 struct mlx5_ifc_peir_reg_bits {
7809 u8 reserved_at_0[0x8];
7811 u8 reserved_at_10[0x10];
7813 u8 reserved_at_20[0xc];
7814 u8 error_count[0x4];
7815 u8 reserved_at_30[0x10];
7817 u8 reserved_at_40[0xc];
7819 u8 reserved_at_50[0x8];
7823 struct mlx5_ifc_pcam_enhanced_features_bits {
7824 u8 reserved_at_0[0x7b];
7826 u8 rx_buffer_fullness_counters[0x1];
7827 u8 ptys_connector_type[0x1];
7828 u8 reserved_at_7d[0x1];
7829 u8 ppcnt_discard_group[0x1];
7830 u8 ppcnt_statistical_group[0x1];
7833 struct mlx5_ifc_pcam_reg_bits {
7834 u8 reserved_at_0[0x8];
7835 u8 feature_group[0x8];
7836 u8 reserved_at_10[0x8];
7837 u8 access_reg_group[0x8];
7839 u8 reserved_at_20[0x20];
7842 u8 reserved_at_0[0x80];
7843 } port_access_reg_cap_mask;
7845 u8 reserved_at_c0[0x80];
7848 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7849 u8 reserved_at_0[0x80];
7852 u8 reserved_at_1c0[0xc0];
7855 struct mlx5_ifc_mcam_enhanced_features_bits {
7856 u8 reserved_at_0[0x7b];
7857 u8 pcie_outbound_stalled[0x1];
7858 u8 tx_overflow_buffer_pkt[0x1];
7859 u8 mtpps_enh_out_per_adj[0x1];
7861 u8 pcie_performance_group[0x1];
7864 struct mlx5_ifc_mcam_access_reg_bits {
7865 u8 reserved_at_0[0x1c];
7869 u8 reserved_at_1f[0x1];
7871 u8 regs_95_to_64[0x20];
7872 u8 regs_63_to_32[0x20];
7873 u8 regs_31_to_0[0x20];
7876 struct mlx5_ifc_mcam_reg_bits {
7877 u8 reserved_at_0[0x8];
7878 u8 feature_group[0x8];
7879 u8 reserved_at_10[0x8];
7880 u8 access_reg_group[0x8];
7882 u8 reserved_at_20[0x20];
7885 struct mlx5_ifc_mcam_access_reg_bits access_regs;
7886 u8 reserved_at_0[0x80];
7887 } mng_access_reg_cap_mask;
7889 u8 reserved_at_c0[0x80];
7892 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7893 u8 reserved_at_0[0x80];
7894 } mng_feature_cap_mask;
7896 u8 reserved_at_1c0[0x80];
7899 struct mlx5_ifc_qcam_access_reg_cap_mask {
7900 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7902 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7906 u8 qcam_access_reg_cap_mask_0[0x1];
7909 struct mlx5_ifc_qcam_qos_feature_cap_mask {
7910 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
7911 u8 qpts_trust_both[0x1];
7914 struct mlx5_ifc_qcam_reg_bits {
7915 u8 reserved_at_0[0x8];
7916 u8 feature_group[0x8];
7917 u8 reserved_at_10[0x8];
7918 u8 access_reg_group[0x8];
7919 u8 reserved_at_20[0x20];
7922 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7923 u8 reserved_at_0[0x80];
7924 } qos_access_reg_cap_mask;
7926 u8 reserved_at_c0[0x80];
7929 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7930 u8 reserved_at_0[0x80];
7931 } qos_feature_cap_mask;
7933 u8 reserved_at_1c0[0x80];
7936 struct mlx5_ifc_pcap_reg_bits {
7937 u8 reserved_at_0[0x8];
7939 u8 reserved_at_10[0x10];
7941 u8 port_capability_mask[4][0x20];
7944 struct mlx5_ifc_paos_reg_bits {
7947 u8 reserved_at_10[0x4];
7948 u8 admin_status[0x4];
7949 u8 reserved_at_18[0x4];
7950 u8 oper_status[0x4];
7954 u8 reserved_at_22[0x1c];
7957 u8 reserved_at_40[0x40];
7960 struct mlx5_ifc_pamp_reg_bits {
7961 u8 reserved_at_0[0x8];
7962 u8 opamp_group[0x8];
7963 u8 reserved_at_10[0xc];
7964 u8 opamp_group_type[0x4];
7966 u8 start_index[0x10];
7967 u8 reserved_at_30[0x4];
7968 u8 num_of_indices[0xc];
7970 u8 index_data[18][0x10];
7973 struct mlx5_ifc_pcmr_reg_bits {
7974 u8 reserved_at_0[0x8];
7976 u8 reserved_at_10[0x2e];
7978 u8 reserved_at_3f[0x1f];
7980 u8 reserved_at_5f[0x1];
7983 struct mlx5_ifc_lane_2_module_mapping_bits {
7984 u8 reserved_at_0[0x6];
7986 u8 reserved_at_8[0x6];
7988 u8 reserved_at_10[0x8];
7992 struct mlx5_ifc_bufferx_reg_bits {
7993 u8 reserved_at_0[0x6];
7996 u8 reserved_at_8[0xc];
7999 u8 xoff_threshold[0x10];
8000 u8 xon_threshold[0x10];
8003 struct mlx5_ifc_set_node_in_bits {
8004 u8 node_description[64][0x8];
8007 struct mlx5_ifc_register_power_settings_bits {
8008 u8 reserved_at_0[0x18];
8009 u8 power_settings_level[0x8];
8011 u8 reserved_at_20[0x60];
8014 struct mlx5_ifc_register_host_endianness_bits {
8016 u8 reserved_at_1[0x1f];
8018 u8 reserved_at_20[0x60];
8021 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8022 u8 reserved_at_0[0x20];
8026 u8 addressh_63_32[0x20];
8028 u8 addressl_31_0[0x20];
8031 struct mlx5_ifc_ud_adrs_vector_bits {
8035 u8 reserved_at_41[0x7];
8036 u8 destination_qp_dct[0x18];
8038 u8 static_rate[0x4];
8039 u8 sl_eth_prio[0x4];
8042 u8 rlid_udp_sport[0x10];
8044 u8 reserved_at_80[0x20];
8046 u8 rmac_47_16[0x20];
8052 u8 reserved_at_e0[0x1];
8054 u8 reserved_at_e2[0x2];
8055 u8 src_addr_index[0x8];
8056 u8 flow_label[0x14];
8058 u8 rgid_rip[16][0x8];
8061 struct mlx5_ifc_pages_req_event_bits {
8062 u8 reserved_at_0[0x10];
8063 u8 function_id[0x10];
8067 u8 reserved_at_40[0xa0];
8070 struct mlx5_ifc_eqe_bits {
8071 u8 reserved_at_0[0x8];
8073 u8 reserved_at_10[0x8];
8074 u8 event_sub_type[0x8];
8076 u8 reserved_at_20[0xe0];
8078 union mlx5_ifc_event_auto_bits event_data;
8080 u8 reserved_at_1e0[0x10];
8082 u8 reserved_at_1f8[0x7];
8087 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8090 struct mlx5_ifc_cmd_queue_entry_bits {
8092 u8 reserved_at_8[0x18];
8094 u8 input_length[0x20];
8096 u8 input_mailbox_pointer_63_32[0x20];
8098 u8 input_mailbox_pointer_31_9[0x17];
8099 u8 reserved_at_77[0x9];
8101 u8 command_input_inline_data[16][0x8];
8103 u8 command_output_inline_data[16][0x8];
8105 u8 output_mailbox_pointer_63_32[0x20];
8107 u8 output_mailbox_pointer_31_9[0x17];
8108 u8 reserved_at_1b7[0x9];
8110 u8 output_length[0x20];
8114 u8 reserved_at_1f0[0x8];
8119 struct mlx5_ifc_cmd_out_bits {
8121 u8 reserved_at_8[0x18];
8125 u8 command_output[0x20];
8128 struct mlx5_ifc_cmd_in_bits {
8130 u8 reserved_at_10[0x10];
8132 u8 reserved_at_20[0x10];
8135 u8 command[0][0x20];
8138 struct mlx5_ifc_cmd_if_box_bits {
8139 u8 mailbox_data[512][0x8];
8141 u8 reserved_at_1000[0x180];
8143 u8 next_pointer_63_32[0x20];
8145 u8 next_pointer_31_10[0x16];
8146 u8 reserved_at_11b6[0xa];
8148 u8 block_number[0x20];
8150 u8 reserved_at_11e0[0x8];
8152 u8 ctrl_signature[0x8];
8156 struct mlx5_ifc_mtt_bits {
8157 u8 ptag_63_32[0x20];
8160 u8 reserved_at_38[0x6];
8165 struct mlx5_ifc_query_wol_rol_out_bits {
8167 u8 reserved_at_8[0x18];
8171 u8 reserved_at_40[0x10];
8175 u8 reserved_at_60[0x20];
8178 struct mlx5_ifc_query_wol_rol_in_bits {
8180 u8 reserved_at_10[0x10];
8182 u8 reserved_at_20[0x10];
8185 u8 reserved_at_40[0x40];
8188 struct mlx5_ifc_set_wol_rol_out_bits {
8190 u8 reserved_at_8[0x18];
8194 u8 reserved_at_40[0x40];
8197 struct mlx5_ifc_set_wol_rol_in_bits {
8199 u8 reserved_at_10[0x10];
8201 u8 reserved_at_20[0x10];
8204 u8 rol_mode_valid[0x1];
8205 u8 wol_mode_valid[0x1];
8206 u8 reserved_at_42[0xe];
8210 u8 reserved_at_60[0x20];
8214 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8215 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8216 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8220 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8221 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8222 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8226 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8227 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8228 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8232 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8233 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8234 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8235 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8236 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8239 struct mlx5_ifc_initial_seg_bits {
8240 u8 fw_rev_minor[0x10];
8241 u8 fw_rev_major[0x10];
8243 u8 cmd_interface_rev[0x10];
8244 u8 fw_rev_subminor[0x10];
8246 u8 reserved_at_40[0x40];
8248 u8 cmdq_phy_addr_63_32[0x20];
8250 u8 cmdq_phy_addr_31_12[0x14];
8251 u8 reserved_at_b4[0x2];
8252 u8 nic_interface[0x2];
8253 u8 log_cmdq_size[0x4];
8254 u8 log_cmdq_stride[0x4];
8256 u8 command_doorbell_vector[0x20];
8258 u8 reserved_at_e0[0xf00];
8260 u8 initializing[0x1];
8261 u8 reserved_at_fe1[0x4];
8262 u8 nic_interface_supported[0x3];
8263 u8 reserved_at_fe8[0x18];
8265 struct mlx5_ifc_health_buffer_bits health_buffer;
8267 u8 no_dram_nic_offset[0x20];
8269 u8 reserved_at_1220[0x6e40];
8271 u8 reserved_at_8060[0x1f];
8274 u8 health_syndrome[0x8];
8275 u8 health_counter[0x18];
8277 u8 reserved_at_80a0[0x17fc0];
8280 struct mlx5_ifc_mtpps_reg_bits {
8281 u8 reserved_at_0[0xc];
8282 u8 cap_number_of_pps_pins[0x4];
8283 u8 reserved_at_10[0x4];
8284 u8 cap_max_num_of_pps_in_pins[0x4];
8285 u8 reserved_at_18[0x4];
8286 u8 cap_max_num_of_pps_out_pins[0x4];
8288 u8 reserved_at_20[0x24];
8289 u8 cap_pin_3_mode[0x4];
8290 u8 reserved_at_48[0x4];
8291 u8 cap_pin_2_mode[0x4];
8292 u8 reserved_at_50[0x4];
8293 u8 cap_pin_1_mode[0x4];
8294 u8 reserved_at_58[0x4];
8295 u8 cap_pin_0_mode[0x4];
8297 u8 reserved_at_60[0x4];
8298 u8 cap_pin_7_mode[0x4];
8299 u8 reserved_at_68[0x4];
8300 u8 cap_pin_6_mode[0x4];
8301 u8 reserved_at_70[0x4];
8302 u8 cap_pin_5_mode[0x4];
8303 u8 reserved_at_78[0x4];
8304 u8 cap_pin_4_mode[0x4];
8306 u8 field_select[0x20];
8307 u8 reserved_at_a0[0x60];
8310 u8 reserved_at_101[0xb];
8312 u8 reserved_at_110[0x4];
8316 u8 reserved_at_120[0x20];
8318 u8 time_stamp[0x40];
8320 u8 out_pulse_duration[0x10];
8321 u8 out_periodic_adjustment[0x10];
8322 u8 enhanced_out_periodic_adjustment[0x20];
8324 u8 reserved_at_1c0[0x20];
8327 struct mlx5_ifc_mtppse_reg_bits {
8328 u8 reserved_at_0[0x18];
8331 u8 reserved_at_21[0x1b];
8332 u8 event_generation_mode[0x4];
8333 u8 reserved_at_40[0x40];
8336 struct mlx5_ifc_mcqi_cap_bits {
8337 u8 supported_info_bitmask[0x20];
8339 u8 component_size[0x20];
8341 u8 max_component_size[0x20];
8343 u8 log_mcda_word_size[0x4];
8344 u8 reserved_at_64[0xc];
8345 u8 mcda_max_write_size[0x10];
8348 u8 reserved_at_81[0x1];
8349 u8 match_chip_id[0x1];
8351 u8 check_user_timestamp[0x1];
8352 u8 match_base_guid_mac[0x1];
8353 u8 reserved_at_86[0x1a];
8356 struct mlx5_ifc_mcqi_reg_bits {
8357 u8 read_pending_component[0x1];
8358 u8 reserved_at_1[0xf];
8359 u8 component_index[0x10];
8361 u8 reserved_at_20[0x20];
8363 u8 reserved_at_40[0x1b];
8370 u8 reserved_at_a0[0x10];
8376 struct mlx5_ifc_mcc_reg_bits {
8377 u8 reserved_at_0[0x4];
8378 u8 time_elapsed_since_last_cmd[0xc];
8379 u8 reserved_at_10[0x8];
8380 u8 instruction[0x8];
8382 u8 reserved_at_20[0x10];
8383 u8 component_index[0x10];
8385 u8 reserved_at_40[0x8];
8386 u8 update_handle[0x18];
8388 u8 handle_owner_type[0x4];
8389 u8 handle_owner_host_id[0x4];
8390 u8 reserved_at_68[0x1];
8391 u8 control_progress[0x7];
8393 u8 reserved_at_78[0x4];
8394 u8 control_state[0x4];
8396 u8 component_size[0x20];
8398 u8 reserved_at_a0[0x60];
8401 struct mlx5_ifc_mcda_reg_bits {
8402 u8 reserved_at_0[0x8];
8403 u8 update_handle[0x18];
8407 u8 reserved_at_40[0x10];
8410 u8 reserved_at_60[0x20];
8415 union mlx5_ifc_ports_control_registers_document_bits {
8416 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8417 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8418 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8419 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8420 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8421 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8422 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8423 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8424 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8425 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8426 struct mlx5_ifc_paos_reg_bits paos_reg;
8427 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8428 struct mlx5_ifc_peir_reg_bits peir_reg;
8429 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8430 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8431 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8432 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8433 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8434 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8435 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8436 struct mlx5_ifc_plib_reg_bits plib_reg;
8437 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8438 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8439 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8440 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8441 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8442 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8443 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8444 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8445 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8446 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8447 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8448 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8449 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8450 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8451 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8452 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8453 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8454 struct mlx5_ifc_ptys_reg_bits ptys_reg;
8455 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8456 struct mlx5_ifc_pude_reg_bits pude_reg;
8457 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8458 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8459 struct mlx5_ifc_sltp_reg_bits sltp_reg;
8460 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8461 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8462 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
8463 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8464 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8465 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8466 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8467 struct mlx5_ifc_mcda_reg_bits mcda_reg;
8468 u8 reserved_at_0[0x60e0];
8471 union mlx5_ifc_debug_enhancements_document_bits {
8472 struct mlx5_ifc_health_buffer_bits health_buffer;
8473 u8 reserved_at_0[0x200];
8476 union mlx5_ifc_uplink_pci_interface_document_bits {
8477 struct mlx5_ifc_initial_seg_bits initial_seg;
8478 u8 reserved_at_0[0x20060];
8481 struct mlx5_ifc_set_flow_table_root_out_bits {
8483 u8 reserved_at_8[0x18];
8487 u8 reserved_at_40[0x40];
8490 struct mlx5_ifc_set_flow_table_root_in_bits {
8492 u8 reserved_at_10[0x10];
8494 u8 reserved_at_20[0x10];
8497 u8 other_vport[0x1];
8498 u8 reserved_at_41[0xf];
8499 u8 vport_number[0x10];
8501 u8 reserved_at_60[0x20];
8504 u8 reserved_at_88[0x18];
8506 u8 reserved_at_a0[0x8];
8509 u8 reserved_at_c0[0x8];
8510 u8 underlay_qpn[0x18];
8511 u8 reserved_at_e0[0x120];
8515 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8516 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8519 struct mlx5_ifc_modify_flow_table_out_bits {
8521 u8 reserved_at_8[0x18];
8525 u8 reserved_at_40[0x40];
8528 struct mlx5_ifc_modify_flow_table_in_bits {
8530 u8 reserved_at_10[0x10];
8532 u8 reserved_at_20[0x10];
8535 u8 other_vport[0x1];
8536 u8 reserved_at_41[0xf];
8537 u8 vport_number[0x10];
8539 u8 reserved_at_60[0x10];
8540 u8 modify_field_select[0x10];
8543 u8 reserved_at_88[0x18];
8545 u8 reserved_at_a0[0x8];
8548 struct mlx5_ifc_flow_table_context_bits flow_table_context;
8551 struct mlx5_ifc_ets_tcn_config_reg_bits {
8555 u8 reserved_at_3[0x9];
8557 u8 reserved_at_10[0x9];
8558 u8 bw_allocation[0x7];
8560 u8 reserved_at_20[0xc];
8561 u8 max_bw_units[0x4];
8562 u8 reserved_at_30[0x8];
8563 u8 max_bw_value[0x8];
8566 struct mlx5_ifc_ets_global_config_reg_bits {
8567 u8 reserved_at_0[0x2];
8569 u8 reserved_at_3[0x1d];
8571 u8 reserved_at_20[0xc];
8572 u8 max_bw_units[0x4];
8573 u8 reserved_at_30[0x8];
8574 u8 max_bw_value[0x8];
8577 struct mlx5_ifc_qetc_reg_bits {
8578 u8 reserved_at_0[0x8];
8579 u8 port_number[0x8];
8580 u8 reserved_at_10[0x30];
8582 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8583 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8586 struct mlx5_ifc_qpdpm_dscp_reg_bits {
8588 u8 reserved_at_01[0x0b];
8592 struct mlx5_ifc_qpdpm_reg_bits {
8593 u8 reserved_at_0[0x8];
8595 u8 reserved_at_10[0x10];
8596 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
8599 struct mlx5_ifc_qpts_reg_bits {
8600 u8 reserved_at_0[0x8];
8602 u8 reserved_at_10[0x2d];
8603 u8 trust_state[0x3];
8606 struct mlx5_ifc_qtct_reg_bits {
8607 u8 reserved_at_0[0x8];
8608 u8 port_number[0x8];
8609 u8 reserved_at_10[0xd];
8612 u8 reserved_at_20[0x1d];
8616 struct mlx5_ifc_mcia_reg_bits {
8618 u8 reserved_at_1[0x7];
8620 u8 reserved_at_10[0x8];
8623 u8 i2c_device_address[0x8];
8624 u8 page_number[0x8];
8625 u8 device_address[0x10];
8627 u8 reserved_at_40[0x10];
8630 u8 reserved_at_60[0x20];
8646 struct mlx5_ifc_dcbx_param_bits {
8647 u8 dcbx_cee_cap[0x1];
8648 u8 dcbx_ieee_cap[0x1];
8649 u8 dcbx_standby_cap[0x1];
8650 u8 reserved_at_0[0x5];
8651 u8 port_number[0x8];
8652 u8 reserved_at_10[0xa];
8653 u8 max_application_table_size[6];
8654 u8 reserved_at_20[0x15];
8655 u8 version_oper[0x3];
8656 u8 reserved_at_38[5];
8657 u8 version_admin[0x3];
8658 u8 willing_admin[0x1];
8659 u8 reserved_at_41[0x3];
8660 u8 pfc_cap_oper[0x4];
8661 u8 reserved_at_48[0x4];
8662 u8 pfc_cap_admin[0x4];
8663 u8 reserved_at_50[0x4];
8664 u8 num_of_tc_oper[0x4];
8665 u8 reserved_at_58[0x4];
8666 u8 num_of_tc_admin[0x4];
8667 u8 remote_willing[0x1];
8668 u8 reserved_at_61[3];
8669 u8 remote_pfc_cap[4];
8670 u8 reserved_at_68[0x14];
8671 u8 remote_num_of_tc[0x4];
8672 u8 reserved_at_80[0x18];
8674 u8 reserved_at_a0[0x160];
8677 struct mlx5_ifc_lagc_bits {
8678 u8 reserved_at_0[0x1d];
8681 u8 reserved_at_20[0x14];
8682 u8 tx_remap_affinity_2[0x4];
8683 u8 reserved_at_38[0x4];
8684 u8 tx_remap_affinity_1[0x4];
8687 struct mlx5_ifc_create_lag_out_bits {
8689 u8 reserved_at_8[0x18];
8693 u8 reserved_at_40[0x40];
8696 struct mlx5_ifc_create_lag_in_bits {
8698 u8 reserved_at_10[0x10];
8700 u8 reserved_at_20[0x10];
8703 struct mlx5_ifc_lagc_bits ctx;
8706 struct mlx5_ifc_modify_lag_out_bits {
8708 u8 reserved_at_8[0x18];
8712 u8 reserved_at_40[0x40];
8715 struct mlx5_ifc_modify_lag_in_bits {
8717 u8 reserved_at_10[0x10];
8719 u8 reserved_at_20[0x10];
8722 u8 reserved_at_40[0x20];
8723 u8 field_select[0x20];
8725 struct mlx5_ifc_lagc_bits ctx;
8728 struct mlx5_ifc_query_lag_out_bits {
8730 u8 reserved_at_8[0x18];
8734 u8 reserved_at_40[0x40];
8736 struct mlx5_ifc_lagc_bits ctx;
8739 struct mlx5_ifc_query_lag_in_bits {
8741 u8 reserved_at_10[0x10];
8743 u8 reserved_at_20[0x10];
8746 u8 reserved_at_40[0x40];
8749 struct mlx5_ifc_destroy_lag_out_bits {
8751 u8 reserved_at_8[0x18];
8755 u8 reserved_at_40[0x40];
8758 struct mlx5_ifc_destroy_lag_in_bits {
8760 u8 reserved_at_10[0x10];
8762 u8 reserved_at_20[0x10];
8765 u8 reserved_at_40[0x40];
8768 struct mlx5_ifc_create_vport_lag_out_bits {
8770 u8 reserved_at_8[0x18];
8774 u8 reserved_at_40[0x40];
8777 struct mlx5_ifc_create_vport_lag_in_bits {
8779 u8 reserved_at_10[0x10];
8781 u8 reserved_at_20[0x10];
8784 u8 reserved_at_40[0x40];
8787 struct mlx5_ifc_destroy_vport_lag_out_bits {
8789 u8 reserved_at_8[0x18];
8793 u8 reserved_at_40[0x40];
8796 struct mlx5_ifc_destroy_vport_lag_in_bits {
8798 u8 reserved_at_10[0x10];
8800 u8 reserved_at_20[0x10];
8803 u8 reserved_at_40[0x40];
8806 #endif /* MLX5_IFC_H */