include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63 };
  64
  65 enum {
  66         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  67         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  68         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  69         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  70 };
  71
  72 enum {
  73         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  74         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  75 };
  76
  77 enum {
  78         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
  79         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
  80         MLX5_CMD_OP_INIT_HCA                      = 0x102,
  81         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
  82         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
  83         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
  84         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
  85         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
  86         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
  87         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
  88         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
  89         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
  90         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
  91         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
  92         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
  93         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
  94         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
  95         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
  96         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
  97         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
  98         MLX5_CMD_OP_GEN_EQE                       = 0x304,
  99         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 100         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 101         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 102         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 103         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 104         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 105         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 106         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 107         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 108         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 109         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 110         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 111         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 112         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 113         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 114         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 115         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 116         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 117         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 118         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 119         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 120         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 121         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 122         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 123         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 124         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 125         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 126         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 127         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 128         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 129         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 130         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 131         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 132         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 133         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 134         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 135         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 136         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 137         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 138         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 139         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 140         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 141         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 142         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 143         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 144         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 145         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 146         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 147         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 148         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 149         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 150         MLX5_CMD_OP_SET_RATE_LIMIT                = 0x780,
 151         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 152         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 153         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 154         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 155         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 156         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 157         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 158         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 159         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 160         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 161         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 162         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 163         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 164         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 165         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 166         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 167         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 168         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 169         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 170         MLX5_CMD_OP_NOP                           = 0x80d,
 171         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 172         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 173         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 174         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 175         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 176         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 177         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 178         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 179         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 180         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 181         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 182         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 183         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 184         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 185         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 186         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 187         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 188         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 189         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 190         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 191         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 192         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 193         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 194         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 195         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 196         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 197         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 198         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 199         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 200         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 201         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 202         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 203         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 204         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 205         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 206         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 207         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 208         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 209         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 210         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 211         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 212         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 213         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 214         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 215         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 216         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 217         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 218         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 219         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 220         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 221         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 222         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 223         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 224         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 225         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 226         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 227         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 228         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 229         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 230         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 231         MLX5_CMD_OP_ALLOC_ENCAP_HEADER            = 0x93d,
 232         MLX5_CMD_OP_DEALLOC_ENCAP_HEADER          = 0x93e,
 233         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 234         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 235         MLX5_CMD_OP_MAX
 236 };
 237
 238 struct mlx5_ifc_flow_table_fields_supported_bits {
 239         u8         outer_dmac[0x1];
 240         u8         outer_smac[0x1];
 241         u8         outer_ether_type[0x1];
 242         u8         outer_ip_version[0x1];
 243         u8         outer_first_prio[0x1];
 244         u8         outer_first_cfi[0x1];
 245         u8         outer_first_vid[0x1];
 246         u8         outer_ipv4_ttl[0x1];
 247         u8         outer_second_prio[0x1];
 248         u8         outer_second_cfi[0x1];
 249         u8         outer_second_vid[0x1];
 250         u8         reserved_at_b[0x1];
 251         u8         outer_sip[0x1];
 252         u8         outer_dip[0x1];
 253         u8         outer_frag[0x1];
 254         u8         outer_ip_protocol[0x1];
 255         u8         outer_ip_ecn[0x1];
 256         u8         outer_ip_dscp[0x1];
 257         u8         outer_udp_sport[0x1];
 258         u8         outer_udp_dport[0x1];
 259         u8         outer_tcp_sport[0x1];
 260         u8         outer_tcp_dport[0x1];
 261         u8         outer_tcp_flags[0x1];
 262         u8         outer_gre_protocol[0x1];
 263         u8         outer_gre_key[0x1];
 264         u8         outer_vxlan_vni[0x1];
 265         u8         reserved_at_1a[0x5];
 266         u8         source_eswitch_port[0x1];
 267
 268         u8         inner_dmac[0x1];
 269         u8         inner_smac[0x1];
 270         u8         inner_ether_type[0x1];
 271         u8         inner_ip_version[0x1];
 272         u8         inner_first_prio[0x1];
 273         u8         inner_first_cfi[0x1];
 274         u8         inner_first_vid[0x1];
 275         u8         reserved_at_27[0x1];
 276         u8         inner_second_prio[0x1];
 277         u8         inner_second_cfi[0x1];
 278         u8         inner_second_vid[0x1];
 279         u8         reserved_at_2b[0x1];
 280         u8         inner_sip[0x1];
 281         u8         inner_dip[0x1];
 282         u8         inner_frag[0x1];
 283         u8         inner_ip_protocol[0x1];
 284         u8         inner_ip_ecn[0x1];
 285         u8         inner_ip_dscp[0x1];
 286         u8         inner_udp_sport[0x1];
 287         u8         inner_udp_dport[0x1];
 288         u8         inner_tcp_sport[0x1];
 289         u8         inner_tcp_dport[0x1];
 290         u8         inner_tcp_flags[0x1];
 291         u8         reserved_at_37[0x9];
 292
 293         u8         reserved_at_40[0x40];
 294 };
 295
 296 struct mlx5_ifc_flow_table_prop_layout_bits {
 297         u8         ft_support[0x1];
 298         u8         reserved_at_1[0x1];
 299         u8         flow_counter[0x1];
 300         u8         flow_modify_en[0x1];
 301         u8         modify_root[0x1];
 302         u8         identified_miss_table_mode[0x1];
 303         u8         flow_table_modify[0x1];
 304         u8         encap[0x1];
 305         u8         decap[0x1];
 306         u8         reserved_at_9[0x17];
 307
 308         u8         reserved_at_20[0x2];
 309         u8         log_max_ft_size[0x6];
 310         u8         log_max_modify_header_context[0x8];
 311         u8         max_modify_header_actions[0x8];
 312         u8         max_ft_level[0x8];
 313
 314         u8         reserved_at_40[0x20];
 315
 316         u8         reserved_at_60[0x18];
 317         u8         log_max_ft_num[0x8];
 318
 319         u8         reserved_at_80[0x18];
 320         u8         log_max_destination[0x8];
 321
 322         u8         reserved_at_a0[0x18];
 323         u8         log_max_flow[0x8];
 324
 325         u8         reserved_at_c0[0x40];
 326
 327         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 328
 329         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 330 };
 331
 332 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 333         u8         send[0x1];
 334         u8         receive[0x1];
 335         u8         write[0x1];
 336         u8         read[0x1];
 337         u8         atomic[0x1];
 338         u8         srq_receive[0x1];
 339         u8         reserved_at_6[0x1a];
 340 };
 341
 342 struct mlx5_ifc_ipv4_layout_bits {
 343         u8         reserved_at_0[0x60];
 344
 345         u8         ipv4[0x20];
 346 };
 347
 348 struct mlx5_ifc_ipv6_layout_bits {
 349         u8         ipv6[16][0x8];
 350 };
 351
 352 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 353         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 354         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 355         u8         reserved_at_0[0x80];
 356 };
 357
 358 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 359         u8         smac_47_16[0x20];
 360
 361         u8         smac_15_0[0x10];
 362         u8         ethertype[0x10];
 363
 364         u8         dmac_47_16[0x20];
 365
 366         u8         dmac_15_0[0x10];
 367         u8         first_prio[0x3];
 368         u8         first_cfi[0x1];
 369         u8         first_vid[0xc];
 370
 371         u8         ip_protocol[0x8];
 372         u8         ip_dscp[0x6];
 373         u8         ip_ecn[0x2];
 374         u8         cvlan_tag[0x1];
 375         u8         svlan_tag[0x1];
 376         u8         frag[0x1];
 377         u8         ip_version[0x4];
 378         u8         tcp_flags[0x9];
 379
 380         u8         tcp_sport[0x10];
 381         u8         tcp_dport[0x10];
 382
 383         u8         reserved_at_c0[0x18];
 384         u8         ttl_hoplimit[0x8];
 385
 386         u8         udp_sport[0x10];
 387         u8         udp_dport[0x10];
 388
 389         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 390
 391         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 392 };
 393
 394 struct mlx5_ifc_fte_match_set_misc_bits {
 395         u8         reserved_at_0[0x8];
 396         u8         source_sqn[0x18];
 397
 398         u8         reserved_at_20[0x10];
 399         u8         source_port[0x10];
 400
 401         u8         outer_second_prio[0x3];
 402         u8         outer_second_cfi[0x1];
 403         u8         outer_second_vid[0xc];
 404         u8         inner_second_prio[0x3];
 405         u8         inner_second_cfi[0x1];
 406         u8         inner_second_vid[0xc];
 407
 408         u8         outer_second_cvlan_tag[0x1];
 409         u8         inner_second_cvlan_tag[0x1];
 410         u8         outer_second_svlan_tag[0x1];
 411         u8         inner_second_svlan_tag[0x1];
 412         u8         reserved_at_64[0xc];
 413         u8         gre_protocol[0x10];
 414
 415         u8         gre_key_h[0x18];
 416         u8         gre_key_l[0x8];
 417
 418         u8         vxlan_vni[0x18];
 419         u8         reserved_at_b8[0x8];
 420
 421         u8         reserved_at_c0[0x20];
 422
 423         u8         reserved_at_e0[0xc];
 424         u8         outer_ipv6_flow_label[0x14];
 425
 426         u8         reserved_at_100[0xc];
 427         u8         inner_ipv6_flow_label[0x14];
 428
 429         u8         reserved_at_120[0xe0];
 430 };
 431
 432 struct mlx5_ifc_cmd_pas_bits {
 433         u8         pa_h[0x20];
 434
 435         u8         pa_l[0x14];
 436         u8         reserved_at_34[0xc];
 437 };
 438
 439 struct mlx5_ifc_uint64_bits {
 440         u8         hi[0x20];
 441
 442         u8         lo[0x20];
 443 };
 444
 445 enum {
 446         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 447         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 448         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 449         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 450         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 451         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 452         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 453         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 454         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 455         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 456 };
 457
 458 struct mlx5_ifc_ads_bits {
 459         u8         fl[0x1];
 460         u8         free_ar[0x1];
 461         u8         reserved_at_2[0xe];
 462         u8         pkey_index[0x10];
 463
 464         u8         reserved_at_20[0x8];
 465         u8         grh[0x1];
 466         u8         mlid[0x7];
 467         u8         rlid[0x10];
 468
 469         u8         ack_timeout[0x5];
 470         u8         reserved_at_45[0x3];
 471         u8         src_addr_index[0x8];
 472         u8         reserved_at_50[0x4];
 473         u8         stat_rate[0x4];
 474         u8         hop_limit[0x8];
 475
 476         u8         reserved_at_60[0x4];
 477         u8         tclass[0x8];
 478         u8         flow_label[0x14];
 479
 480         u8         rgid_rip[16][0x8];
 481
 482         u8         reserved_at_100[0x4];
 483         u8         f_dscp[0x1];
 484         u8         f_ecn[0x1];
 485         u8         reserved_at_106[0x1];
 486         u8         f_eth_prio[0x1];
 487         u8         ecn[0x2];
 488         u8         dscp[0x6];
 489         u8         udp_sport[0x10];
 490
 491         u8         dei_cfi[0x1];
 492         u8         eth_prio[0x3];
 493         u8         sl[0x4];
 494         u8         port[0x8];
 495         u8         rmac_47_32[0x10];
 496
 497         u8         rmac_31_0[0x20];
 498 };
 499
 500 struct mlx5_ifc_flow_table_nic_cap_bits {
 501         u8         nic_rx_multi_path_tirs[0x1];
 502         u8         nic_rx_multi_path_tirs_fts[0x1];
 503         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 504         u8         reserved_at_3[0x1fd];
 505
 506         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 507
 508         u8         reserved_at_400[0x200];
 509
 510         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 511
 512         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 513
 514         u8         reserved_at_a00[0x200];
 515
 516         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 517
 518         u8         reserved_at_e00[0x7200];
 519 };
 520
 521 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 522         u8     reserved_at_0[0x200];
 523
 524         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 525
 526         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 527
 528         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 529
 530         u8      reserved_at_800[0x7800];
 531 };
 532
 533 struct mlx5_ifc_e_switch_cap_bits {
 534         u8         vport_svlan_strip[0x1];
 535         u8         vport_cvlan_strip[0x1];
 536         u8         vport_svlan_insert[0x1];
 537         u8         vport_cvlan_insert_if_not_exist[0x1];
 538         u8         vport_cvlan_insert_overwrite[0x1];
 539         u8         reserved_at_5[0x19];
 540         u8         nic_vport_node_guid_modify[0x1];
 541         u8         nic_vport_port_guid_modify[0x1];
 542
 543         u8         vxlan_encap_decap[0x1];
 544         u8         nvgre_encap_decap[0x1];
 545         u8         reserved_at_22[0x9];
 546         u8         log_max_encap_headers[0x5];
 547         u8         reserved_2b[0x6];
 548         u8         max_encap_header_size[0xa];
 549
 550         u8         reserved_40[0x7c0];
 551
 552 };
 553
 554 struct mlx5_ifc_qos_cap_bits {
 555         u8         packet_pacing[0x1];
 556         u8         esw_scheduling[0x1];
 557         u8         esw_bw_share[0x1];
 558         u8         esw_rate_limit[0x1];
 559         u8         reserved_at_4[0x1c];
 560
 561         u8         reserved_at_20[0x20];
 562
 563         u8         packet_pacing_max_rate[0x20];
 564
 565         u8         packet_pacing_min_rate[0x20];
 566
 567         u8         reserved_at_80[0x10];
 568         u8         packet_pacing_rate_table_size[0x10];
 569
 570         u8         esw_element_type[0x10];
 571         u8         esw_tsar_type[0x10];
 572
 573         u8         reserved_at_c0[0x10];
 574         u8         max_qos_para_vport[0x10];
 575
 576         u8         max_tsar_bw_share[0x20];
 577
 578         u8         reserved_at_100[0x700];
 579 };
 580
 581 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 582         u8         csum_cap[0x1];
 583         u8         vlan_cap[0x1];
 584         u8         lro_cap[0x1];
 585         u8         lro_psh_flag[0x1];
 586         u8         lro_time_stamp[0x1];
 587         u8         reserved_at_5[0x2];
 588         u8         wqe_vlan_insert[0x1];
 589         u8         self_lb_en_modifiable[0x1];
 590         u8         reserved_at_9[0x2];
 591         u8         max_lso_cap[0x5];
 592         u8         multi_pkt_send_wqe[0x2];
 593         u8         wqe_inline_mode[0x2];
 594         u8         rss_ind_tbl_cap[0x4];
 595         u8         reg_umr_sq[0x1];
 596         u8         scatter_fcs[0x1];
 597         u8         reserved_at_1a[0x1];
 598         u8         tunnel_lso_const_out_ip_id[0x1];
 599         u8         reserved_at_1c[0x2];
 600         u8         tunnel_statless_gre[0x1];
 601         u8         tunnel_stateless_vxlan[0x1];
 602
 603         u8         reserved_at_20[0x20];
 604
 605         u8         reserved_at_40[0x10];
 606         u8         lro_min_mss_size[0x10];
 607
 608         u8         reserved_at_60[0x120];
 609
 610         u8         lro_timer_supported_periods[4][0x20];
 611
 612         u8         reserved_at_200[0x600];
 613 };
 614
 615 struct mlx5_ifc_roce_cap_bits {
 616         u8         roce_apm[0x1];
 617         u8         reserved_at_1[0x1f];
 618
 619         u8         reserved_at_20[0x60];
 620
 621         u8         reserved_at_80[0xc];
 622         u8         l3_type[0x4];
 623         u8         reserved_at_90[0x8];
 624         u8         roce_version[0x8];
 625
 626         u8         reserved_at_a0[0x10];
 627         u8         r_roce_dest_udp_port[0x10];
 628
 629         u8         r_roce_max_src_udp_port[0x10];
 630         u8         r_roce_min_src_udp_port[0x10];
 631
 632         u8         reserved_at_e0[0x10];
 633         u8         roce_address_table_size[0x10];
 634
 635         u8         reserved_at_100[0x700];
 636 };
 637
 638 enum {
 639         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 640         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 641         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 642         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 643         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 644         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 645         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 646         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 647         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 648 };
 649
 650 enum {
 651         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 652         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 653         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 654         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 655         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 656         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 657         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 658         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 659         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 660 };
 661
 662 struct mlx5_ifc_atomic_caps_bits {
 663         u8         reserved_at_0[0x40];
 664
 665         u8         atomic_req_8B_endianness_mode[0x2];
 666         u8         reserved_at_42[0x4];
 667         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 668
 669         u8         reserved_at_47[0x19];
 670
 671         u8         reserved_at_60[0x20];
 672
 673         u8         reserved_at_80[0x10];
 674         u8         atomic_operations[0x10];
 675
 676         u8         reserved_at_a0[0x10];
 677         u8         atomic_size_qp[0x10];
 678
 679         u8         reserved_at_c0[0x10];
 680         u8         atomic_size_dc[0x10];
 681
 682         u8         reserved_at_e0[0x720];
 683 };
 684
 685 struct mlx5_ifc_odp_cap_bits {
 686         u8         reserved_at_0[0x40];
 687
 688         u8         sig[0x1];
 689         u8         reserved_at_41[0x1f];
 690
 691         u8         reserved_at_60[0x20];
 692
 693         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 694
 695         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 696
 697         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 698
 699         u8         reserved_at_e0[0x720];
 700 };
 701
 702 struct mlx5_ifc_calc_op {
 703         u8        reserved_at_0[0x10];
 704         u8        reserved_at_10[0x9];
 705         u8        op_swap_endianness[0x1];
 706         u8        op_min[0x1];
 707         u8        op_xor[0x1];
 708         u8        op_or[0x1];
 709         u8        op_and[0x1];
 710         u8        op_max[0x1];
 711         u8        op_add[0x1];
 712 };
 713
 714 struct mlx5_ifc_vector_calc_cap_bits {
 715         u8         calc_matrix[0x1];
 716         u8         reserved_at_1[0x1f];
 717         u8         reserved_at_20[0x8];
 718         u8         max_vec_count[0x8];
 719         u8         reserved_at_30[0xd];
 720         u8         max_chunk_size[0x3];
 721         struct mlx5_ifc_calc_op calc0;
 722         struct mlx5_ifc_calc_op calc1;
 723         struct mlx5_ifc_calc_op calc2;
 724         struct mlx5_ifc_calc_op calc3;
 725
 726         u8         reserved_at_e0[0x720];
 727 };
 728
 729 enum {
 730         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 731         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 732         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 733 };
 734
 735 enum {
 736         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 737         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 738 };
 739
 740 enum {
 741         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
 742         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
 743         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
 744         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
 745         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
 746 };
 747
 748 enum {
 749         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
 750         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
 751         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
 752         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
 753         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
 754         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
 755 };
 756
 757 enum {
 758         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
 759         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
 760 };
 761
 762 enum {
 763         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
 764         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
 765         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
 766 };
 767
 768 enum {
 769         MLX5_CAP_PORT_TYPE_IB  = 0x0,
 770         MLX5_CAP_PORT_TYPE_ETH = 0x1,
 771 };
 772
 773 enum {
 774         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
 775         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
 776         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
 777 };
 778
 779 struct mlx5_ifc_cmd_hca_cap_bits {
 780         u8         reserved_at_0[0x80];
 781
 782         u8         log_max_srq_sz[0x8];
 783         u8         log_max_qp_sz[0x8];
 784         u8         reserved_at_90[0xb];
 785         u8         log_max_qp[0x5];
 786
 787         u8         reserved_at_a0[0xb];
 788         u8         log_max_srq[0x5];
 789         u8         reserved_at_b0[0x10];
 790
 791         u8         reserved_at_c0[0x8];
 792         u8         log_max_cq_sz[0x8];
 793         u8         reserved_at_d0[0xb];
 794         u8         log_max_cq[0x5];
 795
 796         u8         log_max_eq_sz[0x8];
 797         u8         reserved_at_e8[0x2];
 798         u8         log_max_mkey[0x6];
 799         u8         reserved_at_f0[0xc];
 800         u8         log_max_eq[0x4];
 801
 802         u8         max_indirection[0x8];
 803         u8         fixed_buffer_size[0x1];
 804         u8         log_max_mrw_sz[0x7];
 805         u8         force_teardown[0x1];
 806         u8         reserved_at_111[0x1];
 807         u8         log_max_bsf_list_size[0x6];
 808         u8         umr_extended_translation_offset[0x1];
 809         u8         null_mkey[0x1];
 810         u8         log_max_klm_list_size[0x6];
 811
 812         u8         reserved_at_120[0xa];
 813         u8         log_max_ra_req_dc[0x6];
 814         u8         reserved_at_130[0xa];
 815         u8         log_max_ra_res_dc[0x6];
 816
 817         u8         reserved_at_140[0xa];
 818         u8         log_max_ra_req_qp[0x6];
 819         u8         reserved_at_150[0xa];
 820         u8         log_max_ra_res_qp[0x6];
 821
 822         u8         end_pad[0x1];
 823         u8         cc_query_allowed[0x1];
 824         u8         cc_modify_allowed[0x1];
 825         u8         start_pad[0x1];
 826         u8         cache_line_128byte[0x1];
 827         u8         reserved_at_163[0xb];
 828         u8         gid_table_size[0x10];
 829
 830         u8         out_of_seq_cnt[0x1];
 831         u8         vport_counters[0x1];
 832         u8         retransmission_q_counters[0x1];
 833         u8         reserved_at_183[0x1];
 834         u8         modify_rq_counter_set_id[0x1];
 835         u8         reserved_at_185[0x1];
 836         u8         max_qp_cnt[0xa];
 837         u8         pkey_table_size[0x10];
 838
 839         u8         vport_group_manager[0x1];
 840         u8         vhca_group_manager[0x1];
 841         u8         ib_virt[0x1];
 842         u8         eth_virt[0x1];
 843         u8         reserved_at_1a4[0x1];
 844         u8         ets[0x1];
 845         u8         nic_flow_table[0x1];
 846         u8         eswitch_flow_table[0x1];
 847         u8         early_vf_enable[0x1];
 848         u8         mcam_reg[0x1];
 849         u8         pcam_reg[0x1];
 850         u8         local_ca_ack_delay[0x5];
 851         u8         port_module_event[0x1];
 852         u8         reserved_at_1b1[0x1];
 853         u8         ports_check[0x1];
 854         u8         reserved_at_1b3[0x1];
 855         u8         disable_link_up[0x1];
 856         u8         beacon_led[0x1];
 857         u8         port_type[0x2];
 858         u8         num_ports[0x8];
 859
 860         u8         reserved_at_1c0[0x1];
 861         u8         pps[0x1];
 862         u8         pps_modify[0x1];
 863         u8         log_max_msg[0x5];
 864         u8         reserved_at_1c8[0x4];
 865         u8         max_tc[0x4];
 866         u8         reserved_at_1d0[0x1];
 867         u8         dcbx[0x1];
 868         u8         reserved_at_1d2[0x3];
 869         u8         fpga[0x1];
 870         u8         rol_s[0x1];
 871         u8         rol_g[0x1];
 872         u8         reserved_at_1d8[0x1];
 873         u8         wol_s[0x1];
 874         u8         wol_g[0x1];
 875         u8         wol_a[0x1];
 876         u8         wol_b[0x1];
 877         u8         wol_m[0x1];
 878         u8         wol_u[0x1];
 879         u8         wol_p[0x1];
 880
 881         u8         stat_rate_support[0x10];
 882         u8         reserved_at_1f0[0xc];
 883         u8         cqe_version[0x4];
 884
 885         u8         compact_address_vector[0x1];
 886         u8         striding_rq[0x1];
 887         u8         reserved_at_202[0x1];
 888         u8         ipoib_enhanced_offloads[0x1];
 889         u8         ipoib_basic_offloads[0x1];
 890         u8         reserved_at_205[0x5];
 891         u8         umr_fence[0x2];
 892         u8         reserved_at_20c[0x3];
 893         u8         drain_sigerr[0x1];
 894         u8         cmdif_checksum[0x2];
 895         u8         sigerr_cqe[0x1];
 896         u8         reserved_at_213[0x1];
 897         u8         wq_signature[0x1];
 898         u8         sctr_data_cqe[0x1];
 899         u8         reserved_at_216[0x1];
 900         u8         sho[0x1];
 901         u8         tph[0x1];
 902         u8         rf[0x1];
 903         u8         dct[0x1];
 904         u8         qos[0x1];
 905         u8         eth_net_offloads[0x1];
 906         u8         roce[0x1];
 907         u8         atomic[0x1];
 908         u8         reserved_at_21f[0x1];
 909
 910         u8         cq_oi[0x1];
 911         u8         cq_resize[0x1];
 912         u8         cq_moderation[0x1];
 913         u8         reserved_at_223[0x3];
 914         u8         cq_eq_remap[0x1];
 915         u8         pg[0x1];
 916         u8         block_lb_mc[0x1];
 917         u8         reserved_at_229[0x1];
 918         u8         scqe_break_moderation[0x1];
 919         u8         cq_period_start_from_cqe[0x1];
 920         u8         cd[0x1];
 921         u8         reserved_at_22d[0x1];
 922         u8         apm[0x1];
 923         u8         vector_calc[0x1];
 924         u8         umr_ptr_rlky[0x1];
 925         u8         imaicl[0x1];
 926         u8         reserved_at_232[0x4];
 927         u8         qkv[0x1];
 928         u8         pkv[0x1];
 929         u8         set_deth_sqpn[0x1];
 930         u8         reserved_at_239[0x3];
 931         u8         xrc[0x1];
 932         u8         ud[0x1];
 933         u8         uc[0x1];
 934         u8         rc[0x1];
 935
 936         u8         uar_4k[0x1];
 937         u8         reserved_at_241[0x9];
 938         u8         uar_sz[0x6];
 939         u8         reserved_at_250[0x8];
 940         u8         log_pg_sz[0x8];
 941
 942         u8         bf[0x1];
 943         u8         driver_version[0x1];
 944         u8         pad_tx_eth_packet[0x1];
 945         u8         reserved_at_263[0x8];
 946         u8         log_bf_reg_size[0x5];
 947
 948         u8         reserved_at_270[0xb];
 949         u8         lag_master[0x1];
 950         u8         num_lag_ports[0x4];
 951
 952         u8         reserved_at_280[0x10];
 953         u8         max_wqe_sz_sq[0x10];
 954
 955         u8         reserved_at_2a0[0x10];
 956         u8         max_wqe_sz_rq[0x10];
 957
 958         u8         reserved_at_2c0[0x10];
 959         u8         max_wqe_sz_sq_dc[0x10];
 960
 961         u8         reserved_at_2e0[0x7];
 962         u8         max_qp_mcg[0x19];
 963
 964         u8         reserved_at_300[0x18];
 965         u8         log_max_mcg[0x8];
 966
 967         u8         reserved_at_320[0x3];
 968         u8         log_max_transport_domain[0x5];
 969         u8         reserved_at_328[0x3];
 970         u8         log_max_pd[0x5];
 971         u8         reserved_at_330[0xb];
 972         u8         log_max_xrcd[0x5];
 973
 974         u8         reserved_at_340[0x8];
 975         u8         log_max_flow_counter_bulk[0x8];
 976         u8         max_flow_counter[0x10];
 977
 978
 979         u8         reserved_at_360[0x3];
 980         u8         log_max_rq[0x5];
 981         u8         reserved_at_368[0x3];
 982         u8         log_max_sq[0x5];
 983         u8         reserved_at_370[0x3];
 984         u8         log_max_tir[0x5];
 985         u8         reserved_at_378[0x3];
 986         u8         log_max_tis[0x5];
 987
 988         u8         basic_cyclic_rcv_wqe[0x1];
 989         u8         reserved_at_381[0x2];
 990         u8         log_max_rmp[0x5];
 991         u8         reserved_at_388[0x3];
 992         u8         log_max_rqt[0x5];
 993         u8         reserved_at_390[0x3];
 994         u8         log_max_rqt_size[0x5];
 995         u8         reserved_at_398[0x3];
 996         u8         log_max_tis_per_sq[0x5];
 997
 998         u8         reserved_at_3a0[0x3];
 999         u8         log_max_stride_sz_rq[0x5];
1000         u8         reserved_at_3a8[0x3];
1001         u8         log_min_stride_sz_rq[0x5];
1002         u8         reserved_at_3b0[0x3];
1003         u8         log_max_stride_sz_sq[0x5];
1004         u8         reserved_at_3b8[0x3];
1005         u8         log_min_stride_sz_sq[0x5];
1006
1007         u8         reserved_at_3c0[0x1b];
1008         u8         log_max_wq_sz[0x5];
1009
1010         u8         nic_vport_change_event[0x1];
1011         u8         reserved_at_3e1[0xa];
1012         u8         log_max_vlan_list[0x5];
1013         u8         reserved_at_3f0[0x3];
1014         u8         log_max_current_mc_list[0x5];
1015         u8         reserved_at_3f8[0x3];
1016         u8         log_max_current_uc_list[0x5];
1017
1018         u8         reserved_at_400[0x80];
1019
1020         u8         reserved_at_480[0x3];
1021         u8         log_max_l2_table[0x5];
1022         u8         reserved_at_488[0x8];
1023         u8         log_uar_page_sz[0x10];
1024
1025         u8         reserved_at_4a0[0x20];
1026         u8         device_frequency_mhz[0x20];
1027         u8         device_frequency_khz[0x20];
1028
1029         u8         reserved_at_500[0x20];
1030         u8         num_of_uars_per_page[0x20];
1031         u8         reserved_at_540[0x40];
1032
1033         u8         reserved_at_580[0x3f];
1034         u8         cqe_compression[0x1];
1035
1036         u8         cqe_compression_timeout[0x10];
1037         u8         cqe_compression_max_num[0x10];
1038
1039         u8         reserved_at_5e0[0x10];
1040         u8         tag_matching[0x1];
1041         u8         rndv_offload_rc[0x1];
1042         u8         rndv_offload_dc[0x1];
1043         u8         log_tag_matching_list_sz[0x5];
1044         u8         reserved_at_5f8[0x3];
1045         u8         log_max_xrq[0x5];
1046
1047         u8         reserved_at_600[0x200];
1048 };
1049
1050 enum mlx5_flow_destination_type {
1051         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1052         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1053         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1054
1055         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1056 };
1057
1058 struct mlx5_ifc_dest_format_struct_bits {
1059         u8         destination_type[0x8];
1060         u8         destination_id[0x18];
1061
1062         u8         reserved_at_20[0x20];
1063 };
1064
1065 struct mlx5_ifc_flow_counter_list_bits {
1066         u8         clear[0x1];
1067         u8         num_of_counters[0xf];
1068         u8         flow_counter_id[0x10];
1069
1070         u8         reserved_at_20[0x20];
1071 };
1072
1073 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1074         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1075         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1076         u8         reserved_at_0[0x40];
1077 };
1078
1079 struct mlx5_ifc_fte_match_param_bits {
1080         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1081
1082         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1083
1084         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1085
1086         u8         reserved_at_600[0xa00];
1087 };
1088
1089 enum {
1090         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1091         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1092         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1093         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1094         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1095 };
1096
1097 struct mlx5_ifc_rx_hash_field_select_bits {
1098         u8         l3_prot_type[0x1];
1099         u8         l4_prot_type[0x1];
1100         u8         selected_fields[0x1e];
1101 };
1102
1103 enum {
1104         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1105         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1106 };
1107
1108 enum {
1109         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1110         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1111 };
1112
1113 struct mlx5_ifc_wq_bits {
1114         u8         wq_type[0x4];
1115         u8         wq_signature[0x1];
1116         u8         end_padding_mode[0x2];
1117         u8         cd_slave[0x1];
1118         u8         reserved_at_8[0x18];
1119
1120         u8         hds_skip_first_sge[0x1];
1121         u8         log2_hds_buf_size[0x3];
1122         u8         reserved_at_24[0x7];
1123         u8         page_offset[0x5];
1124         u8         lwm[0x10];
1125
1126         u8         reserved_at_40[0x8];
1127         u8         pd[0x18];
1128
1129         u8         reserved_at_60[0x8];
1130         u8         uar_page[0x18];
1131
1132         u8         dbr_addr[0x40];
1133
1134         u8         hw_counter[0x20];
1135
1136         u8         sw_counter[0x20];
1137
1138         u8         reserved_at_100[0xc];
1139         u8         log_wq_stride[0x4];
1140         u8         reserved_at_110[0x3];
1141         u8         log_wq_pg_sz[0x5];
1142         u8         reserved_at_118[0x3];
1143         u8         log_wq_sz[0x5];
1144
1145         u8         reserved_at_120[0x15];
1146         u8         log_wqe_num_of_strides[0x3];
1147         u8         two_byte_shift_en[0x1];
1148         u8         reserved_at_139[0x4];
1149         u8         log_wqe_stride_size[0x3];
1150
1151         u8         reserved_at_140[0x4c0];
1152
1153         struct mlx5_ifc_cmd_pas_bits pas[0];
1154 };
1155
1156 struct mlx5_ifc_rq_num_bits {
1157         u8         reserved_at_0[0x8];
1158         u8         rq_num[0x18];
1159 };
1160
1161 struct mlx5_ifc_mac_address_layout_bits {
1162         u8         reserved_at_0[0x10];
1163         u8         mac_addr_47_32[0x10];
1164
1165         u8         mac_addr_31_0[0x20];
1166 };
1167
1168 struct mlx5_ifc_vlan_layout_bits {
1169         u8         reserved_at_0[0x14];
1170         u8         vlan[0x0c];
1171
1172         u8         reserved_at_20[0x20];
1173 };
1174
1175 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1176         u8         reserved_at_0[0xa0];
1177
1178         u8         min_time_between_cnps[0x20];
1179
1180         u8         reserved_at_c0[0x12];
1181         u8         cnp_dscp[0x6];
1182         u8         reserved_at_d8[0x5];
1183         u8         cnp_802p_prio[0x3];
1184
1185         u8         reserved_at_e0[0x720];
1186 };
1187
1188 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1189         u8         reserved_at_0[0x60];
1190
1191         u8         reserved_at_60[0x4];
1192         u8         clamp_tgt_rate[0x1];
1193         u8         reserved_at_65[0x3];
1194         u8         clamp_tgt_rate_after_time_inc[0x1];
1195         u8         reserved_at_69[0x17];
1196
1197         u8         reserved_at_80[0x20];
1198
1199         u8         rpg_time_reset[0x20];
1200
1201         u8         rpg_byte_reset[0x20];
1202
1203         u8         rpg_threshold[0x20];
1204
1205         u8         rpg_max_rate[0x20];
1206
1207         u8         rpg_ai_rate[0x20];
1208
1209         u8         rpg_hai_rate[0x20];
1210
1211         u8         rpg_gd[0x20];
1212
1213         u8         rpg_min_dec_fac[0x20];
1214
1215         u8         rpg_min_rate[0x20];
1216
1217         u8         reserved_at_1c0[0xe0];
1218
1219         u8         rate_to_set_on_first_cnp[0x20];
1220
1221         u8         dce_tcp_g[0x20];
1222
1223         u8         dce_tcp_rtt[0x20];
1224
1225         u8         rate_reduce_monitor_period[0x20];
1226
1227         u8         reserved_at_320[0x20];
1228
1229         u8         initial_alpha_value[0x20];
1230
1231         u8         reserved_at_360[0x4a0];
1232 };
1233
1234 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1235         u8         reserved_at_0[0x80];
1236
1237         u8         rppp_max_rps[0x20];
1238
1239         u8         rpg_time_reset[0x20];
1240
1241         u8         rpg_byte_reset[0x20];
1242
1243         u8         rpg_threshold[0x20];
1244
1245         u8         rpg_max_rate[0x20];
1246
1247         u8         rpg_ai_rate[0x20];
1248
1249         u8         rpg_hai_rate[0x20];
1250
1251         u8         rpg_gd[0x20];
1252
1253         u8         rpg_min_dec_fac[0x20];
1254
1255         u8         rpg_min_rate[0x20];
1256
1257         u8         reserved_at_1c0[0x640];
1258 };
1259
1260 enum {
1261         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1262         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1263         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1264 };
1265
1266 struct mlx5_ifc_resize_field_select_bits {
1267         u8         resize_field_select[0x20];
1268 };
1269
1270 enum {
1271         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1272         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1273         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1274         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1275 };
1276
1277 struct mlx5_ifc_modify_field_select_bits {
1278         u8         modify_field_select[0x20];
1279 };
1280
1281 struct mlx5_ifc_field_select_r_roce_np_bits {
1282         u8         field_select_r_roce_np[0x20];
1283 };
1284
1285 struct mlx5_ifc_field_select_r_roce_rp_bits {
1286         u8         field_select_r_roce_rp[0x20];
1287 };
1288
1289 enum {
1290         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1291         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1292         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1293         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1294         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1295         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1296         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1297         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1298         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1299         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1300 };
1301
1302 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1303         u8         field_select_8021qaurp[0x20];
1304 };
1305
1306 struct mlx5_ifc_phys_layer_cntrs_bits {
1307         u8         time_since_last_clear_high[0x20];
1308
1309         u8         time_since_last_clear_low[0x20];
1310
1311         u8         symbol_errors_high[0x20];
1312
1313         u8         symbol_errors_low[0x20];
1314
1315         u8         sync_headers_errors_high[0x20];
1316
1317         u8         sync_headers_errors_low[0x20];
1318
1319         u8         edpl_bip_errors_lane0_high[0x20];
1320
1321         u8         edpl_bip_errors_lane0_low[0x20];
1322
1323         u8         edpl_bip_errors_lane1_high[0x20];
1324
1325         u8         edpl_bip_errors_lane1_low[0x20];
1326
1327         u8         edpl_bip_errors_lane2_high[0x20];
1328
1329         u8         edpl_bip_errors_lane2_low[0x20];
1330
1331         u8         edpl_bip_errors_lane3_high[0x20];
1332
1333         u8         edpl_bip_errors_lane3_low[0x20];
1334
1335         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1336
1337         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1338
1339         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1340
1341         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1342
1343         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1344
1345         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1346
1347         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1348
1349         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1350
1351         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1352
1353         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1354
1355         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1356
1357         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1358
1359         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1360
1361         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1362
1363         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1364
1365         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1366
1367         u8         rs_fec_corrected_blocks_high[0x20];
1368
1369         u8         rs_fec_corrected_blocks_low[0x20];
1370
1371         u8         rs_fec_uncorrectable_blocks_high[0x20];
1372
1373         u8         rs_fec_uncorrectable_blocks_low[0x20];
1374
1375         u8         rs_fec_no_errors_blocks_high[0x20];
1376
1377         u8         rs_fec_no_errors_blocks_low[0x20];
1378
1379         u8         rs_fec_single_error_blocks_high[0x20];
1380
1381         u8         rs_fec_single_error_blocks_low[0x20];
1382
1383         u8         rs_fec_corrected_symbols_total_high[0x20];
1384
1385         u8         rs_fec_corrected_symbols_total_low[0x20];
1386
1387         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1388
1389         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1390
1391         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1392
1393         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1394
1395         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1396
1397         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1398
1399         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1400
1401         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1402
1403         u8         link_down_events[0x20];
1404
1405         u8         successful_recovery_events[0x20];
1406
1407         u8         reserved_at_640[0x180];
1408 };
1409
1410 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1411         u8         time_since_last_clear_high[0x20];
1412
1413         u8         time_since_last_clear_low[0x20];
1414
1415         u8         phy_received_bits_high[0x20];
1416
1417         u8         phy_received_bits_low[0x20];
1418
1419         u8         phy_symbol_errors_high[0x20];
1420
1421         u8         phy_symbol_errors_low[0x20];
1422
1423         u8         phy_corrected_bits_high[0x20];
1424
1425         u8         phy_corrected_bits_low[0x20];
1426
1427         u8         phy_corrected_bits_lane0_high[0x20];
1428
1429         u8         phy_corrected_bits_lane0_low[0x20];
1430
1431         u8         phy_corrected_bits_lane1_high[0x20];
1432
1433         u8         phy_corrected_bits_lane1_low[0x20];
1434
1435         u8         phy_corrected_bits_lane2_high[0x20];
1436
1437         u8         phy_corrected_bits_lane2_low[0x20];
1438
1439         u8         phy_corrected_bits_lane3_high[0x20];
1440
1441         u8         phy_corrected_bits_lane3_low[0x20];
1442
1443         u8         reserved_at_200[0x5c0];
1444 };
1445
1446 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1447         u8         symbol_error_counter[0x10];
1448
1449         u8         link_error_recovery_counter[0x8];
1450
1451         u8         link_downed_counter[0x8];
1452
1453         u8         port_rcv_errors[0x10];
1454
1455         u8         port_rcv_remote_physical_errors[0x10];
1456
1457         u8         port_rcv_switch_relay_errors[0x10];
1458
1459         u8         port_xmit_discards[0x10];
1460
1461         u8         port_xmit_constraint_errors[0x8];
1462
1463         u8         port_rcv_constraint_errors[0x8];
1464
1465         u8         reserved_at_70[0x8];
1466
1467         u8         link_overrun_errors[0x8];
1468
1469         u8         reserved_at_80[0x10];
1470
1471         u8         vl_15_dropped[0x10];
1472
1473         u8         reserved_at_a0[0x80];
1474
1475         u8         port_xmit_wait[0x20];
1476 };
1477
1478 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1479         u8         transmit_queue_high[0x20];
1480
1481         u8         transmit_queue_low[0x20];
1482
1483         u8         reserved_at_40[0x780];
1484 };
1485
1486 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1487         u8         rx_octets_high[0x20];
1488
1489         u8         rx_octets_low[0x20];
1490
1491         u8         reserved_at_40[0xc0];
1492
1493         u8         rx_frames_high[0x20];
1494
1495         u8         rx_frames_low[0x20];
1496
1497         u8         tx_octets_high[0x20];
1498
1499         u8         tx_octets_low[0x20];
1500
1501         u8         reserved_at_180[0xc0];
1502
1503         u8         tx_frames_high[0x20];
1504
1505         u8         tx_frames_low[0x20];
1506
1507         u8         rx_pause_high[0x20];
1508
1509         u8         rx_pause_low[0x20];
1510
1511         u8         rx_pause_duration_high[0x20];
1512
1513         u8         rx_pause_duration_low[0x20];
1514
1515         u8         tx_pause_high[0x20];
1516
1517         u8         tx_pause_low[0x20];
1518
1519         u8         tx_pause_duration_high[0x20];
1520
1521         u8         tx_pause_duration_low[0x20];
1522
1523         u8         rx_pause_transition_high[0x20];
1524
1525         u8         rx_pause_transition_low[0x20];
1526
1527         u8         reserved_at_3c0[0x400];
1528 };
1529
1530 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1531         u8         port_transmit_wait_high[0x20];
1532
1533         u8         port_transmit_wait_low[0x20];
1534
1535         u8         reserved_at_40[0x780];
1536 };
1537
1538 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1539         u8         dot3stats_alignment_errors_high[0x20];
1540
1541         u8         dot3stats_alignment_errors_low[0x20];
1542
1543         u8         dot3stats_fcs_errors_high[0x20];
1544
1545         u8         dot3stats_fcs_errors_low[0x20];
1546
1547         u8         dot3stats_single_collision_frames_high[0x20];
1548
1549         u8         dot3stats_single_collision_frames_low[0x20];
1550
1551         u8         dot3stats_multiple_collision_frames_high[0x20];
1552
1553         u8         dot3stats_multiple_collision_frames_low[0x20];
1554
1555         u8         dot3stats_sqe_test_errors_high[0x20];
1556
1557         u8         dot3stats_sqe_test_errors_low[0x20];
1558
1559         u8         dot3stats_deferred_transmissions_high[0x20];
1560
1561         u8         dot3stats_deferred_transmissions_low[0x20];
1562
1563         u8         dot3stats_late_collisions_high[0x20];
1564
1565         u8         dot3stats_late_collisions_low[0x20];
1566
1567         u8         dot3stats_excessive_collisions_high[0x20];
1568
1569         u8         dot3stats_excessive_collisions_low[0x20];
1570
1571         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1572
1573         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1574
1575         u8         dot3stats_carrier_sense_errors_high[0x20];
1576
1577         u8         dot3stats_carrier_sense_errors_low[0x20];
1578
1579         u8         dot3stats_frame_too_longs_high[0x20];
1580
1581         u8         dot3stats_frame_too_longs_low[0x20];
1582
1583         u8         dot3stats_internal_mac_receive_errors_high[0x20];
1584
1585         u8         dot3stats_internal_mac_receive_errors_low[0x20];
1586
1587         u8         dot3stats_symbol_errors_high[0x20];
1588
1589         u8         dot3stats_symbol_errors_low[0x20];
1590
1591         u8         dot3control_in_unknown_opcodes_high[0x20];
1592
1593         u8         dot3control_in_unknown_opcodes_low[0x20];
1594
1595         u8         dot3in_pause_frames_high[0x20];
1596
1597         u8         dot3in_pause_frames_low[0x20];
1598
1599         u8         dot3out_pause_frames_high[0x20];
1600
1601         u8         dot3out_pause_frames_low[0x20];
1602
1603         u8         reserved_at_400[0x3c0];
1604 };
1605
1606 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1607         u8         ether_stats_drop_events_high[0x20];
1608
1609         u8         ether_stats_drop_events_low[0x20];
1610
1611         u8         ether_stats_octets_high[0x20];
1612
1613         u8         ether_stats_octets_low[0x20];
1614
1615         u8         ether_stats_pkts_high[0x20];
1616
1617         u8         ether_stats_pkts_low[0x20];
1618
1619         u8         ether_stats_broadcast_pkts_high[0x20];
1620
1621         u8         ether_stats_broadcast_pkts_low[0x20];
1622
1623         u8         ether_stats_multicast_pkts_high[0x20];
1624
1625         u8         ether_stats_multicast_pkts_low[0x20];
1626
1627         u8         ether_stats_crc_align_errors_high[0x20];
1628
1629         u8         ether_stats_crc_align_errors_low[0x20];
1630
1631         u8         ether_stats_undersize_pkts_high[0x20];
1632
1633         u8         ether_stats_undersize_pkts_low[0x20];
1634
1635         u8         ether_stats_oversize_pkts_high[0x20];
1636
1637         u8         ether_stats_oversize_pkts_low[0x20];
1638
1639         u8         ether_stats_fragments_high[0x20];
1640
1641         u8         ether_stats_fragments_low[0x20];
1642
1643         u8         ether_stats_jabbers_high[0x20];
1644
1645         u8         ether_stats_jabbers_low[0x20];
1646
1647         u8         ether_stats_collisions_high[0x20];
1648
1649         u8         ether_stats_collisions_low[0x20];
1650
1651         u8         ether_stats_pkts64octets_high[0x20];
1652
1653         u8         ether_stats_pkts64octets_low[0x20];
1654
1655         u8         ether_stats_pkts65to127octets_high[0x20];
1656
1657         u8         ether_stats_pkts65to127octets_low[0x20];
1658
1659         u8         ether_stats_pkts128to255octets_high[0x20];
1660
1661         u8         ether_stats_pkts128to255octets_low[0x20];
1662
1663         u8         ether_stats_pkts256to511octets_high[0x20];
1664
1665         u8         ether_stats_pkts256to511octets_low[0x20];
1666
1667         u8         ether_stats_pkts512to1023octets_high[0x20];
1668
1669         u8         ether_stats_pkts512to1023octets_low[0x20];
1670
1671         u8         ether_stats_pkts1024to1518octets_high[0x20];
1672
1673         u8         ether_stats_pkts1024to1518octets_low[0x20];
1674
1675         u8         ether_stats_pkts1519to2047octets_high[0x20];
1676
1677         u8         ether_stats_pkts1519to2047octets_low[0x20];
1678
1679         u8         ether_stats_pkts2048to4095octets_high[0x20];
1680
1681         u8         ether_stats_pkts2048to4095octets_low[0x20];
1682
1683         u8         ether_stats_pkts4096to8191octets_high[0x20];
1684
1685         u8         ether_stats_pkts4096to8191octets_low[0x20];
1686
1687         u8         ether_stats_pkts8192to10239octets_high[0x20];
1688
1689         u8         ether_stats_pkts8192to10239octets_low[0x20];
1690
1691         u8         reserved_at_540[0x280];
1692 };
1693
1694 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1695         u8         if_in_octets_high[0x20];
1696
1697         u8         if_in_octets_low[0x20];
1698
1699         u8         if_in_ucast_pkts_high[0x20];
1700
1701         u8         if_in_ucast_pkts_low[0x20];
1702
1703         u8         if_in_discards_high[0x20];
1704
1705         u8         if_in_discards_low[0x20];
1706
1707         u8         if_in_errors_high[0x20];
1708
1709         u8         if_in_errors_low[0x20];
1710
1711         u8         if_in_unknown_protos_high[0x20];
1712
1713         u8         if_in_unknown_protos_low[0x20];
1714
1715         u8         if_out_octets_high[0x20];
1716
1717         u8         if_out_octets_low[0x20];
1718
1719         u8         if_out_ucast_pkts_high[0x20];
1720
1721         u8         if_out_ucast_pkts_low[0x20];
1722
1723         u8         if_out_discards_high[0x20];
1724
1725         u8         if_out_discards_low[0x20];
1726
1727         u8         if_out_errors_high[0x20];
1728
1729         u8         if_out_errors_low[0x20];
1730
1731         u8         if_in_multicast_pkts_high[0x20];
1732
1733         u8         if_in_multicast_pkts_low[0x20];
1734
1735         u8         if_in_broadcast_pkts_high[0x20];
1736
1737         u8         if_in_broadcast_pkts_low[0x20];
1738
1739         u8         if_out_multicast_pkts_high[0x20];
1740
1741         u8         if_out_multicast_pkts_low[0x20];
1742
1743         u8         if_out_broadcast_pkts_high[0x20];
1744
1745         u8         if_out_broadcast_pkts_low[0x20];
1746
1747         u8         reserved_at_340[0x480];
1748 };
1749
1750 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1751         u8         a_frames_transmitted_ok_high[0x20];
1752
1753         u8         a_frames_transmitted_ok_low[0x20];
1754
1755         u8         a_frames_received_ok_high[0x20];
1756
1757         u8         a_frames_received_ok_low[0x20];
1758
1759         u8         a_frame_check_sequence_errors_high[0x20];
1760
1761         u8         a_frame_check_sequence_errors_low[0x20];
1762
1763         u8         a_alignment_errors_high[0x20];
1764
1765         u8         a_alignment_errors_low[0x20];
1766
1767         u8         a_octets_transmitted_ok_high[0x20];
1768
1769         u8         a_octets_transmitted_ok_low[0x20];
1770
1771         u8         a_octets_received_ok_high[0x20];
1772
1773         u8         a_octets_received_ok_low[0x20];
1774
1775         u8         a_multicast_frames_xmitted_ok_high[0x20];
1776
1777         u8         a_multicast_frames_xmitted_ok_low[0x20];
1778
1779         u8         a_broadcast_frames_xmitted_ok_high[0x20];
1780
1781         u8         a_broadcast_frames_xmitted_ok_low[0x20];
1782
1783         u8         a_multicast_frames_received_ok_high[0x20];
1784
1785         u8         a_multicast_frames_received_ok_low[0x20];
1786
1787         u8         a_broadcast_frames_received_ok_high[0x20];
1788
1789         u8         a_broadcast_frames_received_ok_low[0x20];
1790
1791         u8         a_in_range_length_errors_high[0x20];
1792
1793         u8         a_in_range_length_errors_low[0x20];
1794
1795         u8         a_out_of_range_length_field_high[0x20];
1796
1797         u8         a_out_of_range_length_field_low[0x20];
1798
1799         u8         a_frame_too_long_errors_high[0x20];
1800
1801         u8         a_frame_too_long_errors_low[0x20];
1802
1803         u8         a_symbol_error_during_carrier_high[0x20];
1804
1805         u8         a_symbol_error_during_carrier_low[0x20];
1806
1807         u8         a_mac_control_frames_transmitted_high[0x20];
1808
1809         u8         a_mac_control_frames_transmitted_low[0x20];
1810
1811         u8         a_mac_control_frames_received_high[0x20];
1812
1813         u8         a_mac_control_frames_received_low[0x20];
1814
1815         u8         a_unsupported_opcodes_received_high[0x20];
1816
1817         u8         a_unsupported_opcodes_received_low[0x20];
1818
1819         u8         a_pause_mac_ctrl_frames_received_high[0x20];
1820
1821         u8         a_pause_mac_ctrl_frames_received_low[0x20];
1822
1823         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
1824
1825         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
1826
1827         u8         reserved_at_4c0[0x300];
1828 };
1829
1830 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1831         u8         life_time_counter_high[0x20];
1832
1833         u8         life_time_counter_low[0x20];
1834
1835         u8         rx_errors[0x20];
1836
1837         u8         tx_errors[0x20];
1838
1839         u8         l0_to_recovery_eieos[0x20];
1840
1841         u8         l0_to_recovery_ts[0x20];
1842
1843         u8         l0_to_recovery_framing[0x20];
1844
1845         u8         l0_to_recovery_retrain[0x20];
1846
1847         u8         crc_error_dllp[0x20];
1848
1849         u8         crc_error_tlp[0x20];
1850
1851         u8         reserved_at_140[0x680];
1852 };
1853
1854 struct mlx5_ifc_cmd_inter_comp_event_bits {
1855         u8         command_completion_vector[0x20];
1856
1857         u8         reserved_at_20[0xc0];
1858 };
1859
1860 struct mlx5_ifc_stall_vl_event_bits {
1861         u8         reserved_at_0[0x18];
1862         u8         port_num[0x1];
1863         u8         reserved_at_19[0x3];
1864         u8         vl[0x4];
1865
1866         u8         reserved_at_20[0xa0];
1867 };
1868
1869 struct mlx5_ifc_db_bf_congestion_event_bits {
1870         u8         event_subtype[0x8];
1871         u8         reserved_at_8[0x8];
1872         u8         congestion_level[0x8];
1873         u8         reserved_at_18[0x8];
1874
1875         u8         reserved_at_20[0xa0];
1876 };
1877
1878 struct mlx5_ifc_gpio_event_bits {
1879         u8         reserved_at_0[0x60];
1880
1881         u8         gpio_event_hi[0x20];
1882
1883         u8         gpio_event_lo[0x20];
1884
1885         u8         reserved_at_a0[0x40];
1886 };
1887
1888 struct mlx5_ifc_port_state_change_event_bits {
1889         u8         reserved_at_0[0x40];
1890
1891         u8         port_num[0x4];
1892         u8         reserved_at_44[0x1c];
1893
1894         u8         reserved_at_60[0x80];
1895 };
1896
1897 struct mlx5_ifc_dropped_packet_logged_bits {
1898         u8         reserved_at_0[0xe0];
1899 };
1900
1901 enum {
1902         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
1903         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
1904 };
1905
1906 struct mlx5_ifc_cq_error_bits {
1907         u8         reserved_at_0[0x8];
1908         u8         cqn[0x18];
1909
1910         u8         reserved_at_20[0x20];
1911
1912         u8         reserved_at_40[0x18];
1913         u8         syndrome[0x8];
1914
1915         u8         reserved_at_60[0x80];
1916 };
1917
1918 struct mlx5_ifc_rdma_page_fault_event_bits {
1919         u8         bytes_committed[0x20];
1920
1921         u8         r_key[0x20];
1922
1923         u8         reserved_at_40[0x10];
1924         u8         packet_len[0x10];
1925
1926         u8         rdma_op_len[0x20];
1927
1928         u8         rdma_va[0x40];
1929
1930         u8         reserved_at_c0[0x5];
1931         u8         rdma[0x1];
1932         u8         write[0x1];
1933         u8         requestor[0x1];
1934         u8         qp_number[0x18];
1935 };
1936
1937 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1938         u8         bytes_committed[0x20];
1939
1940         u8         reserved_at_20[0x10];
1941         u8         wqe_index[0x10];
1942
1943         u8         reserved_at_40[0x10];
1944         u8         len[0x10];
1945
1946         u8         reserved_at_60[0x60];
1947
1948         u8         reserved_at_c0[0x5];
1949         u8         rdma[0x1];
1950         u8         write_read[0x1];
1951         u8         requestor[0x1];
1952         u8         qpn[0x18];
1953 };
1954
1955 struct mlx5_ifc_qp_events_bits {
1956         u8         reserved_at_0[0xa0];
1957
1958         u8         type[0x8];
1959         u8         reserved_at_a8[0x18];
1960
1961         u8         reserved_at_c0[0x8];
1962         u8         qpn_rqn_sqn[0x18];
1963 };
1964
1965 struct mlx5_ifc_dct_events_bits {
1966         u8         reserved_at_0[0xc0];
1967
1968         u8         reserved_at_c0[0x8];
1969         u8         dct_number[0x18];
1970 };
1971
1972 struct mlx5_ifc_comp_event_bits {
1973         u8         reserved_at_0[0xc0];
1974
1975         u8         reserved_at_c0[0x8];
1976         u8         cq_number[0x18];
1977 };
1978
1979 enum {
1980         MLX5_QPC_STATE_RST        = 0x0,
1981         MLX5_QPC_STATE_INIT       = 0x1,
1982         MLX5_QPC_STATE_RTR        = 0x2,
1983         MLX5_QPC_STATE_RTS        = 0x3,
1984         MLX5_QPC_STATE_SQER       = 0x4,
1985         MLX5_QPC_STATE_ERR        = 0x6,
1986         MLX5_QPC_STATE_SQD        = 0x7,
1987         MLX5_QPC_STATE_SUSPENDED  = 0x9,
1988 };
1989
1990 enum {
1991         MLX5_QPC_ST_RC            = 0x0,
1992         MLX5_QPC_ST_UC            = 0x1,
1993         MLX5_QPC_ST_UD            = 0x2,
1994         MLX5_QPC_ST_XRC           = 0x3,
1995         MLX5_QPC_ST_DCI           = 0x5,
1996         MLX5_QPC_ST_QP0           = 0x7,
1997         MLX5_QPC_ST_QP1           = 0x8,
1998         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
1999         MLX5_QPC_ST_REG_UMR       = 0xc,
2000 };
2001
2002 enum {
2003         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2004         MLX5_QPC_PM_STATE_REARM     = 0x1,
2005         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2006         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2007 };
2008
2009 enum {
2010         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2011         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2012 };
2013
2014 enum {
2015         MLX5_QPC_MTU_256_BYTES        = 0x1,
2016         MLX5_QPC_MTU_512_BYTES        = 0x2,
2017         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2018         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2019         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2020         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2021 };
2022
2023 enum {
2024         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2025         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2026         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2027         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2028         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2029         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2030         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2031         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2032 };
2033
2034 enum {
2035         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2036         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2037         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2038 };
2039
2040 enum {
2041         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2042         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2043         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2044 };
2045
2046 struct mlx5_ifc_qpc_bits {
2047         u8         state[0x4];
2048         u8         lag_tx_port_affinity[0x4];
2049         u8         st[0x8];
2050         u8         reserved_at_10[0x3];
2051         u8         pm_state[0x2];
2052         u8         reserved_at_15[0x7];
2053         u8         end_padding_mode[0x2];
2054         u8         reserved_at_1e[0x2];
2055
2056         u8         wq_signature[0x1];
2057         u8         block_lb_mc[0x1];
2058         u8         atomic_like_write_en[0x1];
2059         u8         latency_sensitive[0x1];
2060         u8         reserved_at_24[0x1];
2061         u8         drain_sigerr[0x1];
2062         u8         reserved_at_26[0x2];
2063         u8         pd[0x18];
2064
2065         u8         mtu[0x3];
2066         u8         log_msg_max[0x5];
2067         u8         reserved_at_48[0x1];
2068         u8         log_rq_size[0x4];
2069         u8         log_rq_stride[0x3];
2070         u8         no_sq[0x1];
2071         u8         log_sq_size[0x4];
2072         u8         reserved_at_55[0x6];
2073         u8         rlky[0x1];
2074         u8         ulp_stateless_offload_mode[0x4];
2075
2076         u8         counter_set_id[0x8];
2077         u8         uar_page[0x18];
2078
2079         u8         reserved_at_80[0x8];
2080         u8         user_index[0x18];
2081
2082         u8         reserved_at_a0[0x3];
2083         u8         log_page_size[0x5];
2084         u8         remote_qpn[0x18];
2085
2086         struct mlx5_ifc_ads_bits primary_address_path;
2087
2088         struct mlx5_ifc_ads_bits secondary_address_path;
2089
2090         u8         log_ack_req_freq[0x4];
2091         u8         reserved_at_384[0x4];
2092         u8         log_sra_max[0x3];
2093         u8         reserved_at_38b[0x2];
2094         u8         retry_count[0x3];
2095         u8         rnr_retry[0x3];
2096         u8         reserved_at_393[0x1];
2097         u8         fre[0x1];
2098         u8         cur_rnr_retry[0x3];
2099         u8         cur_retry_count[0x3];
2100         u8         reserved_at_39b[0x5];
2101
2102         u8         reserved_at_3a0[0x20];
2103
2104         u8         reserved_at_3c0[0x8];
2105         u8         next_send_psn[0x18];
2106
2107         u8         reserved_at_3e0[0x8];
2108         u8         cqn_snd[0x18];
2109
2110         u8         reserved_at_400[0x8];
2111         u8         deth_sqpn[0x18];
2112
2113         u8         reserved_at_420[0x20];
2114
2115         u8         reserved_at_440[0x8];
2116         u8         last_acked_psn[0x18];
2117
2118         u8         reserved_at_460[0x8];
2119         u8         ssn[0x18];
2120
2121         u8         reserved_at_480[0x8];
2122         u8         log_rra_max[0x3];
2123         u8         reserved_at_48b[0x1];
2124         u8         atomic_mode[0x4];
2125         u8         rre[0x1];
2126         u8         rwe[0x1];
2127         u8         rae[0x1];
2128         u8         reserved_at_493[0x1];
2129         u8         page_offset[0x6];
2130         u8         reserved_at_49a[0x3];
2131         u8         cd_slave_receive[0x1];
2132         u8         cd_slave_send[0x1];
2133         u8         cd_master[0x1];
2134
2135         u8         reserved_at_4a0[0x3];
2136         u8         min_rnr_nak[0x5];
2137         u8         next_rcv_psn[0x18];
2138
2139         u8         reserved_at_4c0[0x8];
2140         u8         xrcd[0x18];
2141
2142         u8         reserved_at_4e0[0x8];
2143         u8         cqn_rcv[0x18];
2144
2145         u8         dbr_addr[0x40];
2146
2147         u8         q_key[0x20];
2148
2149         u8         reserved_at_560[0x5];
2150         u8         rq_type[0x3];
2151         u8         srqn_rmpn_xrqn[0x18];
2152
2153         u8         reserved_at_580[0x8];
2154         u8         rmsn[0x18];
2155
2156         u8         hw_sq_wqebb_counter[0x10];
2157         u8         sw_sq_wqebb_counter[0x10];
2158
2159         u8         hw_rq_counter[0x20];
2160
2161         u8         sw_rq_counter[0x20];
2162
2163         u8         reserved_at_600[0x20];
2164
2165         u8         reserved_at_620[0xf];
2166         u8         cgs[0x1];
2167         u8         cs_req[0x8];
2168         u8         cs_res[0x8];
2169
2170         u8         dc_access_key[0x40];
2171
2172         u8         reserved_at_680[0xc0];
2173 };
2174
2175 struct mlx5_ifc_roce_addr_layout_bits {
2176         u8         source_l3_address[16][0x8];
2177
2178         u8         reserved_at_80[0x3];
2179         u8         vlan_valid[0x1];
2180         u8         vlan_id[0xc];
2181         u8         source_mac_47_32[0x10];
2182
2183         u8         source_mac_31_0[0x20];
2184
2185         u8         reserved_at_c0[0x14];
2186         u8         roce_l3_type[0x4];
2187         u8         roce_version[0x8];
2188
2189         u8         reserved_at_e0[0x20];
2190 };
2191
2192 union mlx5_ifc_hca_cap_union_bits {
2193         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2194         struct mlx5_ifc_odp_cap_bits odp_cap;
2195         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2196         struct mlx5_ifc_roce_cap_bits roce_cap;
2197         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2198         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2199         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2200         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2201         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2202         struct mlx5_ifc_qos_cap_bits qos_cap;
2203         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2204         u8         reserved_at_0[0x8000];
2205 };
2206
2207 enum {
2208         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2209         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2210         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2211         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2212         MLX5_FLOW_CONTEXT_ACTION_ENCAP     = 0x10,
2213         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2214         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2215 };
2216
2217 struct mlx5_ifc_flow_context_bits {
2218         u8         reserved_at_0[0x20];
2219
2220         u8         group_id[0x20];
2221
2222         u8         reserved_at_40[0x8];
2223         u8         flow_tag[0x18];
2224
2225         u8         reserved_at_60[0x10];
2226         u8         action[0x10];
2227
2228         u8         reserved_at_80[0x8];
2229         u8         destination_list_size[0x18];
2230
2231         u8         reserved_at_a0[0x8];
2232         u8         flow_counter_list_size[0x18];
2233
2234         u8         encap_id[0x20];
2235
2236         u8         modify_header_id[0x20];
2237
2238         u8         reserved_at_100[0x100];
2239
2240         struct mlx5_ifc_fte_match_param_bits match_value;
2241
2242         u8         reserved_at_1200[0x600];
2243
2244         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2245 };
2246
2247 enum {
2248         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2249         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2250 };
2251
2252 struct mlx5_ifc_xrc_srqc_bits {
2253         u8         state[0x4];
2254         u8         log_xrc_srq_size[0x4];
2255         u8         reserved_at_8[0x18];
2256
2257         u8         wq_signature[0x1];
2258         u8         cont_srq[0x1];
2259         u8         reserved_at_22[0x1];
2260         u8         rlky[0x1];
2261         u8         basic_cyclic_rcv_wqe[0x1];
2262         u8         log_rq_stride[0x3];
2263         u8         xrcd[0x18];
2264
2265         u8         page_offset[0x6];
2266         u8         reserved_at_46[0x2];
2267         u8         cqn[0x18];
2268
2269         u8         reserved_at_60[0x20];
2270
2271         u8         user_index_equal_xrc_srqn[0x1];
2272         u8         reserved_at_81[0x1];
2273         u8         log_page_size[0x6];
2274         u8         user_index[0x18];
2275
2276         u8         reserved_at_a0[0x20];
2277
2278         u8         reserved_at_c0[0x8];
2279         u8         pd[0x18];
2280
2281         u8         lwm[0x10];
2282         u8         wqe_cnt[0x10];
2283
2284         u8         reserved_at_100[0x40];
2285
2286         u8         db_record_addr_h[0x20];
2287
2288         u8         db_record_addr_l[0x1e];
2289         u8         reserved_at_17e[0x2];
2290
2291         u8         reserved_at_180[0x80];
2292 };
2293
2294 struct mlx5_ifc_traffic_counter_bits {
2295         u8         packets[0x40];
2296
2297         u8         octets[0x40];
2298 };
2299
2300 struct mlx5_ifc_tisc_bits {
2301         u8         strict_lag_tx_port_affinity[0x1];
2302         u8         reserved_at_1[0x3];
2303         u8         lag_tx_port_affinity[0x04];
2304
2305         u8         reserved_at_8[0x4];
2306         u8         prio[0x4];
2307         u8         reserved_at_10[0x10];
2308
2309         u8         reserved_at_20[0x100];
2310
2311         u8         reserved_at_120[0x8];
2312         u8         transport_domain[0x18];
2313
2314         u8         reserved_at_140[0x8];
2315         u8         underlay_qpn[0x18];
2316         u8         reserved_at_160[0x3a0];
2317 };
2318
2319 enum {
2320         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2321         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2322 };
2323
2324 enum {
2325         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2326         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2327 };
2328
2329 enum {
2330         MLX5_RX_HASH_FN_NONE           = 0x0,
2331         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2332         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2333 };
2334
2335 enum {
2336         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_    = 0x1,
2337         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_  = 0x2,
2338 };
2339
2340 struct mlx5_ifc_tirc_bits {
2341         u8         reserved_at_0[0x20];
2342
2343         u8         disp_type[0x4];
2344         u8         reserved_at_24[0x1c];
2345
2346         u8         reserved_at_40[0x40];
2347
2348         u8         reserved_at_80[0x4];
2349         u8         lro_timeout_period_usecs[0x10];
2350         u8         lro_enable_mask[0x4];
2351         u8         lro_max_ip_payload_size[0x8];
2352
2353         u8         reserved_at_a0[0x40];
2354
2355         u8         reserved_at_e0[0x8];
2356         u8         inline_rqn[0x18];
2357
2358         u8         rx_hash_symmetric[0x1];
2359         u8         reserved_at_101[0x1];
2360         u8         tunneled_offload_en[0x1];
2361         u8         reserved_at_103[0x5];
2362         u8         indirect_table[0x18];
2363
2364         u8         rx_hash_fn[0x4];
2365         u8         reserved_at_124[0x2];
2366         u8         self_lb_block[0x2];
2367         u8         transport_domain[0x18];
2368
2369         u8         rx_hash_toeplitz_key[10][0x20];
2370
2371         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2372
2373         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2374
2375         u8         reserved_at_2c0[0x4c0];
2376 };
2377
2378 enum {
2379         MLX5_SRQC_STATE_GOOD   = 0x0,
2380         MLX5_SRQC_STATE_ERROR  = 0x1,
2381 };
2382
2383 struct mlx5_ifc_srqc_bits {
2384         u8         state[0x4];
2385         u8         log_srq_size[0x4];
2386         u8         reserved_at_8[0x18];
2387
2388         u8         wq_signature[0x1];
2389         u8         cont_srq[0x1];
2390         u8         reserved_at_22[0x1];
2391         u8         rlky[0x1];
2392         u8         reserved_at_24[0x1];
2393         u8         log_rq_stride[0x3];
2394         u8         xrcd[0x18];
2395
2396         u8         page_offset[0x6];
2397         u8         reserved_at_46[0x2];
2398         u8         cqn[0x18];
2399
2400         u8         reserved_at_60[0x20];
2401
2402         u8         reserved_at_80[0x2];
2403         u8         log_page_size[0x6];
2404         u8         reserved_at_88[0x18];
2405
2406         u8         reserved_at_a0[0x20];
2407
2408         u8         reserved_at_c0[0x8];
2409         u8         pd[0x18];
2410
2411         u8         lwm[0x10];
2412         u8         wqe_cnt[0x10];
2413
2414         u8         reserved_at_100[0x40];
2415
2416         u8         dbr_addr[0x40];
2417
2418         u8         reserved_at_180[0x80];
2419 };
2420
2421 enum {
2422         MLX5_SQC_STATE_RST  = 0x0,
2423         MLX5_SQC_STATE_RDY  = 0x1,
2424         MLX5_SQC_STATE_ERR  = 0x3,
2425 };
2426
2427 struct mlx5_ifc_sqc_bits {
2428         u8         rlky[0x1];
2429         u8         cd_master[0x1];
2430         u8         fre[0x1];
2431         u8         flush_in_error_en[0x1];
2432         u8         reserved_at_4[0x1];
2433         u8         min_wqe_inline_mode[0x3];
2434         u8         state[0x4];
2435         u8         reg_umr[0x1];
2436         u8         reserved_at_d[0x13];
2437
2438         u8         reserved_at_20[0x8];
2439         u8         user_index[0x18];
2440
2441         u8         reserved_at_40[0x8];
2442         u8         cqn[0x18];
2443
2444         u8         reserved_at_60[0x90];
2445
2446         u8         packet_pacing_rate_limit_index[0x10];
2447         u8         tis_lst_sz[0x10];
2448         u8         reserved_at_110[0x10];
2449
2450         u8         reserved_at_120[0x40];
2451
2452         u8         reserved_at_160[0x8];
2453         u8         tis_num_0[0x18];
2454
2455         struct mlx5_ifc_wq_bits wq;
2456 };
2457
2458 enum {
2459         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2460         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2461         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2462         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2463 };
2464
2465 struct mlx5_ifc_scheduling_context_bits {
2466         u8         element_type[0x8];
2467         u8         reserved_at_8[0x18];
2468
2469         u8         element_attributes[0x20];
2470
2471         u8         parent_element_id[0x20];
2472
2473         u8         reserved_at_60[0x40];
2474
2475         u8         bw_share[0x20];
2476
2477         u8         max_average_bw[0x20];
2478
2479         u8         reserved_at_e0[0x120];
2480 };
2481
2482 struct mlx5_ifc_rqtc_bits {
2483         u8         reserved_at_0[0xa0];
2484
2485         u8         reserved_at_a0[0x10];
2486         u8         rqt_max_size[0x10];
2487
2488         u8         reserved_at_c0[0x10];
2489         u8         rqt_actual_size[0x10];
2490
2491         u8         reserved_at_e0[0x6a0];
2492
2493         struct mlx5_ifc_rq_num_bits rq_num[0];
2494 };
2495
2496 enum {
2497         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
2498         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
2499 };
2500
2501 enum {
2502         MLX5_RQC_STATE_RST  = 0x0,
2503         MLX5_RQC_STATE_RDY  = 0x1,
2504         MLX5_RQC_STATE_ERR  = 0x3,
2505 };
2506
2507 struct mlx5_ifc_rqc_bits {
2508         u8         rlky[0x1];
2509         u8         reserved_at_1[0x1];
2510         u8         scatter_fcs[0x1];
2511         u8         vsd[0x1];
2512         u8         mem_rq_type[0x4];
2513         u8         state[0x4];
2514         u8         reserved_at_c[0x1];
2515         u8         flush_in_error_en[0x1];
2516         u8         reserved_at_e[0x12];
2517
2518         u8         reserved_at_20[0x8];
2519         u8         user_index[0x18];
2520
2521         u8         reserved_at_40[0x8];
2522         u8         cqn[0x18];
2523
2524         u8         counter_set_id[0x8];
2525         u8         reserved_at_68[0x18];
2526
2527         u8         reserved_at_80[0x8];
2528         u8         rmpn[0x18];
2529
2530         u8         reserved_at_a0[0xe0];
2531
2532         struct mlx5_ifc_wq_bits wq;
2533 };
2534
2535 enum {
2536         MLX5_RMPC_STATE_RDY  = 0x1,
2537         MLX5_RMPC_STATE_ERR  = 0x3,
2538 };
2539
2540 struct mlx5_ifc_rmpc_bits {
2541         u8         reserved_at_0[0x8];
2542         u8         state[0x4];
2543         u8         reserved_at_c[0x14];
2544
2545         u8         basic_cyclic_rcv_wqe[0x1];
2546         u8         reserved_at_21[0x1f];
2547
2548         u8         reserved_at_40[0x140];
2549
2550         struct mlx5_ifc_wq_bits wq;
2551 };
2552
2553 struct mlx5_ifc_nic_vport_context_bits {
2554         u8         reserved_at_0[0x5];
2555         u8         min_wqe_inline_mode[0x3];
2556         u8         reserved_at_8[0x17];
2557         u8         roce_en[0x1];
2558
2559         u8         arm_change_event[0x1];
2560         u8         reserved_at_21[0x1a];
2561         u8         event_on_mtu[0x1];
2562         u8         event_on_promisc_change[0x1];
2563         u8         event_on_vlan_change[0x1];
2564         u8         event_on_mc_address_change[0x1];
2565         u8         event_on_uc_address_change[0x1];
2566
2567         u8         reserved_at_40[0xf0];
2568
2569         u8         mtu[0x10];
2570
2571         u8         system_image_guid[0x40];
2572         u8         port_guid[0x40];
2573         u8         node_guid[0x40];
2574
2575         u8         reserved_at_200[0x140];
2576         u8         qkey_violation_counter[0x10];
2577         u8         reserved_at_350[0x430];
2578
2579         u8         promisc_uc[0x1];
2580         u8         promisc_mc[0x1];
2581         u8         promisc_all[0x1];
2582         u8         reserved_at_783[0x2];
2583         u8         allowed_list_type[0x3];
2584         u8         reserved_at_788[0xc];
2585         u8         allowed_list_size[0xc];
2586
2587         struct mlx5_ifc_mac_address_layout_bits permanent_address;
2588
2589         u8         reserved_at_7e0[0x20];
2590
2591         u8         current_uc_mac_address[0][0x40];
2592 };
2593
2594 enum {
2595         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
2596         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
2597         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
2598         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
2599 };
2600
2601 struct mlx5_ifc_mkc_bits {
2602         u8         reserved_at_0[0x1];
2603         u8         free[0x1];
2604         u8         reserved_at_2[0xd];
2605         u8         small_fence_on_rdma_read_response[0x1];
2606         u8         umr_en[0x1];
2607         u8         a[0x1];
2608         u8         rw[0x1];
2609         u8         rr[0x1];
2610         u8         lw[0x1];
2611         u8         lr[0x1];
2612         u8         access_mode[0x2];
2613         u8         reserved_at_18[0x8];
2614
2615         u8         qpn[0x18];
2616         u8         mkey_7_0[0x8];
2617
2618         u8         reserved_at_40[0x20];
2619
2620         u8         length64[0x1];
2621         u8         bsf_en[0x1];
2622         u8         sync_umr[0x1];
2623         u8         reserved_at_63[0x2];
2624         u8         expected_sigerr_count[0x1];
2625         u8         reserved_at_66[0x1];
2626         u8         en_rinval[0x1];
2627         u8         pd[0x18];
2628
2629         u8         start_addr[0x40];
2630
2631         u8         len[0x40];
2632
2633         u8         bsf_octword_size[0x20];
2634
2635         u8         reserved_at_120[0x80];
2636
2637         u8         translations_octword_size[0x20];
2638
2639         u8         reserved_at_1c0[0x1b];
2640         u8         log_page_size[0x5];
2641
2642         u8         reserved_at_1e0[0x20];
2643 };
2644
2645 struct mlx5_ifc_pkey_bits {
2646         u8         reserved_at_0[0x10];
2647         u8         pkey[0x10];
2648 };
2649
2650 struct mlx5_ifc_array128_auto_bits {
2651         u8         array128_auto[16][0x8];
2652 };
2653
2654 struct mlx5_ifc_hca_vport_context_bits {
2655         u8         field_select[0x20];
2656
2657         u8         reserved_at_20[0xe0];
2658
2659         u8         sm_virt_aware[0x1];
2660         u8         has_smi[0x1];
2661         u8         has_raw[0x1];
2662         u8         grh_required[0x1];
2663         u8         reserved_at_104[0xc];
2664         u8         port_physical_state[0x4];
2665         u8         vport_state_policy[0x4];
2666         u8         port_state[0x4];
2667         u8         vport_state[0x4];
2668
2669         u8         reserved_at_120[0x20];
2670
2671         u8         system_image_guid[0x40];
2672
2673         u8         port_guid[0x40];
2674
2675         u8         node_guid[0x40];
2676
2677         u8         cap_mask1[0x20];
2678
2679         u8         cap_mask1_field_select[0x20];
2680
2681         u8         cap_mask2[0x20];
2682
2683         u8         cap_mask2_field_select[0x20];
2684
2685         u8         reserved_at_280[0x80];
2686
2687         u8         lid[0x10];
2688         u8         reserved_at_310[0x4];
2689         u8         init_type_reply[0x4];
2690         u8         lmc[0x3];
2691         u8         subnet_timeout[0x5];
2692
2693         u8         sm_lid[0x10];
2694         u8         sm_sl[0x4];
2695         u8         reserved_at_334[0xc];
2696
2697         u8         qkey_violation_counter[0x10];
2698         u8         pkey_violation_counter[0x10];
2699
2700         u8         reserved_at_360[0xca0];
2701 };
2702
2703 struct mlx5_ifc_esw_vport_context_bits {
2704         u8         reserved_at_0[0x3];
2705         u8         vport_svlan_strip[0x1];
2706         u8         vport_cvlan_strip[0x1];
2707         u8         vport_svlan_insert[0x1];
2708         u8         vport_cvlan_insert[0x2];
2709         u8         reserved_at_8[0x18];
2710
2711         u8         reserved_at_20[0x20];
2712
2713         u8         svlan_cfi[0x1];
2714         u8         svlan_pcp[0x3];
2715         u8         svlan_id[0xc];
2716         u8         cvlan_cfi[0x1];
2717         u8         cvlan_pcp[0x3];
2718         u8         cvlan_id[0xc];
2719
2720         u8         reserved_at_60[0x7a0];
2721 };
2722
2723 enum {
2724         MLX5_EQC_STATUS_OK                = 0x0,
2725         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
2726 };
2727
2728 enum {
2729         MLX5_EQC_ST_ARMED  = 0x9,
2730         MLX5_EQC_ST_FIRED  = 0xa,
2731 };
2732
2733 struct mlx5_ifc_eqc_bits {
2734         u8         status[0x4];
2735         u8         reserved_at_4[0x9];
2736         u8         ec[0x1];
2737         u8         oi[0x1];
2738         u8         reserved_at_f[0x5];
2739         u8         st[0x4];
2740         u8         reserved_at_18[0x8];
2741
2742         u8         reserved_at_20[0x20];
2743
2744         u8         reserved_at_40[0x14];
2745         u8         page_offset[0x6];
2746         u8         reserved_at_5a[0x6];
2747
2748         u8         reserved_at_60[0x3];
2749         u8         log_eq_size[0x5];
2750         u8         uar_page[0x18];
2751
2752         u8         reserved_at_80[0x20];
2753
2754         u8         reserved_at_a0[0x18];
2755         u8         intr[0x8];
2756
2757         u8         reserved_at_c0[0x3];
2758         u8         log_page_size[0x5];
2759         u8         reserved_at_c8[0x18];
2760
2761         u8         reserved_at_e0[0x60];
2762
2763         u8         reserved_at_140[0x8];
2764         u8         consumer_counter[0x18];
2765
2766         u8         reserved_at_160[0x8];
2767         u8         producer_counter[0x18];
2768
2769         u8         reserved_at_180[0x80];
2770 };
2771
2772 enum {
2773         MLX5_DCTC_STATE_ACTIVE    = 0x0,
2774         MLX5_DCTC_STATE_DRAINING  = 0x1,
2775         MLX5_DCTC_STATE_DRAINED   = 0x2,
2776 };
2777
2778 enum {
2779         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
2780         MLX5_DCTC_CS_RES_NA         = 0x1,
2781         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
2782 };
2783
2784 enum {
2785         MLX5_DCTC_MTU_256_BYTES  = 0x1,
2786         MLX5_DCTC_MTU_512_BYTES  = 0x2,
2787         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
2788         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
2789         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
2790 };
2791
2792 struct mlx5_ifc_dctc_bits {
2793         u8         reserved_at_0[0x4];
2794         u8         state[0x4];
2795         u8         reserved_at_8[0x18];
2796
2797         u8         reserved_at_20[0x8];
2798         u8         user_index[0x18];
2799
2800         u8         reserved_at_40[0x8];
2801         u8         cqn[0x18];
2802
2803         u8         counter_set_id[0x8];
2804         u8         atomic_mode[0x4];
2805         u8         rre[0x1];
2806         u8         rwe[0x1];
2807         u8         rae[0x1];
2808         u8         atomic_like_write_en[0x1];
2809         u8         latency_sensitive[0x1];
2810         u8         rlky[0x1];
2811         u8         free_ar[0x1];
2812         u8         reserved_at_73[0xd];
2813
2814         u8         reserved_at_80[0x8];
2815         u8         cs_res[0x8];
2816         u8         reserved_at_90[0x3];
2817         u8         min_rnr_nak[0x5];
2818         u8         reserved_at_98[0x8];
2819
2820         u8         reserved_at_a0[0x8];
2821         u8         srqn_xrqn[0x18];
2822
2823         u8         reserved_at_c0[0x8];
2824         u8         pd[0x18];
2825
2826         u8         tclass[0x8];
2827         u8         reserved_at_e8[0x4];
2828         u8         flow_label[0x14];
2829
2830         u8         dc_access_key[0x40];
2831
2832         u8         reserved_at_140[0x5];
2833         u8         mtu[0x3];
2834         u8         port[0x8];
2835         u8         pkey_index[0x10];
2836
2837         u8         reserved_at_160[0x8];
2838         u8         my_addr_index[0x8];
2839         u8         reserved_at_170[0x8];
2840         u8         hop_limit[0x8];
2841
2842         u8         dc_access_key_violation_count[0x20];
2843
2844         u8         reserved_at_1a0[0x14];
2845         u8         dei_cfi[0x1];
2846         u8         eth_prio[0x3];
2847         u8         ecn[0x2];
2848         u8         dscp[0x6];
2849
2850         u8         reserved_at_1c0[0x40];
2851 };
2852
2853 enum {
2854         MLX5_CQC_STATUS_OK             = 0x0,
2855         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
2856         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
2857 };
2858
2859 enum {
2860         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
2861         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
2862 };
2863
2864 enum {
2865         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
2866         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
2867         MLX5_CQC_ST_FIRED                                 = 0xa,
2868 };
2869
2870 enum {
2871         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2872         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2873         MLX5_CQ_PERIOD_NUM_MODES
2874 };
2875
2876 struct mlx5_ifc_cqc_bits {
2877         u8         status[0x4];
2878         u8         reserved_at_4[0x4];
2879         u8         cqe_sz[0x3];
2880         u8         cc[0x1];
2881         u8         reserved_at_c[0x1];
2882         u8         scqe_break_moderation_en[0x1];
2883         u8         oi[0x1];
2884         u8         cq_period_mode[0x2];
2885         u8         cqe_comp_en[0x1];
2886         u8         mini_cqe_res_format[0x2];
2887         u8         st[0x4];
2888         u8         reserved_at_18[0x8];
2889
2890         u8         reserved_at_20[0x20];
2891
2892         u8         reserved_at_40[0x14];
2893         u8         page_offset[0x6];
2894         u8         reserved_at_5a[0x6];
2895
2896         u8         reserved_at_60[0x3];
2897         u8         log_cq_size[0x5];
2898         u8         uar_page[0x18];
2899
2900         u8         reserved_at_80[0x4];
2901         u8         cq_period[0xc];
2902         u8         cq_max_count[0x10];
2903
2904         u8         reserved_at_a0[0x18];
2905         u8         c_eqn[0x8];
2906
2907         u8         reserved_at_c0[0x3];
2908         u8         log_page_size[0x5];
2909         u8         reserved_at_c8[0x18];
2910
2911         u8         reserved_at_e0[0x20];
2912
2913         u8         reserved_at_100[0x8];
2914         u8         last_notified_index[0x18];
2915
2916         u8         reserved_at_120[0x8];
2917         u8         last_solicit_index[0x18];
2918
2919         u8         reserved_at_140[0x8];
2920         u8         consumer_counter[0x18];
2921
2922         u8         reserved_at_160[0x8];
2923         u8         producer_counter[0x18];
2924
2925         u8         reserved_at_180[0x40];
2926
2927         u8         dbr_addr[0x40];
2928 };
2929
2930 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2931         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2932         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2933         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2934         u8         reserved_at_0[0x800];
2935 };
2936
2937 struct mlx5_ifc_query_adapter_param_block_bits {
2938         u8         reserved_at_0[0xc0];
2939
2940         u8         reserved_at_c0[0x8];
2941         u8         ieee_vendor_id[0x18];
2942
2943         u8         reserved_at_e0[0x10];
2944         u8         vsd_vendor_id[0x10];
2945
2946         u8         vsd[208][0x8];
2947
2948         u8         vsd_contd_psid[16][0x8];
2949 };
2950
2951 enum {
2952         MLX5_XRQC_STATE_GOOD   = 0x0,
2953         MLX5_XRQC_STATE_ERROR  = 0x1,
2954 };
2955
2956 enum {
2957         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2958         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
2959 };
2960
2961 enum {
2962         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2963 };
2964
2965 struct mlx5_ifc_tag_matching_topology_context_bits {
2966         u8         log_matching_list_sz[0x4];
2967         u8         reserved_at_4[0xc];
2968         u8         append_next_index[0x10];
2969
2970         u8         sw_phase_cnt[0x10];
2971         u8         hw_phase_cnt[0x10];
2972
2973         u8         reserved_at_40[0x40];
2974 };
2975
2976 struct mlx5_ifc_xrqc_bits {
2977         u8         state[0x4];
2978         u8         rlkey[0x1];
2979         u8         reserved_at_5[0xf];
2980         u8         topology[0x4];
2981         u8         reserved_at_18[0x4];
2982         u8         offload[0x4];
2983
2984         u8         reserved_at_20[0x8];
2985         u8         user_index[0x18];
2986
2987         u8         reserved_at_40[0x8];
2988         u8         cqn[0x18];
2989
2990         u8         reserved_at_60[0xa0];
2991
2992         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2993
2994         u8         reserved_at_180[0x880];
2995
2996         struct mlx5_ifc_wq_bits wq;
2997 };
2998
2999 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3000         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3001         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3002         u8         reserved_at_0[0x20];
3003 };
3004
3005 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3006         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3007         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3008         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3009         u8         reserved_at_0[0x20];
3010 };
3011
3012 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3013         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3014         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3015         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3016         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3017         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3018         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3019         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3020         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3021         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3022         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3023         u8         reserved_at_0[0x7c0];
3024 };
3025
3026 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3027         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3028         u8         reserved_at_0[0x7c0];
3029 };
3030
3031 union mlx5_ifc_event_auto_bits {
3032         struct mlx5_ifc_comp_event_bits comp_event;
3033         struct mlx5_ifc_dct_events_bits dct_events;
3034         struct mlx5_ifc_qp_events_bits qp_events;
3035         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3036         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3037         struct mlx5_ifc_cq_error_bits cq_error;
3038         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3039         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3040         struct mlx5_ifc_gpio_event_bits gpio_event;
3041         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3042         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3043         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3044         u8         reserved_at_0[0xe0];
3045 };
3046
3047 struct mlx5_ifc_health_buffer_bits {
3048         u8         reserved_at_0[0x100];
3049
3050         u8         assert_existptr[0x20];
3051
3052         u8         assert_callra[0x20];
3053
3054         u8         reserved_at_140[0x40];
3055
3056         u8         fw_version[0x20];
3057
3058         u8         hw_id[0x20];
3059
3060         u8         reserved_at_1c0[0x20];
3061
3062         u8         irisc_index[0x8];
3063         u8         synd[0x8];
3064         u8         ext_synd[0x10];
3065 };
3066
3067 struct mlx5_ifc_register_loopback_control_bits {
3068         u8         no_lb[0x1];
3069         u8         reserved_at_1[0x7];
3070         u8         port[0x8];
3071         u8         reserved_at_10[0x10];
3072
3073         u8         reserved_at_20[0x60];
3074 };
3075
3076 struct mlx5_ifc_vport_tc_element_bits {
3077         u8         traffic_class[0x4];
3078         u8         reserved_at_4[0xc];
3079         u8         vport_number[0x10];
3080 };
3081
3082 struct mlx5_ifc_vport_element_bits {
3083         u8         reserved_at_0[0x10];
3084         u8         vport_number[0x10];
3085 };
3086
3087 enum {
3088         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3089         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3090         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3091 };
3092
3093 struct mlx5_ifc_tsar_element_bits {
3094         u8         reserved_at_0[0x8];
3095         u8         tsar_type[0x8];
3096         u8         reserved_at_10[0x10];
3097 };
3098
3099 enum {
3100         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3101         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3102 };
3103
3104 struct mlx5_ifc_teardown_hca_out_bits {
3105         u8         status[0x8];
3106         u8         reserved_at_8[0x18];
3107
3108         u8         syndrome[0x20];
3109
3110         u8         reserved_at_40[0x3f];
3111
3112         u8         force_state[0x1];
3113 };
3114
3115 enum {
3116         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3117         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3118 };
3119
3120 struct mlx5_ifc_teardown_hca_in_bits {
3121         u8         opcode[0x10];
3122         u8         reserved_at_10[0x10];
3123
3124         u8         reserved_at_20[0x10];
3125         u8         op_mod[0x10];
3126
3127         u8         reserved_at_40[0x10];
3128         u8         profile[0x10];
3129
3130         u8         reserved_at_60[0x20];
3131 };
3132
3133 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3134         u8         status[0x8];
3135         u8         reserved_at_8[0x18];
3136
3137         u8         syndrome[0x20];
3138
3139         u8         reserved_at_40[0x40];
3140 };
3141
3142 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3143         u8         opcode[0x10];
3144         u8         reserved_at_10[0x10];
3145
3146         u8         reserved_at_20[0x10];
3147         u8         op_mod[0x10];
3148
3149         u8         reserved_at_40[0x8];
3150         u8         qpn[0x18];
3151
3152         u8         reserved_at_60[0x20];
3153
3154         u8         opt_param_mask[0x20];
3155
3156         u8         reserved_at_a0[0x20];
3157
3158         struct mlx5_ifc_qpc_bits qpc;
3159
3160         u8         reserved_at_800[0x80];
3161 };
3162
3163 struct mlx5_ifc_sqd2rts_qp_out_bits {
3164         u8         status[0x8];
3165         u8         reserved_at_8[0x18];
3166
3167         u8         syndrome[0x20];
3168
3169         u8         reserved_at_40[0x40];
3170 };
3171
3172 struct mlx5_ifc_sqd2rts_qp_in_bits {
3173         u8         opcode[0x10];
3174         u8         reserved_at_10[0x10];
3175
3176         u8         reserved_at_20[0x10];
3177         u8         op_mod[0x10];
3178
3179         u8         reserved_at_40[0x8];
3180         u8         qpn[0x18];
3181
3182         u8         reserved_at_60[0x20];
3183
3184         u8         opt_param_mask[0x20];
3185
3186         u8         reserved_at_a0[0x20];
3187
3188         struct mlx5_ifc_qpc_bits qpc;
3189
3190         u8         reserved_at_800[0x80];
3191 };
3192
3193 struct mlx5_ifc_set_roce_address_out_bits {
3194         u8         status[0x8];
3195         u8         reserved_at_8[0x18];
3196
3197         u8         syndrome[0x20];
3198
3199         u8         reserved_at_40[0x40];
3200 };
3201
3202 struct mlx5_ifc_set_roce_address_in_bits {
3203         u8         opcode[0x10];
3204         u8         reserved_at_10[0x10];
3205
3206         u8         reserved_at_20[0x10];
3207         u8         op_mod[0x10];
3208
3209         u8         roce_address_index[0x10];
3210         u8         reserved_at_50[0x10];
3211
3212         u8         reserved_at_60[0x20];
3213
3214         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3215 };
3216
3217 struct mlx5_ifc_set_mad_demux_out_bits {
3218         u8         status[0x8];
3219         u8         reserved_at_8[0x18];
3220
3221         u8         syndrome[0x20];
3222
3223         u8         reserved_at_40[0x40];
3224 };
3225
3226 enum {
3227         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3228         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3229 };
3230
3231 struct mlx5_ifc_set_mad_demux_in_bits {
3232         u8         opcode[0x10];
3233         u8         reserved_at_10[0x10];
3234
3235         u8         reserved_at_20[0x10];
3236         u8         op_mod[0x10];
3237
3238         u8         reserved_at_40[0x20];
3239
3240         u8         reserved_at_60[0x6];
3241         u8         demux_mode[0x2];
3242         u8         reserved_at_68[0x18];
3243 };
3244
3245 struct mlx5_ifc_set_l2_table_entry_out_bits {
3246         u8         status[0x8];
3247         u8         reserved_at_8[0x18];
3248
3249         u8         syndrome[0x20];
3250
3251         u8         reserved_at_40[0x40];
3252 };
3253
3254 struct mlx5_ifc_set_l2_table_entry_in_bits {
3255         u8         opcode[0x10];
3256         u8         reserved_at_10[0x10];
3257
3258         u8         reserved_at_20[0x10];
3259         u8         op_mod[0x10];
3260
3261         u8         reserved_at_40[0x60];
3262
3263         u8         reserved_at_a0[0x8];
3264         u8         table_index[0x18];
3265
3266         u8         reserved_at_c0[0x20];
3267
3268         u8         reserved_at_e0[0x13];
3269         u8         vlan_valid[0x1];
3270         u8         vlan[0xc];
3271
3272         struct mlx5_ifc_mac_address_layout_bits mac_address;
3273
3274         u8         reserved_at_140[0xc0];
3275 };
3276
3277 struct mlx5_ifc_set_issi_out_bits {
3278         u8         status[0x8];
3279         u8         reserved_at_8[0x18];
3280
3281         u8         syndrome[0x20];
3282
3283         u8         reserved_at_40[0x40];
3284 };
3285
3286 struct mlx5_ifc_set_issi_in_bits {
3287         u8         opcode[0x10];
3288         u8         reserved_at_10[0x10];
3289
3290         u8         reserved_at_20[0x10];
3291         u8         op_mod[0x10];
3292
3293         u8         reserved_at_40[0x10];
3294         u8         current_issi[0x10];
3295
3296         u8         reserved_at_60[0x20];
3297 };
3298
3299 struct mlx5_ifc_set_hca_cap_out_bits {
3300         u8         status[0x8];
3301         u8         reserved_at_8[0x18];
3302
3303         u8         syndrome[0x20];
3304
3305         u8         reserved_at_40[0x40];
3306 };
3307
3308 struct mlx5_ifc_set_hca_cap_in_bits {
3309         u8         opcode[0x10];
3310         u8         reserved_at_10[0x10];
3311
3312         u8         reserved_at_20[0x10];
3313         u8         op_mod[0x10];
3314
3315         u8         reserved_at_40[0x40];
3316
3317         union mlx5_ifc_hca_cap_union_bits capability;
3318 };
3319
3320 enum {
3321         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3322         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3323         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3324         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3325 };
3326
3327 struct mlx5_ifc_set_fte_out_bits {
3328         u8         status[0x8];
3329         u8         reserved_at_8[0x18];
3330
3331         u8         syndrome[0x20];
3332
3333         u8         reserved_at_40[0x40];
3334 };
3335
3336 struct mlx5_ifc_set_fte_in_bits {
3337         u8         opcode[0x10];
3338         u8         reserved_at_10[0x10];
3339
3340         u8         reserved_at_20[0x10];
3341         u8         op_mod[0x10];
3342
3343         u8         other_vport[0x1];
3344         u8         reserved_at_41[0xf];
3345         u8         vport_number[0x10];
3346
3347         u8         reserved_at_60[0x20];
3348
3349         u8         table_type[0x8];
3350         u8         reserved_at_88[0x18];
3351
3352         u8         reserved_at_a0[0x8];
3353         u8         table_id[0x18];
3354
3355         u8         reserved_at_c0[0x18];
3356         u8         modify_enable_mask[0x8];
3357
3358         u8         reserved_at_e0[0x20];
3359
3360         u8         flow_index[0x20];
3361
3362         u8         reserved_at_120[0xe0];
3363
3364         struct mlx5_ifc_flow_context_bits flow_context;
3365 };
3366
3367 struct mlx5_ifc_rts2rts_qp_out_bits {
3368         u8         status[0x8];
3369         u8         reserved_at_8[0x18];
3370
3371         u8         syndrome[0x20];
3372
3373         u8         reserved_at_40[0x40];
3374 };
3375
3376 struct mlx5_ifc_rts2rts_qp_in_bits {
3377         u8         opcode[0x10];
3378         u8         reserved_at_10[0x10];
3379
3380         u8         reserved_at_20[0x10];
3381         u8         op_mod[0x10];
3382
3383         u8         reserved_at_40[0x8];
3384         u8         qpn[0x18];
3385
3386         u8         reserved_at_60[0x20];
3387
3388         u8         opt_param_mask[0x20];
3389
3390         u8         reserved_at_a0[0x20];
3391
3392         struct mlx5_ifc_qpc_bits qpc;
3393
3394         u8         reserved_at_800[0x80];
3395 };
3396
3397 struct mlx5_ifc_rtr2rts_qp_out_bits {
3398         u8         status[0x8];
3399         u8         reserved_at_8[0x18];
3400
3401         u8         syndrome[0x20];
3402
3403         u8         reserved_at_40[0x40];
3404 };
3405
3406 struct mlx5_ifc_rtr2rts_qp_in_bits {
3407         u8         opcode[0x10];
3408         u8         reserved_at_10[0x10];
3409
3410         u8         reserved_at_20[0x10];
3411         u8         op_mod[0x10];
3412
3413         u8         reserved_at_40[0x8];
3414         u8         qpn[0x18];
3415
3416         u8         reserved_at_60[0x20];
3417
3418         u8         opt_param_mask[0x20];
3419
3420         u8         reserved_at_a0[0x20];
3421
3422         struct mlx5_ifc_qpc_bits qpc;
3423
3424         u8         reserved_at_800[0x80];
3425 };
3426
3427 struct mlx5_ifc_rst2init_qp_out_bits {
3428         u8         status[0x8];
3429         u8         reserved_at_8[0x18];
3430
3431         u8         syndrome[0x20];
3432
3433         u8         reserved_at_40[0x40];
3434 };
3435
3436 struct mlx5_ifc_rst2init_qp_in_bits {
3437         u8         opcode[0x10];
3438         u8         reserved_at_10[0x10];
3439
3440         u8         reserved_at_20[0x10];
3441         u8         op_mod[0x10];
3442
3443         u8         reserved_at_40[0x8];
3444         u8         qpn[0x18];
3445
3446         u8         reserved_at_60[0x20];
3447
3448         u8         opt_param_mask[0x20];
3449
3450         u8         reserved_at_a0[0x20];
3451
3452         struct mlx5_ifc_qpc_bits qpc;
3453
3454         u8         reserved_at_800[0x80];
3455 };
3456
3457 struct mlx5_ifc_query_xrq_out_bits {
3458         u8         status[0x8];
3459         u8         reserved_at_8[0x18];
3460
3461         u8         syndrome[0x20];
3462
3463         u8         reserved_at_40[0x40];
3464
3465         struct mlx5_ifc_xrqc_bits xrq_context;
3466 };
3467
3468 struct mlx5_ifc_query_xrq_in_bits {
3469         u8         opcode[0x10];
3470         u8         reserved_at_10[0x10];
3471
3472         u8         reserved_at_20[0x10];
3473         u8         op_mod[0x10];
3474
3475         u8         reserved_at_40[0x8];
3476         u8         xrqn[0x18];
3477
3478         u8         reserved_at_60[0x20];
3479 };
3480
3481 struct mlx5_ifc_query_xrc_srq_out_bits {
3482         u8         status[0x8];
3483         u8         reserved_at_8[0x18];
3484
3485         u8         syndrome[0x20];
3486
3487         u8         reserved_at_40[0x40];
3488
3489         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3490
3491         u8         reserved_at_280[0x600];
3492
3493         u8         pas[0][0x40];
3494 };
3495
3496 struct mlx5_ifc_query_xrc_srq_in_bits {
3497         u8         opcode[0x10];
3498         u8         reserved_at_10[0x10];
3499
3500         u8         reserved_at_20[0x10];
3501         u8         op_mod[0x10];
3502
3503         u8         reserved_at_40[0x8];
3504         u8         xrc_srqn[0x18];
3505
3506         u8         reserved_at_60[0x20];
3507 };
3508
3509 enum {
3510         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
3511         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
3512 };
3513
3514 struct mlx5_ifc_query_vport_state_out_bits {
3515         u8         status[0x8];
3516         u8         reserved_at_8[0x18];
3517
3518         u8         syndrome[0x20];
3519
3520         u8         reserved_at_40[0x20];
3521
3522         u8         reserved_at_60[0x18];
3523         u8         admin_state[0x4];
3524         u8         state[0x4];
3525 };
3526
3527 enum {
3528         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT  = 0x0,
3529         MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT   = 0x1,
3530 };
3531
3532 struct mlx5_ifc_query_vport_state_in_bits {
3533         u8         opcode[0x10];
3534         u8         reserved_at_10[0x10];
3535
3536         u8         reserved_at_20[0x10];
3537         u8         op_mod[0x10];
3538
3539         u8         other_vport[0x1];
3540         u8         reserved_at_41[0xf];
3541         u8         vport_number[0x10];
3542
3543         u8         reserved_at_60[0x20];
3544 };
3545
3546 struct mlx5_ifc_query_vport_counter_out_bits {
3547         u8         status[0x8];
3548         u8         reserved_at_8[0x18];
3549
3550         u8         syndrome[0x20];
3551
3552         u8         reserved_at_40[0x40];
3553
3554         struct mlx5_ifc_traffic_counter_bits received_errors;
3555
3556         struct mlx5_ifc_traffic_counter_bits transmit_errors;
3557
3558         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3559
3560         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3561
3562         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3563
3564         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3565
3566         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3567
3568         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3569
3570         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3571
3572         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3573
3574         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3575
3576         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3577
3578         u8         reserved_at_680[0xa00];
3579 };
3580
3581 enum {
3582         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
3583 };
3584
3585 struct mlx5_ifc_query_vport_counter_in_bits {
3586         u8         opcode[0x10];
3587         u8         reserved_at_10[0x10];
3588
3589         u8         reserved_at_20[0x10];
3590         u8         op_mod[0x10];
3591
3592         u8         other_vport[0x1];
3593         u8         reserved_at_41[0xb];
3594         u8         port_num[0x4];
3595         u8         vport_number[0x10];
3596
3597         u8         reserved_at_60[0x60];
3598
3599         u8         clear[0x1];
3600         u8         reserved_at_c1[0x1f];
3601
3602         u8         reserved_at_e0[0x20];
3603 };
3604
3605 struct mlx5_ifc_query_tis_out_bits {
3606         u8         status[0x8];
3607         u8         reserved_at_8[0x18];
3608
3609         u8         syndrome[0x20];
3610
3611         u8         reserved_at_40[0x40];
3612
3613         struct mlx5_ifc_tisc_bits tis_context;
3614 };
3615
3616 struct mlx5_ifc_query_tis_in_bits {
3617         u8         opcode[0x10];
3618         u8         reserved_at_10[0x10];
3619
3620         u8         reserved_at_20[0x10];
3621         u8         op_mod[0x10];
3622
3623         u8         reserved_at_40[0x8];
3624         u8         tisn[0x18];
3625
3626         u8         reserved_at_60[0x20];
3627 };
3628
3629 struct mlx5_ifc_query_tir_out_bits {
3630         u8         status[0x8];
3631         u8         reserved_at_8[0x18];
3632
3633         u8         syndrome[0x20];
3634
3635         u8         reserved_at_40[0xc0];
3636
3637         struct mlx5_ifc_tirc_bits tir_context;
3638 };
3639
3640 struct mlx5_ifc_query_tir_in_bits {
3641         u8         opcode[0x10];
3642         u8         reserved_at_10[0x10];
3643
3644         u8         reserved_at_20[0x10];
3645         u8         op_mod[0x10];
3646
3647         u8         reserved_at_40[0x8];
3648         u8         tirn[0x18];
3649
3650         u8         reserved_at_60[0x20];
3651 };
3652
3653 struct mlx5_ifc_query_srq_out_bits {
3654         u8         status[0x8];
3655         u8         reserved_at_8[0x18];
3656
3657         u8         syndrome[0x20];
3658
3659         u8         reserved_at_40[0x40];
3660
3661         struct mlx5_ifc_srqc_bits srq_context_entry;
3662
3663         u8         reserved_at_280[0x600];
3664
3665         u8         pas[0][0x40];
3666 };
3667
3668 struct mlx5_ifc_query_srq_in_bits {
3669         u8         opcode[0x10];
3670         u8         reserved_at_10[0x10];
3671
3672         u8         reserved_at_20[0x10];
3673         u8         op_mod[0x10];
3674
3675         u8         reserved_at_40[0x8];
3676         u8         srqn[0x18];
3677
3678         u8         reserved_at_60[0x20];
3679 };
3680
3681 struct mlx5_ifc_query_sq_out_bits {
3682         u8         status[0x8];
3683         u8         reserved_at_8[0x18];
3684
3685         u8         syndrome[0x20];
3686
3687         u8         reserved_at_40[0xc0];
3688
3689         struct mlx5_ifc_sqc_bits sq_context;
3690 };
3691
3692 struct mlx5_ifc_query_sq_in_bits {
3693         u8         opcode[0x10];
3694         u8         reserved_at_10[0x10];
3695
3696         u8         reserved_at_20[0x10];
3697         u8         op_mod[0x10];
3698
3699         u8         reserved_at_40[0x8];
3700         u8         sqn[0x18];
3701
3702         u8         reserved_at_60[0x20];
3703 };
3704
3705 struct mlx5_ifc_query_special_contexts_out_bits {
3706         u8         status[0x8];
3707         u8         reserved_at_8[0x18];
3708
3709         u8         syndrome[0x20];
3710
3711         u8         dump_fill_mkey[0x20];
3712
3713         u8         resd_lkey[0x20];
3714
3715         u8         null_mkey[0x20];
3716
3717         u8         reserved_at_a0[0x60];
3718 };
3719
3720 struct mlx5_ifc_query_special_contexts_in_bits {
3721         u8         opcode[0x10];
3722         u8         reserved_at_10[0x10];
3723
3724         u8         reserved_at_20[0x10];
3725         u8         op_mod[0x10];
3726
3727         u8         reserved_at_40[0x40];
3728 };
3729
3730 struct mlx5_ifc_query_scheduling_element_out_bits {
3731         u8         opcode[0x10];
3732         u8         reserved_at_10[0x10];
3733
3734         u8         reserved_at_20[0x10];
3735         u8         op_mod[0x10];
3736
3737         u8         reserved_at_40[0xc0];
3738
3739         struct mlx5_ifc_scheduling_context_bits scheduling_context;
3740
3741         u8         reserved_at_300[0x100];
3742 };
3743
3744 enum {
3745         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3746 };
3747
3748 struct mlx5_ifc_query_scheduling_element_in_bits {
3749         u8         opcode[0x10];
3750         u8         reserved_at_10[0x10];
3751
3752         u8         reserved_at_20[0x10];
3753         u8         op_mod[0x10];
3754
3755         u8         scheduling_hierarchy[0x8];
3756         u8         reserved_at_48[0x18];
3757
3758         u8         scheduling_element_id[0x20];
3759
3760         u8         reserved_at_80[0x180];
3761 };
3762
3763 struct mlx5_ifc_query_rqt_out_bits {
3764         u8         status[0x8];
3765         u8         reserved_at_8[0x18];
3766
3767         u8         syndrome[0x20];
3768
3769         u8         reserved_at_40[0xc0];
3770
3771         struct mlx5_ifc_rqtc_bits rqt_context;
3772 };
3773
3774 struct mlx5_ifc_query_rqt_in_bits {
3775         u8         opcode[0x10];
3776         u8         reserved_at_10[0x10];
3777
3778         u8         reserved_at_20[0x10];
3779         u8         op_mod[0x10];
3780
3781         u8         reserved_at_40[0x8];
3782         u8         rqtn[0x18];
3783
3784         u8         reserved_at_60[0x20];
3785 };
3786
3787 struct mlx5_ifc_query_rq_out_bits {
3788         u8         status[0x8];
3789         u8         reserved_at_8[0x18];
3790
3791         u8         syndrome[0x20];
3792
3793         u8         reserved_at_40[0xc0];
3794
3795         struct mlx5_ifc_rqc_bits rq_context;
3796 };
3797
3798 struct mlx5_ifc_query_rq_in_bits {
3799         u8         opcode[0x10];
3800         u8         reserved_at_10[0x10];
3801
3802         u8         reserved_at_20[0x10];
3803         u8         op_mod[0x10];
3804
3805         u8         reserved_at_40[0x8];
3806         u8         rqn[0x18];
3807
3808         u8         reserved_at_60[0x20];
3809 };
3810
3811 struct mlx5_ifc_query_roce_address_out_bits {
3812         u8         status[0x8];
3813         u8         reserved_at_8[0x18];
3814
3815         u8         syndrome[0x20];
3816
3817         u8         reserved_at_40[0x40];
3818
3819         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3820 };
3821
3822 struct mlx5_ifc_query_roce_address_in_bits {
3823         u8         opcode[0x10];
3824         u8         reserved_at_10[0x10];
3825
3826         u8         reserved_at_20[0x10];
3827         u8         op_mod[0x10];
3828
3829         u8         roce_address_index[0x10];
3830         u8         reserved_at_50[0x10];
3831
3832         u8         reserved_at_60[0x20];
3833 };
3834
3835 struct mlx5_ifc_query_rmp_out_bits {
3836         u8         status[0x8];
3837         u8         reserved_at_8[0x18];
3838
3839         u8         syndrome[0x20];
3840
3841         u8         reserved_at_40[0xc0];
3842
3843         struct mlx5_ifc_rmpc_bits rmp_context;
3844 };
3845
3846 struct mlx5_ifc_query_rmp_in_bits {
3847         u8         opcode[0x10];
3848         u8         reserved_at_10[0x10];
3849
3850         u8         reserved_at_20[0x10];
3851         u8         op_mod[0x10];
3852
3853         u8         reserved_at_40[0x8];
3854         u8         rmpn[0x18];
3855
3856         u8         reserved_at_60[0x20];
3857 };
3858
3859 struct mlx5_ifc_query_qp_out_bits {
3860         u8         status[0x8];
3861         u8         reserved_at_8[0x18];
3862
3863         u8         syndrome[0x20];
3864
3865         u8         reserved_at_40[0x40];
3866
3867         u8         opt_param_mask[0x20];
3868
3869         u8         reserved_at_a0[0x20];
3870
3871         struct mlx5_ifc_qpc_bits qpc;
3872
3873         u8         reserved_at_800[0x80];
3874
3875         u8         pas[0][0x40];
3876 };
3877
3878 struct mlx5_ifc_query_qp_in_bits {
3879         u8         opcode[0x10];
3880         u8         reserved_at_10[0x10];
3881
3882         u8         reserved_at_20[0x10];
3883         u8         op_mod[0x10];
3884
3885         u8         reserved_at_40[0x8];
3886         u8         qpn[0x18];
3887
3888         u8         reserved_at_60[0x20];
3889 };
3890
3891 struct mlx5_ifc_query_q_counter_out_bits {
3892         u8         status[0x8];
3893         u8         reserved_at_8[0x18];
3894
3895         u8         syndrome[0x20];
3896
3897         u8         reserved_at_40[0x40];
3898
3899         u8         rx_write_requests[0x20];
3900
3901         u8         reserved_at_a0[0x20];
3902
3903         u8         rx_read_requests[0x20];
3904
3905         u8         reserved_at_e0[0x20];
3906
3907         u8         rx_atomic_requests[0x20];
3908
3909         u8         reserved_at_120[0x20];
3910
3911         u8         rx_dct_connect[0x20];
3912
3913         u8         reserved_at_160[0x20];
3914
3915         u8         out_of_buffer[0x20];
3916
3917         u8         reserved_at_1a0[0x20];
3918
3919         u8         out_of_sequence[0x20];
3920
3921         u8         reserved_at_1e0[0x20];
3922
3923         u8         duplicate_request[0x20];
3924
3925         u8         reserved_at_220[0x20];
3926
3927         u8         rnr_nak_retry_err[0x20];
3928
3929         u8         reserved_at_260[0x20];
3930
3931         u8         packet_seq_err[0x20];
3932
3933         u8         reserved_at_2a0[0x20];
3934
3935         u8         implied_nak_seq_err[0x20];
3936
3937         u8         reserved_at_2e0[0x20];
3938
3939         u8         local_ack_timeout_err[0x20];
3940
3941         u8         reserved_at_320[0x4e0];
3942 };
3943
3944 struct mlx5_ifc_query_q_counter_in_bits {
3945         u8         opcode[0x10];
3946         u8         reserved_at_10[0x10];
3947
3948         u8         reserved_at_20[0x10];
3949         u8         op_mod[0x10];
3950
3951         u8         reserved_at_40[0x80];
3952
3953         u8         clear[0x1];
3954         u8         reserved_at_c1[0x1f];
3955
3956         u8         reserved_at_e0[0x18];
3957         u8         counter_set_id[0x8];
3958 };
3959
3960 struct mlx5_ifc_query_pages_out_bits {
3961         u8         status[0x8];
3962         u8         reserved_at_8[0x18];
3963
3964         u8         syndrome[0x20];
3965
3966         u8         reserved_at_40[0x10];
3967         u8         function_id[0x10];
3968
3969         u8         num_pages[0x20];
3970 };
3971
3972 enum {
3973         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
3974         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
3975         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
3976 };
3977
3978 struct mlx5_ifc_query_pages_in_bits {
3979         u8         opcode[0x10];
3980         u8         reserved_at_10[0x10];
3981
3982         u8         reserved_at_20[0x10];
3983         u8         op_mod[0x10];
3984
3985         u8         reserved_at_40[0x10];
3986         u8         function_id[0x10];
3987
3988         u8         reserved_at_60[0x20];
3989 };
3990
3991 struct mlx5_ifc_query_nic_vport_context_out_bits {
3992         u8         status[0x8];
3993         u8         reserved_at_8[0x18];
3994
3995         u8         syndrome[0x20];
3996
3997         u8         reserved_at_40[0x40];
3998
3999         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4000 };
4001
4002 struct mlx5_ifc_query_nic_vport_context_in_bits {
4003         u8         opcode[0x10];
4004         u8         reserved_at_10[0x10];
4005
4006         u8         reserved_at_20[0x10];
4007         u8         op_mod[0x10];
4008
4009         u8         other_vport[0x1];
4010         u8         reserved_at_41[0xf];
4011         u8         vport_number[0x10];
4012
4013         u8         reserved_at_60[0x5];
4014         u8         allowed_list_type[0x3];
4015         u8         reserved_at_68[0x18];
4016 };
4017
4018 struct mlx5_ifc_query_mkey_out_bits {
4019         u8         status[0x8];
4020         u8         reserved_at_8[0x18];
4021
4022         u8         syndrome[0x20];
4023
4024         u8         reserved_at_40[0x40];
4025
4026         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4027
4028         u8         reserved_at_280[0x600];
4029
4030         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4031
4032         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4033 };
4034
4035 struct mlx5_ifc_query_mkey_in_bits {
4036         u8         opcode[0x10];
4037         u8         reserved_at_10[0x10];
4038
4039         u8         reserved_at_20[0x10];
4040         u8         op_mod[0x10];
4041
4042         u8         reserved_at_40[0x8];
4043         u8         mkey_index[0x18];
4044
4045         u8         pg_access[0x1];
4046         u8         reserved_at_61[0x1f];
4047 };
4048
4049 struct mlx5_ifc_query_mad_demux_out_bits {
4050         u8         status[0x8];
4051         u8         reserved_at_8[0x18];
4052
4053         u8         syndrome[0x20];
4054
4055         u8         reserved_at_40[0x40];
4056
4057         u8         mad_dumux_parameters_block[0x20];
4058 };
4059
4060 struct mlx5_ifc_query_mad_demux_in_bits {
4061         u8         opcode[0x10];
4062         u8         reserved_at_10[0x10];
4063
4064         u8         reserved_at_20[0x10];
4065         u8         op_mod[0x10];
4066
4067         u8         reserved_at_40[0x40];
4068 };
4069
4070 struct mlx5_ifc_query_l2_table_entry_out_bits {
4071         u8         status[0x8];
4072         u8         reserved_at_8[0x18];
4073
4074         u8         syndrome[0x20];
4075
4076         u8         reserved_at_40[0xa0];
4077
4078         u8         reserved_at_e0[0x13];
4079         u8         vlan_valid[0x1];
4080         u8         vlan[0xc];
4081
4082         struct mlx5_ifc_mac_address_layout_bits mac_address;
4083
4084         u8         reserved_at_140[0xc0];
4085 };
4086
4087 struct mlx5_ifc_query_l2_table_entry_in_bits {
4088         u8         opcode[0x10];
4089         u8         reserved_at_10[0x10];
4090
4091         u8         reserved_at_20[0x10];
4092         u8         op_mod[0x10];
4093
4094         u8         reserved_at_40[0x60];
4095
4096         u8         reserved_at_a0[0x8];
4097         u8         table_index[0x18];
4098
4099         u8         reserved_at_c0[0x140];
4100 };
4101
4102 struct mlx5_ifc_query_issi_out_bits {
4103         u8         status[0x8];
4104         u8         reserved_at_8[0x18];
4105
4106         u8         syndrome[0x20];
4107
4108         u8         reserved_at_40[0x10];
4109         u8         current_issi[0x10];
4110
4111         u8         reserved_at_60[0xa0];
4112
4113         u8         reserved_at_100[76][0x8];
4114         u8         supported_issi_dw0[0x20];
4115 };
4116
4117 struct mlx5_ifc_query_issi_in_bits {
4118         u8         opcode[0x10];
4119         u8         reserved_at_10[0x10];
4120
4121         u8         reserved_at_20[0x10];
4122         u8         op_mod[0x10];
4123
4124         u8         reserved_at_40[0x40];
4125 };
4126
4127 struct mlx5_ifc_set_driver_version_out_bits {
4128         u8         status[0x8];
4129         u8         reserved_0[0x18];
4130
4131         u8         syndrome[0x20];
4132         u8         reserved_1[0x40];
4133 };
4134
4135 struct mlx5_ifc_set_driver_version_in_bits {
4136         u8         opcode[0x10];
4137         u8         reserved_0[0x10];
4138
4139         u8         reserved_1[0x10];
4140         u8         op_mod[0x10];
4141
4142         u8         reserved_2[0x40];
4143         u8         driver_version[64][0x8];
4144 };
4145
4146 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4147         u8         status[0x8];
4148         u8         reserved_at_8[0x18];
4149
4150         u8         syndrome[0x20];
4151
4152         u8         reserved_at_40[0x40];
4153
4154         struct mlx5_ifc_pkey_bits pkey[0];
4155 };
4156
4157 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4158         u8         opcode[0x10];
4159         u8         reserved_at_10[0x10];
4160
4161         u8         reserved_at_20[0x10];
4162         u8         op_mod[0x10];
4163
4164         u8         other_vport[0x1];
4165         u8         reserved_at_41[0xb];
4166         u8         port_num[0x4];
4167         u8         vport_number[0x10];
4168
4169         u8         reserved_at_60[0x10];
4170         u8         pkey_index[0x10];
4171 };
4172
4173 enum {
4174         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4175         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4176         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4177 };
4178
4179 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4180         u8         status[0x8];
4181         u8         reserved_at_8[0x18];
4182
4183         u8         syndrome[0x20];
4184
4185         u8         reserved_at_40[0x20];
4186
4187         u8         gids_num[0x10];
4188         u8         reserved_at_70[0x10];
4189
4190         struct mlx5_ifc_array128_auto_bits gid[0];
4191 };
4192
4193 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4194         u8         opcode[0x10];
4195         u8         reserved_at_10[0x10];
4196
4197         u8         reserved_at_20[0x10];
4198         u8         op_mod[0x10];
4199
4200         u8         other_vport[0x1];
4201         u8         reserved_at_41[0xb];
4202         u8         port_num[0x4];
4203         u8         vport_number[0x10];
4204
4205         u8         reserved_at_60[0x10];
4206         u8         gid_index[0x10];
4207 };
4208
4209 struct mlx5_ifc_query_hca_vport_context_out_bits {
4210         u8         status[0x8];
4211         u8         reserved_at_8[0x18];
4212
4213         u8         syndrome[0x20];
4214
4215         u8         reserved_at_40[0x40];
4216
4217         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4218 };
4219
4220 struct mlx5_ifc_query_hca_vport_context_in_bits {
4221         u8         opcode[0x10];
4222         u8         reserved_at_10[0x10];
4223
4224         u8         reserved_at_20[0x10];
4225         u8         op_mod[0x10];
4226
4227         u8         other_vport[0x1];
4228         u8         reserved_at_41[0xb];
4229         u8         port_num[0x4];
4230         u8         vport_number[0x10];
4231
4232         u8         reserved_at_60[0x20];
4233 };
4234
4235 struct mlx5_ifc_query_hca_cap_out_bits {
4236         u8         status[0x8];
4237         u8         reserved_at_8[0x18];
4238
4239         u8         syndrome[0x20];
4240
4241         u8         reserved_at_40[0x40];
4242
4243         union mlx5_ifc_hca_cap_union_bits capability;
4244 };
4245
4246 struct mlx5_ifc_query_hca_cap_in_bits {
4247         u8         opcode[0x10];
4248         u8         reserved_at_10[0x10];
4249
4250         u8         reserved_at_20[0x10];
4251         u8         op_mod[0x10];
4252
4253         u8         reserved_at_40[0x40];
4254 };
4255
4256 struct mlx5_ifc_query_flow_table_out_bits {
4257         u8         status[0x8];
4258         u8         reserved_at_8[0x18];
4259
4260         u8         syndrome[0x20];
4261
4262         u8         reserved_at_40[0x80];
4263
4264         u8         reserved_at_c0[0x8];
4265         u8         level[0x8];
4266         u8         reserved_at_d0[0x8];
4267         u8         log_size[0x8];
4268
4269         u8         reserved_at_e0[0x120];
4270 };
4271
4272 struct mlx5_ifc_query_flow_table_in_bits {
4273         u8         opcode[0x10];
4274         u8         reserved_at_10[0x10];
4275
4276         u8         reserved_at_20[0x10];
4277         u8         op_mod[0x10];
4278
4279         u8         reserved_at_40[0x40];
4280
4281         u8         table_type[0x8];
4282         u8         reserved_at_88[0x18];
4283
4284         u8         reserved_at_a0[0x8];
4285         u8         table_id[0x18];
4286
4287         u8         reserved_at_c0[0x140];
4288 };
4289
4290 struct mlx5_ifc_query_fte_out_bits {
4291         u8         status[0x8];
4292         u8         reserved_at_8[0x18];
4293
4294         u8         syndrome[0x20];
4295
4296         u8         reserved_at_40[0x1c0];
4297
4298         struct mlx5_ifc_flow_context_bits flow_context;
4299 };
4300
4301 struct mlx5_ifc_query_fte_in_bits {
4302         u8         opcode[0x10];
4303         u8         reserved_at_10[0x10];
4304
4305         u8         reserved_at_20[0x10];
4306         u8         op_mod[0x10];
4307
4308         u8         reserved_at_40[0x40];
4309
4310         u8         table_type[0x8];
4311         u8         reserved_at_88[0x18];
4312
4313         u8         reserved_at_a0[0x8];
4314         u8         table_id[0x18];
4315
4316         u8         reserved_at_c0[0x40];
4317
4318         u8         flow_index[0x20];
4319
4320         u8         reserved_at_120[0xe0];
4321 };
4322
4323 enum {
4324         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
4325         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
4326         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
4327 };
4328
4329 struct mlx5_ifc_query_flow_group_out_bits {
4330         u8         status[0x8];
4331         u8         reserved_at_8[0x18];
4332
4333         u8         syndrome[0x20];
4334
4335         u8         reserved_at_40[0xa0];
4336
4337         u8         start_flow_index[0x20];
4338
4339         u8         reserved_at_100[0x20];
4340
4341         u8         end_flow_index[0x20];
4342
4343         u8         reserved_at_140[0xa0];
4344
4345         u8         reserved_at_1e0[0x18];
4346         u8         match_criteria_enable[0x8];
4347
4348         struct mlx5_ifc_fte_match_param_bits match_criteria;
4349
4350         u8         reserved_at_1200[0xe00];
4351 };
4352
4353 struct mlx5_ifc_query_flow_group_in_bits {
4354         u8         opcode[0x10];
4355         u8         reserved_at_10[0x10];
4356
4357         u8         reserved_at_20[0x10];
4358         u8         op_mod[0x10];
4359
4360         u8         reserved_at_40[0x40];
4361
4362         u8         table_type[0x8];
4363         u8         reserved_at_88[0x18];
4364
4365         u8         reserved_at_a0[0x8];
4366         u8         table_id[0x18];
4367
4368         u8         group_id[0x20];
4369
4370         u8         reserved_at_e0[0x120];
4371 };
4372
4373 struct mlx5_ifc_query_flow_counter_out_bits {
4374         u8         status[0x8];
4375         u8         reserved_at_8[0x18];
4376
4377         u8         syndrome[0x20];
4378
4379         u8         reserved_at_40[0x40];
4380
4381         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4382 };
4383
4384 struct mlx5_ifc_query_flow_counter_in_bits {
4385         u8         opcode[0x10];
4386         u8         reserved_at_10[0x10];
4387
4388         u8         reserved_at_20[0x10];
4389         u8         op_mod[0x10];
4390
4391         u8         reserved_at_40[0x80];
4392
4393         u8         clear[0x1];
4394         u8         reserved_at_c1[0xf];
4395         u8         num_of_counters[0x10];
4396
4397         u8         reserved_at_e0[0x10];
4398         u8         flow_counter_id[0x10];
4399 };
4400
4401 struct mlx5_ifc_query_esw_vport_context_out_bits {
4402         u8         status[0x8];
4403         u8         reserved_at_8[0x18];
4404
4405         u8         syndrome[0x20];
4406
4407         u8         reserved_at_40[0x40];
4408
4409         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4410 };
4411
4412 struct mlx5_ifc_query_esw_vport_context_in_bits {
4413         u8         opcode[0x10];
4414         u8         reserved_at_10[0x10];
4415
4416         u8         reserved_at_20[0x10];
4417         u8         op_mod[0x10];
4418
4419         u8         other_vport[0x1];
4420         u8         reserved_at_41[0xf];
4421         u8         vport_number[0x10];
4422
4423         u8         reserved_at_60[0x20];
4424 };
4425
4426 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4427         u8         status[0x8];
4428         u8         reserved_at_8[0x18];
4429
4430         u8         syndrome[0x20];
4431
4432         u8         reserved_at_40[0x40];
4433 };
4434
4435 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4436         u8         reserved_at_0[0x1c];
4437         u8         vport_cvlan_insert[0x1];
4438         u8         vport_svlan_insert[0x1];
4439         u8         vport_cvlan_strip[0x1];
4440         u8         vport_svlan_strip[0x1];
4441 };
4442
4443 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4444         u8         opcode[0x10];
4445         u8         reserved_at_10[0x10];
4446
4447         u8         reserved_at_20[0x10];
4448         u8         op_mod[0x10];
4449
4450         u8         other_vport[0x1];
4451         u8         reserved_at_41[0xf];
4452         u8         vport_number[0x10];
4453
4454         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4455
4456         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4457 };
4458
4459 struct mlx5_ifc_query_eq_out_bits {
4460         u8         status[0x8];
4461         u8         reserved_at_8[0x18];
4462
4463         u8         syndrome[0x20];
4464
4465         u8         reserved_at_40[0x40];
4466
4467         struct mlx5_ifc_eqc_bits eq_context_entry;
4468
4469         u8         reserved_at_280[0x40];
4470
4471         u8         event_bitmask[0x40];
4472
4473         u8         reserved_at_300[0x580];
4474
4475         u8         pas[0][0x40];
4476 };
4477
4478 struct mlx5_ifc_query_eq_in_bits {
4479         u8         opcode[0x10];
4480         u8         reserved_at_10[0x10];
4481
4482         u8         reserved_at_20[0x10];
4483         u8         op_mod[0x10];
4484
4485         u8         reserved_at_40[0x18];
4486         u8         eq_number[0x8];
4487
4488         u8         reserved_at_60[0x20];
4489 };
4490
4491 struct mlx5_ifc_encap_header_in_bits {
4492         u8         reserved_at_0[0x5];
4493         u8         header_type[0x3];
4494         u8         reserved_at_8[0xe];
4495         u8         encap_header_size[0xa];
4496
4497         u8         reserved_at_20[0x10];
4498         u8         encap_header[2][0x8];
4499
4500         u8         more_encap_header[0][0x8];
4501 };
4502
4503 struct mlx5_ifc_query_encap_header_out_bits {
4504         u8         status[0x8];
4505         u8         reserved_at_8[0x18];
4506
4507         u8         syndrome[0x20];
4508
4509         u8         reserved_at_40[0xa0];
4510
4511         struct mlx5_ifc_encap_header_in_bits encap_header[0];
4512 };
4513
4514 struct mlx5_ifc_query_encap_header_in_bits {
4515         u8         opcode[0x10];
4516         u8         reserved_at_10[0x10];
4517
4518         u8         reserved_at_20[0x10];
4519         u8         op_mod[0x10];
4520
4521         u8         encap_id[0x20];
4522
4523         u8         reserved_at_60[0xa0];
4524 };
4525
4526 struct mlx5_ifc_alloc_encap_header_out_bits {
4527         u8         status[0x8];
4528         u8         reserved_at_8[0x18];
4529
4530         u8         syndrome[0x20];
4531
4532         u8         encap_id[0x20];
4533
4534         u8         reserved_at_60[0x20];
4535 };
4536
4537 struct mlx5_ifc_alloc_encap_header_in_bits {
4538         u8         opcode[0x10];
4539         u8         reserved_at_10[0x10];
4540
4541         u8         reserved_at_20[0x10];
4542         u8         op_mod[0x10];
4543
4544         u8         reserved_at_40[0xa0];
4545
4546         struct mlx5_ifc_encap_header_in_bits encap_header;
4547 };
4548
4549 struct mlx5_ifc_dealloc_encap_header_out_bits {
4550         u8         status[0x8];
4551         u8         reserved_at_8[0x18];
4552
4553         u8         syndrome[0x20];
4554
4555         u8         reserved_at_40[0x40];
4556 };
4557
4558 struct mlx5_ifc_dealloc_encap_header_in_bits {
4559         u8         opcode[0x10];
4560         u8         reserved_at_10[0x10];
4561
4562         u8         reserved_20[0x10];
4563         u8         op_mod[0x10];
4564
4565         u8         encap_id[0x20];
4566
4567         u8         reserved_60[0x20];
4568 };
4569
4570 struct mlx5_ifc_set_action_in_bits {
4571         u8         action_type[0x4];
4572         u8         field[0xc];
4573         u8         reserved_at_10[0x3];
4574         u8         offset[0x5];
4575         u8         reserved_at_18[0x3];
4576         u8         length[0x5];
4577
4578         u8         data[0x20];
4579 };
4580
4581 struct mlx5_ifc_add_action_in_bits {
4582         u8         action_type[0x4];
4583         u8         field[0xc];
4584         u8         reserved_at_10[0x10];
4585
4586         u8         data[0x20];
4587 };
4588
4589 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4590         struct mlx5_ifc_set_action_in_bits set_action_in;
4591         struct mlx5_ifc_add_action_in_bits add_action_in;
4592         u8         reserved_at_0[0x40];
4593 };
4594
4595 enum {
4596         MLX5_ACTION_TYPE_SET   = 0x1,
4597         MLX5_ACTION_TYPE_ADD   = 0x2,
4598 };
4599
4600 enum {
4601         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
4602         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
4603         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
4604         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
4605         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
4606         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
4607         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
4608         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
4609         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
4610         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
4611         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
4612         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
4613         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
4614         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
4615         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
4616         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
4617         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
4618         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
4619         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
4620         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
4621         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
4622         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
4623 };
4624
4625 struct mlx5_ifc_alloc_modify_header_context_out_bits {
4626         u8         status[0x8];
4627         u8         reserved_at_8[0x18];
4628
4629         u8         syndrome[0x20];
4630
4631         u8         modify_header_id[0x20];
4632
4633         u8         reserved_at_60[0x20];
4634 };
4635
4636 struct mlx5_ifc_alloc_modify_header_context_in_bits {
4637         u8         opcode[0x10];
4638         u8         reserved_at_10[0x10];
4639
4640         u8         reserved_at_20[0x10];
4641         u8         op_mod[0x10];
4642
4643         u8         reserved_at_40[0x20];
4644
4645         u8         table_type[0x8];
4646         u8         reserved_at_68[0x10];
4647         u8         num_of_actions[0x8];
4648
4649         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4650 };
4651
4652 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4653         u8         status[0x8];
4654         u8         reserved_at_8[0x18];
4655
4656         u8         syndrome[0x20];
4657
4658         u8         reserved_at_40[0x40];
4659 };
4660
4661 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4662         u8         opcode[0x10];
4663         u8         reserved_at_10[0x10];
4664
4665         u8         reserved_at_20[0x10];
4666         u8         op_mod[0x10];
4667
4668         u8         modify_header_id[0x20];
4669
4670         u8         reserved_at_60[0x20];
4671 };
4672
4673 struct mlx5_ifc_query_dct_out_bits {
4674         u8         status[0x8];
4675         u8         reserved_at_8[0x18];
4676
4677         u8         syndrome[0x20];
4678
4679         u8         reserved_at_40[0x40];
4680
4681         struct mlx5_ifc_dctc_bits dct_context_entry;
4682
4683         u8         reserved_at_280[0x180];
4684 };
4685
4686 struct mlx5_ifc_query_dct_in_bits {
4687         u8         opcode[0x10];
4688         u8         reserved_at_10[0x10];
4689
4690         u8         reserved_at_20[0x10];
4691         u8         op_mod[0x10];
4692
4693         u8         reserved_at_40[0x8];
4694         u8         dctn[0x18];
4695
4696         u8         reserved_at_60[0x20];
4697 };
4698
4699 struct mlx5_ifc_query_cq_out_bits {
4700         u8         status[0x8];
4701         u8         reserved_at_8[0x18];
4702
4703         u8         syndrome[0x20];
4704
4705         u8         reserved_at_40[0x40];
4706
4707         struct mlx5_ifc_cqc_bits cq_context;
4708
4709         u8         reserved_at_280[0x600];
4710
4711         u8         pas[0][0x40];
4712 };
4713
4714 struct mlx5_ifc_query_cq_in_bits {
4715         u8         opcode[0x10];
4716         u8         reserved_at_10[0x10];
4717
4718         u8         reserved_at_20[0x10];
4719         u8         op_mod[0x10];
4720
4721         u8         reserved_at_40[0x8];
4722         u8         cqn[0x18];
4723
4724         u8         reserved_at_60[0x20];
4725 };
4726
4727 struct mlx5_ifc_query_cong_status_out_bits {
4728         u8         status[0x8];
4729         u8         reserved_at_8[0x18];
4730
4731         u8         syndrome[0x20];
4732
4733         u8         reserved_at_40[0x20];
4734
4735         u8         enable[0x1];
4736         u8         tag_enable[0x1];
4737         u8         reserved_at_62[0x1e];
4738 };
4739
4740 struct mlx5_ifc_query_cong_status_in_bits {
4741         u8         opcode[0x10];
4742         u8         reserved_at_10[0x10];
4743
4744         u8         reserved_at_20[0x10];
4745         u8         op_mod[0x10];
4746
4747         u8         reserved_at_40[0x18];
4748         u8         priority[0x4];
4749         u8         cong_protocol[0x4];
4750
4751         u8         reserved_at_60[0x20];
4752 };
4753
4754 struct mlx5_ifc_query_cong_statistics_out_bits {
4755         u8         status[0x8];
4756         u8         reserved_at_8[0x18];
4757
4758         u8         syndrome[0x20];
4759
4760         u8         reserved_at_40[0x40];
4761
4762         u8         rp_cur_flows[0x20];
4763
4764         u8         sum_flows[0x20];
4765
4766         u8         rp_cnp_ignored_high[0x20];
4767
4768         u8         rp_cnp_ignored_low[0x20];
4769
4770         u8         rp_cnp_handled_high[0x20];
4771
4772         u8         rp_cnp_handled_low[0x20];
4773
4774         u8         reserved_at_140[0x100];
4775
4776         u8         time_stamp_high[0x20];
4777
4778         u8         time_stamp_low[0x20];
4779
4780         u8         accumulators_period[0x20];
4781
4782         u8         np_ecn_marked_roce_packets_high[0x20];
4783
4784         u8         np_ecn_marked_roce_packets_low[0x20];
4785
4786         u8         np_cnp_sent_high[0x20];
4787
4788         u8         np_cnp_sent_low[0x20];
4789
4790         u8         reserved_at_320[0x560];
4791 };
4792
4793 struct mlx5_ifc_query_cong_statistics_in_bits {
4794         u8         opcode[0x10];
4795         u8         reserved_at_10[0x10];
4796
4797         u8         reserved_at_20[0x10];
4798         u8         op_mod[0x10];
4799
4800         u8         clear[0x1];
4801         u8         reserved_at_41[0x1f];
4802
4803         u8         reserved_at_60[0x20];
4804 };
4805
4806 struct mlx5_ifc_query_cong_params_out_bits {
4807         u8         status[0x8];
4808         u8         reserved_at_8[0x18];
4809
4810         u8         syndrome[0x20];
4811
4812         u8         reserved_at_40[0x40];
4813
4814         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4815 };
4816
4817 struct mlx5_ifc_query_cong_params_in_bits {
4818         u8         opcode[0x10];
4819         u8         reserved_at_10[0x10];
4820
4821         u8         reserved_at_20[0x10];
4822         u8         op_mod[0x10];
4823
4824         u8         reserved_at_40[0x1c];
4825         u8         cong_protocol[0x4];
4826
4827         u8         reserved_at_60[0x20];
4828 };
4829
4830 struct mlx5_ifc_query_adapter_out_bits {
4831         u8         status[0x8];
4832         u8         reserved_at_8[0x18];
4833
4834         u8         syndrome[0x20];
4835
4836         u8         reserved_at_40[0x40];
4837
4838         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4839 };
4840
4841 struct mlx5_ifc_query_adapter_in_bits {
4842         u8         opcode[0x10];
4843         u8         reserved_at_10[0x10];
4844
4845         u8         reserved_at_20[0x10];
4846         u8         op_mod[0x10];
4847
4848         u8         reserved_at_40[0x40];
4849 };
4850
4851 struct mlx5_ifc_qp_2rst_out_bits {
4852         u8         status[0x8];
4853         u8         reserved_at_8[0x18];
4854
4855         u8         syndrome[0x20];
4856
4857         u8         reserved_at_40[0x40];
4858 };
4859
4860 struct mlx5_ifc_qp_2rst_in_bits {
4861         u8         opcode[0x10];
4862         u8         reserved_at_10[0x10];
4863
4864         u8         reserved_at_20[0x10];
4865         u8         op_mod[0x10];
4866
4867         u8         reserved_at_40[0x8];
4868         u8         qpn[0x18];
4869
4870         u8         reserved_at_60[0x20];
4871 };
4872
4873 struct mlx5_ifc_qp_2err_out_bits {
4874         u8         status[0x8];
4875         u8         reserved_at_8[0x18];
4876
4877         u8         syndrome[0x20];
4878
4879         u8         reserved_at_40[0x40];
4880 };
4881
4882 struct mlx5_ifc_qp_2err_in_bits {
4883         u8         opcode[0x10];
4884         u8         reserved_at_10[0x10];
4885
4886         u8         reserved_at_20[0x10];
4887         u8         op_mod[0x10];
4888
4889         u8         reserved_at_40[0x8];
4890         u8         qpn[0x18];
4891
4892         u8         reserved_at_60[0x20];
4893 };
4894
4895 struct mlx5_ifc_page_fault_resume_out_bits {
4896         u8         status[0x8];
4897         u8         reserved_at_8[0x18];
4898
4899         u8         syndrome[0x20];
4900
4901         u8         reserved_at_40[0x40];
4902 };
4903
4904 struct mlx5_ifc_page_fault_resume_in_bits {
4905         u8         opcode[0x10];
4906         u8         reserved_at_10[0x10];
4907
4908         u8         reserved_at_20[0x10];
4909         u8         op_mod[0x10];
4910
4911         u8         error[0x1];
4912         u8         reserved_at_41[0x4];
4913         u8         page_fault_type[0x3];
4914         u8         wq_number[0x18];
4915
4916         u8         reserved_at_60[0x8];
4917         u8         token[0x18];
4918 };
4919
4920 struct mlx5_ifc_nop_out_bits {
4921         u8         status[0x8];
4922         u8         reserved_at_8[0x18];
4923
4924         u8         syndrome[0x20];
4925
4926         u8         reserved_at_40[0x40];
4927 };
4928
4929 struct mlx5_ifc_nop_in_bits {
4930         u8         opcode[0x10];
4931         u8         reserved_at_10[0x10];
4932
4933         u8         reserved_at_20[0x10];
4934         u8         op_mod[0x10];
4935
4936         u8         reserved_at_40[0x40];
4937 };
4938
4939 struct mlx5_ifc_modify_vport_state_out_bits {
4940         u8         status[0x8];
4941         u8         reserved_at_8[0x18];
4942
4943         u8         syndrome[0x20];
4944
4945         u8         reserved_at_40[0x40];
4946 };
4947
4948 struct mlx5_ifc_modify_vport_state_in_bits {
4949         u8         opcode[0x10];
4950         u8         reserved_at_10[0x10];
4951
4952         u8         reserved_at_20[0x10];
4953         u8         op_mod[0x10];
4954
4955         u8         other_vport[0x1];
4956         u8         reserved_at_41[0xf];
4957         u8         vport_number[0x10];
4958
4959         u8         reserved_at_60[0x18];
4960         u8         admin_state[0x4];
4961         u8         reserved_at_7c[0x4];
4962 };
4963
4964 struct mlx5_ifc_modify_tis_out_bits {
4965         u8         status[0x8];
4966         u8         reserved_at_8[0x18];
4967
4968         u8         syndrome[0x20];
4969
4970         u8         reserved_at_40[0x40];
4971 };
4972
4973 struct mlx5_ifc_modify_tis_bitmask_bits {
4974         u8         reserved_at_0[0x20];
4975
4976         u8         reserved_at_20[0x1d];
4977         u8         lag_tx_port_affinity[0x1];
4978         u8         strict_lag_tx_port_affinity[0x1];
4979         u8         prio[0x1];
4980 };
4981
4982 struct mlx5_ifc_modify_tis_in_bits {
4983         u8         opcode[0x10];
4984         u8         reserved_at_10[0x10];
4985
4986         u8         reserved_at_20[0x10];
4987         u8         op_mod[0x10];
4988
4989         u8         reserved_at_40[0x8];
4990         u8         tisn[0x18];
4991
4992         u8         reserved_at_60[0x20];
4993
4994         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4995
4996         u8         reserved_at_c0[0x40];
4997
4998         struct mlx5_ifc_tisc_bits ctx;
4999 };
5000
5001 struct mlx5_ifc_modify_tir_bitmask_bits {
5002         u8         reserved_at_0[0x20];
5003
5004         u8         reserved_at_20[0x1b];
5005         u8         self_lb_en[0x1];
5006         u8         reserved_at_3c[0x1];
5007         u8         hash[0x1];
5008         u8         reserved_at_3e[0x1];
5009         u8         lro[0x1];
5010 };
5011
5012 struct mlx5_ifc_modify_tir_out_bits {
5013         u8         status[0x8];
5014         u8         reserved_at_8[0x18];
5015
5016         u8         syndrome[0x20];
5017
5018         u8         reserved_at_40[0x40];
5019 };
5020
5021 struct mlx5_ifc_modify_tir_in_bits {
5022         u8         opcode[0x10];
5023         u8         reserved_at_10[0x10];
5024
5025         u8         reserved_at_20[0x10];
5026         u8         op_mod[0x10];
5027
5028         u8         reserved_at_40[0x8];
5029         u8         tirn[0x18];
5030
5031         u8         reserved_at_60[0x20];
5032
5033         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5034
5035         u8         reserved_at_c0[0x40];
5036
5037         struct mlx5_ifc_tirc_bits ctx;
5038 };
5039
5040 struct mlx5_ifc_modify_sq_out_bits {
5041         u8         status[0x8];
5042         u8         reserved_at_8[0x18];
5043
5044         u8         syndrome[0x20];
5045
5046         u8         reserved_at_40[0x40];
5047 };
5048
5049 struct mlx5_ifc_modify_sq_in_bits {
5050         u8         opcode[0x10];
5051         u8         reserved_at_10[0x10];
5052
5053         u8         reserved_at_20[0x10];
5054         u8         op_mod[0x10];
5055
5056         u8         sq_state[0x4];
5057         u8         reserved_at_44[0x4];
5058         u8         sqn[0x18];
5059
5060         u8         reserved_at_60[0x20];
5061
5062         u8         modify_bitmask[0x40];
5063
5064         u8         reserved_at_c0[0x40];
5065
5066         struct mlx5_ifc_sqc_bits ctx;
5067 };
5068
5069 struct mlx5_ifc_modify_scheduling_element_out_bits {
5070         u8         status[0x8];
5071         u8         reserved_at_8[0x18];
5072
5073         u8         syndrome[0x20];
5074
5075         u8         reserved_at_40[0x1c0];
5076 };
5077
5078 enum {
5079         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5080         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5081 };
5082
5083 struct mlx5_ifc_modify_scheduling_element_in_bits {
5084         u8         opcode[0x10];
5085         u8         reserved_at_10[0x10];
5086
5087         u8         reserved_at_20[0x10];
5088         u8         op_mod[0x10];
5089
5090         u8         scheduling_hierarchy[0x8];
5091         u8         reserved_at_48[0x18];
5092
5093         u8         scheduling_element_id[0x20];
5094
5095         u8         reserved_at_80[0x20];
5096
5097         u8         modify_bitmask[0x20];
5098
5099         u8         reserved_at_c0[0x40];
5100
5101         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5102
5103         u8         reserved_at_300[0x100];
5104 };
5105
5106 struct mlx5_ifc_modify_rqt_out_bits {
5107         u8         status[0x8];
5108         u8         reserved_at_8[0x18];
5109
5110         u8         syndrome[0x20];
5111
5112         u8         reserved_at_40[0x40];
5113 };
5114
5115 struct mlx5_ifc_rqt_bitmask_bits {
5116         u8         reserved_at_0[0x20];
5117
5118         u8         reserved_at_20[0x1f];
5119         u8         rqn_list[0x1];
5120 };
5121
5122 struct mlx5_ifc_modify_rqt_in_bits {
5123         u8         opcode[0x10];
5124         u8         reserved_at_10[0x10];
5125
5126         u8         reserved_at_20[0x10];
5127         u8         op_mod[0x10];
5128
5129         u8         reserved_at_40[0x8];
5130         u8         rqtn[0x18];
5131
5132         u8         reserved_at_60[0x20];
5133
5134         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5135
5136         u8         reserved_at_c0[0x40];
5137
5138         struct mlx5_ifc_rqtc_bits ctx;
5139 };
5140
5141 struct mlx5_ifc_modify_rq_out_bits {
5142         u8         status[0x8];
5143         u8         reserved_at_8[0x18];
5144
5145         u8         syndrome[0x20];
5146
5147         u8         reserved_at_40[0x40];
5148 };
5149
5150 enum {
5151         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5152         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5153         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5154 };
5155
5156 struct mlx5_ifc_modify_rq_in_bits {
5157         u8         opcode[0x10];
5158         u8         reserved_at_10[0x10];
5159
5160         u8         reserved_at_20[0x10];
5161         u8         op_mod[0x10];
5162
5163         u8         rq_state[0x4];
5164         u8         reserved_at_44[0x4];
5165         u8         rqn[0x18];
5166
5167         u8         reserved_at_60[0x20];
5168
5169         u8         modify_bitmask[0x40];
5170
5171         u8         reserved_at_c0[0x40];
5172
5173         struct mlx5_ifc_rqc_bits ctx;
5174 };
5175
5176 struct mlx5_ifc_modify_rmp_out_bits {
5177         u8         status[0x8];
5178         u8         reserved_at_8[0x18];
5179
5180         u8         syndrome[0x20];
5181
5182         u8         reserved_at_40[0x40];
5183 };
5184
5185 struct mlx5_ifc_rmp_bitmask_bits {
5186         u8         reserved_at_0[0x20];
5187
5188         u8         reserved_at_20[0x1f];
5189         u8         lwm[0x1];
5190 };
5191
5192 struct mlx5_ifc_modify_rmp_in_bits {
5193         u8         opcode[0x10];
5194         u8         reserved_at_10[0x10];
5195
5196         u8         reserved_at_20[0x10];
5197         u8         op_mod[0x10];
5198
5199         u8         rmp_state[0x4];
5200         u8         reserved_at_44[0x4];
5201         u8         rmpn[0x18];
5202
5203         u8         reserved_at_60[0x20];
5204
5205         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5206
5207         u8         reserved_at_c0[0x40];
5208
5209         struct mlx5_ifc_rmpc_bits ctx;
5210 };
5211
5212 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5213         u8         status[0x8];
5214         u8         reserved_at_8[0x18];
5215
5216         u8         syndrome[0x20];
5217
5218         u8         reserved_at_40[0x40];
5219 };
5220
5221 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5222         u8         reserved_at_0[0x16];
5223         u8         node_guid[0x1];
5224         u8         port_guid[0x1];
5225         u8         min_inline[0x1];
5226         u8         mtu[0x1];
5227         u8         change_event[0x1];
5228         u8         promisc[0x1];
5229         u8         permanent_address[0x1];
5230         u8         addresses_list[0x1];
5231         u8         roce_en[0x1];
5232         u8         reserved_at_1f[0x1];
5233 };
5234
5235 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5236         u8         opcode[0x10];
5237         u8         reserved_at_10[0x10];
5238
5239         u8         reserved_at_20[0x10];
5240         u8         op_mod[0x10];
5241
5242         u8         other_vport[0x1];
5243         u8         reserved_at_41[0xf];
5244         u8         vport_number[0x10];
5245
5246         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5247
5248         u8         reserved_at_80[0x780];
5249
5250         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5251 };
5252
5253 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5254         u8         status[0x8];
5255         u8         reserved_at_8[0x18];
5256
5257         u8         syndrome[0x20];
5258
5259         u8         reserved_at_40[0x40];
5260 };
5261
5262 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5263         u8         opcode[0x10];
5264         u8         reserved_at_10[0x10];
5265
5266         u8         reserved_at_20[0x10];
5267         u8         op_mod[0x10];
5268
5269         u8         other_vport[0x1];
5270         u8         reserved_at_41[0xb];
5271         u8         port_num[0x4];
5272         u8         vport_number[0x10];
5273
5274         u8         reserved_at_60[0x20];
5275
5276         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5277 };
5278
5279 struct mlx5_ifc_modify_cq_out_bits {
5280         u8         status[0x8];
5281         u8         reserved_at_8[0x18];
5282
5283         u8         syndrome[0x20];
5284
5285         u8         reserved_at_40[0x40];
5286 };
5287
5288 enum {
5289         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5290         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5291 };
5292
5293 struct mlx5_ifc_modify_cq_in_bits {
5294         u8         opcode[0x10];
5295         u8         reserved_at_10[0x10];
5296
5297         u8         reserved_at_20[0x10];
5298         u8         op_mod[0x10];
5299
5300         u8         reserved_at_40[0x8];
5301         u8         cqn[0x18];
5302
5303         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5304
5305         struct mlx5_ifc_cqc_bits cq_context;
5306
5307         u8         reserved_at_280[0x600];
5308
5309         u8         pas[0][0x40];
5310 };
5311
5312 struct mlx5_ifc_modify_cong_status_out_bits {
5313         u8         status[0x8];
5314         u8         reserved_at_8[0x18];
5315
5316         u8         syndrome[0x20];
5317
5318         u8         reserved_at_40[0x40];
5319 };
5320
5321 struct mlx5_ifc_modify_cong_status_in_bits {
5322         u8         opcode[0x10];
5323         u8         reserved_at_10[0x10];
5324
5325         u8         reserved_at_20[0x10];
5326         u8         op_mod[0x10];
5327
5328         u8         reserved_at_40[0x18];
5329         u8         priority[0x4];
5330         u8         cong_protocol[0x4];
5331
5332         u8         enable[0x1];
5333         u8         tag_enable[0x1];
5334         u8         reserved_at_62[0x1e];
5335 };
5336
5337 struct mlx5_ifc_modify_cong_params_out_bits {
5338         u8         status[0x8];
5339         u8         reserved_at_8[0x18];
5340
5341         u8         syndrome[0x20];
5342
5343         u8         reserved_at_40[0x40];
5344 };
5345
5346 struct mlx5_ifc_modify_cong_params_in_bits {
5347         u8         opcode[0x10];
5348         u8         reserved_at_10[0x10];
5349
5350         u8         reserved_at_20[0x10];
5351         u8         op_mod[0x10];
5352
5353         u8         reserved_at_40[0x1c];
5354         u8         cong_protocol[0x4];
5355
5356         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5357
5358         u8         reserved_at_80[0x80];
5359
5360         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5361 };
5362
5363 struct mlx5_ifc_manage_pages_out_bits {
5364         u8         status[0x8];
5365         u8         reserved_at_8[0x18];
5366
5367         u8         syndrome[0x20];
5368
5369         u8         output_num_entries[0x20];
5370
5371         u8         reserved_at_60[0x20];
5372
5373         u8         pas[0][0x40];
5374 };
5375
5376 enum {
5377         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
5378         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
5379         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
5380 };
5381
5382 struct mlx5_ifc_manage_pages_in_bits {
5383         u8         opcode[0x10];
5384         u8         reserved_at_10[0x10];
5385
5386         u8         reserved_at_20[0x10];
5387         u8         op_mod[0x10];
5388
5389         u8         reserved_at_40[0x10];
5390         u8         function_id[0x10];
5391
5392         u8         input_num_entries[0x20];
5393
5394         u8         pas[0][0x40];
5395 };
5396
5397 struct mlx5_ifc_mad_ifc_out_bits {
5398         u8         status[0x8];
5399         u8         reserved_at_8[0x18];
5400
5401         u8         syndrome[0x20];
5402
5403         u8         reserved_at_40[0x40];
5404
5405         u8         response_mad_packet[256][0x8];
5406 };
5407
5408 struct mlx5_ifc_mad_ifc_in_bits {
5409         u8         opcode[0x10];
5410         u8         reserved_at_10[0x10];
5411
5412         u8         reserved_at_20[0x10];
5413         u8         op_mod[0x10];
5414
5415         u8         remote_lid[0x10];
5416         u8         reserved_at_50[0x8];
5417         u8         port[0x8];
5418
5419         u8         reserved_at_60[0x20];
5420
5421         u8         mad[256][0x8];
5422 };
5423
5424 struct mlx5_ifc_init_hca_out_bits {
5425         u8         status[0x8];
5426         u8         reserved_at_8[0x18];
5427
5428         u8         syndrome[0x20];
5429
5430         u8         reserved_at_40[0x40];
5431 };
5432
5433 struct mlx5_ifc_init_hca_in_bits {
5434         u8         opcode[0x10];
5435         u8         reserved_at_10[0x10];
5436
5437         u8         reserved_at_20[0x10];
5438         u8         op_mod[0x10];
5439
5440         u8         reserved_at_40[0x40];
5441 };
5442
5443 struct mlx5_ifc_init2rtr_qp_out_bits {
5444         u8         status[0x8];
5445         u8         reserved_at_8[0x18];
5446
5447         u8         syndrome[0x20];
5448
5449         u8         reserved_at_40[0x40];
5450 };
5451
5452 struct mlx5_ifc_init2rtr_qp_in_bits {
5453         u8         opcode[0x10];
5454         u8         reserved_at_10[0x10];
5455
5456         u8         reserved_at_20[0x10];
5457         u8         op_mod[0x10];
5458
5459         u8         reserved_at_40[0x8];
5460         u8         qpn[0x18];
5461
5462         u8         reserved_at_60[0x20];
5463
5464         u8         opt_param_mask[0x20];
5465
5466         u8         reserved_at_a0[0x20];
5467
5468         struct mlx5_ifc_qpc_bits qpc;
5469
5470         u8         reserved_at_800[0x80];
5471 };
5472
5473 struct mlx5_ifc_init2init_qp_out_bits {
5474         u8         status[0x8];
5475         u8         reserved_at_8[0x18];
5476
5477         u8         syndrome[0x20];
5478
5479         u8         reserved_at_40[0x40];
5480 };
5481
5482 struct mlx5_ifc_init2init_qp_in_bits {
5483         u8         opcode[0x10];
5484         u8         reserved_at_10[0x10];
5485
5486         u8         reserved_at_20[0x10];
5487         u8         op_mod[0x10];
5488
5489         u8         reserved_at_40[0x8];
5490         u8         qpn[0x18];
5491
5492         u8         reserved_at_60[0x20];
5493
5494         u8         opt_param_mask[0x20];
5495
5496         u8         reserved_at_a0[0x20];
5497
5498         struct mlx5_ifc_qpc_bits qpc;
5499
5500         u8         reserved_at_800[0x80];
5501 };
5502
5503 struct mlx5_ifc_get_dropped_packet_log_out_bits {
5504         u8         status[0x8];
5505         u8         reserved_at_8[0x18];
5506
5507         u8         syndrome[0x20];
5508
5509         u8         reserved_at_40[0x40];
5510
5511         u8         packet_headers_log[128][0x8];
5512
5513         u8         packet_syndrome[64][0x8];
5514 };
5515
5516 struct mlx5_ifc_get_dropped_packet_log_in_bits {
5517         u8         opcode[0x10];
5518         u8         reserved_at_10[0x10];
5519
5520         u8         reserved_at_20[0x10];
5521         u8         op_mod[0x10];
5522
5523         u8         reserved_at_40[0x40];
5524 };
5525
5526 struct mlx5_ifc_gen_eqe_in_bits {
5527         u8         opcode[0x10];
5528         u8         reserved_at_10[0x10];
5529
5530         u8         reserved_at_20[0x10];
5531         u8         op_mod[0x10];
5532
5533         u8         reserved_at_40[0x18];
5534         u8         eq_number[0x8];
5535
5536         u8         reserved_at_60[0x20];
5537
5538         u8         eqe[64][0x8];
5539 };
5540
5541 struct mlx5_ifc_gen_eq_out_bits {
5542         u8         status[0x8];
5543         u8         reserved_at_8[0x18];
5544
5545         u8         syndrome[0x20];
5546
5547         u8         reserved_at_40[0x40];
5548 };
5549
5550 struct mlx5_ifc_enable_hca_out_bits {
5551         u8         status[0x8];
5552         u8         reserved_at_8[0x18];
5553
5554         u8         syndrome[0x20];
5555
5556         u8         reserved_at_40[0x20];
5557 };
5558
5559 struct mlx5_ifc_enable_hca_in_bits {
5560         u8         opcode[0x10];
5561         u8         reserved_at_10[0x10];
5562
5563         u8         reserved_at_20[0x10];
5564         u8         op_mod[0x10];
5565
5566         u8         reserved_at_40[0x10];
5567         u8         function_id[0x10];
5568
5569         u8         reserved_at_60[0x20];
5570 };
5571
5572 struct mlx5_ifc_drain_dct_out_bits {
5573         u8         status[0x8];
5574         u8         reserved_at_8[0x18];
5575
5576         u8         syndrome[0x20];
5577
5578         u8         reserved_at_40[0x40];
5579 };
5580
5581 struct mlx5_ifc_drain_dct_in_bits {
5582         u8         opcode[0x10];
5583         u8         reserved_at_10[0x10];
5584
5585         u8         reserved_at_20[0x10];
5586         u8         op_mod[0x10];
5587
5588         u8         reserved_at_40[0x8];
5589         u8         dctn[0x18];
5590
5591         u8         reserved_at_60[0x20];
5592 };
5593
5594 struct mlx5_ifc_disable_hca_out_bits {
5595         u8         status[0x8];
5596         u8         reserved_at_8[0x18];
5597
5598         u8         syndrome[0x20];
5599
5600         u8         reserved_at_40[0x20];
5601 };
5602
5603 struct mlx5_ifc_disable_hca_in_bits {
5604         u8         opcode[0x10];
5605         u8         reserved_at_10[0x10];
5606
5607         u8         reserved_at_20[0x10];
5608         u8         op_mod[0x10];
5609
5610         u8         reserved_at_40[0x10];
5611         u8         function_id[0x10];
5612
5613         u8         reserved_at_60[0x20];
5614 };
5615
5616 struct mlx5_ifc_detach_from_mcg_out_bits {
5617         u8         status[0x8];
5618         u8         reserved_at_8[0x18];
5619
5620         u8         syndrome[0x20];
5621
5622         u8         reserved_at_40[0x40];
5623 };
5624
5625 struct mlx5_ifc_detach_from_mcg_in_bits {
5626         u8         opcode[0x10];
5627         u8         reserved_at_10[0x10];
5628
5629         u8         reserved_at_20[0x10];
5630         u8         op_mod[0x10];
5631
5632         u8         reserved_at_40[0x8];
5633         u8         qpn[0x18];
5634
5635         u8         reserved_at_60[0x20];
5636
5637         u8         multicast_gid[16][0x8];
5638 };
5639
5640 struct mlx5_ifc_destroy_xrq_out_bits {
5641         u8         status[0x8];
5642         u8         reserved_at_8[0x18];
5643
5644         u8         syndrome[0x20];
5645
5646         u8         reserved_at_40[0x40];
5647 };
5648
5649 struct mlx5_ifc_destroy_xrq_in_bits {
5650         u8         opcode[0x10];
5651         u8         reserved_at_10[0x10];
5652
5653         u8         reserved_at_20[0x10];
5654         u8         op_mod[0x10];
5655
5656         u8         reserved_at_40[0x8];
5657         u8         xrqn[0x18];
5658
5659         u8         reserved_at_60[0x20];
5660 };
5661
5662 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5663         u8         status[0x8];
5664         u8         reserved_at_8[0x18];
5665
5666         u8         syndrome[0x20];
5667
5668         u8         reserved_at_40[0x40];
5669 };
5670
5671 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5672         u8         opcode[0x10];
5673         u8         reserved_at_10[0x10];
5674
5675         u8         reserved_at_20[0x10];
5676         u8         op_mod[0x10];
5677
5678         u8         reserved_at_40[0x8];
5679         u8         xrc_srqn[0x18];
5680
5681         u8         reserved_at_60[0x20];
5682 };
5683
5684 struct mlx5_ifc_destroy_tis_out_bits {
5685         u8         status[0x8];
5686         u8         reserved_at_8[0x18];
5687
5688         u8         syndrome[0x20];
5689
5690         u8         reserved_at_40[0x40];
5691 };
5692
5693 struct mlx5_ifc_destroy_tis_in_bits {
5694         u8         opcode[0x10];
5695         u8         reserved_at_10[0x10];
5696
5697         u8         reserved_at_20[0x10];
5698         u8         op_mod[0x10];
5699
5700         u8         reserved_at_40[0x8];
5701         u8         tisn[0x18];
5702
5703         u8         reserved_at_60[0x20];
5704 };
5705
5706 struct mlx5_ifc_destroy_tir_out_bits {
5707         u8         status[0x8];
5708         u8         reserved_at_8[0x18];
5709
5710         u8         syndrome[0x20];
5711
5712         u8         reserved_at_40[0x40];
5713 };
5714
5715 struct mlx5_ifc_destroy_tir_in_bits {
5716         u8         opcode[0x10];
5717         u8         reserved_at_10[0x10];
5718
5719         u8         reserved_at_20[0x10];
5720         u8         op_mod[0x10];
5721
5722         u8         reserved_at_40[0x8];
5723         u8         tirn[0x18];
5724
5725         u8         reserved_at_60[0x20];
5726 };
5727
5728 struct mlx5_ifc_destroy_srq_out_bits {
5729         u8         status[0x8];
5730         u8         reserved_at_8[0x18];
5731
5732         u8         syndrome[0x20];
5733
5734         u8         reserved_at_40[0x40];
5735 };
5736
5737 struct mlx5_ifc_destroy_srq_in_bits {
5738         u8         opcode[0x10];
5739         u8         reserved_at_10[0x10];
5740
5741         u8         reserved_at_20[0x10];
5742         u8         op_mod[0x10];
5743
5744         u8         reserved_at_40[0x8];
5745         u8         srqn[0x18];
5746
5747         u8         reserved_at_60[0x20];
5748 };
5749
5750 struct mlx5_ifc_destroy_sq_out_bits {
5751         u8         status[0x8];
5752         u8         reserved_at_8[0x18];
5753
5754         u8         syndrome[0x20];
5755
5756         u8         reserved_at_40[0x40];
5757 };
5758
5759 struct mlx5_ifc_destroy_sq_in_bits {
5760         u8         opcode[0x10];
5761         u8         reserved_at_10[0x10];
5762
5763         u8         reserved_at_20[0x10];
5764         u8         op_mod[0x10];
5765
5766         u8         reserved_at_40[0x8];
5767         u8         sqn[0x18];
5768
5769         u8         reserved_at_60[0x20];
5770 };
5771
5772 struct mlx5_ifc_destroy_scheduling_element_out_bits {
5773         u8         status[0x8];
5774         u8         reserved_at_8[0x18];
5775
5776         u8         syndrome[0x20];
5777
5778         u8         reserved_at_40[0x1c0];
5779 };
5780
5781 struct mlx5_ifc_destroy_scheduling_element_in_bits {
5782         u8         opcode[0x10];
5783         u8         reserved_at_10[0x10];
5784
5785         u8         reserved_at_20[0x10];
5786         u8         op_mod[0x10];
5787
5788         u8         scheduling_hierarchy[0x8];
5789         u8         reserved_at_48[0x18];
5790
5791         u8         scheduling_element_id[0x20];
5792
5793         u8         reserved_at_80[0x180];
5794 };
5795
5796 struct mlx5_ifc_destroy_rqt_out_bits {
5797         u8         status[0x8];
5798         u8         reserved_at_8[0x18];
5799
5800         u8         syndrome[0x20];
5801
5802         u8         reserved_at_40[0x40];
5803 };
5804
5805 struct mlx5_ifc_destroy_rqt_in_bits {
5806         u8         opcode[0x10];
5807         u8         reserved_at_10[0x10];
5808
5809         u8         reserved_at_20[0x10];
5810         u8         op_mod[0x10];
5811
5812         u8         reserved_at_40[0x8];
5813         u8         rqtn[0x18];
5814
5815         u8         reserved_at_60[0x20];
5816 };
5817
5818 struct mlx5_ifc_destroy_rq_out_bits {
5819         u8         status[0x8];
5820         u8         reserved_at_8[0x18];
5821
5822         u8         syndrome[0x20];
5823
5824         u8         reserved_at_40[0x40];
5825 };
5826
5827 struct mlx5_ifc_destroy_rq_in_bits {
5828         u8         opcode[0x10];
5829         u8         reserved_at_10[0x10];
5830
5831         u8         reserved_at_20[0x10];
5832         u8         op_mod[0x10];
5833
5834         u8         reserved_at_40[0x8];
5835         u8         rqn[0x18];
5836
5837         u8         reserved_at_60[0x20];
5838 };
5839
5840 struct mlx5_ifc_destroy_rmp_out_bits {
5841         u8         status[0x8];
5842         u8         reserved_at_8[0x18];
5843
5844         u8         syndrome[0x20];
5845
5846         u8         reserved_at_40[0x40];
5847 };
5848
5849 struct mlx5_ifc_destroy_rmp_in_bits {
5850         u8         opcode[0x10];
5851         u8         reserved_at_10[0x10];
5852
5853         u8         reserved_at_20[0x10];
5854         u8         op_mod[0x10];
5855
5856         u8         reserved_at_40[0x8];
5857         u8         rmpn[0x18];
5858
5859         u8         reserved_at_60[0x20];
5860 };
5861
5862 struct mlx5_ifc_destroy_qp_out_bits {
5863         u8         status[0x8];
5864         u8         reserved_at_8[0x18];
5865
5866         u8         syndrome[0x20];
5867
5868         u8         reserved_at_40[0x40];
5869 };
5870
5871 struct mlx5_ifc_destroy_qp_in_bits {
5872         u8         opcode[0x10];
5873         u8         reserved_at_10[0x10];
5874
5875         u8         reserved_at_20[0x10];
5876         u8         op_mod[0x10];
5877
5878         u8         reserved_at_40[0x8];
5879         u8         qpn[0x18];
5880
5881         u8         reserved_at_60[0x20];
5882 };
5883
5884 struct mlx5_ifc_destroy_psv_out_bits {
5885         u8         status[0x8];
5886         u8         reserved_at_8[0x18];
5887
5888         u8         syndrome[0x20];
5889
5890         u8         reserved_at_40[0x40];
5891 };
5892
5893 struct mlx5_ifc_destroy_psv_in_bits {
5894         u8         opcode[0x10];
5895         u8         reserved_at_10[0x10];
5896
5897         u8         reserved_at_20[0x10];
5898         u8         op_mod[0x10];
5899
5900         u8         reserved_at_40[0x8];
5901         u8         psvn[0x18];
5902
5903         u8         reserved_at_60[0x20];
5904 };
5905
5906 struct mlx5_ifc_destroy_mkey_out_bits {
5907         u8         status[0x8];
5908         u8         reserved_at_8[0x18];
5909
5910         u8         syndrome[0x20];
5911
5912         u8         reserved_at_40[0x40];
5913 };
5914
5915 struct mlx5_ifc_destroy_mkey_in_bits {
5916         u8         opcode[0x10];
5917         u8         reserved_at_10[0x10];
5918
5919         u8         reserved_at_20[0x10];
5920         u8         op_mod[0x10];
5921
5922         u8         reserved_at_40[0x8];
5923         u8         mkey_index[0x18];
5924
5925         u8         reserved_at_60[0x20];
5926 };
5927
5928 struct mlx5_ifc_destroy_flow_table_out_bits {
5929         u8         status[0x8];
5930         u8         reserved_at_8[0x18];
5931
5932         u8         syndrome[0x20];
5933
5934         u8         reserved_at_40[0x40];
5935 };
5936
5937 struct mlx5_ifc_destroy_flow_table_in_bits {
5938         u8         opcode[0x10];
5939         u8         reserved_at_10[0x10];
5940
5941         u8         reserved_at_20[0x10];
5942         u8         op_mod[0x10];
5943
5944         u8         other_vport[0x1];
5945         u8         reserved_at_41[0xf];
5946         u8         vport_number[0x10];
5947
5948         u8         reserved_at_60[0x20];
5949
5950         u8         table_type[0x8];
5951         u8         reserved_at_88[0x18];
5952
5953         u8         reserved_at_a0[0x8];
5954         u8         table_id[0x18];
5955
5956         u8         reserved_at_c0[0x140];
5957 };
5958
5959 struct mlx5_ifc_destroy_flow_group_out_bits {
5960         u8         status[0x8];
5961         u8         reserved_at_8[0x18];
5962
5963         u8         syndrome[0x20];
5964
5965         u8         reserved_at_40[0x40];
5966 };
5967
5968 struct mlx5_ifc_destroy_flow_group_in_bits {
5969         u8         opcode[0x10];
5970         u8         reserved_at_10[0x10];
5971
5972         u8         reserved_at_20[0x10];
5973         u8         op_mod[0x10];
5974
5975         u8         other_vport[0x1];
5976         u8         reserved_at_41[0xf];
5977         u8         vport_number[0x10];
5978
5979         u8         reserved_at_60[0x20];
5980
5981         u8         table_type[0x8];
5982         u8         reserved_at_88[0x18];
5983
5984         u8         reserved_at_a0[0x8];
5985         u8         table_id[0x18];
5986
5987         u8         group_id[0x20];
5988
5989         u8         reserved_at_e0[0x120];
5990 };
5991
5992 struct mlx5_ifc_destroy_eq_out_bits {
5993         u8         status[0x8];
5994         u8         reserved_at_8[0x18];
5995
5996         u8         syndrome[0x20];
5997
5998         u8         reserved_at_40[0x40];
5999 };
6000
6001 struct mlx5_ifc_destroy_eq_in_bits {
6002         u8         opcode[0x10];
6003         u8         reserved_at_10[0x10];
6004
6005         u8         reserved_at_20[0x10];
6006         u8         op_mod[0x10];
6007
6008         u8         reserved_at_40[0x18];
6009         u8         eq_number[0x8];
6010
6011         u8         reserved_at_60[0x20];
6012 };
6013
6014 struct mlx5_ifc_destroy_dct_out_bits {
6015         u8         status[0x8];
6016         u8         reserved_at_8[0x18];
6017
6018         u8         syndrome[0x20];
6019
6020         u8         reserved_at_40[0x40];
6021 };
6022
6023 struct mlx5_ifc_destroy_dct_in_bits {
6024         u8         opcode[0x10];
6025         u8         reserved_at_10[0x10];
6026
6027         u8         reserved_at_20[0x10];
6028         u8         op_mod[0x10];
6029
6030         u8         reserved_at_40[0x8];
6031         u8         dctn[0x18];
6032
6033         u8         reserved_at_60[0x20];
6034 };
6035
6036 struct mlx5_ifc_destroy_cq_out_bits {
6037         u8         status[0x8];
6038         u8         reserved_at_8[0x18];
6039
6040         u8         syndrome[0x20];
6041
6042         u8         reserved_at_40[0x40];
6043 };
6044
6045 struct mlx5_ifc_destroy_cq_in_bits {
6046         u8         opcode[0x10];
6047         u8         reserved_at_10[0x10];
6048
6049         u8         reserved_at_20[0x10];
6050         u8         op_mod[0x10];
6051
6052         u8         reserved_at_40[0x8];
6053         u8         cqn[0x18];
6054
6055         u8         reserved_at_60[0x20];
6056 };
6057
6058 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6059         u8         status[0x8];
6060         u8         reserved_at_8[0x18];
6061
6062         u8         syndrome[0x20];
6063
6064         u8         reserved_at_40[0x40];
6065 };
6066
6067 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6068         u8         opcode[0x10];
6069         u8         reserved_at_10[0x10];
6070
6071         u8         reserved_at_20[0x10];
6072         u8         op_mod[0x10];
6073
6074         u8         reserved_at_40[0x20];
6075
6076         u8         reserved_at_60[0x10];
6077         u8         vxlan_udp_port[0x10];
6078 };
6079
6080 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6081         u8         status[0x8];
6082         u8         reserved_at_8[0x18];
6083
6084         u8         syndrome[0x20];
6085
6086         u8         reserved_at_40[0x40];
6087 };
6088
6089 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6090         u8         opcode[0x10];
6091         u8         reserved_at_10[0x10];
6092
6093         u8         reserved_at_20[0x10];
6094         u8         op_mod[0x10];
6095
6096         u8         reserved_at_40[0x60];
6097
6098         u8         reserved_at_a0[0x8];
6099         u8         table_index[0x18];
6100
6101         u8         reserved_at_c0[0x140];
6102 };
6103
6104 struct mlx5_ifc_delete_fte_out_bits {
6105         u8         status[0x8];
6106         u8         reserved_at_8[0x18];
6107
6108         u8         syndrome[0x20];
6109
6110         u8         reserved_at_40[0x40];
6111 };
6112
6113 struct mlx5_ifc_delete_fte_in_bits {
6114         u8         opcode[0x10];
6115         u8         reserved_at_10[0x10];
6116
6117         u8         reserved_at_20[0x10];
6118         u8         op_mod[0x10];
6119
6120         u8         other_vport[0x1];
6121         u8         reserved_at_41[0xf];
6122         u8         vport_number[0x10];
6123
6124         u8         reserved_at_60[0x20];
6125
6126         u8         table_type[0x8];
6127         u8         reserved_at_88[0x18];
6128
6129         u8         reserved_at_a0[0x8];
6130         u8         table_id[0x18];
6131
6132         u8         reserved_at_c0[0x40];
6133
6134         u8         flow_index[0x20];
6135
6136         u8         reserved_at_120[0xe0];
6137 };
6138
6139 struct mlx5_ifc_dealloc_xrcd_out_bits {
6140         u8         status[0x8];
6141         u8         reserved_at_8[0x18];
6142
6143         u8         syndrome[0x20];
6144
6145         u8         reserved_at_40[0x40];
6146 };
6147
6148 struct mlx5_ifc_dealloc_xrcd_in_bits {
6149         u8         opcode[0x10];
6150         u8         reserved_at_10[0x10];
6151
6152         u8         reserved_at_20[0x10];
6153         u8         op_mod[0x10];
6154
6155         u8         reserved_at_40[0x8];
6156         u8         xrcd[0x18];
6157
6158         u8         reserved_at_60[0x20];
6159 };
6160
6161 struct mlx5_ifc_dealloc_uar_out_bits {
6162         u8         status[0x8];
6163         u8         reserved_at_8[0x18];
6164
6165         u8         syndrome[0x20];
6166
6167         u8         reserved_at_40[0x40];
6168 };
6169
6170 struct mlx5_ifc_dealloc_uar_in_bits {
6171         u8         opcode[0x10];
6172         u8         reserved_at_10[0x10];
6173
6174         u8         reserved_at_20[0x10];
6175         u8         op_mod[0x10];
6176
6177         u8         reserved_at_40[0x8];
6178         u8         uar[0x18];
6179
6180         u8         reserved_at_60[0x20];
6181 };
6182
6183 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6184         u8         status[0x8];
6185         u8         reserved_at_8[0x18];
6186
6187         u8         syndrome[0x20];
6188
6189         u8         reserved_at_40[0x40];
6190 };
6191
6192 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6193         u8         opcode[0x10];
6194         u8         reserved_at_10[0x10];
6195
6196         u8         reserved_at_20[0x10];
6197         u8         op_mod[0x10];
6198
6199         u8         reserved_at_40[0x8];
6200         u8         transport_domain[0x18];
6201
6202         u8         reserved_at_60[0x20];
6203 };
6204
6205 struct mlx5_ifc_dealloc_q_counter_out_bits {
6206         u8         status[0x8];
6207         u8         reserved_at_8[0x18];
6208
6209         u8         syndrome[0x20];
6210
6211         u8         reserved_at_40[0x40];
6212 };
6213
6214 struct mlx5_ifc_dealloc_q_counter_in_bits {
6215         u8         opcode[0x10];
6216         u8         reserved_at_10[0x10];
6217
6218         u8         reserved_at_20[0x10];
6219         u8         op_mod[0x10];
6220
6221         u8         reserved_at_40[0x18];
6222         u8         counter_set_id[0x8];
6223
6224         u8         reserved_at_60[0x20];
6225 };
6226
6227 struct mlx5_ifc_dealloc_pd_out_bits {
6228         u8         status[0x8];
6229         u8         reserved_at_8[0x18];
6230
6231         u8         syndrome[0x20];
6232
6233         u8         reserved_at_40[0x40];
6234 };
6235
6236 struct mlx5_ifc_dealloc_pd_in_bits {
6237         u8         opcode[0x10];
6238         u8         reserved_at_10[0x10];
6239
6240         u8         reserved_at_20[0x10];
6241         u8         op_mod[0x10];
6242
6243         u8         reserved_at_40[0x8];
6244         u8         pd[0x18];
6245
6246         u8         reserved_at_60[0x20];
6247 };
6248
6249 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6250         u8         status[0x8];
6251         u8         reserved_at_8[0x18];
6252
6253         u8         syndrome[0x20];
6254
6255         u8         reserved_at_40[0x40];
6256 };
6257
6258 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6259         u8         opcode[0x10];
6260         u8         reserved_at_10[0x10];
6261
6262         u8         reserved_at_20[0x10];
6263         u8         op_mod[0x10];
6264
6265         u8         reserved_at_40[0x10];
6266         u8         flow_counter_id[0x10];
6267
6268         u8         reserved_at_60[0x20];
6269 };
6270
6271 struct mlx5_ifc_create_xrq_out_bits {
6272         u8         status[0x8];
6273         u8         reserved_at_8[0x18];
6274
6275         u8         syndrome[0x20];
6276
6277         u8         reserved_at_40[0x8];
6278         u8         xrqn[0x18];
6279
6280         u8         reserved_at_60[0x20];
6281 };
6282
6283 struct mlx5_ifc_create_xrq_in_bits {
6284         u8         opcode[0x10];
6285         u8         reserved_at_10[0x10];
6286
6287         u8         reserved_at_20[0x10];
6288         u8         op_mod[0x10];
6289
6290         u8         reserved_at_40[0x40];
6291
6292         struct mlx5_ifc_xrqc_bits xrq_context;
6293 };
6294
6295 struct mlx5_ifc_create_xrc_srq_out_bits {
6296         u8         status[0x8];
6297         u8         reserved_at_8[0x18];
6298
6299         u8         syndrome[0x20];
6300
6301         u8         reserved_at_40[0x8];
6302         u8         xrc_srqn[0x18];
6303
6304         u8         reserved_at_60[0x20];
6305 };
6306
6307 struct mlx5_ifc_create_xrc_srq_in_bits {
6308         u8         opcode[0x10];
6309         u8         reserved_at_10[0x10];
6310
6311         u8         reserved_at_20[0x10];
6312         u8         op_mod[0x10];
6313
6314         u8         reserved_at_40[0x40];
6315
6316         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6317
6318         u8         reserved_at_280[0x600];
6319
6320         u8         pas[0][0x40];
6321 };
6322
6323 struct mlx5_ifc_create_tis_out_bits {
6324         u8         status[0x8];
6325         u8         reserved_at_8[0x18];
6326
6327         u8         syndrome[0x20];
6328
6329         u8         reserved_at_40[0x8];
6330         u8         tisn[0x18];
6331
6332         u8         reserved_at_60[0x20];
6333 };
6334
6335 struct mlx5_ifc_create_tis_in_bits {
6336         u8         opcode[0x10];
6337         u8         reserved_at_10[0x10];
6338
6339         u8         reserved_at_20[0x10];
6340         u8         op_mod[0x10];
6341
6342         u8         reserved_at_40[0xc0];
6343
6344         struct mlx5_ifc_tisc_bits ctx;
6345 };
6346
6347 struct mlx5_ifc_create_tir_out_bits {
6348         u8         status[0x8];
6349         u8         reserved_at_8[0x18];
6350
6351         u8         syndrome[0x20];
6352
6353         u8         reserved_at_40[0x8];
6354         u8         tirn[0x18];
6355
6356         u8         reserved_at_60[0x20];
6357 };
6358
6359 struct mlx5_ifc_create_tir_in_bits {
6360         u8         opcode[0x10];
6361         u8         reserved_at_10[0x10];
6362
6363         u8         reserved_at_20[0x10];
6364         u8         op_mod[0x10];
6365
6366         u8         reserved_at_40[0xc0];
6367
6368         struct mlx5_ifc_tirc_bits ctx;
6369 };
6370
6371 struct mlx5_ifc_create_srq_out_bits {
6372         u8         status[0x8];
6373         u8         reserved_at_8[0x18];
6374
6375         u8         syndrome[0x20];
6376
6377         u8         reserved_at_40[0x8];
6378         u8         srqn[0x18];
6379
6380         u8         reserved_at_60[0x20];
6381 };
6382
6383 struct mlx5_ifc_create_srq_in_bits {
6384         u8         opcode[0x10];
6385         u8         reserved_at_10[0x10];
6386
6387         u8         reserved_at_20[0x10];
6388         u8         op_mod[0x10];
6389
6390         u8         reserved_at_40[0x40];
6391
6392         struct mlx5_ifc_srqc_bits srq_context_entry;
6393
6394         u8         reserved_at_280[0x600];
6395
6396         u8         pas[0][0x40];
6397 };
6398
6399 struct mlx5_ifc_create_sq_out_bits {
6400         u8         status[0x8];
6401         u8         reserved_at_8[0x18];
6402
6403         u8         syndrome[0x20];
6404
6405         u8         reserved_at_40[0x8];
6406         u8         sqn[0x18];
6407
6408         u8         reserved_at_60[0x20];
6409 };
6410
6411 struct mlx5_ifc_create_sq_in_bits {
6412         u8         opcode[0x10];
6413         u8         reserved_at_10[0x10];
6414
6415         u8         reserved_at_20[0x10];
6416         u8         op_mod[0x10];
6417
6418         u8         reserved_at_40[0xc0];
6419
6420         struct mlx5_ifc_sqc_bits ctx;
6421 };
6422
6423 struct mlx5_ifc_create_scheduling_element_out_bits {
6424         u8         status[0x8];
6425         u8         reserved_at_8[0x18];
6426
6427         u8         syndrome[0x20];
6428
6429         u8         reserved_at_40[0x40];
6430
6431         u8         scheduling_element_id[0x20];
6432
6433         u8         reserved_at_a0[0x160];
6434 };
6435
6436 struct mlx5_ifc_create_scheduling_element_in_bits {
6437         u8         opcode[0x10];
6438         u8         reserved_at_10[0x10];
6439
6440         u8         reserved_at_20[0x10];
6441         u8         op_mod[0x10];
6442
6443         u8         scheduling_hierarchy[0x8];
6444         u8         reserved_at_48[0x18];
6445
6446         u8         reserved_at_60[0xa0];
6447
6448         struct mlx5_ifc_scheduling_context_bits scheduling_context;
6449
6450         u8         reserved_at_300[0x100];
6451 };
6452
6453 struct mlx5_ifc_create_rqt_out_bits {
6454         u8         status[0x8];
6455         u8         reserved_at_8[0x18];
6456
6457         u8         syndrome[0x20];
6458
6459         u8         reserved_at_40[0x8];
6460         u8         rqtn[0x18];
6461
6462         u8         reserved_at_60[0x20];
6463 };
6464
6465 struct mlx5_ifc_create_rqt_in_bits {
6466         u8         opcode[0x10];
6467         u8         reserved_at_10[0x10];
6468
6469         u8         reserved_at_20[0x10];
6470         u8         op_mod[0x10];
6471
6472         u8         reserved_at_40[0xc0];
6473
6474         struct mlx5_ifc_rqtc_bits rqt_context;
6475 };
6476
6477 struct mlx5_ifc_create_rq_out_bits {
6478         u8         status[0x8];
6479         u8         reserved_at_8[0x18];
6480
6481         u8         syndrome[0x20];
6482
6483         u8         reserved_at_40[0x8];
6484         u8         rqn[0x18];
6485
6486         u8         reserved_at_60[0x20];
6487 };
6488
6489 struct mlx5_ifc_create_rq_in_bits {
6490         u8         opcode[0x10];
6491         u8         reserved_at_10[0x10];
6492
6493         u8         reserved_at_20[0x10];
6494         u8         op_mod[0x10];
6495
6496         u8         reserved_at_40[0xc0];
6497
6498         struct mlx5_ifc_rqc_bits ctx;
6499 };
6500
6501 struct mlx5_ifc_create_rmp_out_bits {
6502         u8         status[0x8];
6503         u8         reserved_at_8[0x18];
6504
6505         u8         syndrome[0x20];
6506
6507         u8         reserved_at_40[0x8];
6508         u8         rmpn[0x18];
6509
6510         u8         reserved_at_60[0x20];
6511 };
6512
6513 struct mlx5_ifc_create_rmp_in_bits {
6514         u8         opcode[0x10];
6515         u8         reserved_at_10[0x10];
6516
6517         u8         reserved_at_20[0x10];
6518         u8         op_mod[0x10];
6519
6520         u8         reserved_at_40[0xc0];
6521
6522         struct mlx5_ifc_rmpc_bits ctx;
6523 };
6524
6525 struct mlx5_ifc_create_qp_out_bits {
6526         u8         status[0x8];
6527         u8         reserved_at_8[0x18];
6528
6529         u8         syndrome[0x20];
6530
6531         u8         reserved_at_40[0x8];
6532         u8         qpn[0x18];
6533
6534         u8         reserved_at_60[0x20];
6535 };
6536
6537 struct mlx5_ifc_create_qp_in_bits {
6538         u8         opcode[0x10];
6539         u8         reserved_at_10[0x10];
6540
6541         u8         reserved_at_20[0x10];
6542         u8         op_mod[0x10];
6543
6544         u8         reserved_at_40[0x40];
6545
6546         u8         opt_param_mask[0x20];
6547
6548         u8         reserved_at_a0[0x20];
6549
6550         struct mlx5_ifc_qpc_bits qpc;
6551
6552         u8         reserved_at_800[0x80];
6553
6554         u8         pas[0][0x40];
6555 };
6556
6557 struct mlx5_ifc_create_psv_out_bits {
6558         u8         status[0x8];
6559         u8         reserved_at_8[0x18];
6560
6561         u8         syndrome[0x20];
6562
6563         u8         reserved_at_40[0x40];
6564
6565         u8         reserved_at_80[0x8];
6566         u8         psv0_index[0x18];
6567
6568         u8         reserved_at_a0[0x8];
6569         u8         psv1_index[0x18];
6570
6571         u8         reserved_at_c0[0x8];
6572         u8         psv2_index[0x18];
6573
6574         u8         reserved_at_e0[0x8];
6575         u8         psv3_index[0x18];
6576 };
6577
6578 struct mlx5_ifc_create_psv_in_bits {
6579         u8         opcode[0x10];
6580         u8         reserved_at_10[0x10];
6581
6582         u8         reserved_at_20[0x10];
6583         u8         op_mod[0x10];
6584
6585         u8         num_psv[0x4];
6586         u8         reserved_at_44[0x4];
6587         u8         pd[0x18];
6588
6589         u8         reserved_at_60[0x20];
6590 };
6591
6592 struct mlx5_ifc_create_mkey_out_bits {
6593         u8         status[0x8];
6594         u8         reserved_at_8[0x18];
6595
6596         u8         syndrome[0x20];
6597
6598         u8         reserved_at_40[0x8];
6599         u8         mkey_index[0x18];
6600
6601         u8         reserved_at_60[0x20];
6602 };
6603
6604 struct mlx5_ifc_create_mkey_in_bits {
6605         u8         opcode[0x10];
6606         u8         reserved_at_10[0x10];
6607
6608         u8         reserved_at_20[0x10];
6609         u8         op_mod[0x10];
6610
6611         u8         reserved_at_40[0x20];
6612
6613         u8         pg_access[0x1];
6614         u8         reserved_at_61[0x1f];
6615
6616         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6617
6618         u8         reserved_at_280[0x80];
6619
6620         u8         translations_octword_actual_size[0x20];
6621
6622         u8         reserved_at_320[0x560];
6623
6624         u8         klm_pas_mtt[0][0x20];
6625 };
6626
6627 struct mlx5_ifc_create_flow_table_out_bits {
6628         u8         status[0x8];
6629         u8         reserved_at_8[0x18];
6630
6631         u8         syndrome[0x20];
6632
6633         u8         reserved_at_40[0x8];
6634         u8         table_id[0x18];
6635
6636         u8         reserved_at_60[0x20];
6637 };
6638
6639 struct mlx5_ifc_flow_table_context_bits {
6640         u8         encap_en[0x1];
6641         u8         decap_en[0x1];
6642         u8         reserved_at_2[0x2];
6643         u8         table_miss_action[0x4];
6644         u8         level[0x8];
6645         u8         reserved_at_10[0x8];
6646         u8         log_size[0x8];
6647
6648         u8         reserved_at_20[0x8];
6649         u8         table_miss_id[0x18];
6650
6651         u8         reserved_at_40[0x8];
6652         u8         lag_master_next_table_id[0x18];
6653
6654         u8         reserved_at_60[0xe0];
6655 };
6656
6657 struct mlx5_ifc_create_flow_table_in_bits {
6658         u8         opcode[0x10];
6659         u8         reserved_at_10[0x10];
6660
6661         u8         reserved_at_20[0x10];
6662         u8         op_mod[0x10];
6663
6664         u8         other_vport[0x1];
6665         u8         reserved_at_41[0xf];
6666         u8         vport_number[0x10];
6667
6668         u8         reserved_at_60[0x20];
6669
6670         u8         table_type[0x8];
6671         u8         reserved_at_88[0x18];
6672
6673         u8         reserved_at_a0[0x20];
6674
6675         struct mlx5_ifc_flow_table_context_bits flow_table_context;
6676 };
6677
6678 struct mlx5_ifc_create_flow_group_out_bits {
6679         u8         status[0x8];
6680         u8         reserved_at_8[0x18];
6681
6682         u8         syndrome[0x20];
6683
6684         u8         reserved_at_40[0x8];
6685         u8         group_id[0x18];
6686
6687         u8         reserved_at_60[0x20];
6688 };
6689
6690 enum {
6691         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
6692         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
6693         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
6694 };
6695
6696 struct mlx5_ifc_create_flow_group_in_bits {
6697         u8         opcode[0x10];
6698         u8         reserved_at_10[0x10];
6699
6700         u8         reserved_at_20[0x10];
6701         u8         op_mod[0x10];
6702
6703         u8         other_vport[0x1];
6704         u8         reserved_at_41[0xf];
6705         u8         vport_number[0x10];
6706
6707         u8         reserved_at_60[0x20];
6708
6709         u8         table_type[0x8];
6710         u8         reserved_at_88[0x18];
6711
6712         u8         reserved_at_a0[0x8];
6713         u8         table_id[0x18];
6714
6715         u8         reserved_at_c0[0x20];
6716
6717         u8         start_flow_index[0x20];
6718
6719         u8         reserved_at_100[0x20];
6720
6721         u8         end_flow_index[0x20];
6722
6723         u8         reserved_at_140[0xa0];
6724
6725         u8         reserved_at_1e0[0x18];
6726         u8         match_criteria_enable[0x8];
6727
6728         struct mlx5_ifc_fte_match_param_bits match_criteria;
6729
6730         u8         reserved_at_1200[0xe00];
6731 };
6732
6733 struct mlx5_ifc_create_eq_out_bits {
6734         u8         status[0x8];
6735         u8         reserved_at_8[0x18];
6736
6737         u8         syndrome[0x20];
6738
6739         u8         reserved_at_40[0x18];
6740         u8         eq_number[0x8];
6741
6742         u8         reserved_at_60[0x20];
6743 };
6744
6745 struct mlx5_ifc_create_eq_in_bits {
6746         u8         opcode[0x10];
6747         u8         reserved_at_10[0x10];
6748
6749         u8         reserved_at_20[0x10];
6750         u8         op_mod[0x10];
6751
6752         u8         reserved_at_40[0x40];
6753
6754         struct mlx5_ifc_eqc_bits eq_context_entry;
6755
6756         u8         reserved_at_280[0x40];
6757
6758         u8         event_bitmask[0x40];
6759
6760         u8         reserved_at_300[0x580];
6761
6762         u8         pas[0][0x40];
6763 };
6764
6765 struct mlx5_ifc_create_dct_out_bits {
6766         u8         status[0x8];
6767         u8         reserved_at_8[0x18];
6768
6769         u8         syndrome[0x20];
6770
6771         u8         reserved_at_40[0x8];
6772         u8         dctn[0x18];
6773
6774         u8         reserved_at_60[0x20];
6775 };
6776
6777 struct mlx5_ifc_create_dct_in_bits {
6778         u8         opcode[0x10];
6779         u8         reserved_at_10[0x10];
6780
6781         u8         reserved_at_20[0x10];
6782         u8         op_mod[0x10];
6783
6784         u8         reserved_at_40[0x40];
6785
6786         struct mlx5_ifc_dctc_bits dct_context_entry;
6787
6788         u8         reserved_at_280[0x180];
6789 };
6790
6791 struct mlx5_ifc_create_cq_out_bits {
6792         u8         status[0x8];
6793         u8         reserved_at_8[0x18];
6794
6795         u8         syndrome[0x20];
6796
6797         u8         reserved_at_40[0x8];
6798         u8         cqn[0x18];
6799
6800         u8         reserved_at_60[0x20];
6801 };
6802
6803 struct mlx5_ifc_create_cq_in_bits {
6804         u8         opcode[0x10];
6805         u8         reserved_at_10[0x10];
6806
6807         u8         reserved_at_20[0x10];
6808         u8         op_mod[0x10];
6809
6810         u8         reserved_at_40[0x40];
6811
6812         struct mlx5_ifc_cqc_bits cq_context;
6813
6814         u8         reserved_at_280[0x600];
6815
6816         u8         pas[0][0x40];
6817 };
6818
6819 struct mlx5_ifc_config_int_moderation_out_bits {
6820         u8         status[0x8];
6821         u8         reserved_at_8[0x18];
6822
6823         u8         syndrome[0x20];
6824
6825         u8         reserved_at_40[0x4];
6826         u8         min_delay[0xc];
6827         u8         int_vector[0x10];
6828
6829         u8         reserved_at_60[0x20];
6830 };
6831
6832 enum {
6833         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
6834         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
6835 };
6836
6837 struct mlx5_ifc_config_int_moderation_in_bits {
6838         u8         opcode[0x10];
6839         u8         reserved_at_10[0x10];
6840
6841         u8         reserved_at_20[0x10];
6842         u8         op_mod[0x10];
6843
6844         u8         reserved_at_40[0x4];
6845         u8         min_delay[0xc];
6846         u8         int_vector[0x10];
6847
6848         u8         reserved_at_60[0x20];
6849 };
6850
6851 struct mlx5_ifc_attach_to_mcg_out_bits {
6852         u8         status[0x8];
6853         u8         reserved_at_8[0x18];
6854
6855         u8         syndrome[0x20];
6856
6857         u8         reserved_at_40[0x40];
6858 };
6859
6860 struct mlx5_ifc_attach_to_mcg_in_bits {
6861         u8         opcode[0x10];
6862         u8         reserved_at_10[0x10];
6863
6864         u8         reserved_at_20[0x10];
6865         u8         op_mod[0x10];
6866
6867         u8         reserved_at_40[0x8];
6868         u8         qpn[0x18];
6869
6870         u8         reserved_at_60[0x20];
6871
6872         u8         multicast_gid[16][0x8];
6873 };
6874
6875 struct mlx5_ifc_arm_xrq_out_bits {
6876         u8         status[0x8];
6877         u8         reserved_at_8[0x18];
6878
6879         u8         syndrome[0x20];
6880
6881         u8         reserved_at_40[0x40];
6882 };
6883
6884 struct mlx5_ifc_arm_xrq_in_bits {
6885         u8         opcode[0x10];
6886         u8         reserved_at_10[0x10];
6887
6888         u8         reserved_at_20[0x10];
6889         u8         op_mod[0x10];
6890
6891         u8         reserved_at_40[0x8];
6892         u8         xrqn[0x18];
6893
6894         u8         reserved_at_60[0x10];
6895         u8         lwm[0x10];
6896 };
6897
6898 struct mlx5_ifc_arm_xrc_srq_out_bits {
6899         u8         status[0x8];
6900         u8         reserved_at_8[0x18];
6901
6902         u8         syndrome[0x20];
6903
6904         u8         reserved_at_40[0x40];
6905 };
6906
6907 enum {
6908         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
6909 };
6910
6911 struct mlx5_ifc_arm_xrc_srq_in_bits {
6912         u8         opcode[0x10];
6913         u8         reserved_at_10[0x10];
6914
6915         u8         reserved_at_20[0x10];
6916         u8         op_mod[0x10];
6917
6918         u8         reserved_at_40[0x8];
6919         u8         xrc_srqn[0x18];
6920
6921         u8         reserved_at_60[0x10];
6922         u8         lwm[0x10];
6923 };
6924
6925 struct mlx5_ifc_arm_rq_out_bits {
6926         u8         status[0x8];
6927         u8         reserved_at_8[0x18];
6928
6929         u8         syndrome[0x20];
6930
6931         u8         reserved_at_40[0x40];
6932 };
6933
6934 enum {
6935         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6936         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
6937 };
6938
6939 struct mlx5_ifc_arm_rq_in_bits {
6940         u8         opcode[0x10];
6941         u8         reserved_at_10[0x10];
6942
6943         u8         reserved_at_20[0x10];
6944         u8         op_mod[0x10];
6945
6946         u8         reserved_at_40[0x8];
6947         u8         srq_number[0x18];
6948
6949         u8         reserved_at_60[0x10];
6950         u8         lwm[0x10];
6951 };
6952
6953 struct mlx5_ifc_arm_dct_out_bits {
6954         u8         status[0x8];
6955         u8         reserved_at_8[0x18];
6956
6957         u8         syndrome[0x20];
6958
6959         u8         reserved_at_40[0x40];
6960 };
6961
6962 struct mlx5_ifc_arm_dct_in_bits {
6963         u8         opcode[0x10];
6964         u8         reserved_at_10[0x10];
6965
6966         u8         reserved_at_20[0x10];
6967         u8         op_mod[0x10];
6968
6969         u8         reserved_at_40[0x8];
6970         u8         dct_number[0x18];
6971
6972         u8         reserved_at_60[0x20];
6973 };
6974
6975 struct mlx5_ifc_alloc_xrcd_out_bits {
6976         u8         status[0x8];
6977         u8         reserved_at_8[0x18];
6978
6979         u8         syndrome[0x20];
6980
6981         u8         reserved_at_40[0x8];
6982         u8         xrcd[0x18];
6983
6984         u8         reserved_at_60[0x20];
6985 };
6986
6987 struct mlx5_ifc_alloc_xrcd_in_bits {
6988         u8         opcode[0x10];
6989         u8         reserved_at_10[0x10];
6990
6991         u8         reserved_at_20[0x10];
6992         u8         op_mod[0x10];
6993
6994         u8         reserved_at_40[0x40];
6995 };
6996
6997 struct mlx5_ifc_alloc_uar_out_bits {
6998         u8         status[0x8];
6999         u8         reserved_at_8[0x18];
7000
7001         u8         syndrome[0x20];
7002
7003         u8         reserved_at_40[0x8];
7004         u8         uar[0x18];
7005
7006         u8         reserved_at_60[0x20];
7007 };
7008
7009 struct mlx5_ifc_alloc_uar_in_bits {
7010         u8         opcode[0x10];
7011         u8         reserved_at_10[0x10];
7012
7013         u8         reserved_at_20[0x10];
7014         u8         op_mod[0x10];
7015
7016         u8         reserved_at_40[0x40];
7017 };
7018
7019 struct mlx5_ifc_alloc_transport_domain_out_bits {
7020         u8         status[0x8];
7021         u8         reserved_at_8[0x18];
7022
7023         u8         syndrome[0x20];
7024
7025         u8         reserved_at_40[0x8];
7026         u8         transport_domain[0x18];
7027
7028         u8         reserved_at_60[0x20];
7029 };
7030
7031 struct mlx5_ifc_alloc_transport_domain_in_bits {
7032         u8         opcode[0x10];
7033         u8         reserved_at_10[0x10];
7034
7035         u8         reserved_at_20[0x10];
7036         u8         op_mod[0x10];
7037
7038         u8         reserved_at_40[0x40];
7039 };
7040
7041 struct mlx5_ifc_alloc_q_counter_out_bits {
7042         u8         status[0x8];
7043         u8         reserved_at_8[0x18];
7044
7045         u8         syndrome[0x20];
7046
7047         u8         reserved_at_40[0x18];
7048         u8         counter_set_id[0x8];
7049
7050         u8         reserved_at_60[0x20];
7051 };
7052
7053 struct mlx5_ifc_alloc_q_counter_in_bits {
7054         u8         opcode[0x10];
7055         u8         reserved_at_10[0x10];
7056
7057         u8         reserved_at_20[0x10];
7058         u8         op_mod[0x10];
7059
7060         u8         reserved_at_40[0x40];
7061 };
7062
7063 struct mlx5_ifc_alloc_pd_out_bits {
7064         u8         status[0x8];
7065         u8         reserved_at_8[0x18];
7066
7067         u8         syndrome[0x20];
7068
7069         u8         reserved_at_40[0x8];
7070         u8         pd[0x18];
7071
7072         u8         reserved_at_60[0x20];
7073 };
7074
7075 struct mlx5_ifc_alloc_pd_in_bits {
7076         u8         opcode[0x10];
7077         u8         reserved_at_10[0x10];
7078
7079         u8         reserved_at_20[0x10];
7080         u8         op_mod[0x10];
7081
7082         u8         reserved_at_40[0x40];
7083 };
7084
7085 struct mlx5_ifc_alloc_flow_counter_out_bits {
7086         u8         status[0x8];
7087         u8         reserved_at_8[0x18];
7088
7089         u8         syndrome[0x20];
7090
7091         u8         reserved_at_40[0x10];
7092         u8         flow_counter_id[0x10];
7093
7094         u8         reserved_at_60[0x20];
7095 };
7096
7097 struct mlx5_ifc_alloc_flow_counter_in_bits {
7098         u8         opcode[0x10];
7099         u8         reserved_at_10[0x10];
7100
7101         u8         reserved_at_20[0x10];
7102         u8         op_mod[0x10];
7103
7104         u8         reserved_at_40[0x40];
7105 };
7106
7107 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7108         u8         status[0x8];
7109         u8         reserved_at_8[0x18];
7110
7111         u8         syndrome[0x20];
7112
7113         u8         reserved_at_40[0x40];
7114 };
7115
7116 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7117         u8         opcode[0x10];
7118         u8         reserved_at_10[0x10];
7119
7120         u8         reserved_at_20[0x10];
7121         u8         op_mod[0x10];
7122
7123         u8         reserved_at_40[0x20];
7124
7125         u8         reserved_at_60[0x10];
7126         u8         vxlan_udp_port[0x10];
7127 };
7128
7129 struct mlx5_ifc_set_rate_limit_out_bits {
7130         u8         status[0x8];
7131         u8         reserved_at_8[0x18];
7132
7133         u8         syndrome[0x20];
7134
7135         u8         reserved_at_40[0x40];
7136 };
7137
7138 struct mlx5_ifc_set_rate_limit_in_bits {
7139         u8         opcode[0x10];
7140         u8         reserved_at_10[0x10];
7141
7142         u8         reserved_at_20[0x10];
7143         u8         op_mod[0x10];
7144
7145         u8         reserved_at_40[0x10];
7146         u8         rate_limit_index[0x10];
7147
7148         u8         reserved_at_60[0x20];
7149
7150         u8         rate_limit[0x20];
7151 };
7152
7153 struct mlx5_ifc_access_register_out_bits {
7154         u8         status[0x8];
7155         u8         reserved_at_8[0x18];
7156
7157         u8         syndrome[0x20];
7158
7159         u8         reserved_at_40[0x40];
7160
7161         u8         register_data[0][0x20];
7162 };
7163
7164 enum {
7165         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7166         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7167 };
7168
7169 struct mlx5_ifc_access_register_in_bits {
7170         u8         opcode[0x10];
7171         u8         reserved_at_10[0x10];
7172
7173         u8         reserved_at_20[0x10];
7174         u8         op_mod[0x10];
7175
7176         u8         reserved_at_40[0x10];
7177         u8         register_id[0x10];
7178
7179         u8         argument[0x20];
7180
7181         u8         register_data[0][0x20];
7182 };
7183
7184 struct mlx5_ifc_sltp_reg_bits {
7185         u8         status[0x4];
7186         u8         version[0x4];
7187         u8         local_port[0x8];
7188         u8         pnat[0x2];
7189         u8         reserved_at_12[0x2];
7190         u8         lane[0x4];
7191         u8         reserved_at_18[0x8];
7192
7193         u8         reserved_at_20[0x20];
7194
7195         u8         reserved_at_40[0x7];
7196         u8         polarity[0x1];
7197         u8         ob_tap0[0x8];
7198         u8         ob_tap1[0x8];
7199         u8         ob_tap2[0x8];
7200
7201         u8         reserved_at_60[0xc];
7202         u8         ob_preemp_mode[0x4];
7203         u8         ob_reg[0x8];
7204         u8         ob_bias[0x8];
7205
7206         u8         reserved_at_80[0x20];
7207 };
7208
7209 struct mlx5_ifc_slrg_reg_bits {
7210         u8         status[0x4];
7211         u8         version[0x4];
7212         u8         local_port[0x8];
7213         u8         pnat[0x2];
7214         u8         reserved_at_12[0x2];
7215         u8         lane[0x4];
7216         u8         reserved_at_18[0x8];
7217
7218         u8         time_to_link_up[0x10];
7219         u8         reserved_at_30[0xc];
7220         u8         grade_lane_speed[0x4];
7221
7222         u8         grade_version[0x8];
7223         u8         grade[0x18];
7224
7225         u8         reserved_at_60[0x4];
7226         u8         height_grade_type[0x4];
7227         u8         height_grade[0x18];
7228
7229         u8         height_dz[0x10];
7230         u8         height_dv[0x10];
7231
7232         u8         reserved_at_a0[0x10];
7233         u8         height_sigma[0x10];
7234
7235         u8         reserved_at_c0[0x20];
7236
7237         u8         reserved_at_e0[0x4];
7238         u8         phase_grade_type[0x4];
7239         u8         phase_grade[0x18];
7240
7241         u8         reserved_at_100[0x8];
7242         u8         phase_eo_pos[0x8];
7243         u8         reserved_at_110[0x8];
7244         u8         phase_eo_neg[0x8];
7245
7246         u8         ffe_set_tested[0x10];
7247         u8         test_errors_per_lane[0x10];
7248 };
7249
7250 struct mlx5_ifc_pvlc_reg_bits {
7251         u8         reserved_at_0[0x8];
7252         u8         local_port[0x8];
7253         u8         reserved_at_10[0x10];
7254
7255         u8         reserved_at_20[0x1c];
7256         u8         vl_hw_cap[0x4];
7257
7258         u8         reserved_at_40[0x1c];
7259         u8         vl_admin[0x4];
7260
7261         u8         reserved_at_60[0x1c];
7262         u8         vl_operational[0x4];
7263 };
7264
7265 struct mlx5_ifc_pude_reg_bits {
7266         u8         swid[0x8];
7267         u8         local_port[0x8];
7268         u8         reserved_at_10[0x4];
7269         u8         admin_status[0x4];
7270         u8         reserved_at_18[0x4];
7271         u8         oper_status[0x4];
7272
7273         u8         reserved_at_20[0x60];
7274 };
7275
7276 struct mlx5_ifc_ptys_reg_bits {
7277         u8         reserved_at_0[0x1];
7278         u8         an_disable_admin[0x1];
7279         u8         an_disable_cap[0x1];
7280         u8         reserved_at_3[0x5];
7281         u8         local_port[0x8];
7282         u8         reserved_at_10[0xd];
7283         u8         proto_mask[0x3];
7284
7285         u8         an_status[0x4];
7286         u8         reserved_at_24[0x3c];
7287
7288         u8         eth_proto_capability[0x20];
7289
7290         u8         ib_link_width_capability[0x10];
7291         u8         ib_proto_capability[0x10];
7292
7293         u8         reserved_at_a0[0x20];
7294
7295         u8         eth_proto_admin[0x20];
7296
7297         u8         ib_link_width_admin[0x10];
7298         u8         ib_proto_admin[0x10];
7299
7300         u8         reserved_at_100[0x20];
7301
7302         u8         eth_proto_oper[0x20];
7303
7304         u8         ib_link_width_oper[0x10];
7305         u8         ib_proto_oper[0x10];
7306
7307         u8         reserved_at_160[0x1c];
7308         u8         connector_type[0x4];
7309
7310         u8         eth_proto_lp_advertise[0x20];
7311
7312         u8         reserved_at_1a0[0x60];
7313 };
7314
7315 struct mlx5_ifc_mlcr_reg_bits {
7316         u8         reserved_at_0[0x8];
7317         u8         local_port[0x8];
7318         u8         reserved_at_10[0x20];
7319
7320         u8         beacon_duration[0x10];
7321         u8         reserved_at_40[0x10];
7322
7323         u8         beacon_remain[0x10];
7324 };
7325
7326 struct mlx5_ifc_ptas_reg_bits {
7327         u8         reserved_at_0[0x20];
7328
7329         u8         algorithm_options[0x10];
7330         u8         reserved_at_30[0x4];
7331         u8         repetitions_mode[0x4];
7332         u8         num_of_repetitions[0x8];
7333
7334         u8         grade_version[0x8];
7335         u8         height_grade_type[0x4];
7336         u8         phase_grade_type[0x4];
7337         u8         height_grade_weight[0x8];
7338         u8         phase_grade_weight[0x8];
7339
7340         u8         gisim_measure_bits[0x10];
7341         u8         adaptive_tap_measure_bits[0x10];
7342
7343         u8         ber_bath_high_error_threshold[0x10];
7344         u8         ber_bath_mid_error_threshold[0x10];
7345
7346         u8         ber_bath_low_error_threshold[0x10];
7347         u8         one_ratio_high_threshold[0x10];
7348
7349         u8         one_ratio_high_mid_threshold[0x10];
7350         u8         one_ratio_low_mid_threshold[0x10];
7351
7352         u8         one_ratio_low_threshold[0x10];
7353         u8         ndeo_error_threshold[0x10];
7354
7355         u8         mixer_offset_step_size[0x10];
7356         u8         reserved_at_110[0x8];
7357         u8         mix90_phase_for_voltage_bath[0x8];
7358
7359         u8         mixer_offset_start[0x10];
7360         u8         mixer_offset_end[0x10];
7361
7362         u8         reserved_at_140[0x15];
7363         u8         ber_test_time[0xb];
7364 };
7365
7366 struct mlx5_ifc_pspa_reg_bits {
7367         u8         swid[0x8];
7368         u8         local_port[0x8];
7369         u8         sub_port[0x8];
7370         u8         reserved_at_18[0x8];
7371
7372         u8         reserved_at_20[0x20];
7373 };
7374
7375 struct mlx5_ifc_pqdr_reg_bits {
7376         u8         reserved_at_0[0x8];
7377         u8         local_port[0x8];
7378         u8         reserved_at_10[0x5];
7379         u8         prio[0x3];
7380         u8         reserved_at_18[0x6];
7381         u8         mode[0x2];
7382
7383         u8         reserved_at_20[0x20];
7384
7385         u8         reserved_at_40[0x10];
7386         u8         min_threshold[0x10];
7387
7388         u8         reserved_at_60[0x10];
7389         u8         max_threshold[0x10];
7390
7391         u8         reserved_at_80[0x10];
7392         u8         mark_probability_denominator[0x10];
7393
7394         u8         reserved_at_a0[0x60];
7395 };
7396
7397 struct mlx5_ifc_ppsc_reg_bits {
7398         u8         reserved_at_0[0x8];
7399         u8         local_port[0x8];
7400         u8         reserved_at_10[0x10];
7401
7402         u8         reserved_at_20[0x60];
7403
7404         u8         reserved_at_80[0x1c];
7405         u8         wrps_admin[0x4];
7406
7407         u8         reserved_at_a0[0x1c];
7408         u8         wrps_status[0x4];
7409
7410         u8         reserved_at_c0[0x8];
7411         u8         up_threshold[0x8];
7412         u8         reserved_at_d0[0x8];
7413         u8         down_threshold[0x8];
7414
7415         u8         reserved_at_e0[0x20];
7416
7417         u8         reserved_at_100[0x1c];
7418         u8         srps_admin[0x4];
7419
7420         u8         reserved_at_120[0x1c];
7421         u8         srps_status[0x4];
7422
7423         u8         reserved_at_140[0x40];
7424 };
7425
7426 struct mlx5_ifc_pplr_reg_bits {
7427         u8         reserved_at_0[0x8];
7428         u8         local_port[0x8];
7429         u8         reserved_at_10[0x10];
7430
7431         u8         reserved_at_20[0x8];
7432         u8         lb_cap[0x8];
7433         u8         reserved_at_30[0x8];
7434         u8         lb_en[0x8];
7435 };
7436
7437 struct mlx5_ifc_pplm_reg_bits {
7438         u8         reserved_at_0[0x8];
7439         u8         local_port[0x8];
7440         u8         reserved_at_10[0x10];
7441
7442         u8         reserved_at_20[0x20];
7443
7444         u8         port_profile_mode[0x8];
7445         u8         static_port_profile[0x8];
7446         u8         active_port_profile[0x8];
7447         u8         reserved_at_58[0x8];
7448
7449         u8         retransmission_active[0x8];
7450         u8         fec_mode_active[0x18];
7451
7452         u8         reserved_at_80[0x20];
7453 };
7454
7455 struct mlx5_ifc_ppcnt_reg_bits {
7456         u8         swid[0x8];
7457         u8         local_port[0x8];
7458         u8         pnat[0x2];
7459         u8         reserved_at_12[0x8];
7460         u8         grp[0x6];
7461
7462         u8         clr[0x1];
7463         u8         reserved_at_21[0x1c];
7464         u8         prio_tc[0x3];
7465
7466         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7467 };
7468
7469 struct mlx5_ifc_mpcnt_reg_bits {
7470         u8         reserved_at_0[0x8];
7471         u8         pcie_index[0x8];
7472         u8         reserved_at_10[0xa];
7473         u8         grp[0x6];
7474
7475         u8         clr[0x1];
7476         u8         reserved_at_21[0x1f];
7477
7478         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7479 };
7480
7481 struct mlx5_ifc_ppad_reg_bits {
7482         u8         reserved_at_0[0x3];
7483         u8         single_mac[0x1];
7484         u8         reserved_at_4[0x4];
7485         u8         local_port[0x8];
7486         u8         mac_47_32[0x10];
7487
7488         u8         mac_31_0[0x20];
7489
7490         u8         reserved_at_40[0x40];
7491 };
7492
7493 struct mlx5_ifc_pmtu_reg_bits {
7494         u8         reserved_at_0[0x8];
7495         u8         local_port[0x8];
7496         u8         reserved_at_10[0x10];
7497
7498         u8         max_mtu[0x10];
7499         u8         reserved_at_30[0x10];
7500
7501         u8         admin_mtu[0x10];
7502         u8         reserved_at_50[0x10];
7503
7504         u8         oper_mtu[0x10];
7505         u8         reserved_at_70[0x10];
7506 };
7507
7508 struct mlx5_ifc_pmpr_reg_bits {
7509         u8         reserved_at_0[0x8];
7510         u8         module[0x8];
7511         u8         reserved_at_10[0x10];
7512
7513         u8         reserved_at_20[0x18];
7514         u8         attenuation_5g[0x8];
7515
7516         u8         reserved_at_40[0x18];
7517         u8         attenuation_7g[0x8];
7518
7519         u8         reserved_at_60[0x18];
7520         u8         attenuation_12g[0x8];
7521 };
7522
7523 struct mlx5_ifc_pmpe_reg_bits {
7524         u8         reserved_at_0[0x8];
7525         u8         module[0x8];
7526         u8         reserved_at_10[0xc];
7527         u8         module_status[0x4];
7528
7529         u8         reserved_at_20[0x60];
7530 };
7531
7532 struct mlx5_ifc_pmpc_reg_bits {
7533         u8         module_state_updated[32][0x8];
7534 };
7535
7536 struct mlx5_ifc_pmlpn_reg_bits {
7537         u8         reserved_at_0[0x4];
7538         u8         mlpn_status[0x4];
7539         u8         local_port[0x8];
7540         u8         reserved_at_10[0x10];
7541
7542         u8         e[0x1];
7543         u8         reserved_at_21[0x1f];
7544 };
7545
7546 struct mlx5_ifc_pmlp_reg_bits {
7547         u8         rxtx[0x1];
7548         u8         reserved_at_1[0x7];
7549         u8         local_port[0x8];
7550         u8         reserved_at_10[0x8];
7551         u8         width[0x8];
7552
7553         u8         lane0_module_mapping[0x20];
7554
7555         u8         lane1_module_mapping[0x20];
7556
7557         u8         lane2_module_mapping[0x20];
7558
7559         u8         lane3_module_mapping[0x20];
7560
7561         u8         reserved_at_a0[0x160];
7562 };
7563
7564 struct mlx5_ifc_pmaos_reg_bits {
7565         u8         reserved_at_0[0x8];
7566         u8         module[0x8];
7567         u8         reserved_at_10[0x4];
7568         u8         admin_status[0x4];
7569         u8         reserved_at_18[0x4];
7570         u8         oper_status[0x4];
7571
7572         u8         ase[0x1];
7573         u8         ee[0x1];
7574         u8         reserved_at_22[0x1c];
7575         u8         e[0x2];
7576
7577         u8         reserved_at_40[0x40];
7578 };
7579
7580 struct mlx5_ifc_plpc_reg_bits {
7581         u8         reserved_at_0[0x4];
7582         u8         profile_id[0xc];
7583         u8         reserved_at_10[0x4];
7584         u8         proto_mask[0x4];
7585         u8         reserved_at_18[0x8];
7586
7587         u8         reserved_at_20[0x10];
7588         u8         lane_speed[0x10];
7589
7590         u8         reserved_at_40[0x17];
7591         u8         lpbf[0x1];
7592         u8         fec_mode_policy[0x8];
7593
7594         u8         retransmission_capability[0x8];
7595         u8         fec_mode_capability[0x18];
7596
7597         u8         retransmission_support_admin[0x8];
7598         u8         fec_mode_support_admin[0x18];
7599
7600         u8         retransmission_request_admin[0x8];
7601         u8         fec_mode_request_admin[0x18];
7602
7603         u8         reserved_at_c0[0x80];
7604 };
7605
7606 struct mlx5_ifc_plib_reg_bits {
7607         u8         reserved_at_0[0x8];
7608         u8         local_port[0x8];
7609         u8         reserved_at_10[0x8];
7610         u8         ib_port[0x8];
7611
7612         u8         reserved_at_20[0x60];
7613 };
7614
7615 struct mlx5_ifc_plbf_reg_bits {
7616         u8         reserved_at_0[0x8];
7617         u8         local_port[0x8];
7618         u8         reserved_at_10[0xd];
7619         u8         lbf_mode[0x3];
7620
7621         u8         reserved_at_20[0x20];
7622 };
7623
7624 struct mlx5_ifc_pipg_reg_bits {
7625         u8         reserved_at_0[0x8];
7626         u8         local_port[0x8];
7627         u8         reserved_at_10[0x10];
7628
7629         u8         dic[0x1];
7630         u8         reserved_at_21[0x19];
7631         u8         ipg[0x4];
7632         u8         reserved_at_3e[0x2];
7633 };
7634
7635 struct mlx5_ifc_pifr_reg_bits {
7636         u8         reserved_at_0[0x8];
7637         u8         local_port[0x8];
7638         u8         reserved_at_10[0x10];
7639
7640         u8         reserved_at_20[0xe0];
7641
7642         u8         port_filter[8][0x20];
7643
7644         u8         port_filter_update_en[8][0x20];
7645 };
7646
7647 struct mlx5_ifc_pfcc_reg_bits {
7648         u8         reserved_at_0[0x8];
7649         u8         local_port[0x8];
7650         u8         reserved_at_10[0x10];
7651
7652         u8         ppan[0x4];
7653         u8         reserved_at_24[0x4];
7654         u8         prio_mask_tx[0x8];
7655         u8         reserved_at_30[0x8];
7656         u8         prio_mask_rx[0x8];
7657
7658         u8         pptx[0x1];
7659         u8         aptx[0x1];
7660         u8         reserved_at_42[0x6];
7661         u8         pfctx[0x8];
7662         u8         reserved_at_50[0x10];
7663
7664         u8         pprx[0x1];
7665         u8         aprx[0x1];
7666         u8         reserved_at_62[0x6];
7667         u8         pfcrx[0x8];
7668         u8         reserved_at_70[0x10];
7669
7670         u8         reserved_at_80[0x80];
7671 };
7672
7673 struct mlx5_ifc_pelc_reg_bits {
7674         u8         op[0x4];
7675         u8         reserved_at_4[0x4];
7676         u8         local_port[0x8];
7677         u8         reserved_at_10[0x10];
7678
7679         u8         op_admin[0x8];
7680         u8         op_capability[0x8];
7681         u8         op_request[0x8];
7682         u8         op_active[0x8];
7683
7684         u8         admin[0x40];
7685
7686         u8         capability[0x40];
7687
7688         u8         request[0x40];
7689
7690         u8         active[0x40];
7691
7692         u8         reserved_at_140[0x80];
7693 };
7694
7695 struct mlx5_ifc_peir_reg_bits {
7696         u8         reserved_at_0[0x8];
7697         u8         local_port[0x8];
7698         u8         reserved_at_10[0x10];
7699
7700         u8         reserved_at_20[0xc];
7701         u8         error_count[0x4];
7702         u8         reserved_at_30[0x10];
7703
7704         u8         reserved_at_40[0xc];
7705         u8         lane[0x4];
7706         u8         reserved_at_50[0x8];
7707         u8         error_type[0x8];
7708 };
7709
7710 struct mlx5_ifc_pcam_enhanced_features_bits {
7711         u8         reserved_at_0[0x7c];
7712
7713         u8         ptys_connector_type[0x1];
7714         u8         reserved_at_7d[0x1];
7715         u8         ppcnt_discard_group[0x1];
7716         u8         ppcnt_statistical_group[0x1];
7717 };
7718
7719 struct mlx5_ifc_pcam_reg_bits {
7720         u8         reserved_at_0[0x8];
7721         u8         feature_group[0x8];
7722         u8         reserved_at_10[0x8];
7723         u8         access_reg_group[0x8];
7724
7725         u8         reserved_at_20[0x20];
7726
7727         union {
7728                 u8         reserved_at_0[0x80];
7729         } port_access_reg_cap_mask;
7730
7731         u8         reserved_at_c0[0x80];
7732
7733         union {
7734                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7735                 u8         reserved_at_0[0x80];
7736         } feature_cap_mask;
7737
7738         u8         reserved_at_1c0[0xc0];
7739 };
7740
7741 struct mlx5_ifc_mcam_enhanced_features_bits {
7742         u8         reserved_at_0[0x7f];
7743
7744         u8         pcie_performance_group[0x1];
7745 };
7746
7747 struct mlx5_ifc_mcam_reg_bits {
7748         u8         reserved_at_0[0x8];
7749         u8         feature_group[0x8];
7750         u8         reserved_at_10[0x8];
7751         u8         access_reg_group[0x8];
7752
7753         u8         reserved_at_20[0x20];
7754
7755         union {
7756                 u8         reserved_at_0[0x80];
7757         } mng_access_reg_cap_mask;
7758
7759         u8         reserved_at_c0[0x80];
7760
7761         union {
7762                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7763                 u8         reserved_at_0[0x80];
7764         } mng_feature_cap_mask;
7765
7766         u8         reserved_at_1c0[0x80];
7767 };
7768
7769 struct mlx5_ifc_pcap_reg_bits {
7770         u8         reserved_at_0[0x8];
7771         u8         local_port[0x8];
7772         u8         reserved_at_10[0x10];
7773
7774         u8         port_capability_mask[4][0x20];
7775 };
7776
7777 struct mlx5_ifc_paos_reg_bits {
7778         u8         swid[0x8];
7779         u8         local_port[0x8];
7780         u8         reserved_at_10[0x4];
7781         u8         admin_status[0x4];
7782         u8         reserved_at_18[0x4];
7783         u8         oper_status[0x4];
7784
7785         u8         ase[0x1];
7786         u8         ee[0x1];
7787         u8         reserved_at_22[0x1c];
7788         u8         e[0x2];
7789
7790         u8         reserved_at_40[0x40];
7791 };
7792
7793 struct mlx5_ifc_pamp_reg_bits {
7794         u8         reserved_at_0[0x8];
7795         u8         opamp_group[0x8];
7796         u8         reserved_at_10[0xc];
7797         u8         opamp_group_type[0x4];
7798
7799         u8         start_index[0x10];
7800         u8         reserved_at_30[0x4];
7801         u8         num_of_indices[0xc];
7802
7803         u8         index_data[18][0x10];
7804 };
7805
7806 struct mlx5_ifc_pcmr_reg_bits {
7807         u8         reserved_at_0[0x8];
7808         u8         local_port[0x8];
7809         u8         reserved_at_10[0x2e];
7810         u8         fcs_cap[0x1];
7811         u8         reserved_at_3f[0x1f];
7812         u8         fcs_chk[0x1];
7813         u8         reserved_at_5f[0x1];
7814 };
7815
7816 struct mlx5_ifc_lane_2_module_mapping_bits {
7817         u8         reserved_at_0[0x6];
7818         u8         rx_lane[0x2];
7819         u8         reserved_at_8[0x6];
7820         u8         tx_lane[0x2];
7821         u8         reserved_at_10[0x8];
7822         u8         module[0x8];
7823 };
7824
7825 struct mlx5_ifc_bufferx_reg_bits {
7826         u8         reserved_at_0[0x6];
7827         u8         lossy[0x1];
7828         u8         epsb[0x1];
7829         u8         reserved_at_8[0xc];
7830         u8         size[0xc];
7831
7832         u8         xoff_threshold[0x10];
7833         u8         xon_threshold[0x10];
7834 };
7835
7836 struct mlx5_ifc_set_node_in_bits {
7837         u8         node_description[64][0x8];
7838 };
7839
7840 struct mlx5_ifc_register_power_settings_bits {
7841         u8         reserved_at_0[0x18];
7842         u8         power_settings_level[0x8];
7843
7844         u8         reserved_at_20[0x60];
7845 };
7846
7847 struct mlx5_ifc_register_host_endianness_bits {
7848         u8         he[0x1];
7849         u8         reserved_at_1[0x1f];
7850
7851         u8         reserved_at_20[0x60];
7852 };
7853
7854 struct mlx5_ifc_umr_pointer_desc_argument_bits {
7855         u8         reserved_at_0[0x20];
7856
7857         u8         mkey[0x20];
7858
7859         u8         addressh_63_32[0x20];
7860
7861         u8         addressl_31_0[0x20];
7862 };
7863
7864 struct mlx5_ifc_ud_adrs_vector_bits {
7865         u8         dc_key[0x40];
7866
7867         u8         ext[0x1];
7868         u8         reserved_at_41[0x7];
7869         u8         destination_qp_dct[0x18];
7870
7871         u8         static_rate[0x4];
7872         u8         sl_eth_prio[0x4];
7873         u8         fl[0x1];
7874         u8         mlid[0x7];
7875         u8         rlid_udp_sport[0x10];
7876
7877         u8         reserved_at_80[0x20];
7878
7879         u8         rmac_47_16[0x20];
7880
7881         u8         rmac_15_0[0x10];
7882         u8         tclass[0x8];
7883         u8         hop_limit[0x8];
7884
7885         u8         reserved_at_e0[0x1];
7886         u8         grh[0x1];
7887         u8         reserved_at_e2[0x2];
7888         u8         src_addr_index[0x8];
7889         u8         flow_label[0x14];
7890
7891         u8         rgid_rip[16][0x8];
7892 };
7893
7894 struct mlx5_ifc_pages_req_event_bits {
7895         u8         reserved_at_0[0x10];
7896         u8         function_id[0x10];
7897
7898         u8         num_pages[0x20];
7899
7900         u8         reserved_at_40[0xa0];
7901 };
7902
7903 struct mlx5_ifc_eqe_bits {
7904         u8         reserved_at_0[0x8];
7905         u8         event_type[0x8];
7906         u8         reserved_at_10[0x8];
7907         u8         event_sub_type[0x8];
7908
7909         u8         reserved_at_20[0xe0];
7910
7911         union mlx5_ifc_event_auto_bits event_data;
7912
7913         u8         reserved_at_1e0[0x10];
7914         u8         signature[0x8];
7915         u8         reserved_at_1f8[0x7];
7916         u8         owner[0x1];
7917 };
7918
7919 enum {
7920         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
7921 };
7922
7923 struct mlx5_ifc_cmd_queue_entry_bits {
7924         u8         type[0x8];
7925         u8         reserved_at_8[0x18];
7926
7927         u8         input_length[0x20];
7928
7929         u8         input_mailbox_pointer_63_32[0x20];
7930
7931         u8         input_mailbox_pointer_31_9[0x17];
7932         u8         reserved_at_77[0x9];
7933
7934         u8         command_input_inline_data[16][0x8];
7935
7936         u8         command_output_inline_data[16][0x8];
7937
7938         u8         output_mailbox_pointer_63_32[0x20];
7939
7940         u8         output_mailbox_pointer_31_9[0x17];
7941         u8         reserved_at_1b7[0x9];
7942
7943         u8         output_length[0x20];
7944
7945         u8         token[0x8];
7946         u8         signature[0x8];
7947         u8         reserved_at_1f0[0x8];
7948         u8         status[0x7];
7949         u8         ownership[0x1];
7950 };
7951
7952 struct mlx5_ifc_cmd_out_bits {
7953         u8         status[0x8];
7954         u8         reserved_at_8[0x18];
7955
7956         u8         syndrome[0x20];
7957
7958         u8         command_output[0x20];
7959 };
7960
7961 struct mlx5_ifc_cmd_in_bits {
7962         u8         opcode[0x10];
7963         u8         reserved_at_10[0x10];
7964
7965         u8         reserved_at_20[0x10];
7966         u8         op_mod[0x10];
7967
7968         u8         command[0][0x20];
7969 };
7970
7971 struct mlx5_ifc_cmd_if_box_bits {
7972         u8         mailbox_data[512][0x8];
7973
7974         u8         reserved_at_1000[0x180];
7975
7976         u8         next_pointer_63_32[0x20];
7977
7978         u8         next_pointer_31_10[0x16];
7979         u8         reserved_at_11b6[0xa];
7980
7981         u8         block_number[0x20];
7982
7983         u8         reserved_at_11e0[0x8];
7984         u8         token[0x8];
7985         u8         ctrl_signature[0x8];
7986         u8         signature[0x8];
7987 };
7988
7989 struct mlx5_ifc_mtt_bits {
7990         u8         ptag_63_32[0x20];
7991
7992         u8         ptag_31_8[0x18];
7993         u8         reserved_at_38[0x6];
7994         u8         wr_en[0x1];
7995         u8         rd_en[0x1];
7996 };
7997
7998 struct mlx5_ifc_query_wol_rol_out_bits {
7999         u8         status[0x8];
8000         u8         reserved_at_8[0x18];
8001
8002         u8         syndrome[0x20];
8003
8004         u8         reserved_at_40[0x10];
8005         u8         rol_mode[0x8];
8006         u8         wol_mode[0x8];
8007
8008         u8         reserved_at_60[0x20];
8009 };
8010
8011 struct mlx5_ifc_query_wol_rol_in_bits {
8012         u8         opcode[0x10];
8013         u8         reserved_at_10[0x10];
8014
8015         u8         reserved_at_20[0x10];
8016         u8         op_mod[0x10];
8017
8018         u8         reserved_at_40[0x40];
8019 };
8020
8021 struct mlx5_ifc_set_wol_rol_out_bits {
8022         u8         status[0x8];
8023         u8         reserved_at_8[0x18];
8024
8025         u8         syndrome[0x20];
8026
8027         u8         reserved_at_40[0x40];
8028 };
8029
8030 struct mlx5_ifc_set_wol_rol_in_bits {
8031         u8         opcode[0x10];
8032         u8         reserved_at_10[0x10];
8033
8034         u8         reserved_at_20[0x10];
8035         u8         op_mod[0x10];
8036
8037         u8         rol_mode_valid[0x1];
8038         u8         wol_mode_valid[0x1];
8039         u8         reserved_at_42[0xe];
8040         u8         rol_mode[0x8];
8041         u8         wol_mode[0x8];
8042
8043         u8         reserved_at_60[0x20];
8044 };
8045
8046 enum {
8047         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8048         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8049         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8050 };
8051
8052 enum {
8053         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8054         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8055         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8056 };
8057
8058 enum {
8059         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8060         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8061         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
8062         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
8063         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
8064         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
8065         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
8066         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
8067         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
8068         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
8069         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
8070 };
8071
8072 struct mlx5_ifc_initial_seg_bits {
8073         u8         fw_rev_minor[0x10];
8074         u8         fw_rev_major[0x10];
8075
8076         u8         cmd_interface_rev[0x10];
8077         u8         fw_rev_subminor[0x10];
8078
8079         u8         reserved_at_40[0x40];
8080
8081         u8         cmdq_phy_addr_63_32[0x20];
8082
8083         u8         cmdq_phy_addr_31_12[0x14];
8084         u8         reserved_at_b4[0x2];
8085         u8         nic_interface[0x2];
8086         u8         log_cmdq_size[0x4];
8087         u8         log_cmdq_stride[0x4];
8088
8089         u8         command_doorbell_vector[0x20];
8090
8091         u8         reserved_at_e0[0xf00];
8092
8093         u8         initializing[0x1];
8094         u8         reserved_at_fe1[0x4];
8095         u8         nic_interface_supported[0x3];
8096         u8         reserved_at_fe8[0x18];
8097
8098         struct mlx5_ifc_health_buffer_bits health_buffer;
8099
8100         u8         no_dram_nic_offset[0x20];
8101
8102         u8         reserved_at_1220[0x6e40];
8103
8104         u8         reserved_at_8060[0x1f];
8105         u8         clear_int[0x1];
8106
8107         u8         health_syndrome[0x8];
8108         u8         health_counter[0x18];
8109
8110         u8         reserved_at_80a0[0x17fc0];
8111 };
8112
8113 struct mlx5_ifc_mtpps_reg_bits {
8114         u8         reserved_at_0[0xc];
8115         u8         cap_number_of_pps_pins[0x4];
8116         u8         reserved_at_10[0x4];
8117         u8         cap_max_num_of_pps_in_pins[0x4];
8118         u8         reserved_at_18[0x4];
8119         u8         cap_max_num_of_pps_out_pins[0x4];
8120
8121         u8         reserved_at_20[0x24];
8122         u8         cap_pin_3_mode[0x4];
8123         u8         reserved_at_48[0x4];
8124         u8         cap_pin_2_mode[0x4];
8125         u8         reserved_at_50[0x4];
8126         u8         cap_pin_1_mode[0x4];
8127         u8         reserved_at_58[0x4];
8128         u8         cap_pin_0_mode[0x4];
8129
8130         u8         reserved_at_60[0x4];
8131         u8         cap_pin_7_mode[0x4];
8132         u8         reserved_at_68[0x4];
8133         u8         cap_pin_6_mode[0x4];
8134         u8         reserved_at_70[0x4];
8135         u8         cap_pin_5_mode[0x4];
8136         u8         reserved_at_78[0x4];
8137         u8         cap_pin_4_mode[0x4];
8138
8139         u8         reserved_at_80[0x80];
8140
8141         u8         enable[0x1];
8142         u8         reserved_at_101[0xb];
8143         u8         pattern[0x4];
8144         u8         reserved_at_110[0x4];
8145         u8         pin_mode[0x4];
8146         u8         pin[0x8];
8147
8148         u8         reserved_at_120[0x20];
8149
8150         u8         time_stamp[0x40];
8151
8152         u8         out_pulse_duration[0x10];
8153         u8         out_periodic_adjustment[0x10];
8154
8155         u8         reserved_at_1a0[0x60];
8156 };
8157
8158 struct mlx5_ifc_mtppse_reg_bits {
8159         u8         reserved_at_0[0x18];
8160         u8         pin[0x8];
8161         u8         event_arm[0x1];
8162         u8         reserved_at_21[0x1b];
8163         u8         event_generation_mode[0x4];
8164         u8         reserved_at_40[0x40];
8165 };
8166
8167 union mlx5_ifc_ports_control_registers_document_bits {
8168         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8169         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8170         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8171         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8172         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8173         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8174         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8175         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8176         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8177         struct mlx5_ifc_pamp_reg_bits pamp_reg;
8178         struct mlx5_ifc_paos_reg_bits paos_reg;
8179         struct mlx5_ifc_pcap_reg_bits pcap_reg;
8180         struct mlx5_ifc_peir_reg_bits peir_reg;
8181         struct mlx5_ifc_pelc_reg_bits pelc_reg;
8182         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
8183         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
8184         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8185         struct mlx5_ifc_pifr_reg_bits pifr_reg;
8186         struct mlx5_ifc_pipg_reg_bits pipg_reg;
8187         struct mlx5_ifc_plbf_reg_bits plbf_reg;
8188         struct mlx5_ifc_plib_reg_bits plib_reg;
8189         struct mlx5_ifc_plpc_reg_bits plpc_reg;
8190         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8191         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8192         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8193         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8194         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8195         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8196         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8197         struct mlx5_ifc_ppad_reg_bits ppad_reg;
8198         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8199         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
8200         struct mlx5_ifc_pplm_reg_bits pplm_reg;
8201         struct mlx5_ifc_pplr_reg_bits pplr_reg;
8202         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8203         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8204         struct mlx5_ifc_pspa_reg_bits pspa_reg;
8205         struct mlx5_ifc_ptas_reg_bits ptas_reg;
8206         struct mlx5_ifc_ptys_reg_bits ptys_reg;
8207         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
8208         struct mlx5_ifc_pude_reg_bits pude_reg;
8209         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8210         struct mlx5_ifc_slrg_reg_bits slrg_reg;
8211         struct mlx5_ifc_sltp_reg_bits sltp_reg;
8212         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8213         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
8214         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8215         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
8216         u8         reserved_at_0[0x60e0];
8217 };
8218
8219 union mlx5_ifc_debug_enhancements_document_bits {
8220         struct mlx5_ifc_health_buffer_bits health_buffer;
8221         u8         reserved_at_0[0x200];
8222 };
8223
8224 union mlx5_ifc_uplink_pci_interface_document_bits {
8225         struct mlx5_ifc_initial_seg_bits initial_seg;
8226         u8         reserved_at_0[0x20060];
8227 };
8228
8229 struct mlx5_ifc_set_flow_table_root_out_bits {
8230         u8         status[0x8];
8231         u8         reserved_at_8[0x18];
8232
8233         u8         syndrome[0x20];
8234
8235         u8         reserved_at_40[0x40];
8236 };
8237
8238 struct mlx5_ifc_set_flow_table_root_in_bits {
8239         u8         opcode[0x10];
8240         u8         reserved_at_10[0x10];
8241
8242         u8         reserved_at_20[0x10];
8243         u8         op_mod[0x10];
8244
8245         u8         other_vport[0x1];
8246         u8         reserved_at_41[0xf];
8247         u8         vport_number[0x10];
8248
8249         u8         reserved_at_60[0x20];
8250
8251         u8         table_type[0x8];
8252         u8         reserved_at_88[0x18];
8253
8254         u8         reserved_at_a0[0x8];
8255         u8         table_id[0x18];
8256
8257         u8         reserved_at_c0[0x8];
8258         u8         underlay_qpn[0x18];
8259         u8         reserved_at_e0[0x120];
8260 };
8261
8262 enum {
8263         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
8264         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
8265 };
8266
8267 struct mlx5_ifc_modify_flow_table_out_bits {
8268         u8         status[0x8];
8269         u8         reserved_at_8[0x18];
8270
8271         u8         syndrome[0x20];
8272
8273         u8         reserved_at_40[0x40];
8274 };
8275
8276 struct mlx5_ifc_modify_flow_table_in_bits {
8277         u8         opcode[0x10];
8278         u8         reserved_at_10[0x10];
8279
8280         u8         reserved_at_20[0x10];
8281         u8         op_mod[0x10];
8282
8283         u8         other_vport[0x1];
8284         u8         reserved_at_41[0xf];
8285         u8         vport_number[0x10];
8286
8287         u8         reserved_at_60[0x10];
8288         u8         modify_field_select[0x10];
8289
8290         u8         table_type[0x8];
8291         u8         reserved_at_88[0x18];
8292
8293         u8         reserved_at_a0[0x8];
8294         u8         table_id[0x18];
8295
8296         struct mlx5_ifc_flow_table_context_bits flow_table_context;
8297 };
8298
8299 struct mlx5_ifc_ets_tcn_config_reg_bits {
8300         u8         g[0x1];
8301         u8         b[0x1];
8302         u8         r[0x1];
8303         u8         reserved_at_3[0x9];
8304         u8         group[0x4];
8305         u8         reserved_at_10[0x9];
8306         u8         bw_allocation[0x7];
8307
8308         u8         reserved_at_20[0xc];
8309         u8         max_bw_units[0x4];
8310         u8         reserved_at_30[0x8];
8311         u8         max_bw_value[0x8];
8312 };
8313
8314 struct mlx5_ifc_ets_global_config_reg_bits {
8315         u8         reserved_at_0[0x2];
8316         u8         r[0x1];
8317         u8         reserved_at_3[0x1d];
8318
8319         u8         reserved_at_20[0xc];
8320         u8         max_bw_units[0x4];
8321         u8         reserved_at_30[0x8];
8322         u8         max_bw_value[0x8];
8323 };
8324
8325 struct mlx5_ifc_qetc_reg_bits {
8326         u8                                         reserved_at_0[0x8];
8327         u8                                         port_number[0x8];
8328         u8                                         reserved_at_10[0x30];
8329
8330         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
8331         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8332 };
8333
8334 struct mlx5_ifc_qtct_reg_bits {
8335         u8         reserved_at_0[0x8];
8336         u8         port_number[0x8];
8337         u8         reserved_at_10[0xd];
8338         u8         prio[0x3];
8339
8340         u8         reserved_at_20[0x1d];
8341         u8         tclass[0x3];
8342 };
8343
8344 struct mlx5_ifc_mcia_reg_bits {
8345         u8         l[0x1];
8346         u8         reserved_at_1[0x7];
8347         u8         module[0x8];
8348         u8         reserved_at_10[0x8];
8349         u8         status[0x8];
8350
8351         u8         i2c_device_address[0x8];
8352         u8         page_number[0x8];
8353         u8         device_address[0x10];
8354
8355         u8         reserved_at_40[0x10];
8356         u8         size[0x10];
8357
8358         u8         reserved_at_60[0x20];
8359
8360         u8         dword_0[0x20];
8361         u8         dword_1[0x20];
8362         u8         dword_2[0x20];
8363         u8         dword_3[0x20];
8364         u8         dword_4[0x20];
8365         u8         dword_5[0x20];
8366         u8         dword_6[0x20];
8367         u8         dword_7[0x20];
8368         u8         dword_8[0x20];
8369         u8         dword_9[0x20];
8370         u8         dword_10[0x20];
8371         u8         dword_11[0x20];
8372 };
8373
8374 struct mlx5_ifc_dcbx_param_bits {
8375         u8         dcbx_cee_cap[0x1];
8376         u8         dcbx_ieee_cap[0x1];
8377         u8         dcbx_standby_cap[0x1];
8378         u8         reserved_at_0[0x5];
8379         u8         port_number[0x8];
8380         u8         reserved_at_10[0xa];
8381         u8         max_application_table_size[6];
8382         u8         reserved_at_20[0x15];
8383         u8         version_oper[0x3];
8384         u8         reserved_at_38[5];
8385         u8         version_admin[0x3];
8386         u8         willing_admin[0x1];
8387         u8         reserved_at_41[0x3];
8388         u8         pfc_cap_oper[0x4];
8389         u8         reserved_at_48[0x4];
8390         u8         pfc_cap_admin[0x4];
8391         u8         reserved_at_50[0x4];
8392         u8         num_of_tc_oper[0x4];
8393         u8         reserved_at_58[0x4];
8394         u8         num_of_tc_admin[0x4];
8395         u8         remote_willing[0x1];
8396         u8         reserved_at_61[3];
8397         u8         remote_pfc_cap[4];
8398         u8         reserved_at_68[0x14];
8399         u8         remote_num_of_tc[0x4];
8400         u8         reserved_at_80[0x18];
8401         u8         error[0x8];
8402         u8         reserved_at_a0[0x160];
8403 };
8404
8405 struct mlx5_ifc_lagc_bits {
8406         u8         reserved_at_0[0x1d];
8407         u8         lag_state[0x3];
8408
8409         u8         reserved_at_20[0x14];
8410         u8         tx_remap_affinity_2[0x4];
8411         u8         reserved_at_38[0x4];
8412         u8         tx_remap_affinity_1[0x4];
8413 };
8414
8415 struct mlx5_ifc_create_lag_out_bits {
8416         u8         status[0x8];
8417         u8         reserved_at_8[0x18];
8418
8419         u8         syndrome[0x20];
8420
8421         u8         reserved_at_40[0x40];
8422 };
8423
8424 struct mlx5_ifc_create_lag_in_bits {
8425         u8         opcode[0x10];
8426         u8         reserved_at_10[0x10];
8427
8428         u8         reserved_at_20[0x10];
8429         u8         op_mod[0x10];
8430
8431         struct mlx5_ifc_lagc_bits ctx;
8432 };
8433
8434 struct mlx5_ifc_modify_lag_out_bits {
8435         u8         status[0x8];
8436         u8         reserved_at_8[0x18];
8437
8438         u8         syndrome[0x20];
8439
8440         u8         reserved_at_40[0x40];
8441 };
8442
8443 struct mlx5_ifc_modify_lag_in_bits {
8444         u8         opcode[0x10];
8445         u8         reserved_at_10[0x10];
8446
8447         u8         reserved_at_20[0x10];
8448         u8         op_mod[0x10];
8449
8450         u8         reserved_at_40[0x20];
8451         u8         field_select[0x20];
8452
8453         struct mlx5_ifc_lagc_bits ctx;
8454 };
8455
8456 struct mlx5_ifc_query_lag_out_bits {
8457         u8         status[0x8];
8458         u8         reserved_at_8[0x18];
8459
8460         u8         syndrome[0x20];
8461
8462         u8         reserved_at_40[0x40];
8463
8464         struct mlx5_ifc_lagc_bits ctx;
8465 };
8466
8467 struct mlx5_ifc_query_lag_in_bits {
8468         u8         opcode[0x10];
8469         u8         reserved_at_10[0x10];
8470
8471         u8         reserved_at_20[0x10];
8472         u8         op_mod[0x10];
8473
8474         u8         reserved_at_40[0x40];
8475 };
8476
8477 struct mlx5_ifc_destroy_lag_out_bits {
8478         u8         status[0x8];
8479         u8         reserved_at_8[0x18];
8480
8481         u8         syndrome[0x20];
8482
8483         u8         reserved_at_40[0x40];
8484 };
8485
8486 struct mlx5_ifc_destroy_lag_in_bits {
8487         u8         opcode[0x10];
8488         u8         reserved_at_10[0x10];
8489
8490         u8         reserved_at_20[0x10];
8491         u8         op_mod[0x10];
8492
8493         u8         reserved_at_40[0x40];
8494 };
8495
8496 struct mlx5_ifc_create_vport_lag_out_bits {
8497         u8         status[0x8];
8498         u8         reserved_at_8[0x18];
8499
8500         u8         syndrome[0x20];
8501
8502         u8         reserved_at_40[0x40];
8503 };
8504
8505 struct mlx5_ifc_create_vport_lag_in_bits {
8506         u8         opcode[0x10];
8507         u8         reserved_at_10[0x10];
8508
8509         u8         reserved_at_20[0x10];
8510         u8         op_mod[0x10];
8511
8512         u8         reserved_at_40[0x40];
8513 };
8514
8515 struct mlx5_ifc_destroy_vport_lag_out_bits {
8516         u8         status[0x8];
8517         u8         reserved_at_8[0x18];
8518
8519         u8         syndrome[0x20];
8520
8521         u8         reserved_at_40[0x40];
8522 };
8523
8524 struct mlx5_ifc_destroy_vport_lag_in_bits {
8525         u8         opcode[0x10];
8526         u8         reserved_at_10[0x10];
8527
8528         u8         reserved_at_20[0x10];
8529         u8         op_mod[0x10];
8530
8531         u8         reserved_at_40[0x40];
8532 };
8533
8534 #endif /* MLX5_IFC_H */