2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
205 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
206 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
207 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
208 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
211 struct mlx5_ifc_flow_table_fields_supported_bits {
214 u8 outer_ether_type[0x1];
215 u8 reserved_at_3[0x1];
216 u8 outer_first_prio[0x1];
217 u8 outer_first_cfi[0x1];
218 u8 outer_first_vid[0x1];
219 u8 reserved_at_7[0x1];
220 u8 outer_second_prio[0x1];
221 u8 outer_second_cfi[0x1];
222 u8 outer_second_vid[0x1];
223 u8 reserved_at_b[0x1];
227 u8 outer_ip_protocol[0x1];
228 u8 outer_ip_ecn[0x1];
229 u8 outer_ip_dscp[0x1];
230 u8 outer_udp_sport[0x1];
231 u8 outer_udp_dport[0x1];
232 u8 outer_tcp_sport[0x1];
233 u8 outer_tcp_dport[0x1];
234 u8 outer_tcp_flags[0x1];
235 u8 outer_gre_protocol[0x1];
236 u8 outer_gre_key[0x1];
237 u8 outer_vxlan_vni[0x1];
238 u8 reserved_at_1a[0x5];
239 u8 source_eswitch_port[0x1];
243 u8 inner_ether_type[0x1];
244 u8 reserved_at_23[0x1];
245 u8 inner_first_prio[0x1];
246 u8 inner_first_cfi[0x1];
247 u8 inner_first_vid[0x1];
248 u8 reserved_at_27[0x1];
249 u8 inner_second_prio[0x1];
250 u8 inner_second_cfi[0x1];
251 u8 inner_second_vid[0x1];
252 u8 reserved_at_2b[0x1];
256 u8 inner_ip_protocol[0x1];
257 u8 inner_ip_ecn[0x1];
258 u8 inner_ip_dscp[0x1];
259 u8 inner_udp_sport[0x1];
260 u8 inner_udp_dport[0x1];
261 u8 inner_tcp_sport[0x1];
262 u8 inner_tcp_dport[0x1];
263 u8 inner_tcp_flags[0x1];
264 u8 reserved_at_37[0x9];
266 u8 reserved_at_40[0x40];
269 struct mlx5_ifc_flow_table_prop_layout_bits {
271 u8 reserved_at_1[0x1];
272 u8 flow_counter[0x1];
273 u8 flow_modify_en[0x1];
275 u8 identified_miss_table_mode[0x1];
276 u8 flow_table_modify[0x1];
277 u8 reserved_at_7[0x19];
279 u8 reserved_at_20[0x2];
280 u8 log_max_ft_size[0x6];
281 u8 reserved_at_28[0x10];
282 u8 max_ft_level[0x8];
284 u8 reserved_at_40[0x20];
286 u8 reserved_at_60[0x18];
287 u8 log_max_ft_num[0x8];
289 u8 reserved_at_80[0x18];
290 u8 log_max_destination[0x8];
292 u8 reserved_at_a0[0x18];
293 u8 log_max_flow[0x8];
295 u8 reserved_at_c0[0x40];
297 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
299 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
302 struct mlx5_ifc_odp_per_transport_service_cap_bits {
307 u8 reserved_at_4[0x1];
309 u8 reserved_at_6[0x1a];
312 struct mlx5_ifc_ipv4_layout_bits {
313 u8 reserved_at_0[0x60];
318 struct mlx5_ifc_ipv6_layout_bits {
322 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
323 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
324 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
325 u8 reserved_at_0[0x80];
328 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
345 u8 reserved_at_91[0x1];
347 u8 reserved_at_93[0x4];
353 u8 reserved_at_c0[0x20];
358 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
360 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
363 struct mlx5_ifc_fte_match_set_misc_bits {
364 u8 reserved_at_0[0x20];
366 u8 reserved_at_20[0x10];
367 u8 source_port[0x10];
369 u8 outer_second_prio[0x3];
370 u8 outer_second_cfi[0x1];
371 u8 outer_second_vid[0xc];
372 u8 inner_second_prio[0x3];
373 u8 inner_second_cfi[0x1];
374 u8 inner_second_vid[0xc];
376 u8 outer_second_vlan_tag[0x1];
377 u8 inner_second_vlan_tag[0x1];
378 u8 reserved_at_62[0xe];
379 u8 gre_protocol[0x10];
385 u8 reserved_at_b8[0x8];
387 u8 reserved_at_c0[0x20];
389 u8 reserved_at_e0[0xc];
390 u8 outer_ipv6_flow_label[0x14];
392 u8 reserved_at_100[0xc];
393 u8 inner_ipv6_flow_label[0x14];
395 u8 reserved_at_120[0xe0];
398 struct mlx5_ifc_cmd_pas_bits {
402 u8 reserved_at_34[0xc];
405 struct mlx5_ifc_uint64_bits {
412 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
413 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
414 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
415 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
416 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
417 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
418 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
419 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
420 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
421 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
424 struct mlx5_ifc_ads_bits {
427 u8 reserved_at_2[0xe];
430 u8 reserved_at_20[0x8];
436 u8 reserved_at_45[0x3];
437 u8 src_addr_index[0x8];
438 u8 reserved_at_50[0x4];
442 u8 reserved_at_60[0x4];
446 u8 rgid_rip[16][0x8];
448 u8 reserved_at_100[0x4];
451 u8 reserved_at_106[0x1];
466 struct mlx5_ifc_flow_table_nic_cap_bits {
467 u8 nic_rx_multi_path_tirs[0x1];
468 u8 reserved_at_1[0x1ff];
470 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
472 u8 reserved_at_400[0x200];
474 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
476 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
478 u8 reserved_at_a00[0x200];
480 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
482 u8 reserved_at_e00[0x7200];
485 struct mlx5_ifc_flow_table_eswitch_cap_bits {
486 u8 reserved_at_0[0x200];
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
490 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
492 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
494 u8 reserved_at_800[0x7800];
497 struct mlx5_ifc_e_switch_cap_bits {
498 u8 vport_svlan_strip[0x1];
499 u8 vport_cvlan_strip[0x1];
500 u8 vport_svlan_insert[0x1];
501 u8 vport_cvlan_insert_if_not_exist[0x1];
502 u8 vport_cvlan_insert_overwrite[0x1];
503 u8 reserved_at_5[0x1b];
505 u8 reserved_at_20[0x7e0];
508 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
512 u8 lro_psh_flag[0x1];
513 u8 lro_time_stamp[0x1];
514 u8 reserved_at_5[0x3];
515 u8 self_lb_en_modifiable[0x1];
516 u8 reserved_at_9[0x2];
518 u8 reserved_at_10[0x4];
519 u8 rss_ind_tbl_cap[0x4];
522 u8 reserved_at_1a[0x1];
523 u8 tunnel_lso_const_out_ip_id[0x1];
524 u8 reserved_at_1c[0x2];
525 u8 tunnel_statless_gre[0x1];
526 u8 tunnel_stateless_vxlan[0x1];
528 u8 reserved_at_20[0x20];
530 u8 reserved_at_40[0x10];
531 u8 lro_min_mss_size[0x10];
533 u8 reserved_at_60[0x120];
535 u8 lro_timer_supported_periods[4][0x20];
537 u8 reserved_at_200[0x600];
540 struct mlx5_ifc_roce_cap_bits {
542 u8 reserved_at_1[0x1f];
544 u8 reserved_at_20[0x60];
546 u8 reserved_at_80[0xc];
548 u8 reserved_at_90[0x8];
549 u8 roce_version[0x8];
551 u8 reserved_at_a0[0x10];
552 u8 r_roce_dest_udp_port[0x10];
554 u8 r_roce_max_src_udp_port[0x10];
555 u8 r_roce_min_src_udp_port[0x10];
557 u8 reserved_at_e0[0x10];
558 u8 roce_address_table_size[0x10];
560 u8 reserved_at_100[0x700];
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
566 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
578 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
579 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
580 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
581 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
582 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
583 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
584 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
587 struct mlx5_ifc_atomic_caps_bits {
588 u8 reserved_at_0[0x40];
590 u8 atomic_req_8B_endianess_mode[0x2];
591 u8 reserved_at_42[0x4];
592 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
594 u8 reserved_at_47[0x19];
596 u8 reserved_at_60[0x20];
598 u8 reserved_at_80[0x10];
599 u8 atomic_operations[0x10];
601 u8 reserved_at_a0[0x10];
602 u8 atomic_size_qp[0x10];
604 u8 reserved_at_c0[0x10];
605 u8 atomic_size_dc[0x10];
607 u8 reserved_at_e0[0x720];
610 struct mlx5_ifc_odp_cap_bits {
611 u8 reserved_at_0[0x40];
614 u8 reserved_at_41[0x1f];
616 u8 reserved_at_60[0x20];
618 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
620 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
622 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
624 u8 reserved_at_e0[0x720];
627 struct mlx5_ifc_calc_op {
628 u8 reserved_at_0[0x10];
629 u8 reserved_at_10[0x9];
630 u8 op_swap_endianness[0x1];
639 struct mlx5_ifc_vector_calc_cap_bits {
641 u8 reserved_at_1[0x1f];
642 u8 reserved_at_20[0x8];
643 u8 max_vec_count[0x8];
644 u8 reserved_at_30[0xd];
645 u8 max_chunk_size[0x3];
646 struct mlx5_ifc_calc_op calc0;
647 struct mlx5_ifc_calc_op calc1;
648 struct mlx5_ifc_calc_op calc2;
649 struct mlx5_ifc_calc_op calc3;
651 u8 reserved_at_e0[0x720];
655 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
656 MLX5_WQ_TYPE_CYCLIC = 0x1,
657 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
661 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
662 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
666 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
667 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
668 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
669 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
670 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
674 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
675 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
676 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
677 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
678 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
679 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
683 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
684 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
688 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
689 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
690 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
694 MLX5_CAP_PORT_TYPE_IB = 0x0,
695 MLX5_CAP_PORT_TYPE_ETH = 0x1,
698 struct mlx5_ifc_cmd_hca_cap_bits {
699 u8 reserved_at_0[0x80];
701 u8 log_max_srq_sz[0x8];
702 u8 log_max_qp_sz[0x8];
703 u8 reserved_at_90[0xb];
706 u8 reserved_at_a0[0xb];
708 u8 reserved_at_b0[0x10];
710 u8 reserved_at_c0[0x8];
711 u8 log_max_cq_sz[0x8];
712 u8 reserved_at_d0[0xb];
715 u8 log_max_eq_sz[0x8];
716 u8 reserved_at_e8[0x2];
717 u8 log_max_mkey[0x6];
718 u8 reserved_at_f0[0xc];
721 u8 max_indirection[0x8];
722 u8 reserved_at_108[0x1];
723 u8 log_max_mrw_sz[0x7];
724 u8 reserved_at_110[0x2];
725 u8 log_max_bsf_list_size[0x6];
726 u8 reserved_at_118[0x2];
727 u8 log_max_klm_list_size[0x6];
729 u8 reserved_at_120[0xa];
730 u8 log_max_ra_req_dc[0x6];
731 u8 reserved_at_130[0xa];
732 u8 log_max_ra_res_dc[0x6];
734 u8 reserved_at_140[0xa];
735 u8 log_max_ra_req_qp[0x6];
736 u8 reserved_at_150[0xa];
737 u8 log_max_ra_res_qp[0x6];
740 u8 cc_query_allowed[0x1];
741 u8 cc_modify_allowed[0x1];
742 u8 reserved_at_163[0xd];
743 u8 gid_table_size[0x10];
745 u8 out_of_seq_cnt[0x1];
746 u8 vport_counters[0x1];
747 u8 reserved_at_182[0x4];
749 u8 pkey_table_size[0x10];
751 u8 vport_group_manager[0x1];
752 u8 vhca_group_manager[0x1];
755 u8 reserved_at_1a4[0x1];
757 u8 nic_flow_table[0x1];
758 u8 eswitch_flow_table[0x1];
759 u8 early_vf_enable[0x1];
760 u8 reserved_at_1a9[0x2];
761 u8 local_ca_ack_delay[0x5];
762 u8 reserved_at_1af[0x2];
764 u8 reserved_at_1b2[0x1];
765 u8 disable_link_up[0x1];
770 u8 reserved_at_1c0[0x3];
772 u8 reserved_at_1c8[0x4];
774 u8 reserved_at_1d0[0x6];
777 u8 reserved_at_1d8[0x1];
786 u8 stat_rate_support[0x10];
787 u8 reserved_at_1f0[0xc];
790 u8 compact_address_vector[0x1];
792 u8 reserved_at_201[0x2];
793 u8 ipoib_basic_offloads[0x1];
794 u8 reserved_at_205[0xa];
795 u8 drain_sigerr[0x1];
796 u8 cmdif_checksum[0x2];
798 u8 reserved_at_213[0x1];
799 u8 wq_signature[0x1];
800 u8 sctr_data_cqe[0x1];
801 u8 reserved_at_216[0x1];
806 u8 reserved_at_21b[0x1];
807 u8 eth_net_offloads[0x1];
810 u8 reserved_at_21f[0x1];
814 u8 cq_moderation[0x1];
815 u8 reserved_at_223[0x3];
819 u8 reserved_at_229[0x1];
820 u8 scqe_break_moderation[0x1];
821 u8 cq_period_start_from_cqe[0x1];
823 u8 reserved_at_22d[0x1];
826 u8 umr_ptr_rlky[0x1];
828 u8 reserved_at_232[0x4];
831 u8 set_deth_sqpn[0x1];
832 u8 reserved_at_239[0x3];
838 u8 reserved_at_240[0xa];
840 u8 reserved_at_250[0x8];
844 u8 reserved_at_261[0x1];
845 u8 pad_tx_eth_packet[0x1];
846 u8 reserved_at_263[0x8];
847 u8 log_bf_reg_size[0x5];
848 u8 reserved_at_270[0x10];
850 u8 reserved_at_280[0x10];
851 u8 max_wqe_sz_sq[0x10];
853 u8 reserved_at_2a0[0x10];
854 u8 max_wqe_sz_rq[0x10];
856 u8 reserved_at_2c0[0x10];
857 u8 max_wqe_sz_sq_dc[0x10];
859 u8 reserved_at_2e0[0x7];
862 u8 reserved_at_300[0x18];
865 u8 reserved_at_320[0x3];
866 u8 log_max_transport_domain[0x5];
867 u8 reserved_at_328[0x3];
869 u8 reserved_at_330[0xb];
870 u8 log_max_xrcd[0x5];
872 u8 reserved_at_340[0x20];
874 u8 reserved_at_360[0x3];
876 u8 reserved_at_368[0x3];
878 u8 reserved_at_370[0x3];
880 u8 reserved_at_378[0x3];
883 u8 basic_cyclic_rcv_wqe[0x1];
884 u8 reserved_at_381[0x2];
886 u8 reserved_at_388[0x3];
888 u8 reserved_at_390[0x3];
889 u8 log_max_rqt_size[0x5];
890 u8 reserved_at_398[0x3];
891 u8 log_max_tis_per_sq[0x5];
893 u8 reserved_at_3a0[0x3];
894 u8 log_max_stride_sz_rq[0x5];
895 u8 reserved_at_3a8[0x3];
896 u8 log_min_stride_sz_rq[0x5];
897 u8 reserved_at_3b0[0x3];
898 u8 log_max_stride_sz_sq[0x5];
899 u8 reserved_at_3b8[0x3];
900 u8 log_min_stride_sz_sq[0x5];
902 u8 reserved_at_3c0[0x1b];
903 u8 log_max_wq_sz[0x5];
905 u8 nic_vport_change_event[0x1];
906 u8 reserved_at_3e1[0xa];
907 u8 log_max_vlan_list[0x5];
908 u8 reserved_at_3f0[0x3];
909 u8 log_max_current_mc_list[0x5];
910 u8 reserved_at_3f8[0x3];
911 u8 log_max_current_uc_list[0x5];
913 u8 reserved_at_400[0x80];
915 u8 reserved_at_480[0x3];
916 u8 log_max_l2_table[0x5];
917 u8 reserved_at_488[0x8];
918 u8 log_uar_page_sz[0x10];
920 u8 reserved_at_4a0[0x20];
921 u8 device_frequency_mhz[0x20];
922 u8 device_frequency_khz[0x20];
924 u8 reserved_at_500[0x80];
926 u8 reserved_at_580[0x3f];
927 u8 cqe_compression[0x1];
929 u8 cqe_compression_timeout[0x10];
930 u8 cqe_compression_max_num[0x10];
932 u8 reserved_at_5e0[0x220];
935 enum mlx5_flow_destination_type {
936 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
937 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
938 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
940 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
943 struct mlx5_ifc_dest_format_struct_bits {
944 u8 destination_type[0x8];
945 u8 destination_id[0x18];
947 u8 reserved_at_20[0x20];
950 struct mlx5_ifc_flow_counter_list_bits {
951 u8 reserved_at_0[0x10];
952 u8 flow_counter_id[0x10];
954 u8 reserved_at_20[0x20];
957 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
958 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
959 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
960 u8 reserved_at_0[0x40];
963 struct mlx5_ifc_fte_match_param_bits {
964 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
966 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
968 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
970 u8 reserved_at_600[0xa00];
974 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
975 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
976 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
977 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
978 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
981 struct mlx5_ifc_rx_hash_field_select_bits {
982 u8 l3_prot_type[0x1];
983 u8 l4_prot_type[0x1];
984 u8 selected_fields[0x1e];
988 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
989 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
993 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
994 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
997 struct mlx5_ifc_wq_bits {
999 u8 wq_signature[0x1];
1000 u8 end_padding_mode[0x2];
1002 u8 reserved_at_8[0x18];
1004 u8 hds_skip_first_sge[0x1];
1005 u8 log2_hds_buf_size[0x3];
1006 u8 reserved_at_24[0x7];
1007 u8 page_offset[0x5];
1010 u8 reserved_at_40[0x8];
1013 u8 reserved_at_60[0x8];
1018 u8 hw_counter[0x20];
1020 u8 sw_counter[0x20];
1022 u8 reserved_at_100[0xc];
1023 u8 log_wq_stride[0x4];
1024 u8 reserved_at_110[0x3];
1025 u8 log_wq_pg_sz[0x5];
1026 u8 reserved_at_118[0x3];
1029 u8 reserved_at_120[0x15];
1030 u8 log_wqe_num_of_strides[0x3];
1031 u8 two_byte_shift_en[0x1];
1032 u8 reserved_at_139[0x4];
1033 u8 log_wqe_stride_size[0x3];
1035 u8 reserved_at_140[0x4c0];
1037 struct mlx5_ifc_cmd_pas_bits pas[0];
1040 struct mlx5_ifc_rq_num_bits {
1041 u8 reserved_at_0[0x8];
1045 struct mlx5_ifc_mac_address_layout_bits {
1046 u8 reserved_at_0[0x10];
1047 u8 mac_addr_47_32[0x10];
1049 u8 mac_addr_31_0[0x20];
1052 struct mlx5_ifc_vlan_layout_bits {
1053 u8 reserved_at_0[0x14];
1056 u8 reserved_at_20[0x20];
1059 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1060 u8 reserved_at_0[0xa0];
1062 u8 min_time_between_cnps[0x20];
1064 u8 reserved_at_c0[0x12];
1066 u8 reserved_at_d8[0x5];
1067 u8 cnp_802p_prio[0x3];
1069 u8 reserved_at_e0[0x720];
1072 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1073 u8 reserved_at_0[0x60];
1075 u8 reserved_at_60[0x4];
1076 u8 clamp_tgt_rate[0x1];
1077 u8 reserved_at_65[0x3];
1078 u8 clamp_tgt_rate_after_time_inc[0x1];
1079 u8 reserved_at_69[0x17];
1081 u8 reserved_at_80[0x20];
1083 u8 rpg_time_reset[0x20];
1085 u8 rpg_byte_reset[0x20];
1087 u8 rpg_threshold[0x20];
1089 u8 rpg_max_rate[0x20];
1091 u8 rpg_ai_rate[0x20];
1093 u8 rpg_hai_rate[0x20];
1097 u8 rpg_min_dec_fac[0x20];
1099 u8 rpg_min_rate[0x20];
1101 u8 reserved_at_1c0[0xe0];
1103 u8 rate_to_set_on_first_cnp[0x20];
1107 u8 dce_tcp_rtt[0x20];
1109 u8 rate_reduce_monitor_period[0x20];
1111 u8 reserved_at_320[0x20];
1113 u8 initial_alpha_value[0x20];
1115 u8 reserved_at_360[0x4a0];
1118 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1119 u8 reserved_at_0[0x80];
1121 u8 rppp_max_rps[0x20];
1123 u8 rpg_time_reset[0x20];
1125 u8 rpg_byte_reset[0x20];
1127 u8 rpg_threshold[0x20];
1129 u8 rpg_max_rate[0x20];
1131 u8 rpg_ai_rate[0x20];
1133 u8 rpg_hai_rate[0x20];
1137 u8 rpg_min_dec_fac[0x20];
1139 u8 rpg_min_rate[0x20];
1141 u8 reserved_at_1c0[0x640];
1145 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1146 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1147 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1150 struct mlx5_ifc_resize_field_select_bits {
1151 u8 resize_field_select[0x20];
1155 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1156 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1157 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1158 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1161 struct mlx5_ifc_modify_field_select_bits {
1162 u8 modify_field_select[0x20];
1165 struct mlx5_ifc_field_select_r_roce_np_bits {
1166 u8 field_select_r_roce_np[0x20];
1169 struct mlx5_ifc_field_select_r_roce_rp_bits {
1170 u8 field_select_r_roce_rp[0x20];
1174 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1175 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1176 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1177 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1178 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1179 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1180 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1181 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1182 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1183 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1186 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1187 u8 field_select_8021qaurp[0x20];
1190 struct mlx5_ifc_phys_layer_cntrs_bits {
1191 u8 time_since_last_clear_high[0x20];
1193 u8 time_since_last_clear_low[0x20];
1195 u8 symbol_errors_high[0x20];
1197 u8 symbol_errors_low[0x20];
1199 u8 sync_headers_errors_high[0x20];
1201 u8 sync_headers_errors_low[0x20];
1203 u8 edpl_bip_errors_lane0_high[0x20];
1205 u8 edpl_bip_errors_lane0_low[0x20];
1207 u8 edpl_bip_errors_lane1_high[0x20];
1209 u8 edpl_bip_errors_lane1_low[0x20];
1211 u8 edpl_bip_errors_lane2_high[0x20];
1213 u8 edpl_bip_errors_lane2_low[0x20];
1215 u8 edpl_bip_errors_lane3_high[0x20];
1217 u8 edpl_bip_errors_lane3_low[0x20];
1219 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1221 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1223 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1225 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1227 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1229 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1231 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1233 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1235 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1237 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1239 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1241 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1243 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1245 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1247 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1249 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1251 u8 rs_fec_corrected_blocks_high[0x20];
1253 u8 rs_fec_corrected_blocks_low[0x20];
1255 u8 rs_fec_uncorrectable_blocks_high[0x20];
1257 u8 rs_fec_uncorrectable_blocks_low[0x20];
1259 u8 rs_fec_no_errors_blocks_high[0x20];
1261 u8 rs_fec_no_errors_blocks_low[0x20];
1263 u8 rs_fec_single_error_blocks_high[0x20];
1265 u8 rs_fec_single_error_blocks_low[0x20];
1267 u8 rs_fec_corrected_symbols_total_high[0x20];
1269 u8 rs_fec_corrected_symbols_total_low[0x20];
1271 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1273 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1275 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1277 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1279 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1281 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1283 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1285 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1287 u8 link_down_events[0x20];
1289 u8 successful_recovery_events[0x20];
1291 u8 reserved_at_640[0x180];
1294 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1295 u8 symbol_error_counter[0x10];
1297 u8 link_error_recovery_counter[0x8];
1299 u8 link_downed_counter[0x8];
1301 u8 port_rcv_errors[0x10];
1303 u8 port_rcv_remote_physical_errors[0x10];
1305 u8 port_rcv_switch_relay_errors[0x10];
1307 u8 port_xmit_discards[0x10];
1309 u8 port_xmit_constraint_errors[0x8];
1311 u8 port_rcv_constraint_errors[0x8];
1313 u8 reserved_at_70[0x8];
1315 u8 link_overrun_errors[0x8];
1317 u8 reserved_at_80[0x10];
1319 u8 vl_15_dropped[0x10];
1321 u8 reserved_at_a0[0xa0];
1324 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1325 u8 transmit_queue_high[0x20];
1327 u8 transmit_queue_low[0x20];
1329 u8 reserved_at_40[0x780];
1332 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1333 u8 rx_octets_high[0x20];
1335 u8 rx_octets_low[0x20];
1337 u8 reserved_at_40[0xc0];
1339 u8 rx_frames_high[0x20];
1341 u8 rx_frames_low[0x20];
1343 u8 tx_octets_high[0x20];
1345 u8 tx_octets_low[0x20];
1347 u8 reserved_at_180[0xc0];
1349 u8 tx_frames_high[0x20];
1351 u8 tx_frames_low[0x20];
1353 u8 rx_pause_high[0x20];
1355 u8 rx_pause_low[0x20];
1357 u8 rx_pause_duration_high[0x20];
1359 u8 rx_pause_duration_low[0x20];
1361 u8 tx_pause_high[0x20];
1363 u8 tx_pause_low[0x20];
1365 u8 tx_pause_duration_high[0x20];
1367 u8 tx_pause_duration_low[0x20];
1369 u8 rx_pause_transition_high[0x20];
1371 u8 rx_pause_transition_low[0x20];
1373 u8 reserved_at_3c0[0x400];
1376 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1377 u8 port_transmit_wait_high[0x20];
1379 u8 port_transmit_wait_low[0x20];
1381 u8 reserved_at_40[0x780];
1384 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1385 u8 dot3stats_alignment_errors_high[0x20];
1387 u8 dot3stats_alignment_errors_low[0x20];
1389 u8 dot3stats_fcs_errors_high[0x20];
1391 u8 dot3stats_fcs_errors_low[0x20];
1393 u8 dot3stats_single_collision_frames_high[0x20];
1395 u8 dot3stats_single_collision_frames_low[0x20];
1397 u8 dot3stats_multiple_collision_frames_high[0x20];
1399 u8 dot3stats_multiple_collision_frames_low[0x20];
1401 u8 dot3stats_sqe_test_errors_high[0x20];
1403 u8 dot3stats_sqe_test_errors_low[0x20];
1405 u8 dot3stats_deferred_transmissions_high[0x20];
1407 u8 dot3stats_deferred_transmissions_low[0x20];
1409 u8 dot3stats_late_collisions_high[0x20];
1411 u8 dot3stats_late_collisions_low[0x20];
1413 u8 dot3stats_excessive_collisions_high[0x20];
1415 u8 dot3stats_excessive_collisions_low[0x20];
1417 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1419 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1421 u8 dot3stats_carrier_sense_errors_high[0x20];
1423 u8 dot3stats_carrier_sense_errors_low[0x20];
1425 u8 dot3stats_frame_too_longs_high[0x20];
1427 u8 dot3stats_frame_too_longs_low[0x20];
1429 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1431 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1433 u8 dot3stats_symbol_errors_high[0x20];
1435 u8 dot3stats_symbol_errors_low[0x20];
1437 u8 dot3control_in_unknown_opcodes_high[0x20];
1439 u8 dot3control_in_unknown_opcodes_low[0x20];
1441 u8 dot3in_pause_frames_high[0x20];
1443 u8 dot3in_pause_frames_low[0x20];
1445 u8 dot3out_pause_frames_high[0x20];
1447 u8 dot3out_pause_frames_low[0x20];
1449 u8 reserved_at_400[0x3c0];
1452 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1453 u8 ether_stats_drop_events_high[0x20];
1455 u8 ether_stats_drop_events_low[0x20];
1457 u8 ether_stats_octets_high[0x20];
1459 u8 ether_stats_octets_low[0x20];
1461 u8 ether_stats_pkts_high[0x20];
1463 u8 ether_stats_pkts_low[0x20];
1465 u8 ether_stats_broadcast_pkts_high[0x20];
1467 u8 ether_stats_broadcast_pkts_low[0x20];
1469 u8 ether_stats_multicast_pkts_high[0x20];
1471 u8 ether_stats_multicast_pkts_low[0x20];
1473 u8 ether_stats_crc_align_errors_high[0x20];
1475 u8 ether_stats_crc_align_errors_low[0x20];
1477 u8 ether_stats_undersize_pkts_high[0x20];
1479 u8 ether_stats_undersize_pkts_low[0x20];
1481 u8 ether_stats_oversize_pkts_high[0x20];
1483 u8 ether_stats_oversize_pkts_low[0x20];
1485 u8 ether_stats_fragments_high[0x20];
1487 u8 ether_stats_fragments_low[0x20];
1489 u8 ether_stats_jabbers_high[0x20];
1491 u8 ether_stats_jabbers_low[0x20];
1493 u8 ether_stats_collisions_high[0x20];
1495 u8 ether_stats_collisions_low[0x20];
1497 u8 ether_stats_pkts64octets_high[0x20];
1499 u8 ether_stats_pkts64octets_low[0x20];
1501 u8 ether_stats_pkts65to127octets_high[0x20];
1503 u8 ether_stats_pkts65to127octets_low[0x20];
1505 u8 ether_stats_pkts128to255octets_high[0x20];
1507 u8 ether_stats_pkts128to255octets_low[0x20];
1509 u8 ether_stats_pkts256to511octets_high[0x20];
1511 u8 ether_stats_pkts256to511octets_low[0x20];
1513 u8 ether_stats_pkts512to1023octets_high[0x20];
1515 u8 ether_stats_pkts512to1023octets_low[0x20];
1517 u8 ether_stats_pkts1024to1518octets_high[0x20];
1519 u8 ether_stats_pkts1024to1518octets_low[0x20];
1521 u8 ether_stats_pkts1519to2047octets_high[0x20];
1523 u8 ether_stats_pkts1519to2047octets_low[0x20];
1525 u8 ether_stats_pkts2048to4095octets_high[0x20];
1527 u8 ether_stats_pkts2048to4095octets_low[0x20];
1529 u8 ether_stats_pkts4096to8191octets_high[0x20];
1531 u8 ether_stats_pkts4096to8191octets_low[0x20];
1533 u8 ether_stats_pkts8192to10239octets_high[0x20];
1535 u8 ether_stats_pkts8192to10239octets_low[0x20];
1537 u8 reserved_at_540[0x280];
1540 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1541 u8 if_in_octets_high[0x20];
1543 u8 if_in_octets_low[0x20];
1545 u8 if_in_ucast_pkts_high[0x20];
1547 u8 if_in_ucast_pkts_low[0x20];
1549 u8 if_in_discards_high[0x20];
1551 u8 if_in_discards_low[0x20];
1553 u8 if_in_errors_high[0x20];
1555 u8 if_in_errors_low[0x20];
1557 u8 if_in_unknown_protos_high[0x20];
1559 u8 if_in_unknown_protos_low[0x20];
1561 u8 if_out_octets_high[0x20];
1563 u8 if_out_octets_low[0x20];
1565 u8 if_out_ucast_pkts_high[0x20];
1567 u8 if_out_ucast_pkts_low[0x20];
1569 u8 if_out_discards_high[0x20];
1571 u8 if_out_discards_low[0x20];
1573 u8 if_out_errors_high[0x20];
1575 u8 if_out_errors_low[0x20];
1577 u8 if_in_multicast_pkts_high[0x20];
1579 u8 if_in_multicast_pkts_low[0x20];
1581 u8 if_in_broadcast_pkts_high[0x20];
1583 u8 if_in_broadcast_pkts_low[0x20];
1585 u8 if_out_multicast_pkts_high[0x20];
1587 u8 if_out_multicast_pkts_low[0x20];
1589 u8 if_out_broadcast_pkts_high[0x20];
1591 u8 if_out_broadcast_pkts_low[0x20];
1593 u8 reserved_at_340[0x480];
1596 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1597 u8 a_frames_transmitted_ok_high[0x20];
1599 u8 a_frames_transmitted_ok_low[0x20];
1601 u8 a_frames_received_ok_high[0x20];
1603 u8 a_frames_received_ok_low[0x20];
1605 u8 a_frame_check_sequence_errors_high[0x20];
1607 u8 a_frame_check_sequence_errors_low[0x20];
1609 u8 a_alignment_errors_high[0x20];
1611 u8 a_alignment_errors_low[0x20];
1613 u8 a_octets_transmitted_ok_high[0x20];
1615 u8 a_octets_transmitted_ok_low[0x20];
1617 u8 a_octets_received_ok_high[0x20];
1619 u8 a_octets_received_ok_low[0x20];
1621 u8 a_multicast_frames_xmitted_ok_high[0x20];
1623 u8 a_multicast_frames_xmitted_ok_low[0x20];
1625 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1627 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1629 u8 a_multicast_frames_received_ok_high[0x20];
1631 u8 a_multicast_frames_received_ok_low[0x20];
1633 u8 a_broadcast_frames_received_ok_high[0x20];
1635 u8 a_broadcast_frames_received_ok_low[0x20];
1637 u8 a_in_range_length_errors_high[0x20];
1639 u8 a_in_range_length_errors_low[0x20];
1641 u8 a_out_of_range_length_field_high[0x20];
1643 u8 a_out_of_range_length_field_low[0x20];
1645 u8 a_frame_too_long_errors_high[0x20];
1647 u8 a_frame_too_long_errors_low[0x20];
1649 u8 a_symbol_error_during_carrier_high[0x20];
1651 u8 a_symbol_error_during_carrier_low[0x20];
1653 u8 a_mac_control_frames_transmitted_high[0x20];
1655 u8 a_mac_control_frames_transmitted_low[0x20];
1657 u8 a_mac_control_frames_received_high[0x20];
1659 u8 a_mac_control_frames_received_low[0x20];
1661 u8 a_unsupported_opcodes_received_high[0x20];
1663 u8 a_unsupported_opcodes_received_low[0x20];
1665 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1667 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1669 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1671 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1673 u8 reserved_at_4c0[0x300];
1676 struct mlx5_ifc_cmd_inter_comp_event_bits {
1677 u8 command_completion_vector[0x20];
1679 u8 reserved_at_20[0xc0];
1682 struct mlx5_ifc_stall_vl_event_bits {
1683 u8 reserved_at_0[0x18];
1685 u8 reserved_at_19[0x3];
1688 u8 reserved_at_20[0xa0];
1691 struct mlx5_ifc_db_bf_congestion_event_bits {
1692 u8 event_subtype[0x8];
1693 u8 reserved_at_8[0x8];
1694 u8 congestion_level[0x8];
1695 u8 reserved_at_18[0x8];
1697 u8 reserved_at_20[0xa0];
1700 struct mlx5_ifc_gpio_event_bits {
1701 u8 reserved_at_0[0x60];
1703 u8 gpio_event_hi[0x20];
1705 u8 gpio_event_lo[0x20];
1707 u8 reserved_at_a0[0x40];
1710 struct mlx5_ifc_port_state_change_event_bits {
1711 u8 reserved_at_0[0x40];
1714 u8 reserved_at_44[0x1c];
1716 u8 reserved_at_60[0x80];
1719 struct mlx5_ifc_dropped_packet_logged_bits {
1720 u8 reserved_at_0[0xe0];
1724 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1725 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1728 struct mlx5_ifc_cq_error_bits {
1729 u8 reserved_at_0[0x8];
1732 u8 reserved_at_20[0x20];
1734 u8 reserved_at_40[0x18];
1737 u8 reserved_at_60[0x80];
1740 struct mlx5_ifc_rdma_page_fault_event_bits {
1741 u8 bytes_committed[0x20];
1745 u8 reserved_at_40[0x10];
1746 u8 packet_len[0x10];
1748 u8 rdma_op_len[0x20];
1752 u8 reserved_at_c0[0x5];
1759 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1760 u8 bytes_committed[0x20];
1762 u8 reserved_at_20[0x10];
1765 u8 reserved_at_40[0x10];
1768 u8 reserved_at_60[0x60];
1770 u8 reserved_at_c0[0x5];
1777 struct mlx5_ifc_qp_events_bits {
1778 u8 reserved_at_0[0xa0];
1781 u8 reserved_at_a8[0x18];
1783 u8 reserved_at_c0[0x8];
1784 u8 qpn_rqn_sqn[0x18];
1787 struct mlx5_ifc_dct_events_bits {
1788 u8 reserved_at_0[0xc0];
1790 u8 reserved_at_c0[0x8];
1791 u8 dct_number[0x18];
1794 struct mlx5_ifc_comp_event_bits {
1795 u8 reserved_at_0[0xc0];
1797 u8 reserved_at_c0[0x8];
1802 MLX5_QPC_STATE_RST = 0x0,
1803 MLX5_QPC_STATE_INIT = 0x1,
1804 MLX5_QPC_STATE_RTR = 0x2,
1805 MLX5_QPC_STATE_RTS = 0x3,
1806 MLX5_QPC_STATE_SQER = 0x4,
1807 MLX5_QPC_STATE_ERR = 0x6,
1808 MLX5_QPC_STATE_SQD = 0x7,
1809 MLX5_QPC_STATE_SUSPENDED = 0x9,
1813 MLX5_QPC_ST_RC = 0x0,
1814 MLX5_QPC_ST_UC = 0x1,
1815 MLX5_QPC_ST_UD = 0x2,
1816 MLX5_QPC_ST_XRC = 0x3,
1817 MLX5_QPC_ST_DCI = 0x5,
1818 MLX5_QPC_ST_QP0 = 0x7,
1819 MLX5_QPC_ST_QP1 = 0x8,
1820 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1821 MLX5_QPC_ST_REG_UMR = 0xc,
1825 MLX5_QPC_PM_STATE_ARMED = 0x0,
1826 MLX5_QPC_PM_STATE_REARM = 0x1,
1827 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1828 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1832 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1833 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1837 MLX5_QPC_MTU_256_BYTES = 0x1,
1838 MLX5_QPC_MTU_512_BYTES = 0x2,
1839 MLX5_QPC_MTU_1K_BYTES = 0x3,
1840 MLX5_QPC_MTU_2K_BYTES = 0x4,
1841 MLX5_QPC_MTU_4K_BYTES = 0x5,
1842 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1846 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1847 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1848 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1849 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1850 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1851 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1852 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1853 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1857 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1858 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1859 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1863 MLX5_QPC_CS_RES_DISABLE = 0x0,
1864 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1865 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1868 struct mlx5_ifc_qpc_bits {
1870 u8 reserved_at_4[0x4];
1872 u8 reserved_at_10[0x3];
1874 u8 reserved_at_15[0x7];
1875 u8 end_padding_mode[0x2];
1876 u8 reserved_at_1e[0x2];
1878 u8 wq_signature[0x1];
1879 u8 block_lb_mc[0x1];
1880 u8 atomic_like_write_en[0x1];
1881 u8 latency_sensitive[0x1];
1882 u8 reserved_at_24[0x1];
1883 u8 drain_sigerr[0x1];
1884 u8 reserved_at_26[0x2];
1888 u8 log_msg_max[0x5];
1889 u8 reserved_at_48[0x1];
1890 u8 log_rq_size[0x4];
1891 u8 log_rq_stride[0x3];
1893 u8 log_sq_size[0x4];
1894 u8 reserved_at_55[0x6];
1896 u8 ulp_stateless_offload_mode[0x4];
1898 u8 counter_set_id[0x8];
1901 u8 reserved_at_80[0x8];
1902 u8 user_index[0x18];
1904 u8 reserved_at_a0[0x3];
1905 u8 log_page_size[0x5];
1906 u8 remote_qpn[0x18];
1908 struct mlx5_ifc_ads_bits primary_address_path;
1910 struct mlx5_ifc_ads_bits secondary_address_path;
1912 u8 log_ack_req_freq[0x4];
1913 u8 reserved_at_384[0x4];
1914 u8 log_sra_max[0x3];
1915 u8 reserved_at_38b[0x2];
1916 u8 retry_count[0x3];
1918 u8 reserved_at_393[0x1];
1920 u8 cur_rnr_retry[0x3];
1921 u8 cur_retry_count[0x3];
1922 u8 reserved_at_39b[0x5];
1924 u8 reserved_at_3a0[0x20];
1926 u8 reserved_at_3c0[0x8];
1927 u8 next_send_psn[0x18];
1929 u8 reserved_at_3e0[0x8];
1932 u8 reserved_at_400[0x40];
1934 u8 reserved_at_440[0x8];
1935 u8 last_acked_psn[0x18];
1937 u8 reserved_at_460[0x8];
1940 u8 reserved_at_480[0x8];
1941 u8 log_rra_max[0x3];
1942 u8 reserved_at_48b[0x1];
1943 u8 atomic_mode[0x4];
1947 u8 reserved_at_493[0x1];
1948 u8 page_offset[0x6];
1949 u8 reserved_at_49a[0x3];
1950 u8 cd_slave_receive[0x1];
1951 u8 cd_slave_send[0x1];
1954 u8 reserved_at_4a0[0x3];
1955 u8 min_rnr_nak[0x5];
1956 u8 next_rcv_psn[0x18];
1958 u8 reserved_at_4c0[0x8];
1961 u8 reserved_at_4e0[0x8];
1968 u8 reserved_at_560[0x5];
1972 u8 reserved_at_580[0x8];
1975 u8 hw_sq_wqebb_counter[0x10];
1976 u8 sw_sq_wqebb_counter[0x10];
1978 u8 hw_rq_counter[0x20];
1980 u8 sw_rq_counter[0x20];
1982 u8 reserved_at_600[0x20];
1984 u8 reserved_at_620[0xf];
1989 u8 dc_access_key[0x40];
1991 u8 reserved_at_680[0xc0];
1994 struct mlx5_ifc_roce_addr_layout_bits {
1995 u8 source_l3_address[16][0x8];
1997 u8 reserved_at_80[0x3];
2000 u8 source_mac_47_32[0x10];
2002 u8 source_mac_31_0[0x20];
2004 u8 reserved_at_c0[0x14];
2005 u8 roce_l3_type[0x4];
2006 u8 roce_version[0x8];
2008 u8 reserved_at_e0[0x20];
2011 union mlx5_ifc_hca_cap_union_bits {
2012 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2013 struct mlx5_ifc_odp_cap_bits odp_cap;
2014 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2015 struct mlx5_ifc_roce_cap_bits roce_cap;
2016 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2017 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2018 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2019 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2020 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2021 u8 reserved_at_0[0x8000];
2025 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2026 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2027 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2028 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2031 struct mlx5_ifc_flow_context_bits {
2032 u8 reserved_at_0[0x20];
2036 u8 reserved_at_40[0x8];
2039 u8 reserved_at_60[0x10];
2042 u8 reserved_at_80[0x8];
2043 u8 destination_list_size[0x18];
2045 u8 reserved_at_a0[0x8];
2046 u8 flow_counter_list_size[0x18];
2048 u8 reserved_at_c0[0x140];
2050 struct mlx5_ifc_fte_match_param_bits match_value;
2052 u8 reserved_at_1200[0x600];
2054 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2058 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2059 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2062 struct mlx5_ifc_xrc_srqc_bits {
2064 u8 log_xrc_srq_size[0x4];
2065 u8 reserved_at_8[0x18];
2067 u8 wq_signature[0x1];
2069 u8 reserved_at_22[0x1];
2071 u8 basic_cyclic_rcv_wqe[0x1];
2072 u8 log_rq_stride[0x3];
2075 u8 page_offset[0x6];
2076 u8 reserved_at_46[0x2];
2079 u8 reserved_at_60[0x20];
2081 u8 user_index_equal_xrc_srqn[0x1];
2082 u8 reserved_at_81[0x1];
2083 u8 log_page_size[0x6];
2084 u8 user_index[0x18];
2086 u8 reserved_at_a0[0x20];
2088 u8 reserved_at_c0[0x8];
2094 u8 reserved_at_100[0x40];
2096 u8 db_record_addr_h[0x20];
2098 u8 db_record_addr_l[0x1e];
2099 u8 reserved_at_17e[0x2];
2101 u8 reserved_at_180[0x80];
2104 struct mlx5_ifc_traffic_counter_bits {
2110 struct mlx5_ifc_tisc_bits {
2111 u8 reserved_at_0[0xc];
2113 u8 reserved_at_10[0x10];
2115 u8 reserved_at_20[0x100];
2117 u8 reserved_at_120[0x8];
2118 u8 transport_domain[0x18];
2120 u8 reserved_at_140[0x3c0];
2124 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2125 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2129 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2130 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2134 MLX5_RX_HASH_FN_NONE = 0x0,
2135 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2136 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2140 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2141 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2144 struct mlx5_ifc_tirc_bits {
2145 u8 reserved_at_0[0x20];
2148 u8 reserved_at_24[0x1c];
2150 u8 reserved_at_40[0x40];
2152 u8 reserved_at_80[0x4];
2153 u8 lro_timeout_period_usecs[0x10];
2154 u8 lro_enable_mask[0x4];
2155 u8 lro_max_ip_payload_size[0x8];
2157 u8 reserved_at_a0[0x40];
2159 u8 reserved_at_e0[0x8];
2160 u8 inline_rqn[0x18];
2162 u8 rx_hash_symmetric[0x1];
2163 u8 reserved_at_101[0x1];
2164 u8 tunneled_offload_en[0x1];
2165 u8 reserved_at_103[0x5];
2166 u8 indirect_table[0x18];
2169 u8 reserved_at_124[0x2];
2170 u8 self_lb_block[0x2];
2171 u8 transport_domain[0x18];
2173 u8 rx_hash_toeplitz_key[10][0x20];
2175 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2177 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2179 u8 reserved_at_2c0[0x4c0];
2183 MLX5_SRQC_STATE_GOOD = 0x0,
2184 MLX5_SRQC_STATE_ERROR = 0x1,
2187 struct mlx5_ifc_srqc_bits {
2189 u8 log_srq_size[0x4];
2190 u8 reserved_at_8[0x18];
2192 u8 wq_signature[0x1];
2194 u8 reserved_at_22[0x1];
2196 u8 reserved_at_24[0x1];
2197 u8 log_rq_stride[0x3];
2200 u8 page_offset[0x6];
2201 u8 reserved_at_46[0x2];
2204 u8 reserved_at_60[0x20];
2206 u8 reserved_at_80[0x2];
2207 u8 log_page_size[0x6];
2208 u8 reserved_at_88[0x18];
2210 u8 reserved_at_a0[0x20];
2212 u8 reserved_at_c0[0x8];
2218 u8 reserved_at_100[0x40];
2222 u8 reserved_at_180[0x80];
2226 MLX5_SQC_STATE_RST = 0x0,
2227 MLX5_SQC_STATE_RDY = 0x1,
2228 MLX5_SQC_STATE_ERR = 0x3,
2231 struct mlx5_ifc_sqc_bits {
2235 u8 flush_in_error_en[0x1];
2236 u8 reserved_at_4[0x4];
2239 u8 reserved_at_d[0x13];
2241 u8 reserved_at_20[0x8];
2242 u8 user_index[0x18];
2244 u8 reserved_at_40[0x8];
2247 u8 reserved_at_60[0xa0];
2249 u8 tis_lst_sz[0x10];
2250 u8 reserved_at_110[0x10];
2252 u8 reserved_at_120[0x40];
2254 u8 reserved_at_160[0x8];
2257 struct mlx5_ifc_wq_bits wq;
2260 struct mlx5_ifc_rqtc_bits {
2261 u8 reserved_at_0[0xa0];
2263 u8 reserved_at_a0[0x10];
2264 u8 rqt_max_size[0x10];
2266 u8 reserved_at_c0[0x10];
2267 u8 rqt_actual_size[0x10];
2269 u8 reserved_at_e0[0x6a0];
2271 struct mlx5_ifc_rq_num_bits rq_num[0];
2275 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2276 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2280 MLX5_RQC_STATE_RST = 0x0,
2281 MLX5_RQC_STATE_RDY = 0x1,
2282 MLX5_RQC_STATE_ERR = 0x3,
2285 struct mlx5_ifc_rqc_bits {
2287 u8 reserved_at_1[0x1];
2288 u8 scatter_fcs[0x1];
2290 u8 mem_rq_type[0x4];
2292 u8 reserved_at_c[0x1];
2293 u8 flush_in_error_en[0x1];
2294 u8 reserved_at_e[0x12];
2296 u8 reserved_at_20[0x8];
2297 u8 user_index[0x18];
2299 u8 reserved_at_40[0x8];
2302 u8 counter_set_id[0x8];
2303 u8 reserved_at_68[0x18];
2305 u8 reserved_at_80[0x8];
2308 u8 reserved_at_a0[0xe0];
2310 struct mlx5_ifc_wq_bits wq;
2314 MLX5_RMPC_STATE_RDY = 0x1,
2315 MLX5_RMPC_STATE_ERR = 0x3,
2318 struct mlx5_ifc_rmpc_bits {
2319 u8 reserved_at_0[0x8];
2321 u8 reserved_at_c[0x14];
2323 u8 basic_cyclic_rcv_wqe[0x1];
2324 u8 reserved_at_21[0x1f];
2326 u8 reserved_at_40[0x140];
2328 struct mlx5_ifc_wq_bits wq;
2331 struct mlx5_ifc_nic_vport_context_bits {
2332 u8 reserved_at_0[0x1f];
2335 u8 arm_change_event[0x1];
2336 u8 reserved_at_21[0x1a];
2337 u8 event_on_mtu[0x1];
2338 u8 event_on_promisc_change[0x1];
2339 u8 event_on_vlan_change[0x1];
2340 u8 event_on_mc_address_change[0x1];
2341 u8 event_on_uc_address_change[0x1];
2343 u8 reserved_at_40[0xf0];
2347 u8 system_image_guid[0x40];
2351 u8 reserved_at_200[0x140];
2352 u8 qkey_violation_counter[0x10];
2353 u8 reserved_at_350[0x430];
2357 u8 promisc_all[0x1];
2358 u8 reserved_at_783[0x2];
2359 u8 allowed_list_type[0x3];
2360 u8 reserved_at_788[0xc];
2361 u8 allowed_list_size[0xc];
2363 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2365 u8 reserved_at_7e0[0x20];
2367 u8 current_uc_mac_address[0][0x40];
2371 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2372 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2373 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2376 struct mlx5_ifc_mkc_bits {
2377 u8 reserved_at_0[0x1];
2379 u8 reserved_at_2[0xd];
2380 u8 small_fence_on_rdma_read_response[0x1];
2387 u8 access_mode[0x2];
2388 u8 reserved_at_18[0x8];
2393 u8 reserved_at_40[0x20];
2398 u8 reserved_at_63[0x2];
2399 u8 expected_sigerr_count[0x1];
2400 u8 reserved_at_66[0x1];
2404 u8 start_addr[0x40];
2408 u8 bsf_octword_size[0x20];
2410 u8 reserved_at_120[0x80];
2412 u8 translations_octword_size[0x20];
2414 u8 reserved_at_1c0[0x1b];
2415 u8 log_page_size[0x5];
2417 u8 reserved_at_1e0[0x20];
2420 struct mlx5_ifc_pkey_bits {
2421 u8 reserved_at_0[0x10];
2425 struct mlx5_ifc_array128_auto_bits {
2426 u8 array128_auto[16][0x8];
2429 struct mlx5_ifc_hca_vport_context_bits {
2430 u8 field_select[0x20];
2432 u8 reserved_at_20[0xe0];
2434 u8 sm_virt_aware[0x1];
2437 u8 grh_required[0x1];
2438 u8 reserved_at_104[0xc];
2439 u8 port_physical_state[0x4];
2440 u8 vport_state_policy[0x4];
2442 u8 vport_state[0x4];
2444 u8 reserved_at_120[0x20];
2446 u8 system_image_guid[0x40];
2454 u8 cap_mask1_field_select[0x20];
2458 u8 cap_mask2_field_select[0x20];
2460 u8 reserved_at_280[0x80];
2463 u8 reserved_at_310[0x4];
2464 u8 init_type_reply[0x4];
2466 u8 subnet_timeout[0x5];
2470 u8 reserved_at_334[0xc];
2472 u8 qkey_violation_counter[0x10];
2473 u8 pkey_violation_counter[0x10];
2475 u8 reserved_at_360[0xca0];
2478 struct mlx5_ifc_esw_vport_context_bits {
2479 u8 reserved_at_0[0x3];
2480 u8 vport_svlan_strip[0x1];
2481 u8 vport_cvlan_strip[0x1];
2482 u8 vport_svlan_insert[0x1];
2483 u8 vport_cvlan_insert[0x2];
2484 u8 reserved_at_8[0x18];
2486 u8 reserved_at_20[0x20];
2495 u8 reserved_at_60[0x7a0];
2499 MLX5_EQC_STATUS_OK = 0x0,
2500 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2504 MLX5_EQC_ST_ARMED = 0x9,
2505 MLX5_EQC_ST_FIRED = 0xa,
2508 struct mlx5_ifc_eqc_bits {
2510 u8 reserved_at_4[0x9];
2513 u8 reserved_at_f[0x5];
2515 u8 reserved_at_18[0x8];
2517 u8 reserved_at_20[0x20];
2519 u8 reserved_at_40[0x14];
2520 u8 page_offset[0x6];
2521 u8 reserved_at_5a[0x6];
2523 u8 reserved_at_60[0x3];
2524 u8 log_eq_size[0x5];
2527 u8 reserved_at_80[0x20];
2529 u8 reserved_at_a0[0x18];
2532 u8 reserved_at_c0[0x3];
2533 u8 log_page_size[0x5];
2534 u8 reserved_at_c8[0x18];
2536 u8 reserved_at_e0[0x60];
2538 u8 reserved_at_140[0x8];
2539 u8 consumer_counter[0x18];
2541 u8 reserved_at_160[0x8];
2542 u8 producer_counter[0x18];
2544 u8 reserved_at_180[0x80];
2548 MLX5_DCTC_STATE_ACTIVE = 0x0,
2549 MLX5_DCTC_STATE_DRAINING = 0x1,
2550 MLX5_DCTC_STATE_DRAINED = 0x2,
2554 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2555 MLX5_DCTC_CS_RES_NA = 0x1,
2556 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2560 MLX5_DCTC_MTU_256_BYTES = 0x1,
2561 MLX5_DCTC_MTU_512_BYTES = 0x2,
2562 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2563 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2564 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2567 struct mlx5_ifc_dctc_bits {
2568 u8 reserved_at_0[0x4];
2570 u8 reserved_at_8[0x18];
2572 u8 reserved_at_20[0x8];
2573 u8 user_index[0x18];
2575 u8 reserved_at_40[0x8];
2578 u8 counter_set_id[0x8];
2579 u8 atomic_mode[0x4];
2583 u8 atomic_like_write_en[0x1];
2584 u8 latency_sensitive[0x1];
2587 u8 reserved_at_73[0xd];
2589 u8 reserved_at_80[0x8];
2591 u8 reserved_at_90[0x3];
2592 u8 min_rnr_nak[0x5];
2593 u8 reserved_at_98[0x8];
2595 u8 reserved_at_a0[0x8];
2598 u8 reserved_at_c0[0x8];
2602 u8 reserved_at_e8[0x4];
2603 u8 flow_label[0x14];
2605 u8 dc_access_key[0x40];
2607 u8 reserved_at_140[0x5];
2610 u8 pkey_index[0x10];
2612 u8 reserved_at_160[0x8];
2613 u8 my_addr_index[0x8];
2614 u8 reserved_at_170[0x8];
2617 u8 dc_access_key_violation_count[0x20];
2619 u8 reserved_at_1a0[0x14];
2625 u8 reserved_at_1c0[0x40];
2629 MLX5_CQC_STATUS_OK = 0x0,
2630 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2631 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2635 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2636 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2640 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2641 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2642 MLX5_CQC_ST_FIRED = 0xa,
2646 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2647 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2650 struct mlx5_ifc_cqc_bits {
2652 u8 reserved_at_4[0x4];
2655 u8 reserved_at_c[0x1];
2656 u8 scqe_break_moderation_en[0x1];
2658 u8 cq_period_mode[0x2];
2659 u8 cqe_comp_en[0x1];
2660 u8 mini_cqe_res_format[0x2];
2662 u8 reserved_at_18[0x8];
2664 u8 reserved_at_20[0x20];
2666 u8 reserved_at_40[0x14];
2667 u8 page_offset[0x6];
2668 u8 reserved_at_5a[0x6];
2670 u8 reserved_at_60[0x3];
2671 u8 log_cq_size[0x5];
2674 u8 reserved_at_80[0x4];
2676 u8 cq_max_count[0x10];
2678 u8 reserved_at_a0[0x18];
2681 u8 reserved_at_c0[0x3];
2682 u8 log_page_size[0x5];
2683 u8 reserved_at_c8[0x18];
2685 u8 reserved_at_e0[0x20];
2687 u8 reserved_at_100[0x8];
2688 u8 last_notified_index[0x18];
2690 u8 reserved_at_120[0x8];
2691 u8 last_solicit_index[0x18];
2693 u8 reserved_at_140[0x8];
2694 u8 consumer_counter[0x18];
2696 u8 reserved_at_160[0x8];
2697 u8 producer_counter[0x18];
2699 u8 reserved_at_180[0x40];
2704 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2705 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2706 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2707 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2708 u8 reserved_at_0[0x800];
2711 struct mlx5_ifc_query_adapter_param_block_bits {
2712 u8 reserved_at_0[0xc0];
2714 u8 reserved_at_c0[0x8];
2715 u8 ieee_vendor_id[0x18];
2717 u8 reserved_at_e0[0x10];
2718 u8 vsd_vendor_id[0x10];
2722 u8 vsd_contd_psid[16][0x8];
2725 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2726 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2727 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2728 u8 reserved_at_0[0x20];
2731 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2732 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2733 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2734 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2735 u8 reserved_at_0[0x20];
2738 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2739 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2740 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2741 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2742 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2743 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2744 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2745 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2746 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
2747 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2748 u8 reserved_at_0[0x7c0];
2751 union mlx5_ifc_event_auto_bits {
2752 struct mlx5_ifc_comp_event_bits comp_event;
2753 struct mlx5_ifc_dct_events_bits dct_events;
2754 struct mlx5_ifc_qp_events_bits qp_events;
2755 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2756 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2757 struct mlx5_ifc_cq_error_bits cq_error;
2758 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2759 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2760 struct mlx5_ifc_gpio_event_bits gpio_event;
2761 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2762 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2763 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2764 u8 reserved_at_0[0xe0];
2767 struct mlx5_ifc_health_buffer_bits {
2768 u8 reserved_at_0[0x100];
2770 u8 assert_existptr[0x20];
2772 u8 assert_callra[0x20];
2774 u8 reserved_at_140[0x40];
2776 u8 fw_version[0x20];
2780 u8 reserved_at_1c0[0x20];
2782 u8 irisc_index[0x8];
2787 struct mlx5_ifc_register_loopback_control_bits {
2789 u8 reserved_at_1[0x7];
2791 u8 reserved_at_10[0x10];
2793 u8 reserved_at_20[0x60];
2796 struct mlx5_ifc_teardown_hca_out_bits {
2798 u8 reserved_at_8[0x18];
2802 u8 reserved_at_40[0x40];
2806 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2807 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2810 struct mlx5_ifc_teardown_hca_in_bits {
2812 u8 reserved_at_10[0x10];
2814 u8 reserved_at_20[0x10];
2817 u8 reserved_at_40[0x10];
2820 u8 reserved_at_60[0x20];
2823 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2825 u8 reserved_at_8[0x18];
2829 u8 reserved_at_40[0x40];
2832 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2834 u8 reserved_at_10[0x10];
2836 u8 reserved_at_20[0x10];
2839 u8 reserved_at_40[0x8];
2842 u8 reserved_at_60[0x20];
2844 u8 opt_param_mask[0x20];
2846 u8 reserved_at_a0[0x20];
2848 struct mlx5_ifc_qpc_bits qpc;
2850 u8 reserved_at_800[0x80];
2853 struct mlx5_ifc_sqd2rts_qp_out_bits {
2855 u8 reserved_at_8[0x18];
2859 u8 reserved_at_40[0x40];
2862 struct mlx5_ifc_sqd2rts_qp_in_bits {
2864 u8 reserved_at_10[0x10];
2866 u8 reserved_at_20[0x10];
2869 u8 reserved_at_40[0x8];
2872 u8 reserved_at_60[0x20];
2874 u8 opt_param_mask[0x20];
2876 u8 reserved_at_a0[0x20];
2878 struct mlx5_ifc_qpc_bits qpc;
2880 u8 reserved_at_800[0x80];
2883 struct mlx5_ifc_set_roce_address_out_bits {
2885 u8 reserved_at_8[0x18];
2889 u8 reserved_at_40[0x40];
2892 struct mlx5_ifc_set_roce_address_in_bits {
2894 u8 reserved_at_10[0x10];
2896 u8 reserved_at_20[0x10];
2899 u8 roce_address_index[0x10];
2900 u8 reserved_at_50[0x10];
2902 u8 reserved_at_60[0x20];
2904 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2907 struct mlx5_ifc_set_mad_demux_out_bits {
2909 u8 reserved_at_8[0x18];
2913 u8 reserved_at_40[0x40];
2917 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2918 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2921 struct mlx5_ifc_set_mad_demux_in_bits {
2923 u8 reserved_at_10[0x10];
2925 u8 reserved_at_20[0x10];
2928 u8 reserved_at_40[0x20];
2930 u8 reserved_at_60[0x6];
2932 u8 reserved_at_68[0x18];
2935 struct mlx5_ifc_set_l2_table_entry_out_bits {
2937 u8 reserved_at_8[0x18];
2941 u8 reserved_at_40[0x40];
2944 struct mlx5_ifc_set_l2_table_entry_in_bits {
2946 u8 reserved_at_10[0x10];
2948 u8 reserved_at_20[0x10];
2951 u8 reserved_at_40[0x60];
2953 u8 reserved_at_a0[0x8];
2954 u8 table_index[0x18];
2956 u8 reserved_at_c0[0x20];
2958 u8 reserved_at_e0[0x13];
2962 struct mlx5_ifc_mac_address_layout_bits mac_address;
2964 u8 reserved_at_140[0xc0];
2967 struct mlx5_ifc_set_issi_out_bits {
2969 u8 reserved_at_8[0x18];
2973 u8 reserved_at_40[0x40];
2976 struct mlx5_ifc_set_issi_in_bits {
2978 u8 reserved_at_10[0x10];
2980 u8 reserved_at_20[0x10];
2983 u8 reserved_at_40[0x10];
2984 u8 current_issi[0x10];
2986 u8 reserved_at_60[0x20];
2989 struct mlx5_ifc_set_hca_cap_out_bits {
2991 u8 reserved_at_8[0x18];
2995 u8 reserved_at_40[0x40];
2998 struct mlx5_ifc_set_hca_cap_in_bits {
3000 u8 reserved_at_10[0x10];
3002 u8 reserved_at_20[0x10];
3005 u8 reserved_at_40[0x40];
3007 union mlx5_ifc_hca_cap_union_bits capability;
3011 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3012 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3013 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3014 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3017 struct mlx5_ifc_set_fte_out_bits {
3019 u8 reserved_at_8[0x18];
3023 u8 reserved_at_40[0x40];
3026 struct mlx5_ifc_set_fte_in_bits {
3028 u8 reserved_at_10[0x10];
3030 u8 reserved_at_20[0x10];
3033 u8 other_vport[0x1];
3034 u8 reserved_at_41[0xf];
3035 u8 vport_number[0x10];
3037 u8 reserved_at_60[0x20];
3040 u8 reserved_at_88[0x18];
3042 u8 reserved_at_a0[0x8];
3045 u8 reserved_at_c0[0x18];
3046 u8 modify_enable_mask[0x8];
3048 u8 reserved_at_e0[0x20];
3050 u8 flow_index[0x20];
3052 u8 reserved_at_120[0xe0];
3054 struct mlx5_ifc_flow_context_bits flow_context;
3057 struct mlx5_ifc_rts2rts_qp_out_bits {
3059 u8 reserved_at_8[0x18];
3063 u8 reserved_at_40[0x40];
3066 struct mlx5_ifc_rts2rts_qp_in_bits {
3068 u8 reserved_at_10[0x10];
3070 u8 reserved_at_20[0x10];
3073 u8 reserved_at_40[0x8];
3076 u8 reserved_at_60[0x20];
3078 u8 opt_param_mask[0x20];
3080 u8 reserved_at_a0[0x20];
3082 struct mlx5_ifc_qpc_bits qpc;
3084 u8 reserved_at_800[0x80];
3087 struct mlx5_ifc_rtr2rts_qp_out_bits {
3089 u8 reserved_at_8[0x18];
3093 u8 reserved_at_40[0x40];
3096 struct mlx5_ifc_rtr2rts_qp_in_bits {
3098 u8 reserved_at_10[0x10];
3100 u8 reserved_at_20[0x10];
3103 u8 reserved_at_40[0x8];
3106 u8 reserved_at_60[0x20];
3108 u8 opt_param_mask[0x20];
3110 u8 reserved_at_a0[0x20];
3112 struct mlx5_ifc_qpc_bits qpc;
3114 u8 reserved_at_800[0x80];
3117 struct mlx5_ifc_rst2init_qp_out_bits {
3119 u8 reserved_at_8[0x18];
3123 u8 reserved_at_40[0x40];
3126 struct mlx5_ifc_rst2init_qp_in_bits {
3128 u8 reserved_at_10[0x10];
3130 u8 reserved_at_20[0x10];
3133 u8 reserved_at_40[0x8];
3136 u8 reserved_at_60[0x20];
3138 u8 opt_param_mask[0x20];
3140 u8 reserved_at_a0[0x20];
3142 struct mlx5_ifc_qpc_bits qpc;
3144 u8 reserved_at_800[0x80];
3147 struct mlx5_ifc_query_xrc_srq_out_bits {
3149 u8 reserved_at_8[0x18];
3153 u8 reserved_at_40[0x40];
3155 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3157 u8 reserved_at_280[0x600];
3162 struct mlx5_ifc_query_xrc_srq_in_bits {
3164 u8 reserved_at_10[0x10];
3166 u8 reserved_at_20[0x10];
3169 u8 reserved_at_40[0x8];
3172 u8 reserved_at_60[0x20];
3176 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3177 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3180 struct mlx5_ifc_query_vport_state_out_bits {
3182 u8 reserved_at_8[0x18];
3186 u8 reserved_at_40[0x20];
3188 u8 reserved_at_60[0x18];
3189 u8 admin_state[0x4];
3194 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
3195 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
3198 struct mlx5_ifc_query_vport_state_in_bits {
3200 u8 reserved_at_10[0x10];
3202 u8 reserved_at_20[0x10];
3205 u8 other_vport[0x1];
3206 u8 reserved_at_41[0xf];
3207 u8 vport_number[0x10];
3209 u8 reserved_at_60[0x20];
3212 struct mlx5_ifc_query_vport_counter_out_bits {
3214 u8 reserved_at_8[0x18];
3218 u8 reserved_at_40[0x40];
3220 struct mlx5_ifc_traffic_counter_bits received_errors;
3222 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3224 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3226 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3228 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3230 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3232 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3234 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3236 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3238 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3240 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3242 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3244 u8 reserved_at_680[0xa00];
3248 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3251 struct mlx5_ifc_query_vport_counter_in_bits {
3253 u8 reserved_at_10[0x10];
3255 u8 reserved_at_20[0x10];
3258 u8 other_vport[0x1];
3259 u8 reserved_at_41[0xb];
3261 u8 vport_number[0x10];
3263 u8 reserved_at_60[0x60];
3266 u8 reserved_at_c1[0x1f];
3268 u8 reserved_at_e0[0x20];
3271 struct mlx5_ifc_query_tis_out_bits {
3273 u8 reserved_at_8[0x18];
3277 u8 reserved_at_40[0x40];
3279 struct mlx5_ifc_tisc_bits tis_context;
3282 struct mlx5_ifc_query_tis_in_bits {
3284 u8 reserved_at_10[0x10];
3286 u8 reserved_at_20[0x10];
3289 u8 reserved_at_40[0x8];
3292 u8 reserved_at_60[0x20];
3295 struct mlx5_ifc_query_tir_out_bits {
3297 u8 reserved_at_8[0x18];
3301 u8 reserved_at_40[0xc0];
3303 struct mlx5_ifc_tirc_bits tir_context;
3306 struct mlx5_ifc_query_tir_in_bits {
3308 u8 reserved_at_10[0x10];
3310 u8 reserved_at_20[0x10];
3313 u8 reserved_at_40[0x8];
3316 u8 reserved_at_60[0x20];
3319 struct mlx5_ifc_query_srq_out_bits {
3321 u8 reserved_at_8[0x18];
3325 u8 reserved_at_40[0x40];
3327 struct mlx5_ifc_srqc_bits srq_context_entry;
3329 u8 reserved_at_280[0x600];
3334 struct mlx5_ifc_query_srq_in_bits {
3336 u8 reserved_at_10[0x10];
3338 u8 reserved_at_20[0x10];
3341 u8 reserved_at_40[0x8];
3344 u8 reserved_at_60[0x20];
3347 struct mlx5_ifc_query_sq_out_bits {
3349 u8 reserved_at_8[0x18];
3353 u8 reserved_at_40[0xc0];
3355 struct mlx5_ifc_sqc_bits sq_context;
3358 struct mlx5_ifc_query_sq_in_bits {
3360 u8 reserved_at_10[0x10];
3362 u8 reserved_at_20[0x10];
3365 u8 reserved_at_40[0x8];
3368 u8 reserved_at_60[0x20];
3371 struct mlx5_ifc_query_special_contexts_out_bits {
3373 u8 reserved_at_8[0x18];
3377 u8 reserved_at_40[0x20];
3382 struct mlx5_ifc_query_special_contexts_in_bits {
3384 u8 reserved_at_10[0x10];
3386 u8 reserved_at_20[0x10];
3389 u8 reserved_at_40[0x40];
3392 struct mlx5_ifc_query_rqt_out_bits {
3394 u8 reserved_at_8[0x18];
3398 u8 reserved_at_40[0xc0];
3400 struct mlx5_ifc_rqtc_bits rqt_context;
3403 struct mlx5_ifc_query_rqt_in_bits {
3405 u8 reserved_at_10[0x10];
3407 u8 reserved_at_20[0x10];
3410 u8 reserved_at_40[0x8];
3413 u8 reserved_at_60[0x20];
3416 struct mlx5_ifc_query_rq_out_bits {
3418 u8 reserved_at_8[0x18];
3422 u8 reserved_at_40[0xc0];
3424 struct mlx5_ifc_rqc_bits rq_context;
3427 struct mlx5_ifc_query_rq_in_bits {
3429 u8 reserved_at_10[0x10];
3431 u8 reserved_at_20[0x10];
3434 u8 reserved_at_40[0x8];
3437 u8 reserved_at_60[0x20];
3440 struct mlx5_ifc_query_roce_address_out_bits {
3442 u8 reserved_at_8[0x18];
3446 u8 reserved_at_40[0x40];
3448 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3451 struct mlx5_ifc_query_roce_address_in_bits {
3453 u8 reserved_at_10[0x10];
3455 u8 reserved_at_20[0x10];
3458 u8 roce_address_index[0x10];
3459 u8 reserved_at_50[0x10];
3461 u8 reserved_at_60[0x20];
3464 struct mlx5_ifc_query_rmp_out_bits {
3466 u8 reserved_at_8[0x18];
3470 u8 reserved_at_40[0xc0];
3472 struct mlx5_ifc_rmpc_bits rmp_context;
3475 struct mlx5_ifc_query_rmp_in_bits {
3477 u8 reserved_at_10[0x10];
3479 u8 reserved_at_20[0x10];
3482 u8 reserved_at_40[0x8];
3485 u8 reserved_at_60[0x20];
3488 struct mlx5_ifc_query_qp_out_bits {
3490 u8 reserved_at_8[0x18];
3494 u8 reserved_at_40[0x40];
3496 u8 opt_param_mask[0x20];
3498 u8 reserved_at_a0[0x20];
3500 struct mlx5_ifc_qpc_bits qpc;
3502 u8 reserved_at_800[0x80];
3507 struct mlx5_ifc_query_qp_in_bits {
3509 u8 reserved_at_10[0x10];
3511 u8 reserved_at_20[0x10];
3514 u8 reserved_at_40[0x8];
3517 u8 reserved_at_60[0x20];
3520 struct mlx5_ifc_query_q_counter_out_bits {
3522 u8 reserved_at_8[0x18];
3526 u8 reserved_at_40[0x40];
3528 u8 rx_write_requests[0x20];
3530 u8 reserved_at_a0[0x20];
3532 u8 rx_read_requests[0x20];
3534 u8 reserved_at_e0[0x20];
3536 u8 rx_atomic_requests[0x20];
3538 u8 reserved_at_120[0x20];
3540 u8 rx_dct_connect[0x20];
3542 u8 reserved_at_160[0x20];
3544 u8 out_of_buffer[0x20];
3546 u8 reserved_at_1a0[0x20];
3548 u8 out_of_sequence[0x20];
3550 u8 reserved_at_1e0[0x620];
3553 struct mlx5_ifc_query_q_counter_in_bits {
3555 u8 reserved_at_10[0x10];
3557 u8 reserved_at_20[0x10];
3560 u8 reserved_at_40[0x80];
3563 u8 reserved_at_c1[0x1f];
3565 u8 reserved_at_e0[0x18];
3566 u8 counter_set_id[0x8];
3569 struct mlx5_ifc_query_pages_out_bits {
3571 u8 reserved_at_8[0x18];
3575 u8 reserved_at_40[0x10];
3576 u8 function_id[0x10];
3582 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3583 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3584 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3587 struct mlx5_ifc_query_pages_in_bits {
3589 u8 reserved_at_10[0x10];
3591 u8 reserved_at_20[0x10];
3594 u8 reserved_at_40[0x10];
3595 u8 function_id[0x10];
3597 u8 reserved_at_60[0x20];
3600 struct mlx5_ifc_query_nic_vport_context_out_bits {
3602 u8 reserved_at_8[0x18];
3606 u8 reserved_at_40[0x40];
3608 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3611 struct mlx5_ifc_query_nic_vport_context_in_bits {
3613 u8 reserved_at_10[0x10];
3615 u8 reserved_at_20[0x10];
3618 u8 other_vport[0x1];
3619 u8 reserved_at_41[0xf];
3620 u8 vport_number[0x10];
3622 u8 reserved_at_60[0x5];
3623 u8 allowed_list_type[0x3];
3624 u8 reserved_at_68[0x18];
3627 struct mlx5_ifc_query_mkey_out_bits {
3629 u8 reserved_at_8[0x18];
3633 u8 reserved_at_40[0x40];
3635 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3637 u8 reserved_at_280[0x600];
3639 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3641 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3644 struct mlx5_ifc_query_mkey_in_bits {
3646 u8 reserved_at_10[0x10];
3648 u8 reserved_at_20[0x10];
3651 u8 reserved_at_40[0x8];
3652 u8 mkey_index[0x18];
3655 u8 reserved_at_61[0x1f];
3658 struct mlx5_ifc_query_mad_demux_out_bits {
3660 u8 reserved_at_8[0x18];
3664 u8 reserved_at_40[0x40];
3666 u8 mad_dumux_parameters_block[0x20];
3669 struct mlx5_ifc_query_mad_demux_in_bits {
3671 u8 reserved_at_10[0x10];
3673 u8 reserved_at_20[0x10];
3676 u8 reserved_at_40[0x40];
3679 struct mlx5_ifc_query_l2_table_entry_out_bits {
3681 u8 reserved_at_8[0x18];
3685 u8 reserved_at_40[0xa0];
3687 u8 reserved_at_e0[0x13];
3691 struct mlx5_ifc_mac_address_layout_bits mac_address;
3693 u8 reserved_at_140[0xc0];
3696 struct mlx5_ifc_query_l2_table_entry_in_bits {
3698 u8 reserved_at_10[0x10];
3700 u8 reserved_at_20[0x10];
3703 u8 reserved_at_40[0x60];
3705 u8 reserved_at_a0[0x8];
3706 u8 table_index[0x18];
3708 u8 reserved_at_c0[0x140];
3711 struct mlx5_ifc_query_issi_out_bits {
3713 u8 reserved_at_8[0x18];
3717 u8 reserved_at_40[0x10];
3718 u8 current_issi[0x10];
3720 u8 reserved_at_60[0xa0];
3722 u8 reserved_at_100[76][0x8];
3723 u8 supported_issi_dw0[0x20];
3726 struct mlx5_ifc_query_issi_in_bits {
3728 u8 reserved_at_10[0x10];
3730 u8 reserved_at_20[0x10];
3733 u8 reserved_at_40[0x40];
3736 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3738 u8 reserved_at_8[0x18];
3742 u8 reserved_at_40[0x40];
3744 struct mlx5_ifc_pkey_bits pkey[0];
3747 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3749 u8 reserved_at_10[0x10];
3751 u8 reserved_at_20[0x10];
3754 u8 other_vport[0x1];
3755 u8 reserved_at_41[0xb];
3757 u8 vport_number[0x10];
3759 u8 reserved_at_60[0x10];
3760 u8 pkey_index[0x10];
3764 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3765 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3766 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3769 struct mlx5_ifc_query_hca_vport_gid_out_bits {
3771 u8 reserved_at_8[0x18];
3775 u8 reserved_at_40[0x20];
3778 u8 reserved_at_70[0x10];
3780 struct mlx5_ifc_array128_auto_bits gid[0];
3783 struct mlx5_ifc_query_hca_vport_gid_in_bits {
3785 u8 reserved_at_10[0x10];
3787 u8 reserved_at_20[0x10];
3790 u8 other_vport[0x1];
3791 u8 reserved_at_41[0xb];
3793 u8 vport_number[0x10];
3795 u8 reserved_at_60[0x10];
3799 struct mlx5_ifc_query_hca_vport_context_out_bits {
3801 u8 reserved_at_8[0x18];
3805 u8 reserved_at_40[0x40];
3807 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3810 struct mlx5_ifc_query_hca_vport_context_in_bits {
3812 u8 reserved_at_10[0x10];
3814 u8 reserved_at_20[0x10];
3817 u8 other_vport[0x1];
3818 u8 reserved_at_41[0xb];
3820 u8 vport_number[0x10];
3822 u8 reserved_at_60[0x20];
3825 struct mlx5_ifc_query_hca_cap_out_bits {
3827 u8 reserved_at_8[0x18];
3831 u8 reserved_at_40[0x40];
3833 union mlx5_ifc_hca_cap_union_bits capability;
3836 struct mlx5_ifc_query_hca_cap_in_bits {
3838 u8 reserved_at_10[0x10];
3840 u8 reserved_at_20[0x10];
3843 u8 reserved_at_40[0x40];
3846 struct mlx5_ifc_query_flow_table_out_bits {
3848 u8 reserved_at_8[0x18];
3852 u8 reserved_at_40[0x80];
3854 u8 reserved_at_c0[0x8];
3856 u8 reserved_at_d0[0x8];
3859 u8 reserved_at_e0[0x120];
3862 struct mlx5_ifc_query_flow_table_in_bits {
3864 u8 reserved_at_10[0x10];
3866 u8 reserved_at_20[0x10];
3869 u8 reserved_at_40[0x40];
3872 u8 reserved_at_88[0x18];
3874 u8 reserved_at_a0[0x8];
3877 u8 reserved_at_c0[0x140];
3880 struct mlx5_ifc_query_fte_out_bits {
3882 u8 reserved_at_8[0x18];
3886 u8 reserved_at_40[0x1c0];
3888 struct mlx5_ifc_flow_context_bits flow_context;
3891 struct mlx5_ifc_query_fte_in_bits {
3893 u8 reserved_at_10[0x10];
3895 u8 reserved_at_20[0x10];
3898 u8 reserved_at_40[0x40];
3901 u8 reserved_at_88[0x18];
3903 u8 reserved_at_a0[0x8];
3906 u8 reserved_at_c0[0x40];
3908 u8 flow_index[0x20];
3910 u8 reserved_at_120[0xe0];
3914 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3915 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3916 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3919 struct mlx5_ifc_query_flow_group_out_bits {
3921 u8 reserved_at_8[0x18];
3925 u8 reserved_at_40[0xa0];
3927 u8 start_flow_index[0x20];
3929 u8 reserved_at_100[0x20];
3931 u8 end_flow_index[0x20];
3933 u8 reserved_at_140[0xa0];
3935 u8 reserved_at_1e0[0x18];
3936 u8 match_criteria_enable[0x8];
3938 struct mlx5_ifc_fte_match_param_bits match_criteria;
3940 u8 reserved_at_1200[0xe00];
3943 struct mlx5_ifc_query_flow_group_in_bits {
3945 u8 reserved_at_10[0x10];
3947 u8 reserved_at_20[0x10];
3950 u8 reserved_at_40[0x40];
3953 u8 reserved_at_88[0x18];
3955 u8 reserved_at_a0[0x8];
3960 u8 reserved_at_e0[0x120];
3963 struct mlx5_ifc_query_flow_counter_out_bits {
3965 u8 reserved_at_8[0x18];
3969 u8 reserved_at_40[0x40];
3971 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
3974 struct mlx5_ifc_query_flow_counter_in_bits {
3976 u8 reserved_at_10[0x10];
3978 u8 reserved_at_20[0x10];
3981 u8 reserved_at_40[0x80];
3984 u8 reserved_at_c1[0xf];
3985 u8 num_of_counters[0x10];
3987 u8 reserved_at_e0[0x10];
3988 u8 flow_counter_id[0x10];
3991 struct mlx5_ifc_query_esw_vport_context_out_bits {
3993 u8 reserved_at_8[0x18];
3997 u8 reserved_at_40[0x40];
3999 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4002 struct mlx5_ifc_query_esw_vport_context_in_bits {
4004 u8 reserved_at_10[0x10];
4006 u8 reserved_at_20[0x10];
4009 u8 other_vport[0x1];
4010 u8 reserved_at_41[0xf];
4011 u8 vport_number[0x10];
4013 u8 reserved_at_60[0x20];
4016 struct mlx5_ifc_modify_esw_vport_context_out_bits {
4018 u8 reserved_at_8[0x18];
4022 u8 reserved_at_40[0x40];
4025 struct mlx5_ifc_esw_vport_context_fields_select_bits {
4026 u8 reserved_at_0[0x1c];
4027 u8 vport_cvlan_insert[0x1];
4028 u8 vport_svlan_insert[0x1];
4029 u8 vport_cvlan_strip[0x1];
4030 u8 vport_svlan_strip[0x1];
4033 struct mlx5_ifc_modify_esw_vport_context_in_bits {
4035 u8 reserved_at_10[0x10];
4037 u8 reserved_at_20[0x10];
4040 u8 other_vport[0x1];
4041 u8 reserved_at_41[0xf];
4042 u8 vport_number[0x10];
4044 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4046 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4049 struct mlx5_ifc_query_eq_out_bits {
4051 u8 reserved_at_8[0x18];
4055 u8 reserved_at_40[0x40];
4057 struct mlx5_ifc_eqc_bits eq_context_entry;
4059 u8 reserved_at_280[0x40];
4061 u8 event_bitmask[0x40];
4063 u8 reserved_at_300[0x580];
4068 struct mlx5_ifc_query_eq_in_bits {
4070 u8 reserved_at_10[0x10];
4072 u8 reserved_at_20[0x10];
4075 u8 reserved_at_40[0x18];
4078 u8 reserved_at_60[0x20];
4081 struct mlx5_ifc_query_dct_out_bits {
4083 u8 reserved_at_8[0x18];
4087 u8 reserved_at_40[0x40];
4089 struct mlx5_ifc_dctc_bits dct_context_entry;
4091 u8 reserved_at_280[0x180];
4094 struct mlx5_ifc_query_dct_in_bits {
4096 u8 reserved_at_10[0x10];
4098 u8 reserved_at_20[0x10];
4101 u8 reserved_at_40[0x8];
4104 u8 reserved_at_60[0x20];
4107 struct mlx5_ifc_query_cq_out_bits {
4109 u8 reserved_at_8[0x18];
4113 u8 reserved_at_40[0x40];
4115 struct mlx5_ifc_cqc_bits cq_context;
4117 u8 reserved_at_280[0x600];
4122 struct mlx5_ifc_query_cq_in_bits {
4124 u8 reserved_at_10[0x10];
4126 u8 reserved_at_20[0x10];
4129 u8 reserved_at_40[0x8];
4132 u8 reserved_at_60[0x20];
4135 struct mlx5_ifc_query_cong_status_out_bits {
4137 u8 reserved_at_8[0x18];
4141 u8 reserved_at_40[0x20];
4145 u8 reserved_at_62[0x1e];
4148 struct mlx5_ifc_query_cong_status_in_bits {
4150 u8 reserved_at_10[0x10];
4152 u8 reserved_at_20[0x10];
4155 u8 reserved_at_40[0x18];
4157 u8 cong_protocol[0x4];
4159 u8 reserved_at_60[0x20];
4162 struct mlx5_ifc_query_cong_statistics_out_bits {
4164 u8 reserved_at_8[0x18];
4168 u8 reserved_at_40[0x40];
4174 u8 cnp_ignored_high[0x20];
4176 u8 cnp_ignored_low[0x20];
4178 u8 cnp_handled_high[0x20];
4180 u8 cnp_handled_low[0x20];
4182 u8 reserved_at_140[0x100];
4184 u8 time_stamp_high[0x20];
4186 u8 time_stamp_low[0x20];
4188 u8 accumulators_period[0x20];
4190 u8 ecn_marked_roce_packets_high[0x20];
4192 u8 ecn_marked_roce_packets_low[0x20];
4194 u8 cnps_sent_high[0x20];
4196 u8 cnps_sent_low[0x20];
4198 u8 reserved_at_320[0x560];
4201 struct mlx5_ifc_query_cong_statistics_in_bits {
4203 u8 reserved_at_10[0x10];
4205 u8 reserved_at_20[0x10];
4209 u8 reserved_at_41[0x1f];
4211 u8 reserved_at_60[0x20];
4214 struct mlx5_ifc_query_cong_params_out_bits {
4216 u8 reserved_at_8[0x18];
4220 u8 reserved_at_40[0x40];
4222 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4225 struct mlx5_ifc_query_cong_params_in_bits {
4227 u8 reserved_at_10[0x10];
4229 u8 reserved_at_20[0x10];
4232 u8 reserved_at_40[0x1c];
4233 u8 cong_protocol[0x4];
4235 u8 reserved_at_60[0x20];
4238 struct mlx5_ifc_query_adapter_out_bits {
4240 u8 reserved_at_8[0x18];
4244 u8 reserved_at_40[0x40];
4246 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4249 struct mlx5_ifc_query_adapter_in_bits {
4251 u8 reserved_at_10[0x10];
4253 u8 reserved_at_20[0x10];
4256 u8 reserved_at_40[0x40];
4259 struct mlx5_ifc_qp_2rst_out_bits {
4261 u8 reserved_at_8[0x18];
4265 u8 reserved_at_40[0x40];
4268 struct mlx5_ifc_qp_2rst_in_bits {
4270 u8 reserved_at_10[0x10];
4272 u8 reserved_at_20[0x10];
4275 u8 reserved_at_40[0x8];
4278 u8 reserved_at_60[0x20];
4281 struct mlx5_ifc_qp_2err_out_bits {
4283 u8 reserved_at_8[0x18];
4287 u8 reserved_at_40[0x40];
4290 struct mlx5_ifc_qp_2err_in_bits {
4292 u8 reserved_at_10[0x10];
4294 u8 reserved_at_20[0x10];
4297 u8 reserved_at_40[0x8];
4300 u8 reserved_at_60[0x20];
4303 struct mlx5_ifc_page_fault_resume_out_bits {
4305 u8 reserved_at_8[0x18];
4309 u8 reserved_at_40[0x40];
4312 struct mlx5_ifc_page_fault_resume_in_bits {
4314 u8 reserved_at_10[0x10];
4316 u8 reserved_at_20[0x10];
4320 u8 reserved_at_41[0x4];
4326 u8 reserved_at_60[0x20];
4329 struct mlx5_ifc_nop_out_bits {
4331 u8 reserved_at_8[0x18];
4335 u8 reserved_at_40[0x40];
4338 struct mlx5_ifc_nop_in_bits {
4340 u8 reserved_at_10[0x10];
4342 u8 reserved_at_20[0x10];
4345 u8 reserved_at_40[0x40];
4348 struct mlx5_ifc_modify_vport_state_out_bits {
4350 u8 reserved_at_8[0x18];
4354 u8 reserved_at_40[0x40];
4357 struct mlx5_ifc_modify_vport_state_in_bits {
4359 u8 reserved_at_10[0x10];
4361 u8 reserved_at_20[0x10];
4364 u8 other_vport[0x1];
4365 u8 reserved_at_41[0xf];
4366 u8 vport_number[0x10];
4368 u8 reserved_at_60[0x18];
4369 u8 admin_state[0x4];
4370 u8 reserved_at_7c[0x4];
4373 struct mlx5_ifc_modify_tis_out_bits {
4375 u8 reserved_at_8[0x18];
4379 u8 reserved_at_40[0x40];
4382 struct mlx5_ifc_modify_tis_bitmask_bits {
4383 u8 reserved_at_0[0x20];
4385 u8 reserved_at_20[0x1f];
4389 struct mlx5_ifc_modify_tis_in_bits {
4391 u8 reserved_at_10[0x10];
4393 u8 reserved_at_20[0x10];
4396 u8 reserved_at_40[0x8];
4399 u8 reserved_at_60[0x20];
4401 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
4403 u8 reserved_at_c0[0x40];
4405 struct mlx5_ifc_tisc_bits ctx;
4408 struct mlx5_ifc_modify_tir_bitmask_bits {
4409 u8 reserved_at_0[0x20];
4411 u8 reserved_at_20[0x1b];
4413 u8 reserved_at_3c[0x1];
4415 u8 reserved_at_3e[0x1];
4419 struct mlx5_ifc_modify_tir_out_bits {
4421 u8 reserved_at_8[0x18];
4425 u8 reserved_at_40[0x40];
4428 struct mlx5_ifc_modify_tir_in_bits {
4430 u8 reserved_at_10[0x10];
4432 u8 reserved_at_20[0x10];
4435 u8 reserved_at_40[0x8];
4438 u8 reserved_at_60[0x20];
4440 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
4442 u8 reserved_at_c0[0x40];
4444 struct mlx5_ifc_tirc_bits ctx;
4447 struct mlx5_ifc_modify_sq_out_bits {
4449 u8 reserved_at_8[0x18];
4453 u8 reserved_at_40[0x40];
4456 struct mlx5_ifc_modify_sq_in_bits {
4458 u8 reserved_at_10[0x10];
4460 u8 reserved_at_20[0x10];
4464 u8 reserved_at_44[0x4];
4467 u8 reserved_at_60[0x20];
4469 u8 modify_bitmask[0x40];
4471 u8 reserved_at_c0[0x40];
4473 struct mlx5_ifc_sqc_bits ctx;
4476 struct mlx5_ifc_modify_rqt_out_bits {
4478 u8 reserved_at_8[0x18];
4482 u8 reserved_at_40[0x40];
4485 struct mlx5_ifc_rqt_bitmask_bits {
4486 u8 reserved_at_0[0x20];
4488 u8 reserved_at_20[0x1f];
4492 struct mlx5_ifc_modify_rqt_in_bits {
4494 u8 reserved_at_10[0x10];
4496 u8 reserved_at_20[0x10];
4499 u8 reserved_at_40[0x8];
4502 u8 reserved_at_60[0x20];
4504 struct mlx5_ifc_rqt_bitmask_bits bitmask;
4506 u8 reserved_at_c0[0x40];
4508 struct mlx5_ifc_rqtc_bits ctx;
4511 struct mlx5_ifc_modify_rq_out_bits {
4513 u8 reserved_at_8[0x18];
4517 u8 reserved_at_40[0x40];
4520 struct mlx5_ifc_modify_rq_in_bits {
4522 u8 reserved_at_10[0x10];
4524 u8 reserved_at_20[0x10];
4528 u8 reserved_at_44[0x4];
4531 u8 reserved_at_60[0x20];
4533 u8 modify_bitmask[0x40];
4535 u8 reserved_at_c0[0x40];
4537 struct mlx5_ifc_rqc_bits ctx;
4540 struct mlx5_ifc_modify_rmp_out_bits {
4542 u8 reserved_at_8[0x18];
4546 u8 reserved_at_40[0x40];
4549 struct mlx5_ifc_rmp_bitmask_bits {
4550 u8 reserved_at_0[0x20];
4552 u8 reserved_at_20[0x1f];
4556 struct mlx5_ifc_modify_rmp_in_bits {
4558 u8 reserved_at_10[0x10];
4560 u8 reserved_at_20[0x10];
4564 u8 reserved_at_44[0x4];
4567 u8 reserved_at_60[0x20];
4569 struct mlx5_ifc_rmp_bitmask_bits bitmask;
4571 u8 reserved_at_c0[0x40];
4573 struct mlx5_ifc_rmpc_bits ctx;
4576 struct mlx5_ifc_modify_nic_vport_context_out_bits {
4578 u8 reserved_at_8[0x18];
4582 u8 reserved_at_40[0x40];
4585 struct mlx5_ifc_modify_nic_vport_field_select_bits {
4586 u8 reserved_at_0[0x19];
4588 u8 change_event[0x1];
4590 u8 permanent_address[0x1];
4591 u8 addresses_list[0x1];
4593 u8 reserved_at_1f[0x1];
4596 struct mlx5_ifc_modify_nic_vport_context_in_bits {
4598 u8 reserved_at_10[0x10];
4600 u8 reserved_at_20[0x10];
4603 u8 other_vport[0x1];
4604 u8 reserved_at_41[0xf];
4605 u8 vport_number[0x10];
4607 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4609 u8 reserved_at_80[0x780];
4611 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4614 struct mlx5_ifc_modify_hca_vport_context_out_bits {
4616 u8 reserved_at_8[0x18];
4620 u8 reserved_at_40[0x40];
4623 struct mlx5_ifc_modify_hca_vport_context_in_bits {
4625 u8 reserved_at_10[0x10];
4627 u8 reserved_at_20[0x10];
4630 u8 other_vport[0x1];
4631 u8 reserved_at_41[0xb];
4633 u8 vport_number[0x10];
4635 u8 reserved_at_60[0x20];
4637 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4640 struct mlx5_ifc_modify_cq_out_bits {
4642 u8 reserved_at_8[0x18];
4646 u8 reserved_at_40[0x40];
4650 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4651 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4654 struct mlx5_ifc_modify_cq_in_bits {
4656 u8 reserved_at_10[0x10];
4658 u8 reserved_at_20[0x10];
4661 u8 reserved_at_40[0x8];
4664 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4666 struct mlx5_ifc_cqc_bits cq_context;
4668 u8 reserved_at_280[0x600];
4673 struct mlx5_ifc_modify_cong_status_out_bits {
4675 u8 reserved_at_8[0x18];
4679 u8 reserved_at_40[0x40];
4682 struct mlx5_ifc_modify_cong_status_in_bits {
4684 u8 reserved_at_10[0x10];
4686 u8 reserved_at_20[0x10];
4689 u8 reserved_at_40[0x18];
4691 u8 cong_protocol[0x4];
4695 u8 reserved_at_62[0x1e];
4698 struct mlx5_ifc_modify_cong_params_out_bits {
4700 u8 reserved_at_8[0x18];
4704 u8 reserved_at_40[0x40];
4707 struct mlx5_ifc_modify_cong_params_in_bits {
4709 u8 reserved_at_10[0x10];
4711 u8 reserved_at_20[0x10];
4714 u8 reserved_at_40[0x1c];
4715 u8 cong_protocol[0x4];
4717 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4719 u8 reserved_at_80[0x80];
4721 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4724 struct mlx5_ifc_manage_pages_out_bits {
4726 u8 reserved_at_8[0x18];
4730 u8 output_num_entries[0x20];
4732 u8 reserved_at_60[0x20];
4738 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4739 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4740 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4743 struct mlx5_ifc_manage_pages_in_bits {
4745 u8 reserved_at_10[0x10];
4747 u8 reserved_at_20[0x10];
4750 u8 reserved_at_40[0x10];
4751 u8 function_id[0x10];
4753 u8 input_num_entries[0x20];
4758 struct mlx5_ifc_mad_ifc_out_bits {
4760 u8 reserved_at_8[0x18];
4764 u8 reserved_at_40[0x40];
4766 u8 response_mad_packet[256][0x8];
4769 struct mlx5_ifc_mad_ifc_in_bits {
4771 u8 reserved_at_10[0x10];
4773 u8 reserved_at_20[0x10];
4776 u8 remote_lid[0x10];
4777 u8 reserved_at_50[0x8];
4780 u8 reserved_at_60[0x20];
4785 struct mlx5_ifc_init_hca_out_bits {
4787 u8 reserved_at_8[0x18];
4791 u8 reserved_at_40[0x40];
4794 struct mlx5_ifc_init_hca_in_bits {
4796 u8 reserved_at_10[0x10];
4798 u8 reserved_at_20[0x10];
4801 u8 reserved_at_40[0x40];
4804 struct mlx5_ifc_init2rtr_qp_out_bits {
4806 u8 reserved_at_8[0x18];
4810 u8 reserved_at_40[0x40];
4813 struct mlx5_ifc_init2rtr_qp_in_bits {
4815 u8 reserved_at_10[0x10];
4817 u8 reserved_at_20[0x10];
4820 u8 reserved_at_40[0x8];
4823 u8 reserved_at_60[0x20];
4825 u8 opt_param_mask[0x20];
4827 u8 reserved_at_a0[0x20];
4829 struct mlx5_ifc_qpc_bits qpc;
4831 u8 reserved_at_800[0x80];
4834 struct mlx5_ifc_init2init_qp_out_bits {
4836 u8 reserved_at_8[0x18];
4840 u8 reserved_at_40[0x40];
4843 struct mlx5_ifc_init2init_qp_in_bits {
4845 u8 reserved_at_10[0x10];
4847 u8 reserved_at_20[0x10];
4850 u8 reserved_at_40[0x8];
4853 u8 reserved_at_60[0x20];
4855 u8 opt_param_mask[0x20];
4857 u8 reserved_at_a0[0x20];
4859 struct mlx5_ifc_qpc_bits qpc;
4861 u8 reserved_at_800[0x80];
4864 struct mlx5_ifc_get_dropped_packet_log_out_bits {
4866 u8 reserved_at_8[0x18];
4870 u8 reserved_at_40[0x40];
4872 u8 packet_headers_log[128][0x8];
4874 u8 packet_syndrome[64][0x8];
4877 struct mlx5_ifc_get_dropped_packet_log_in_bits {
4879 u8 reserved_at_10[0x10];
4881 u8 reserved_at_20[0x10];
4884 u8 reserved_at_40[0x40];
4887 struct mlx5_ifc_gen_eqe_in_bits {
4889 u8 reserved_at_10[0x10];
4891 u8 reserved_at_20[0x10];
4894 u8 reserved_at_40[0x18];
4897 u8 reserved_at_60[0x20];
4902 struct mlx5_ifc_gen_eq_out_bits {
4904 u8 reserved_at_8[0x18];
4908 u8 reserved_at_40[0x40];
4911 struct mlx5_ifc_enable_hca_out_bits {
4913 u8 reserved_at_8[0x18];
4917 u8 reserved_at_40[0x20];
4920 struct mlx5_ifc_enable_hca_in_bits {
4922 u8 reserved_at_10[0x10];
4924 u8 reserved_at_20[0x10];
4927 u8 reserved_at_40[0x10];
4928 u8 function_id[0x10];
4930 u8 reserved_at_60[0x20];
4933 struct mlx5_ifc_drain_dct_out_bits {
4935 u8 reserved_at_8[0x18];
4939 u8 reserved_at_40[0x40];
4942 struct mlx5_ifc_drain_dct_in_bits {
4944 u8 reserved_at_10[0x10];
4946 u8 reserved_at_20[0x10];
4949 u8 reserved_at_40[0x8];
4952 u8 reserved_at_60[0x20];
4955 struct mlx5_ifc_disable_hca_out_bits {
4957 u8 reserved_at_8[0x18];
4961 u8 reserved_at_40[0x20];
4964 struct mlx5_ifc_disable_hca_in_bits {
4966 u8 reserved_at_10[0x10];
4968 u8 reserved_at_20[0x10];
4971 u8 reserved_at_40[0x10];
4972 u8 function_id[0x10];
4974 u8 reserved_at_60[0x20];
4977 struct mlx5_ifc_detach_from_mcg_out_bits {
4979 u8 reserved_at_8[0x18];
4983 u8 reserved_at_40[0x40];
4986 struct mlx5_ifc_detach_from_mcg_in_bits {
4988 u8 reserved_at_10[0x10];
4990 u8 reserved_at_20[0x10];
4993 u8 reserved_at_40[0x8];
4996 u8 reserved_at_60[0x20];
4998 u8 multicast_gid[16][0x8];
5001 struct mlx5_ifc_destroy_xrc_srq_out_bits {
5003 u8 reserved_at_8[0x18];
5007 u8 reserved_at_40[0x40];
5010 struct mlx5_ifc_destroy_xrc_srq_in_bits {
5012 u8 reserved_at_10[0x10];
5014 u8 reserved_at_20[0x10];
5017 u8 reserved_at_40[0x8];
5020 u8 reserved_at_60[0x20];
5023 struct mlx5_ifc_destroy_tis_out_bits {
5025 u8 reserved_at_8[0x18];
5029 u8 reserved_at_40[0x40];
5032 struct mlx5_ifc_destroy_tis_in_bits {
5034 u8 reserved_at_10[0x10];
5036 u8 reserved_at_20[0x10];
5039 u8 reserved_at_40[0x8];
5042 u8 reserved_at_60[0x20];
5045 struct mlx5_ifc_destroy_tir_out_bits {
5047 u8 reserved_at_8[0x18];
5051 u8 reserved_at_40[0x40];
5054 struct mlx5_ifc_destroy_tir_in_bits {
5056 u8 reserved_at_10[0x10];
5058 u8 reserved_at_20[0x10];
5061 u8 reserved_at_40[0x8];
5064 u8 reserved_at_60[0x20];
5067 struct mlx5_ifc_destroy_srq_out_bits {
5069 u8 reserved_at_8[0x18];
5073 u8 reserved_at_40[0x40];
5076 struct mlx5_ifc_destroy_srq_in_bits {
5078 u8 reserved_at_10[0x10];
5080 u8 reserved_at_20[0x10];
5083 u8 reserved_at_40[0x8];
5086 u8 reserved_at_60[0x20];
5089 struct mlx5_ifc_destroy_sq_out_bits {
5091 u8 reserved_at_8[0x18];
5095 u8 reserved_at_40[0x40];
5098 struct mlx5_ifc_destroy_sq_in_bits {
5100 u8 reserved_at_10[0x10];
5102 u8 reserved_at_20[0x10];
5105 u8 reserved_at_40[0x8];
5108 u8 reserved_at_60[0x20];
5111 struct mlx5_ifc_destroy_rqt_out_bits {
5113 u8 reserved_at_8[0x18];
5117 u8 reserved_at_40[0x40];
5120 struct mlx5_ifc_destroy_rqt_in_bits {
5122 u8 reserved_at_10[0x10];
5124 u8 reserved_at_20[0x10];
5127 u8 reserved_at_40[0x8];
5130 u8 reserved_at_60[0x20];
5133 struct mlx5_ifc_destroy_rq_out_bits {
5135 u8 reserved_at_8[0x18];
5139 u8 reserved_at_40[0x40];
5142 struct mlx5_ifc_destroy_rq_in_bits {
5144 u8 reserved_at_10[0x10];
5146 u8 reserved_at_20[0x10];
5149 u8 reserved_at_40[0x8];
5152 u8 reserved_at_60[0x20];
5155 struct mlx5_ifc_destroy_rmp_out_bits {
5157 u8 reserved_at_8[0x18];
5161 u8 reserved_at_40[0x40];
5164 struct mlx5_ifc_destroy_rmp_in_bits {
5166 u8 reserved_at_10[0x10];
5168 u8 reserved_at_20[0x10];
5171 u8 reserved_at_40[0x8];
5174 u8 reserved_at_60[0x20];
5177 struct mlx5_ifc_destroy_qp_out_bits {
5179 u8 reserved_at_8[0x18];
5183 u8 reserved_at_40[0x40];
5186 struct mlx5_ifc_destroy_qp_in_bits {
5188 u8 reserved_at_10[0x10];
5190 u8 reserved_at_20[0x10];
5193 u8 reserved_at_40[0x8];
5196 u8 reserved_at_60[0x20];
5199 struct mlx5_ifc_destroy_psv_out_bits {
5201 u8 reserved_at_8[0x18];
5205 u8 reserved_at_40[0x40];
5208 struct mlx5_ifc_destroy_psv_in_bits {
5210 u8 reserved_at_10[0x10];
5212 u8 reserved_at_20[0x10];
5215 u8 reserved_at_40[0x8];
5218 u8 reserved_at_60[0x20];
5221 struct mlx5_ifc_destroy_mkey_out_bits {
5223 u8 reserved_at_8[0x18];
5227 u8 reserved_at_40[0x40];
5230 struct mlx5_ifc_destroy_mkey_in_bits {
5232 u8 reserved_at_10[0x10];
5234 u8 reserved_at_20[0x10];
5237 u8 reserved_at_40[0x8];
5238 u8 mkey_index[0x18];
5240 u8 reserved_at_60[0x20];
5243 struct mlx5_ifc_destroy_flow_table_out_bits {
5245 u8 reserved_at_8[0x18];
5249 u8 reserved_at_40[0x40];
5252 struct mlx5_ifc_destroy_flow_table_in_bits {
5254 u8 reserved_at_10[0x10];
5256 u8 reserved_at_20[0x10];
5259 u8 other_vport[0x1];
5260 u8 reserved_at_41[0xf];
5261 u8 vport_number[0x10];
5263 u8 reserved_at_60[0x20];
5266 u8 reserved_at_88[0x18];
5268 u8 reserved_at_a0[0x8];
5271 u8 reserved_at_c0[0x140];
5274 struct mlx5_ifc_destroy_flow_group_out_bits {
5276 u8 reserved_at_8[0x18];
5280 u8 reserved_at_40[0x40];
5283 struct mlx5_ifc_destroy_flow_group_in_bits {
5285 u8 reserved_at_10[0x10];
5287 u8 reserved_at_20[0x10];
5290 u8 other_vport[0x1];
5291 u8 reserved_at_41[0xf];
5292 u8 vport_number[0x10];
5294 u8 reserved_at_60[0x20];
5297 u8 reserved_at_88[0x18];
5299 u8 reserved_at_a0[0x8];
5304 u8 reserved_at_e0[0x120];
5307 struct mlx5_ifc_destroy_eq_out_bits {
5309 u8 reserved_at_8[0x18];
5313 u8 reserved_at_40[0x40];
5316 struct mlx5_ifc_destroy_eq_in_bits {
5318 u8 reserved_at_10[0x10];
5320 u8 reserved_at_20[0x10];
5323 u8 reserved_at_40[0x18];
5326 u8 reserved_at_60[0x20];
5329 struct mlx5_ifc_destroy_dct_out_bits {
5331 u8 reserved_at_8[0x18];
5335 u8 reserved_at_40[0x40];
5338 struct mlx5_ifc_destroy_dct_in_bits {
5340 u8 reserved_at_10[0x10];
5342 u8 reserved_at_20[0x10];
5345 u8 reserved_at_40[0x8];
5348 u8 reserved_at_60[0x20];
5351 struct mlx5_ifc_destroy_cq_out_bits {
5353 u8 reserved_at_8[0x18];
5357 u8 reserved_at_40[0x40];
5360 struct mlx5_ifc_destroy_cq_in_bits {
5362 u8 reserved_at_10[0x10];
5364 u8 reserved_at_20[0x10];
5367 u8 reserved_at_40[0x8];
5370 u8 reserved_at_60[0x20];
5373 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5375 u8 reserved_at_8[0x18];
5379 u8 reserved_at_40[0x40];
5382 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5384 u8 reserved_at_10[0x10];
5386 u8 reserved_at_20[0x10];
5389 u8 reserved_at_40[0x20];
5391 u8 reserved_at_60[0x10];
5392 u8 vxlan_udp_port[0x10];
5395 struct mlx5_ifc_delete_l2_table_entry_out_bits {
5397 u8 reserved_at_8[0x18];
5401 u8 reserved_at_40[0x40];
5404 struct mlx5_ifc_delete_l2_table_entry_in_bits {
5406 u8 reserved_at_10[0x10];
5408 u8 reserved_at_20[0x10];
5411 u8 reserved_at_40[0x60];
5413 u8 reserved_at_a0[0x8];
5414 u8 table_index[0x18];
5416 u8 reserved_at_c0[0x140];
5419 struct mlx5_ifc_delete_fte_out_bits {
5421 u8 reserved_at_8[0x18];
5425 u8 reserved_at_40[0x40];
5428 struct mlx5_ifc_delete_fte_in_bits {
5430 u8 reserved_at_10[0x10];
5432 u8 reserved_at_20[0x10];
5435 u8 other_vport[0x1];
5436 u8 reserved_at_41[0xf];
5437 u8 vport_number[0x10];
5439 u8 reserved_at_60[0x20];
5442 u8 reserved_at_88[0x18];
5444 u8 reserved_at_a0[0x8];
5447 u8 reserved_at_c0[0x40];
5449 u8 flow_index[0x20];
5451 u8 reserved_at_120[0xe0];
5454 struct mlx5_ifc_dealloc_xrcd_out_bits {
5456 u8 reserved_at_8[0x18];
5460 u8 reserved_at_40[0x40];
5463 struct mlx5_ifc_dealloc_xrcd_in_bits {
5465 u8 reserved_at_10[0x10];
5467 u8 reserved_at_20[0x10];
5470 u8 reserved_at_40[0x8];
5473 u8 reserved_at_60[0x20];
5476 struct mlx5_ifc_dealloc_uar_out_bits {
5478 u8 reserved_at_8[0x18];
5482 u8 reserved_at_40[0x40];
5485 struct mlx5_ifc_dealloc_uar_in_bits {
5487 u8 reserved_at_10[0x10];
5489 u8 reserved_at_20[0x10];
5492 u8 reserved_at_40[0x8];
5495 u8 reserved_at_60[0x20];
5498 struct mlx5_ifc_dealloc_transport_domain_out_bits {
5500 u8 reserved_at_8[0x18];
5504 u8 reserved_at_40[0x40];
5507 struct mlx5_ifc_dealloc_transport_domain_in_bits {
5509 u8 reserved_at_10[0x10];
5511 u8 reserved_at_20[0x10];
5514 u8 reserved_at_40[0x8];
5515 u8 transport_domain[0x18];
5517 u8 reserved_at_60[0x20];
5520 struct mlx5_ifc_dealloc_q_counter_out_bits {
5522 u8 reserved_at_8[0x18];
5526 u8 reserved_at_40[0x40];
5529 struct mlx5_ifc_dealloc_q_counter_in_bits {
5531 u8 reserved_at_10[0x10];
5533 u8 reserved_at_20[0x10];
5536 u8 reserved_at_40[0x18];
5537 u8 counter_set_id[0x8];
5539 u8 reserved_at_60[0x20];
5542 struct mlx5_ifc_dealloc_pd_out_bits {
5544 u8 reserved_at_8[0x18];
5548 u8 reserved_at_40[0x40];
5551 struct mlx5_ifc_dealloc_pd_in_bits {
5553 u8 reserved_at_10[0x10];
5555 u8 reserved_at_20[0x10];
5558 u8 reserved_at_40[0x8];
5561 u8 reserved_at_60[0x20];
5564 struct mlx5_ifc_dealloc_flow_counter_out_bits {
5566 u8 reserved_at_8[0x18];
5570 u8 reserved_at_40[0x40];
5573 struct mlx5_ifc_dealloc_flow_counter_in_bits {
5575 u8 reserved_at_10[0x10];
5577 u8 reserved_at_20[0x10];
5580 u8 reserved_at_40[0x10];
5581 u8 flow_counter_id[0x10];
5583 u8 reserved_at_60[0x20];
5586 struct mlx5_ifc_create_xrc_srq_out_bits {
5588 u8 reserved_at_8[0x18];
5592 u8 reserved_at_40[0x8];
5595 u8 reserved_at_60[0x20];
5598 struct mlx5_ifc_create_xrc_srq_in_bits {
5600 u8 reserved_at_10[0x10];
5602 u8 reserved_at_20[0x10];
5605 u8 reserved_at_40[0x40];
5607 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5609 u8 reserved_at_280[0x600];
5614 struct mlx5_ifc_create_tis_out_bits {
5616 u8 reserved_at_8[0x18];
5620 u8 reserved_at_40[0x8];
5623 u8 reserved_at_60[0x20];
5626 struct mlx5_ifc_create_tis_in_bits {
5628 u8 reserved_at_10[0x10];
5630 u8 reserved_at_20[0x10];
5633 u8 reserved_at_40[0xc0];
5635 struct mlx5_ifc_tisc_bits ctx;
5638 struct mlx5_ifc_create_tir_out_bits {
5640 u8 reserved_at_8[0x18];
5644 u8 reserved_at_40[0x8];
5647 u8 reserved_at_60[0x20];
5650 struct mlx5_ifc_create_tir_in_bits {
5652 u8 reserved_at_10[0x10];
5654 u8 reserved_at_20[0x10];
5657 u8 reserved_at_40[0xc0];
5659 struct mlx5_ifc_tirc_bits ctx;
5662 struct mlx5_ifc_create_srq_out_bits {
5664 u8 reserved_at_8[0x18];
5668 u8 reserved_at_40[0x8];
5671 u8 reserved_at_60[0x20];
5674 struct mlx5_ifc_create_srq_in_bits {
5676 u8 reserved_at_10[0x10];
5678 u8 reserved_at_20[0x10];
5681 u8 reserved_at_40[0x40];
5683 struct mlx5_ifc_srqc_bits srq_context_entry;
5685 u8 reserved_at_280[0x600];
5690 struct mlx5_ifc_create_sq_out_bits {
5692 u8 reserved_at_8[0x18];
5696 u8 reserved_at_40[0x8];
5699 u8 reserved_at_60[0x20];
5702 struct mlx5_ifc_create_sq_in_bits {
5704 u8 reserved_at_10[0x10];
5706 u8 reserved_at_20[0x10];
5709 u8 reserved_at_40[0xc0];
5711 struct mlx5_ifc_sqc_bits ctx;
5714 struct mlx5_ifc_create_rqt_out_bits {
5716 u8 reserved_at_8[0x18];
5720 u8 reserved_at_40[0x8];
5723 u8 reserved_at_60[0x20];
5726 struct mlx5_ifc_create_rqt_in_bits {
5728 u8 reserved_at_10[0x10];
5730 u8 reserved_at_20[0x10];
5733 u8 reserved_at_40[0xc0];
5735 struct mlx5_ifc_rqtc_bits rqt_context;
5738 struct mlx5_ifc_create_rq_out_bits {
5740 u8 reserved_at_8[0x18];
5744 u8 reserved_at_40[0x8];
5747 u8 reserved_at_60[0x20];
5750 struct mlx5_ifc_create_rq_in_bits {
5752 u8 reserved_at_10[0x10];
5754 u8 reserved_at_20[0x10];
5757 u8 reserved_at_40[0xc0];
5759 struct mlx5_ifc_rqc_bits ctx;
5762 struct mlx5_ifc_create_rmp_out_bits {
5764 u8 reserved_at_8[0x18];
5768 u8 reserved_at_40[0x8];
5771 u8 reserved_at_60[0x20];
5774 struct mlx5_ifc_create_rmp_in_bits {
5776 u8 reserved_at_10[0x10];
5778 u8 reserved_at_20[0x10];
5781 u8 reserved_at_40[0xc0];
5783 struct mlx5_ifc_rmpc_bits ctx;
5786 struct mlx5_ifc_create_qp_out_bits {
5788 u8 reserved_at_8[0x18];
5792 u8 reserved_at_40[0x8];
5795 u8 reserved_at_60[0x20];
5798 struct mlx5_ifc_create_qp_in_bits {
5800 u8 reserved_at_10[0x10];
5802 u8 reserved_at_20[0x10];
5805 u8 reserved_at_40[0x40];
5807 u8 opt_param_mask[0x20];
5809 u8 reserved_at_a0[0x20];
5811 struct mlx5_ifc_qpc_bits qpc;
5813 u8 reserved_at_800[0x80];
5818 struct mlx5_ifc_create_psv_out_bits {
5820 u8 reserved_at_8[0x18];
5824 u8 reserved_at_40[0x40];
5826 u8 reserved_at_80[0x8];
5827 u8 psv0_index[0x18];
5829 u8 reserved_at_a0[0x8];
5830 u8 psv1_index[0x18];
5832 u8 reserved_at_c0[0x8];
5833 u8 psv2_index[0x18];
5835 u8 reserved_at_e0[0x8];
5836 u8 psv3_index[0x18];
5839 struct mlx5_ifc_create_psv_in_bits {
5841 u8 reserved_at_10[0x10];
5843 u8 reserved_at_20[0x10];
5847 u8 reserved_at_44[0x4];
5850 u8 reserved_at_60[0x20];
5853 struct mlx5_ifc_create_mkey_out_bits {
5855 u8 reserved_at_8[0x18];
5859 u8 reserved_at_40[0x8];
5860 u8 mkey_index[0x18];
5862 u8 reserved_at_60[0x20];
5865 struct mlx5_ifc_create_mkey_in_bits {
5867 u8 reserved_at_10[0x10];
5869 u8 reserved_at_20[0x10];
5872 u8 reserved_at_40[0x20];
5875 u8 reserved_at_61[0x1f];
5877 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5879 u8 reserved_at_280[0x80];
5881 u8 translations_octword_actual_size[0x20];
5883 u8 reserved_at_320[0x560];
5885 u8 klm_pas_mtt[0][0x20];
5888 struct mlx5_ifc_create_flow_table_out_bits {
5890 u8 reserved_at_8[0x18];
5894 u8 reserved_at_40[0x8];
5897 u8 reserved_at_60[0x20];
5900 struct mlx5_ifc_create_flow_table_in_bits {
5902 u8 reserved_at_10[0x10];
5904 u8 reserved_at_20[0x10];
5907 u8 other_vport[0x1];
5908 u8 reserved_at_41[0xf];
5909 u8 vport_number[0x10];
5911 u8 reserved_at_60[0x20];
5914 u8 reserved_at_88[0x18];
5916 u8 reserved_at_a0[0x20];
5918 u8 reserved_at_c0[0x4];
5919 u8 table_miss_mode[0x4];
5921 u8 reserved_at_d0[0x8];
5924 u8 reserved_at_e0[0x8];
5925 u8 table_miss_id[0x18];
5927 u8 reserved_at_100[0x100];
5930 struct mlx5_ifc_create_flow_group_out_bits {
5932 u8 reserved_at_8[0x18];
5936 u8 reserved_at_40[0x8];
5939 u8 reserved_at_60[0x20];
5943 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5944 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5945 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5948 struct mlx5_ifc_create_flow_group_in_bits {
5950 u8 reserved_at_10[0x10];
5952 u8 reserved_at_20[0x10];
5955 u8 other_vport[0x1];
5956 u8 reserved_at_41[0xf];
5957 u8 vport_number[0x10];
5959 u8 reserved_at_60[0x20];
5962 u8 reserved_at_88[0x18];
5964 u8 reserved_at_a0[0x8];
5967 u8 reserved_at_c0[0x20];
5969 u8 start_flow_index[0x20];
5971 u8 reserved_at_100[0x20];
5973 u8 end_flow_index[0x20];
5975 u8 reserved_at_140[0xa0];
5977 u8 reserved_at_1e0[0x18];
5978 u8 match_criteria_enable[0x8];
5980 struct mlx5_ifc_fte_match_param_bits match_criteria;
5982 u8 reserved_at_1200[0xe00];
5985 struct mlx5_ifc_create_eq_out_bits {
5987 u8 reserved_at_8[0x18];
5991 u8 reserved_at_40[0x18];
5994 u8 reserved_at_60[0x20];
5997 struct mlx5_ifc_create_eq_in_bits {
5999 u8 reserved_at_10[0x10];
6001 u8 reserved_at_20[0x10];
6004 u8 reserved_at_40[0x40];
6006 struct mlx5_ifc_eqc_bits eq_context_entry;
6008 u8 reserved_at_280[0x40];
6010 u8 event_bitmask[0x40];
6012 u8 reserved_at_300[0x580];
6017 struct mlx5_ifc_create_dct_out_bits {
6019 u8 reserved_at_8[0x18];
6023 u8 reserved_at_40[0x8];
6026 u8 reserved_at_60[0x20];
6029 struct mlx5_ifc_create_dct_in_bits {
6031 u8 reserved_at_10[0x10];
6033 u8 reserved_at_20[0x10];
6036 u8 reserved_at_40[0x40];
6038 struct mlx5_ifc_dctc_bits dct_context_entry;
6040 u8 reserved_at_280[0x180];
6043 struct mlx5_ifc_create_cq_out_bits {
6045 u8 reserved_at_8[0x18];
6049 u8 reserved_at_40[0x8];
6052 u8 reserved_at_60[0x20];
6055 struct mlx5_ifc_create_cq_in_bits {
6057 u8 reserved_at_10[0x10];
6059 u8 reserved_at_20[0x10];
6062 u8 reserved_at_40[0x40];
6064 struct mlx5_ifc_cqc_bits cq_context;
6066 u8 reserved_at_280[0x600];
6071 struct mlx5_ifc_config_int_moderation_out_bits {
6073 u8 reserved_at_8[0x18];
6077 u8 reserved_at_40[0x4];
6079 u8 int_vector[0x10];
6081 u8 reserved_at_60[0x20];
6085 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6086 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6089 struct mlx5_ifc_config_int_moderation_in_bits {
6091 u8 reserved_at_10[0x10];
6093 u8 reserved_at_20[0x10];
6096 u8 reserved_at_40[0x4];
6098 u8 int_vector[0x10];
6100 u8 reserved_at_60[0x20];
6103 struct mlx5_ifc_attach_to_mcg_out_bits {
6105 u8 reserved_at_8[0x18];
6109 u8 reserved_at_40[0x40];
6112 struct mlx5_ifc_attach_to_mcg_in_bits {
6114 u8 reserved_at_10[0x10];
6116 u8 reserved_at_20[0x10];
6119 u8 reserved_at_40[0x8];
6122 u8 reserved_at_60[0x20];
6124 u8 multicast_gid[16][0x8];
6127 struct mlx5_ifc_arm_xrc_srq_out_bits {
6129 u8 reserved_at_8[0x18];
6133 u8 reserved_at_40[0x40];
6137 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6140 struct mlx5_ifc_arm_xrc_srq_in_bits {
6142 u8 reserved_at_10[0x10];
6144 u8 reserved_at_20[0x10];
6147 u8 reserved_at_40[0x8];
6150 u8 reserved_at_60[0x10];
6154 struct mlx5_ifc_arm_rq_out_bits {
6156 u8 reserved_at_8[0x18];
6160 u8 reserved_at_40[0x40];
6164 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
6167 struct mlx5_ifc_arm_rq_in_bits {
6169 u8 reserved_at_10[0x10];
6171 u8 reserved_at_20[0x10];
6174 u8 reserved_at_40[0x8];
6175 u8 srq_number[0x18];
6177 u8 reserved_at_60[0x10];
6181 struct mlx5_ifc_arm_dct_out_bits {
6183 u8 reserved_at_8[0x18];
6187 u8 reserved_at_40[0x40];
6190 struct mlx5_ifc_arm_dct_in_bits {
6192 u8 reserved_at_10[0x10];
6194 u8 reserved_at_20[0x10];
6197 u8 reserved_at_40[0x8];
6198 u8 dct_number[0x18];
6200 u8 reserved_at_60[0x20];
6203 struct mlx5_ifc_alloc_xrcd_out_bits {
6205 u8 reserved_at_8[0x18];
6209 u8 reserved_at_40[0x8];
6212 u8 reserved_at_60[0x20];
6215 struct mlx5_ifc_alloc_xrcd_in_bits {
6217 u8 reserved_at_10[0x10];
6219 u8 reserved_at_20[0x10];
6222 u8 reserved_at_40[0x40];
6225 struct mlx5_ifc_alloc_uar_out_bits {
6227 u8 reserved_at_8[0x18];
6231 u8 reserved_at_40[0x8];
6234 u8 reserved_at_60[0x20];
6237 struct mlx5_ifc_alloc_uar_in_bits {
6239 u8 reserved_at_10[0x10];
6241 u8 reserved_at_20[0x10];
6244 u8 reserved_at_40[0x40];
6247 struct mlx5_ifc_alloc_transport_domain_out_bits {
6249 u8 reserved_at_8[0x18];
6253 u8 reserved_at_40[0x8];
6254 u8 transport_domain[0x18];
6256 u8 reserved_at_60[0x20];
6259 struct mlx5_ifc_alloc_transport_domain_in_bits {
6261 u8 reserved_at_10[0x10];
6263 u8 reserved_at_20[0x10];
6266 u8 reserved_at_40[0x40];
6269 struct mlx5_ifc_alloc_q_counter_out_bits {
6271 u8 reserved_at_8[0x18];
6275 u8 reserved_at_40[0x18];
6276 u8 counter_set_id[0x8];
6278 u8 reserved_at_60[0x20];
6281 struct mlx5_ifc_alloc_q_counter_in_bits {
6283 u8 reserved_at_10[0x10];
6285 u8 reserved_at_20[0x10];
6288 u8 reserved_at_40[0x40];
6291 struct mlx5_ifc_alloc_pd_out_bits {
6293 u8 reserved_at_8[0x18];
6297 u8 reserved_at_40[0x8];
6300 u8 reserved_at_60[0x20];
6303 struct mlx5_ifc_alloc_pd_in_bits {
6305 u8 reserved_at_10[0x10];
6307 u8 reserved_at_20[0x10];
6310 u8 reserved_at_40[0x40];
6313 struct mlx5_ifc_alloc_flow_counter_out_bits {
6315 u8 reserved_at_8[0x18];
6319 u8 reserved_at_40[0x10];
6320 u8 flow_counter_id[0x10];
6322 u8 reserved_at_60[0x20];
6325 struct mlx5_ifc_alloc_flow_counter_in_bits {
6327 u8 reserved_at_10[0x10];
6329 u8 reserved_at_20[0x10];
6332 u8 reserved_at_40[0x40];
6335 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6337 u8 reserved_at_8[0x18];
6341 u8 reserved_at_40[0x40];
6344 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6346 u8 reserved_at_10[0x10];
6348 u8 reserved_at_20[0x10];
6351 u8 reserved_at_40[0x20];
6353 u8 reserved_at_60[0x10];
6354 u8 vxlan_udp_port[0x10];
6357 struct mlx5_ifc_access_register_out_bits {
6359 u8 reserved_at_8[0x18];
6363 u8 reserved_at_40[0x40];
6365 u8 register_data[0][0x20];
6369 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6370 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6373 struct mlx5_ifc_access_register_in_bits {
6375 u8 reserved_at_10[0x10];
6377 u8 reserved_at_20[0x10];
6380 u8 reserved_at_40[0x10];
6381 u8 register_id[0x10];
6385 u8 register_data[0][0x20];
6388 struct mlx5_ifc_sltp_reg_bits {
6393 u8 reserved_at_12[0x2];
6395 u8 reserved_at_18[0x8];
6397 u8 reserved_at_20[0x20];
6399 u8 reserved_at_40[0x7];
6405 u8 reserved_at_60[0xc];
6406 u8 ob_preemp_mode[0x4];
6410 u8 reserved_at_80[0x20];
6413 struct mlx5_ifc_slrg_reg_bits {
6418 u8 reserved_at_12[0x2];
6420 u8 reserved_at_18[0x8];
6422 u8 time_to_link_up[0x10];
6423 u8 reserved_at_30[0xc];
6424 u8 grade_lane_speed[0x4];
6426 u8 grade_version[0x8];
6429 u8 reserved_at_60[0x4];
6430 u8 height_grade_type[0x4];
6431 u8 height_grade[0x18];
6436 u8 reserved_at_a0[0x10];
6437 u8 height_sigma[0x10];
6439 u8 reserved_at_c0[0x20];
6441 u8 reserved_at_e0[0x4];
6442 u8 phase_grade_type[0x4];
6443 u8 phase_grade[0x18];
6445 u8 reserved_at_100[0x8];
6446 u8 phase_eo_pos[0x8];
6447 u8 reserved_at_110[0x8];
6448 u8 phase_eo_neg[0x8];
6450 u8 ffe_set_tested[0x10];
6451 u8 test_errors_per_lane[0x10];
6454 struct mlx5_ifc_pvlc_reg_bits {
6455 u8 reserved_at_0[0x8];
6457 u8 reserved_at_10[0x10];
6459 u8 reserved_at_20[0x1c];
6462 u8 reserved_at_40[0x1c];
6465 u8 reserved_at_60[0x1c];
6466 u8 vl_operational[0x4];
6469 struct mlx5_ifc_pude_reg_bits {
6472 u8 reserved_at_10[0x4];
6473 u8 admin_status[0x4];
6474 u8 reserved_at_18[0x4];
6475 u8 oper_status[0x4];
6477 u8 reserved_at_20[0x60];
6480 struct mlx5_ifc_ptys_reg_bits {
6481 u8 reserved_at_0[0x8];
6483 u8 reserved_at_10[0xd];
6486 u8 reserved_at_20[0x40];
6488 u8 eth_proto_capability[0x20];
6490 u8 ib_link_width_capability[0x10];
6491 u8 ib_proto_capability[0x10];
6493 u8 reserved_at_a0[0x20];
6495 u8 eth_proto_admin[0x20];
6497 u8 ib_link_width_admin[0x10];
6498 u8 ib_proto_admin[0x10];
6500 u8 reserved_at_100[0x20];
6502 u8 eth_proto_oper[0x20];
6504 u8 ib_link_width_oper[0x10];
6505 u8 ib_proto_oper[0x10];
6507 u8 reserved_at_160[0x20];
6509 u8 eth_proto_lp_advertise[0x20];
6511 u8 reserved_at_1a0[0x60];
6514 struct mlx5_ifc_mlcr_reg_bits {
6515 u8 reserved_at_0[0x8];
6517 u8 reserved_at_10[0x20];
6519 u8 beacon_duration[0x10];
6520 u8 reserved_at_40[0x10];
6522 u8 beacon_remain[0x10];
6525 struct mlx5_ifc_ptas_reg_bits {
6526 u8 reserved_at_0[0x20];
6528 u8 algorithm_options[0x10];
6529 u8 reserved_at_30[0x4];
6530 u8 repetitions_mode[0x4];
6531 u8 num_of_repetitions[0x8];
6533 u8 grade_version[0x8];
6534 u8 height_grade_type[0x4];
6535 u8 phase_grade_type[0x4];
6536 u8 height_grade_weight[0x8];
6537 u8 phase_grade_weight[0x8];
6539 u8 gisim_measure_bits[0x10];
6540 u8 adaptive_tap_measure_bits[0x10];
6542 u8 ber_bath_high_error_threshold[0x10];
6543 u8 ber_bath_mid_error_threshold[0x10];
6545 u8 ber_bath_low_error_threshold[0x10];
6546 u8 one_ratio_high_threshold[0x10];
6548 u8 one_ratio_high_mid_threshold[0x10];
6549 u8 one_ratio_low_mid_threshold[0x10];
6551 u8 one_ratio_low_threshold[0x10];
6552 u8 ndeo_error_threshold[0x10];
6554 u8 mixer_offset_step_size[0x10];
6555 u8 reserved_at_110[0x8];
6556 u8 mix90_phase_for_voltage_bath[0x8];
6558 u8 mixer_offset_start[0x10];
6559 u8 mixer_offset_end[0x10];
6561 u8 reserved_at_140[0x15];
6562 u8 ber_test_time[0xb];
6565 struct mlx5_ifc_pspa_reg_bits {
6569 u8 reserved_at_18[0x8];
6571 u8 reserved_at_20[0x20];
6574 struct mlx5_ifc_pqdr_reg_bits {
6575 u8 reserved_at_0[0x8];
6577 u8 reserved_at_10[0x5];
6579 u8 reserved_at_18[0x6];
6582 u8 reserved_at_20[0x20];
6584 u8 reserved_at_40[0x10];
6585 u8 min_threshold[0x10];
6587 u8 reserved_at_60[0x10];
6588 u8 max_threshold[0x10];
6590 u8 reserved_at_80[0x10];
6591 u8 mark_probability_denominator[0x10];
6593 u8 reserved_at_a0[0x60];
6596 struct mlx5_ifc_ppsc_reg_bits {
6597 u8 reserved_at_0[0x8];
6599 u8 reserved_at_10[0x10];
6601 u8 reserved_at_20[0x60];
6603 u8 reserved_at_80[0x1c];
6606 u8 reserved_at_a0[0x1c];
6607 u8 wrps_status[0x4];
6609 u8 reserved_at_c0[0x8];
6610 u8 up_threshold[0x8];
6611 u8 reserved_at_d0[0x8];
6612 u8 down_threshold[0x8];
6614 u8 reserved_at_e0[0x20];
6616 u8 reserved_at_100[0x1c];
6619 u8 reserved_at_120[0x1c];
6620 u8 srps_status[0x4];
6622 u8 reserved_at_140[0x40];
6625 struct mlx5_ifc_pplr_reg_bits {
6626 u8 reserved_at_0[0x8];
6628 u8 reserved_at_10[0x10];
6630 u8 reserved_at_20[0x8];
6632 u8 reserved_at_30[0x8];
6636 struct mlx5_ifc_pplm_reg_bits {
6637 u8 reserved_at_0[0x8];
6639 u8 reserved_at_10[0x10];
6641 u8 reserved_at_20[0x20];
6643 u8 port_profile_mode[0x8];
6644 u8 static_port_profile[0x8];
6645 u8 active_port_profile[0x8];
6646 u8 reserved_at_58[0x8];
6648 u8 retransmission_active[0x8];
6649 u8 fec_mode_active[0x18];
6651 u8 reserved_at_80[0x20];
6654 struct mlx5_ifc_ppcnt_reg_bits {
6658 u8 reserved_at_12[0x8];
6662 u8 reserved_at_21[0x1c];
6665 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6668 struct mlx5_ifc_ppad_reg_bits {
6669 u8 reserved_at_0[0x3];
6671 u8 reserved_at_4[0x4];
6677 u8 reserved_at_40[0x40];
6680 struct mlx5_ifc_pmtu_reg_bits {
6681 u8 reserved_at_0[0x8];
6683 u8 reserved_at_10[0x10];
6686 u8 reserved_at_30[0x10];
6689 u8 reserved_at_50[0x10];
6692 u8 reserved_at_70[0x10];
6695 struct mlx5_ifc_pmpr_reg_bits {
6696 u8 reserved_at_0[0x8];
6698 u8 reserved_at_10[0x10];
6700 u8 reserved_at_20[0x18];
6701 u8 attenuation_5g[0x8];
6703 u8 reserved_at_40[0x18];
6704 u8 attenuation_7g[0x8];
6706 u8 reserved_at_60[0x18];
6707 u8 attenuation_12g[0x8];
6710 struct mlx5_ifc_pmpe_reg_bits {
6711 u8 reserved_at_0[0x8];
6713 u8 reserved_at_10[0xc];
6714 u8 module_status[0x4];
6716 u8 reserved_at_20[0x60];
6719 struct mlx5_ifc_pmpc_reg_bits {
6720 u8 module_state_updated[32][0x8];
6723 struct mlx5_ifc_pmlpn_reg_bits {
6724 u8 reserved_at_0[0x4];
6725 u8 mlpn_status[0x4];
6727 u8 reserved_at_10[0x10];
6730 u8 reserved_at_21[0x1f];
6733 struct mlx5_ifc_pmlp_reg_bits {
6735 u8 reserved_at_1[0x7];
6737 u8 reserved_at_10[0x8];
6740 u8 lane0_module_mapping[0x20];
6742 u8 lane1_module_mapping[0x20];
6744 u8 lane2_module_mapping[0x20];
6746 u8 lane3_module_mapping[0x20];
6748 u8 reserved_at_a0[0x160];
6751 struct mlx5_ifc_pmaos_reg_bits {
6752 u8 reserved_at_0[0x8];
6754 u8 reserved_at_10[0x4];
6755 u8 admin_status[0x4];
6756 u8 reserved_at_18[0x4];
6757 u8 oper_status[0x4];
6761 u8 reserved_at_22[0x1c];
6764 u8 reserved_at_40[0x40];
6767 struct mlx5_ifc_plpc_reg_bits {
6768 u8 reserved_at_0[0x4];
6770 u8 reserved_at_10[0x4];
6772 u8 reserved_at_18[0x8];
6774 u8 reserved_at_20[0x10];
6775 u8 lane_speed[0x10];
6777 u8 reserved_at_40[0x17];
6779 u8 fec_mode_policy[0x8];
6781 u8 retransmission_capability[0x8];
6782 u8 fec_mode_capability[0x18];
6784 u8 retransmission_support_admin[0x8];
6785 u8 fec_mode_support_admin[0x18];
6787 u8 retransmission_request_admin[0x8];
6788 u8 fec_mode_request_admin[0x18];
6790 u8 reserved_at_c0[0x80];
6793 struct mlx5_ifc_plib_reg_bits {
6794 u8 reserved_at_0[0x8];
6796 u8 reserved_at_10[0x8];
6799 u8 reserved_at_20[0x60];
6802 struct mlx5_ifc_plbf_reg_bits {
6803 u8 reserved_at_0[0x8];
6805 u8 reserved_at_10[0xd];
6808 u8 reserved_at_20[0x20];
6811 struct mlx5_ifc_pipg_reg_bits {
6812 u8 reserved_at_0[0x8];
6814 u8 reserved_at_10[0x10];
6817 u8 reserved_at_21[0x19];
6819 u8 reserved_at_3e[0x2];
6822 struct mlx5_ifc_pifr_reg_bits {
6823 u8 reserved_at_0[0x8];
6825 u8 reserved_at_10[0x10];
6827 u8 reserved_at_20[0xe0];
6829 u8 port_filter[8][0x20];
6831 u8 port_filter_update_en[8][0x20];
6834 struct mlx5_ifc_pfcc_reg_bits {
6835 u8 reserved_at_0[0x8];
6837 u8 reserved_at_10[0x10];
6840 u8 reserved_at_24[0x4];
6841 u8 prio_mask_tx[0x8];
6842 u8 reserved_at_30[0x8];
6843 u8 prio_mask_rx[0x8];
6847 u8 reserved_at_42[0x6];
6849 u8 reserved_at_50[0x10];
6853 u8 reserved_at_62[0x6];
6855 u8 reserved_at_70[0x10];
6857 u8 reserved_at_80[0x80];
6860 struct mlx5_ifc_pelc_reg_bits {
6862 u8 reserved_at_4[0x4];
6864 u8 reserved_at_10[0x10];
6867 u8 op_capability[0x8];
6873 u8 capability[0x40];
6879 u8 reserved_at_140[0x80];
6882 struct mlx5_ifc_peir_reg_bits {
6883 u8 reserved_at_0[0x8];
6885 u8 reserved_at_10[0x10];
6887 u8 reserved_at_20[0xc];
6888 u8 error_count[0x4];
6889 u8 reserved_at_30[0x10];
6891 u8 reserved_at_40[0xc];
6893 u8 reserved_at_50[0x8];
6897 struct mlx5_ifc_pcap_reg_bits {
6898 u8 reserved_at_0[0x8];
6900 u8 reserved_at_10[0x10];
6902 u8 port_capability_mask[4][0x20];
6905 struct mlx5_ifc_paos_reg_bits {
6908 u8 reserved_at_10[0x4];
6909 u8 admin_status[0x4];
6910 u8 reserved_at_18[0x4];
6911 u8 oper_status[0x4];
6915 u8 reserved_at_22[0x1c];
6918 u8 reserved_at_40[0x40];
6921 struct mlx5_ifc_pamp_reg_bits {
6922 u8 reserved_at_0[0x8];
6923 u8 opamp_group[0x8];
6924 u8 reserved_at_10[0xc];
6925 u8 opamp_group_type[0x4];
6927 u8 start_index[0x10];
6928 u8 reserved_at_30[0x4];
6929 u8 num_of_indices[0xc];
6931 u8 index_data[18][0x10];
6934 struct mlx5_ifc_pcmr_reg_bits {
6935 u8 reserved_at_0[0x8];
6937 u8 reserved_at_10[0x2e];
6939 u8 reserved_at_3f[0x1f];
6941 u8 reserved_at_5f[0x1];
6944 struct mlx5_ifc_lane_2_module_mapping_bits {
6945 u8 reserved_at_0[0x6];
6947 u8 reserved_at_8[0x6];
6949 u8 reserved_at_10[0x8];
6953 struct mlx5_ifc_bufferx_reg_bits {
6954 u8 reserved_at_0[0x6];
6957 u8 reserved_at_8[0xc];
6960 u8 xoff_threshold[0x10];
6961 u8 xon_threshold[0x10];
6964 struct mlx5_ifc_set_node_in_bits {
6965 u8 node_description[64][0x8];
6968 struct mlx5_ifc_register_power_settings_bits {
6969 u8 reserved_at_0[0x18];
6970 u8 power_settings_level[0x8];
6972 u8 reserved_at_20[0x60];
6975 struct mlx5_ifc_register_host_endianness_bits {
6977 u8 reserved_at_1[0x1f];
6979 u8 reserved_at_20[0x60];
6982 struct mlx5_ifc_umr_pointer_desc_argument_bits {
6983 u8 reserved_at_0[0x20];
6987 u8 addressh_63_32[0x20];
6989 u8 addressl_31_0[0x20];
6992 struct mlx5_ifc_ud_adrs_vector_bits {
6996 u8 reserved_at_41[0x7];
6997 u8 destination_qp_dct[0x18];
6999 u8 static_rate[0x4];
7000 u8 sl_eth_prio[0x4];
7003 u8 rlid_udp_sport[0x10];
7005 u8 reserved_at_80[0x20];
7007 u8 rmac_47_16[0x20];
7013 u8 reserved_at_e0[0x1];
7015 u8 reserved_at_e2[0x2];
7016 u8 src_addr_index[0x8];
7017 u8 flow_label[0x14];
7019 u8 rgid_rip[16][0x8];
7022 struct mlx5_ifc_pages_req_event_bits {
7023 u8 reserved_at_0[0x10];
7024 u8 function_id[0x10];
7028 u8 reserved_at_40[0xa0];
7031 struct mlx5_ifc_eqe_bits {
7032 u8 reserved_at_0[0x8];
7034 u8 reserved_at_10[0x8];
7035 u8 event_sub_type[0x8];
7037 u8 reserved_at_20[0xe0];
7039 union mlx5_ifc_event_auto_bits event_data;
7041 u8 reserved_at_1e0[0x10];
7043 u8 reserved_at_1f8[0x7];
7048 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7051 struct mlx5_ifc_cmd_queue_entry_bits {
7053 u8 reserved_at_8[0x18];
7055 u8 input_length[0x20];
7057 u8 input_mailbox_pointer_63_32[0x20];
7059 u8 input_mailbox_pointer_31_9[0x17];
7060 u8 reserved_at_77[0x9];
7062 u8 command_input_inline_data[16][0x8];
7064 u8 command_output_inline_data[16][0x8];
7066 u8 output_mailbox_pointer_63_32[0x20];
7068 u8 output_mailbox_pointer_31_9[0x17];
7069 u8 reserved_at_1b7[0x9];
7071 u8 output_length[0x20];
7075 u8 reserved_at_1f0[0x8];
7080 struct mlx5_ifc_cmd_out_bits {
7082 u8 reserved_at_8[0x18];
7086 u8 command_output[0x20];
7089 struct mlx5_ifc_cmd_in_bits {
7091 u8 reserved_at_10[0x10];
7093 u8 reserved_at_20[0x10];
7096 u8 command[0][0x20];
7099 struct mlx5_ifc_cmd_if_box_bits {
7100 u8 mailbox_data[512][0x8];
7102 u8 reserved_at_1000[0x180];
7104 u8 next_pointer_63_32[0x20];
7106 u8 next_pointer_31_10[0x16];
7107 u8 reserved_at_11b6[0xa];
7109 u8 block_number[0x20];
7111 u8 reserved_at_11e0[0x8];
7113 u8 ctrl_signature[0x8];
7117 struct mlx5_ifc_mtt_bits {
7118 u8 ptag_63_32[0x20];
7121 u8 reserved_at_38[0x6];
7126 struct mlx5_ifc_query_wol_rol_out_bits {
7128 u8 reserved_at_8[0x18];
7132 u8 reserved_at_40[0x10];
7136 u8 reserved_at_60[0x20];
7139 struct mlx5_ifc_query_wol_rol_in_bits {
7141 u8 reserved_at_10[0x10];
7143 u8 reserved_at_20[0x10];
7146 u8 reserved_at_40[0x40];
7149 struct mlx5_ifc_set_wol_rol_out_bits {
7151 u8 reserved_at_8[0x18];
7155 u8 reserved_at_40[0x40];
7158 struct mlx5_ifc_set_wol_rol_in_bits {
7160 u8 reserved_at_10[0x10];
7162 u8 reserved_at_20[0x10];
7165 u8 rol_mode_valid[0x1];
7166 u8 wol_mode_valid[0x1];
7167 u8 reserved_at_42[0xe];
7171 u8 reserved_at_60[0x20];
7175 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7176 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7177 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7181 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7182 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7183 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7187 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7188 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7189 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7196 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7197 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7200 struct mlx5_ifc_initial_seg_bits {
7201 u8 fw_rev_minor[0x10];
7202 u8 fw_rev_major[0x10];
7204 u8 cmd_interface_rev[0x10];
7205 u8 fw_rev_subminor[0x10];
7207 u8 reserved_at_40[0x40];
7209 u8 cmdq_phy_addr_63_32[0x20];
7211 u8 cmdq_phy_addr_31_12[0x14];
7212 u8 reserved_at_b4[0x2];
7213 u8 nic_interface[0x2];
7214 u8 log_cmdq_size[0x4];
7215 u8 log_cmdq_stride[0x4];
7217 u8 command_doorbell_vector[0x20];
7219 u8 reserved_at_e0[0xf00];
7221 u8 initializing[0x1];
7222 u8 reserved_at_fe1[0x4];
7223 u8 nic_interface_supported[0x3];
7224 u8 reserved_at_fe8[0x18];
7226 struct mlx5_ifc_health_buffer_bits health_buffer;
7228 u8 no_dram_nic_offset[0x20];
7230 u8 reserved_at_1220[0x6e40];
7232 u8 reserved_at_8060[0x1f];
7235 u8 health_syndrome[0x8];
7236 u8 health_counter[0x18];
7238 u8 reserved_at_80a0[0x17fc0];
7241 union mlx5_ifc_ports_control_registers_document_bits {
7242 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7243 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7244 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7245 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7246 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7247 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7248 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7249 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7250 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7251 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7252 struct mlx5_ifc_paos_reg_bits paos_reg;
7253 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7254 struct mlx5_ifc_peir_reg_bits peir_reg;
7255 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7256 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
7257 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
7258 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7259 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7260 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7261 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7262 struct mlx5_ifc_plib_reg_bits plib_reg;
7263 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7264 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7265 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7266 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7267 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7268 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7269 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7270 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7271 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7272 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7273 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7274 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7275 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7276 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7277 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7278 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7279 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7280 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
7281 struct mlx5_ifc_pude_reg_bits pude_reg;
7282 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7283 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7284 struct mlx5_ifc_sltp_reg_bits sltp_reg;
7285 u8 reserved_at_0[0x60e0];
7288 union mlx5_ifc_debug_enhancements_document_bits {
7289 struct mlx5_ifc_health_buffer_bits health_buffer;
7290 u8 reserved_at_0[0x200];
7293 union mlx5_ifc_uplink_pci_interface_document_bits {
7294 struct mlx5_ifc_initial_seg_bits initial_seg;
7295 u8 reserved_at_0[0x20060];
7298 struct mlx5_ifc_set_flow_table_root_out_bits {
7300 u8 reserved_at_8[0x18];
7304 u8 reserved_at_40[0x40];
7307 struct mlx5_ifc_set_flow_table_root_in_bits {
7309 u8 reserved_at_10[0x10];
7311 u8 reserved_at_20[0x10];
7314 u8 other_vport[0x1];
7315 u8 reserved_at_41[0xf];
7316 u8 vport_number[0x10];
7318 u8 reserved_at_60[0x20];
7321 u8 reserved_at_88[0x18];
7323 u8 reserved_at_a0[0x8];
7326 u8 reserved_at_c0[0x140];
7330 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7333 struct mlx5_ifc_modify_flow_table_out_bits {
7335 u8 reserved_at_8[0x18];
7339 u8 reserved_at_40[0x40];
7342 struct mlx5_ifc_modify_flow_table_in_bits {
7344 u8 reserved_at_10[0x10];
7346 u8 reserved_at_20[0x10];
7349 u8 other_vport[0x1];
7350 u8 reserved_at_41[0xf];
7351 u8 vport_number[0x10];
7353 u8 reserved_at_60[0x10];
7354 u8 modify_field_select[0x10];
7357 u8 reserved_at_88[0x18];
7359 u8 reserved_at_a0[0x8];
7362 u8 reserved_at_c0[0x4];
7363 u8 table_miss_mode[0x4];
7364 u8 reserved_at_c8[0x18];
7366 u8 reserved_at_e0[0x8];
7367 u8 table_miss_id[0x18];
7369 u8 reserved_at_100[0x100];
7372 struct mlx5_ifc_ets_tcn_config_reg_bits {
7376 u8 reserved_at_3[0x9];
7378 u8 reserved_at_10[0x9];
7379 u8 bw_allocation[0x7];
7381 u8 reserved_at_20[0xc];
7382 u8 max_bw_units[0x4];
7383 u8 reserved_at_30[0x8];
7384 u8 max_bw_value[0x8];
7387 struct mlx5_ifc_ets_global_config_reg_bits {
7388 u8 reserved_at_0[0x2];
7390 u8 reserved_at_3[0x1d];
7392 u8 reserved_at_20[0xc];
7393 u8 max_bw_units[0x4];
7394 u8 reserved_at_30[0x8];
7395 u8 max_bw_value[0x8];
7398 struct mlx5_ifc_qetc_reg_bits {
7399 u8 reserved_at_0[0x8];
7400 u8 port_number[0x8];
7401 u8 reserved_at_10[0x30];
7403 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7404 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7407 struct mlx5_ifc_qtct_reg_bits {
7408 u8 reserved_at_0[0x8];
7409 u8 port_number[0x8];
7410 u8 reserved_at_10[0xd];
7413 u8 reserved_at_20[0x1d];
7417 struct mlx5_ifc_mcia_reg_bits {
7419 u8 reserved_at_1[0x7];
7421 u8 reserved_at_10[0x8];
7424 u8 i2c_device_address[0x8];
7425 u8 page_number[0x8];
7426 u8 device_address[0x10];
7428 u8 reserved_at_40[0x10];
7431 u8 reserved_at_60[0x20];
7447 #endif /* MLX5_IFC_H */