2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
93 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
94 MLX5_OBJ_TYPE_MKEY = 0xff01,
95 MLX5_OBJ_TYPE_QP = 0xff02,
96 MLX5_OBJ_TYPE_PSV = 0xff03,
97 MLX5_OBJ_TYPE_RMP = 0xff04,
98 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
99 MLX5_OBJ_TYPE_RQ = 0xff06,
100 MLX5_OBJ_TYPE_SQ = 0xff07,
101 MLX5_OBJ_TYPE_TIR = 0xff08,
102 MLX5_OBJ_TYPE_TIS = 0xff09,
103 MLX5_OBJ_TYPE_DCT = 0xff0a,
104 MLX5_OBJ_TYPE_XRQ = 0xff0b,
105 MLX5_OBJ_TYPE_RQT = 0xff0e,
106 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
107 MLX5_OBJ_TYPE_CQ = 0xff10,
111 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
112 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
113 MLX5_CMD_OP_INIT_HCA = 0x102,
114 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
115 MLX5_CMD_OP_ENABLE_HCA = 0x104,
116 MLX5_CMD_OP_DISABLE_HCA = 0x105,
117 MLX5_CMD_OP_QUERY_PAGES = 0x107,
118 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
119 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
120 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
121 MLX5_CMD_OP_SET_ISSI = 0x10b,
122 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
123 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
124 MLX5_CMD_OP_ALLOC_SF = 0x113,
125 MLX5_CMD_OP_DEALLOC_SF = 0x114,
126 MLX5_CMD_OP_CREATE_MKEY = 0x200,
127 MLX5_CMD_OP_QUERY_MKEY = 0x201,
128 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
129 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
130 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
131 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
132 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
133 MLX5_CMD_OP_CREATE_EQ = 0x301,
134 MLX5_CMD_OP_DESTROY_EQ = 0x302,
135 MLX5_CMD_OP_QUERY_EQ = 0x303,
136 MLX5_CMD_OP_GEN_EQE = 0x304,
137 MLX5_CMD_OP_CREATE_CQ = 0x400,
138 MLX5_CMD_OP_DESTROY_CQ = 0x401,
139 MLX5_CMD_OP_QUERY_CQ = 0x402,
140 MLX5_CMD_OP_MODIFY_CQ = 0x403,
141 MLX5_CMD_OP_CREATE_QP = 0x500,
142 MLX5_CMD_OP_DESTROY_QP = 0x501,
143 MLX5_CMD_OP_RST2INIT_QP = 0x502,
144 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
145 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
146 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
147 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
148 MLX5_CMD_OP_2ERR_QP = 0x507,
149 MLX5_CMD_OP_2RST_QP = 0x50a,
150 MLX5_CMD_OP_QUERY_QP = 0x50b,
151 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
152 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
153 MLX5_CMD_OP_CREATE_PSV = 0x600,
154 MLX5_CMD_OP_DESTROY_PSV = 0x601,
155 MLX5_CMD_OP_CREATE_SRQ = 0x700,
156 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
157 MLX5_CMD_OP_QUERY_SRQ = 0x702,
158 MLX5_CMD_OP_ARM_RQ = 0x703,
159 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
160 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
161 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
162 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
163 MLX5_CMD_OP_CREATE_DCT = 0x710,
164 MLX5_CMD_OP_DESTROY_DCT = 0x711,
165 MLX5_CMD_OP_DRAIN_DCT = 0x712,
166 MLX5_CMD_OP_QUERY_DCT = 0x713,
167 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
168 MLX5_CMD_OP_CREATE_XRQ = 0x717,
169 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
170 MLX5_CMD_OP_QUERY_XRQ = 0x719,
171 MLX5_CMD_OP_ARM_XRQ = 0x71a,
172 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
173 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
174 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
175 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
176 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
177 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
178 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
179 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
180 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
181 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
182 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
183 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
184 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
185 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
186 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
187 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
188 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
189 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
190 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
191 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
192 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
193 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
194 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
195 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
196 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
197 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
198 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
199 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
200 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
201 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
202 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
203 MLX5_CMD_OP_ALLOC_PD = 0x800,
204 MLX5_CMD_OP_DEALLOC_PD = 0x801,
205 MLX5_CMD_OP_ALLOC_UAR = 0x802,
206 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
207 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
208 MLX5_CMD_OP_ACCESS_REG = 0x805,
209 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
210 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
211 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
212 MLX5_CMD_OP_MAD_IFC = 0x50d,
213 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
214 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
215 MLX5_CMD_OP_NOP = 0x80d,
216 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
217 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
218 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
219 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
230 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
232 MLX5_CMD_OP_CREATE_LAG = 0x840,
233 MLX5_CMD_OP_MODIFY_LAG = 0x841,
234 MLX5_CMD_OP_QUERY_LAG = 0x842,
235 MLX5_CMD_OP_DESTROY_LAG = 0x843,
236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
238 MLX5_CMD_OP_CREATE_TIR = 0x900,
239 MLX5_CMD_OP_MODIFY_TIR = 0x901,
240 MLX5_CMD_OP_DESTROY_TIR = 0x902,
241 MLX5_CMD_OP_QUERY_TIR = 0x903,
242 MLX5_CMD_OP_CREATE_SQ = 0x904,
243 MLX5_CMD_OP_MODIFY_SQ = 0x905,
244 MLX5_CMD_OP_DESTROY_SQ = 0x906,
245 MLX5_CMD_OP_QUERY_SQ = 0x907,
246 MLX5_CMD_OP_CREATE_RQ = 0x908,
247 MLX5_CMD_OP_MODIFY_RQ = 0x909,
248 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
249 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
250 MLX5_CMD_OP_QUERY_RQ = 0x90b,
251 MLX5_CMD_OP_CREATE_RMP = 0x90c,
252 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
253 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
254 MLX5_CMD_OP_QUERY_RMP = 0x90f,
255 MLX5_CMD_OP_CREATE_TIS = 0x912,
256 MLX5_CMD_OP_MODIFY_TIS = 0x913,
257 MLX5_CMD_OP_DESTROY_TIS = 0x914,
258 MLX5_CMD_OP_QUERY_TIS = 0x915,
259 MLX5_CMD_OP_CREATE_RQT = 0x916,
260 MLX5_CMD_OP_MODIFY_RQT = 0x917,
261 MLX5_CMD_OP_DESTROY_RQT = 0x918,
262 MLX5_CMD_OP_QUERY_RQT = 0x919,
263 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
264 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
265 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
266 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
267 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
268 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
269 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
270 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
271 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
272 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
273 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
274 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
275 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
276 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
277 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
278 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
279 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
280 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
281 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
282 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
283 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
284 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
285 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
286 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
287 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
288 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
289 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
290 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
291 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
292 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
293 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
294 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
295 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
299 /* Valid range for general commands that don't work over an object */
301 MLX5_CMD_OP_GENERAL_START = 0xb00,
302 MLX5_CMD_OP_GENERAL_END = 0xd00,
305 struct mlx5_ifc_flow_table_fields_supported_bits {
308 u8 outer_ether_type[0x1];
309 u8 outer_ip_version[0x1];
310 u8 outer_first_prio[0x1];
311 u8 outer_first_cfi[0x1];
312 u8 outer_first_vid[0x1];
313 u8 outer_ipv4_ttl[0x1];
314 u8 outer_second_prio[0x1];
315 u8 outer_second_cfi[0x1];
316 u8 outer_second_vid[0x1];
317 u8 reserved_at_b[0x1];
321 u8 outer_ip_protocol[0x1];
322 u8 outer_ip_ecn[0x1];
323 u8 outer_ip_dscp[0x1];
324 u8 outer_udp_sport[0x1];
325 u8 outer_udp_dport[0x1];
326 u8 outer_tcp_sport[0x1];
327 u8 outer_tcp_dport[0x1];
328 u8 outer_tcp_flags[0x1];
329 u8 outer_gre_protocol[0x1];
330 u8 outer_gre_key[0x1];
331 u8 outer_vxlan_vni[0x1];
332 u8 outer_geneve_vni[0x1];
333 u8 outer_geneve_oam[0x1];
334 u8 outer_geneve_protocol_type[0x1];
335 u8 outer_geneve_opt_len[0x1];
336 u8 reserved_at_1e[0x1];
337 u8 source_eswitch_port[0x1];
341 u8 inner_ether_type[0x1];
342 u8 inner_ip_version[0x1];
343 u8 inner_first_prio[0x1];
344 u8 inner_first_cfi[0x1];
345 u8 inner_first_vid[0x1];
346 u8 reserved_at_27[0x1];
347 u8 inner_second_prio[0x1];
348 u8 inner_second_cfi[0x1];
349 u8 inner_second_vid[0x1];
350 u8 reserved_at_2b[0x1];
354 u8 inner_ip_protocol[0x1];
355 u8 inner_ip_ecn[0x1];
356 u8 inner_ip_dscp[0x1];
357 u8 inner_udp_sport[0x1];
358 u8 inner_udp_dport[0x1];
359 u8 inner_tcp_sport[0x1];
360 u8 inner_tcp_dport[0x1];
361 u8 inner_tcp_flags[0x1];
362 u8 reserved_at_37[0x9];
364 u8 geneve_tlv_option_0_data[0x1];
365 u8 reserved_at_41[0x4];
366 u8 outer_first_mpls_over_udp[0x4];
367 u8 outer_first_mpls_over_gre[0x4];
368 u8 inner_first_mpls[0x4];
369 u8 outer_first_mpls[0x4];
370 u8 reserved_at_55[0x2];
371 u8 outer_esp_spi[0x1];
372 u8 reserved_at_58[0x2];
375 u8 reserved_at_5b[0x25];
378 struct mlx5_ifc_flow_table_prop_layout_bits {
380 u8 reserved_at_1[0x1];
381 u8 flow_counter[0x1];
382 u8 flow_modify_en[0x1];
384 u8 identified_miss_table_mode[0x1];
385 u8 flow_table_modify[0x1];
388 u8 reserved_at_9[0x1];
391 u8 reserved_at_c[0x1];
394 u8 reformat_and_vlan_action[0x1];
395 u8 reserved_at_10[0x1];
397 u8 reformat_l3_tunnel_to_l2[0x1];
398 u8 reformat_l2_to_l3_tunnel[0x1];
399 u8 reformat_and_modify_action[0x1];
400 u8 reserved_at_15[0x2];
401 u8 table_miss_action_domain[0x1];
402 u8 termination_table[0x1];
403 u8 reserved_at_19[0x7];
404 u8 reserved_at_20[0x2];
405 u8 log_max_ft_size[0x6];
406 u8 log_max_modify_header_context[0x8];
407 u8 max_modify_header_actions[0x8];
408 u8 max_ft_level[0x8];
410 u8 reserved_at_40[0x20];
412 u8 reserved_at_60[0x18];
413 u8 log_max_ft_num[0x8];
415 u8 reserved_at_80[0x18];
416 u8 log_max_destination[0x8];
418 u8 log_max_flow_counter[0x8];
419 u8 reserved_at_a8[0x10];
420 u8 log_max_flow[0x8];
422 u8 reserved_at_c0[0x40];
424 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
426 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
429 struct mlx5_ifc_odp_per_transport_service_cap_bits {
436 u8 reserved_at_6[0x1a];
439 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
464 u8 reserved_at_c0[0x18];
465 u8 ttl_hoplimit[0x8];
470 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
472 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
475 struct mlx5_ifc_nvgre_key_bits {
480 union mlx5_ifc_gre_key_bits {
481 struct mlx5_ifc_nvgre_key_bits nvgre;
485 struct mlx5_ifc_fte_match_set_misc_bits {
486 u8 reserved_at_0[0x8];
489 u8 source_eswitch_owner_vhca_id[0x10];
490 u8 source_port[0x10];
492 u8 outer_second_prio[0x3];
493 u8 outer_second_cfi[0x1];
494 u8 outer_second_vid[0xc];
495 u8 inner_second_prio[0x3];
496 u8 inner_second_cfi[0x1];
497 u8 inner_second_vid[0xc];
499 u8 outer_second_cvlan_tag[0x1];
500 u8 inner_second_cvlan_tag[0x1];
501 u8 outer_second_svlan_tag[0x1];
502 u8 inner_second_svlan_tag[0x1];
503 u8 reserved_at_64[0xc];
504 u8 gre_protocol[0x10];
506 union mlx5_ifc_gre_key_bits gre_key;
509 u8 reserved_at_b8[0x8];
512 u8 reserved_at_d8[0x7];
515 u8 reserved_at_e0[0xc];
516 u8 outer_ipv6_flow_label[0x14];
518 u8 reserved_at_100[0xc];
519 u8 inner_ipv6_flow_label[0x14];
521 u8 reserved_at_120[0xa];
522 u8 geneve_opt_len[0x6];
523 u8 geneve_protocol_type[0x10];
525 u8 reserved_at_140[0x8];
527 u8 reserved_at_160[0x20];
528 u8 outer_esp_spi[0x20];
529 u8 reserved_at_1a0[0x60];
532 struct mlx5_ifc_fte_match_mpls_bits {
539 struct mlx5_ifc_fte_match_set_misc2_bits {
540 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
542 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
544 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
546 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
548 u8 metadata_reg_c_7[0x20];
550 u8 metadata_reg_c_6[0x20];
552 u8 metadata_reg_c_5[0x20];
554 u8 metadata_reg_c_4[0x20];
556 u8 metadata_reg_c_3[0x20];
558 u8 metadata_reg_c_2[0x20];
560 u8 metadata_reg_c_1[0x20];
562 u8 metadata_reg_c_0[0x20];
564 u8 metadata_reg_a[0x20];
566 u8 reserved_at_1a0[0x60];
569 struct mlx5_ifc_fte_match_set_misc3_bits {
570 u8 reserved_at_0[0x120];
571 u8 geneve_tlv_option_0_data[0x20];
572 u8 reserved_at_140[0xc0];
575 struct mlx5_ifc_cmd_pas_bits {
579 u8 reserved_at_34[0xc];
582 struct mlx5_ifc_uint64_bits {
589 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
590 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
591 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
592 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
593 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
594 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
595 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
596 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
597 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
598 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
601 struct mlx5_ifc_ads_bits {
604 u8 reserved_at_2[0xe];
607 u8 reserved_at_20[0x8];
613 u8 reserved_at_45[0x3];
614 u8 src_addr_index[0x8];
615 u8 reserved_at_50[0x4];
619 u8 reserved_at_60[0x4];
623 u8 rgid_rip[16][0x8];
625 u8 reserved_at_100[0x4];
628 u8 reserved_at_106[0x1];
637 u8 vhca_port_num[0x8];
643 struct mlx5_ifc_flow_table_nic_cap_bits {
644 u8 nic_rx_multi_path_tirs[0x1];
645 u8 nic_rx_multi_path_tirs_fts[0x1];
646 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
647 u8 reserved_at_3[0x1d];
648 u8 encap_general_header[0x1];
649 u8 reserved_at_21[0xa];
650 u8 log_max_packet_reformat_context[0x5];
651 u8 reserved_at_30[0x6];
652 u8 max_encap_header_size[0xa];
653 u8 reserved_at_40[0x1c0];
655 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
657 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
659 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
661 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
663 u8 reserved_at_a00[0x200];
665 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
667 u8 reserved_at_e00[0x7200];
671 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
672 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
673 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
674 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
675 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
676 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
677 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
678 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
681 struct mlx5_ifc_flow_table_eswitch_cap_bits {
682 u8 fdb_to_vport_reg_c_id[0x8];
683 u8 reserved_at_8[0xf];
685 u8 reserved_at_18[0x2];
686 u8 multi_fdb_encap[0x1];
687 u8 reserved_at_1b[0x1];
688 u8 fdb_multi_path_to_table[0x1];
689 u8 reserved_at_1d[0x3];
691 u8 reserved_at_20[0x1e0];
693 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
695 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
697 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
699 u8 reserved_at_800[0x7800];
703 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
704 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
707 struct mlx5_ifc_e_switch_cap_bits {
708 u8 vport_svlan_strip[0x1];
709 u8 vport_cvlan_strip[0x1];
710 u8 vport_svlan_insert[0x1];
711 u8 vport_cvlan_insert_if_not_exist[0x1];
712 u8 vport_cvlan_insert_overwrite[0x1];
713 u8 reserved_at_5[0x3];
714 u8 esw_uplink_ingress_acl[0x1];
715 u8 reserved_at_9[0x10];
716 u8 esw_functions_changed[0x1];
717 u8 reserved_at_1a[0x1];
718 u8 ecpf_vport_exists[0x1];
719 u8 counter_eswitch_affinity[0x1];
720 u8 merged_eswitch[0x1];
721 u8 nic_vport_node_guid_modify[0x1];
722 u8 nic_vport_port_guid_modify[0x1];
724 u8 vxlan_encap_decap[0x1];
725 u8 nvgre_encap_decap[0x1];
726 u8 reserved_at_22[0x1];
727 u8 log_max_fdb_encap_uplink[0x5];
728 u8 reserved_at_21[0x3];
729 u8 log_max_packet_reformat_context[0x5];
731 u8 max_encap_header_size[0xa];
733 u8 reserved_at_40[0xb];
734 u8 log_max_esw_sf[0x5];
735 u8 esw_sf_base_id[0x10];
737 u8 reserved_at_60[0x7a0];
741 struct mlx5_ifc_qos_cap_bits {
742 u8 packet_pacing[0x1];
743 u8 esw_scheduling[0x1];
744 u8 esw_bw_share[0x1];
745 u8 esw_rate_limit[0x1];
746 u8 reserved_at_4[0x1];
747 u8 packet_pacing_burst_bound[0x1];
748 u8 packet_pacing_typical_size[0x1];
749 u8 reserved_at_7[0x19];
751 u8 reserved_at_20[0x20];
753 u8 packet_pacing_max_rate[0x20];
755 u8 packet_pacing_min_rate[0x20];
757 u8 reserved_at_80[0x10];
758 u8 packet_pacing_rate_table_size[0x10];
760 u8 esw_element_type[0x10];
761 u8 esw_tsar_type[0x10];
763 u8 reserved_at_c0[0x10];
764 u8 max_qos_para_vport[0x10];
766 u8 max_tsar_bw_share[0x20];
768 u8 reserved_at_100[0x700];
771 struct mlx5_ifc_debug_cap_bits {
772 u8 core_dump_general[0x1];
773 u8 core_dump_qp[0x1];
774 u8 reserved_at_2[0x1e];
776 u8 reserved_at_20[0x2];
777 u8 stall_detect[0x1];
778 u8 reserved_at_23[0x1d];
780 u8 reserved_at_40[0x7c0];
783 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
787 u8 lro_psh_flag[0x1];
788 u8 lro_time_stamp[0x1];
789 u8 reserved_at_5[0x2];
790 u8 wqe_vlan_insert[0x1];
791 u8 self_lb_en_modifiable[0x1];
792 u8 reserved_at_9[0x2];
794 u8 multi_pkt_send_wqe[0x2];
795 u8 wqe_inline_mode[0x2];
796 u8 rss_ind_tbl_cap[0x4];
799 u8 enhanced_multi_pkt_send_wqe[0x1];
800 u8 tunnel_lso_const_out_ip_id[0x1];
801 u8 reserved_at_1c[0x2];
802 u8 tunnel_stateless_gre[0x1];
803 u8 tunnel_stateless_vxlan[0x1];
808 u8 cqe_checksum_full[0x1];
809 u8 reserved_at_24[0xc];
810 u8 max_vxlan_udp_ports[0x8];
811 u8 reserved_at_38[0x6];
812 u8 max_geneve_opt_len[0x1];
813 u8 tunnel_stateless_geneve_rx[0x1];
815 u8 reserved_at_40[0x10];
816 u8 lro_min_mss_size[0x10];
818 u8 reserved_at_60[0x120];
820 u8 lro_timer_supported_periods[4][0x20];
822 u8 reserved_at_200[0x600];
825 struct mlx5_ifc_roce_cap_bits {
827 u8 reserved_at_1[0x1f];
829 u8 reserved_at_20[0x60];
831 u8 reserved_at_80[0xc];
833 u8 reserved_at_90[0x8];
834 u8 roce_version[0x8];
836 u8 reserved_at_a0[0x10];
837 u8 r_roce_dest_udp_port[0x10];
839 u8 r_roce_max_src_udp_port[0x10];
840 u8 r_roce_min_src_udp_port[0x10];
842 u8 reserved_at_e0[0x10];
843 u8 roce_address_table_size[0x10];
845 u8 reserved_at_100[0x700];
848 struct mlx5_ifc_device_mem_cap_bits {
850 u8 reserved_at_1[0x1f];
852 u8 reserved_at_20[0xb];
853 u8 log_min_memic_alloc_size[0x5];
854 u8 reserved_at_30[0x8];
855 u8 log_max_memic_addr_alignment[0x8];
857 u8 memic_bar_start_addr[0x40];
859 u8 memic_bar_size[0x20];
861 u8 max_memic_size[0x20];
863 u8 steering_sw_icm_start_address[0x40];
865 u8 reserved_at_100[0x8];
866 u8 log_header_modify_sw_icm_size[0x8];
867 u8 reserved_at_110[0x2];
868 u8 log_sw_icm_alloc_granularity[0x6];
869 u8 log_steering_sw_icm_size[0x8];
871 u8 reserved_at_120[0x20];
873 u8 header_modify_sw_icm_start_address[0x40];
875 u8 reserved_at_180[0x680];
878 struct mlx5_ifc_device_event_cap_bits {
879 u8 user_affiliated_events[4][0x40];
881 u8 user_unaffiliated_events[4][0x40];
885 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
886 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
887 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
888 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
889 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
890 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
891 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
892 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
893 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
897 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
898 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
899 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
900 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
901 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
902 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
903 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
904 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
905 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
908 struct mlx5_ifc_atomic_caps_bits {
909 u8 reserved_at_0[0x40];
911 u8 atomic_req_8B_endianness_mode[0x2];
912 u8 reserved_at_42[0x4];
913 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
915 u8 reserved_at_47[0x19];
917 u8 reserved_at_60[0x20];
919 u8 reserved_at_80[0x10];
920 u8 atomic_operations[0x10];
922 u8 reserved_at_a0[0x10];
923 u8 atomic_size_qp[0x10];
925 u8 reserved_at_c0[0x10];
926 u8 atomic_size_dc[0x10];
928 u8 reserved_at_e0[0x720];
931 struct mlx5_ifc_odp_cap_bits {
932 u8 reserved_at_0[0x40];
935 u8 reserved_at_41[0x1f];
937 u8 reserved_at_60[0x20];
939 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
941 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
943 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
945 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
947 u8 reserved_at_100[0x700];
950 struct mlx5_ifc_calc_op {
951 u8 reserved_at_0[0x10];
952 u8 reserved_at_10[0x9];
953 u8 op_swap_endianness[0x1];
962 struct mlx5_ifc_vector_calc_cap_bits {
964 u8 reserved_at_1[0x1f];
965 u8 reserved_at_20[0x8];
966 u8 max_vec_count[0x8];
967 u8 reserved_at_30[0xd];
968 u8 max_chunk_size[0x3];
969 struct mlx5_ifc_calc_op calc0;
970 struct mlx5_ifc_calc_op calc1;
971 struct mlx5_ifc_calc_op calc2;
972 struct mlx5_ifc_calc_op calc3;
974 u8 reserved_at_c0[0x720];
977 struct mlx5_ifc_tls_cap_bits {
978 u8 tls_1_2_aes_gcm_128[0x1];
979 u8 tls_1_3_aes_gcm_128[0x1];
980 u8 tls_1_2_aes_gcm_256[0x1];
981 u8 tls_1_3_aes_gcm_256[0x1];
982 u8 reserved_at_4[0x1c];
984 u8 reserved_at_20[0x7e0];
988 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
989 MLX5_WQ_TYPE_CYCLIC = 0x1,
990 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
991 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
995 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
996 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1000 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1001 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1002 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1003 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1004 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1008 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1009 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1010 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1011 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1012 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1013 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1017 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1018 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1022 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1023 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1024 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1028 MLX5_CAP_PORT_TYPE_IB = 0x0,
1029 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1033 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1034 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1035 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1039 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1040 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1043 struct mlx5_ifc_cmd_hca_cap_bits {
1044 u8 reserved_at_0[0x30];
1047 u8 reserved_at_40[0x40];
1049 u8 log_max_srq_sz[0x8];
1050 u8 log_max_qp_sz[0x8];
1052 u8 reserved_at_91[0x7];
1053 u8 prio_tag_required[0x1];
1054 u8 reserved_at_99[0x2];
1057 u8 reserved_at_a0[0xb];
1058 u8 log_max_srq[0x5];
1059 u8 reserved_at_b0[0x10];
1061 u8 reserved_at_c0[0x8];
1062 u8 log_max_cq_sz[0x8];
1063 u8 reserved_at_d0[0xb];
1066 u8 log_max_eq_sz[0x8];
1067 u8 reserved_at_e8[0x2];
1068 u8 log_max_mkey[0x6];
1069 u8 reserved_at_f0[0x8];
1070 u8 dump_fill_mkey[0x1];
1071 u8 reserved_at_f9[0x2];
1072 u8 fast_teardown[0x1];
1075 u8 max_indirection[0x8];
1076 u8 fixed_buffer_size[0x1];
1077 u8 log_max_mrw_sz[0x7];
1078 u8 force_teardown[0x1];
1079 u8 reserved_at_111[0x1];
1080 u8 log_max_bsf_list_size[0x6];
1081 u8 umr_extended_translation_offset[0x1];
1083 u8 log_max_klm_list_size[0x6];
1085 u8 reserved_at_120[0xa];
1086 u8 log_max_ra_req_dc[0x6];
1087 u8 reserved_at_130[0xa];
1088 u8 log_max_ra_res_dc[0x6];
1090 u8 reserved_at_140[0xa];
1091 u8 log_max_ra_req_qp[0x6];
1092 u8 reserved_at_150[0xa];
1093 u8 log_max_ra_res_qp[0x6];
1096 u8 cc_query_allowed[0x1];
1097 u8 cc_modify_allowed[0x1];
1099 u8 cache_line_128byte[0x1];
1100 u8 reserved_at_165[0x4];
1101 u8 rts2rts_qp_counters_set_id[0x1];
1102 u8 reserved_at_16a[0x5];
1104 u8 gid_table_size[0x10];
1106 u8 out_of_seq_cnt[0x1];
1107 u8 vport_counters[0x1];
1108 u8 retransmission_q_counters[0x1];
1110 u8 modify_rq_counter_set_id[0x1];
1111 u8 rq_delay_drop[0x1];
1113 u8 pkey_table_size[0x10];
1115 u8 vport_group_manager[0x1];
1116 u8 vhca_group_manager[0x1];
1119 u8 vnic_env_queue_counters[0x1];
1121 u8 nic_flow_table[0x1];
1122 u8 eswitch_manager[0x1];
1123 u8 device_memory[0x1];
1126 u8 local_ca_ack_delay[0x5];
1127 u8 port_module_event[0x1];
1128 u8 enhanced_error_q_counters[0x1];
1129 u8 ports_check[0x1];
1130 u8 reserved_at_1b3[0x1];
1131 u8 disable_link_up[0x1];
1136 u8 reserved_at_1c0[0x1];
1139 u8 log_max_msg[0x5];
1140 u8 reserved_at_1c8[0x4];
1142 u8 temp_warn_event[0x1];
1144 u8 general_notification_event[0x1];
1145 u8 reserved_at_1d3[0x2];
1149 u8 reserved_at_1d8[0x1];
1158 u8 stat_rate_support[0x10];
1159 u8 reserved_at_1f0[0xc];
1160 u8 cqe_version[0x4];
1162 u8 compact_address_vector[0x1];
1163 u8 striding_rq[0x1];
1164 u8 reserved_at_202[0x1];
1165 u8 ipoib_enhanced_offloads[0x1];
1166 u8 ipoib_basic_offloads[0x1];
1167 u8 reserved_at_205[0x1];
1168 u8 repeated_block_disabled[0x1];
1169 u8 umr_modify_entity_size_disabled[0x1];
1170 u8 umr_modify_atomic_disabled[0x1];
1171 u8 umr_indirect_mkey_disabled[0x1];
1173 u8 dc_req_scat_data_cqe[0x1];
1174 u8 reserved_at_20d[0x2];
1175 u8 drain_sigerr[0x1];
1176 u8 cmdif_checksum[0x2];
1178 u8 reserved_at_213[0x1];
1179 u8 wq_signature[0x1];
1180 u8 sctr_data_cqe[0x1];
1181 u8 reserved_at_216[0x1];
1187 u8 eth_net_offloads[0x1];
1190 u8 reserved_at_21f[0x1];
1194 u8 cq_moderation[0x1];
1195 u8 reserved_at_223[0x3];
1196 u8 cq_eq_remap[0x1];
1198 u8 block_lb_mc[0x1];
1199 u8 reserved_at_229[0x1];
1200 u8 scqe_break_moderation[0x1];
1201 u8 cq_period_start_from_cqe[0x1];
1203 u8 reserved_at_22d[0x1];
1205 u8 vector_calc[0x1];
1206 u8 umr_ptr_rlky[0x1];
1208 u8 qp_packet_based[0x1];
1209 u8 reserved_at_233[0x3];
1212 u8 set_deth_sqpn[0x1];
1213 u8 reserved_at_239[0x3];
1220 u8 reserved_at_241[0x9];
1222 u8 reserved_at_250[0x8];
1226 u8 driver_version[0x1];
1227 u8 pad_tx_eth_packet[0x1];
1228 u8 reserved_at_263[0x8];
1229 u8 log_bf_reg_size[0x5];
1231 u8 reserved_at_270[0xb];
1233 u8 num_lag_ports[0x4];
1235 u8 reserved_at_280[0x10];
1236 u8 max_wqe_sz_sq[0x10];
1238 u8 reserved_at_2a0[0x10];
1239 u8 max_wqe_sz_rq[0x10];
1241 u8 max_flow_counter_31_16[0x10];
1242 u8 max_wqe_sz_sq_dc[0x10];
1244 u8 reserved_at_2e0[0x7];
1245 u8 max_qp_mcg[0x19];
1247 u8 reserved_at_300[0x18];
1248 u8 log_max_mcg[0x8];
1250 u8 reserved_at_320[0x3];
1251 u8 log_max_transport_domain[0x5];
1252 u8 reserved_at_328[0x3];
1254 u8 reserved_at_330[0xb];
1255 u8 log_max_xrcd[0x5];
1257 u8 nic_receive_steering_discard[0x1];
1258 u8 receive_discard_vport_down[0x1];
1259 u8 transmit_discard_vport_down[0x1];
1260 u8 reserved_at_343[0x5];
1261 u8 log_max_flow_counter_bulk[0x8];
1262 u8 max_flow_counter_15_0[0x10];
1265 u8 reserved_at_360[0x3];
1267 u8 reserved_at_368[0x3];
1269 u8 reserved_at_370[0x3];
1270 u8 log_max_tir[0x5];
1271 u8 reserved_at_378[0x3];
1272 u8 log_max_tis[0x5];
1274 u8 basic_cyclic_rcv_wqe[0x1];
1275 u8 reserved_at_381[0x2];
1276 u8 log_max_rmp[0x5];
1277 u8 reserved_at_388[0x3];
1278 u8 log_max_rqt[0x5];
1279 u8 reserved_at_390[0x3];
1280 u8 log_max_rqt_size[0x5];
1281 u8 reserved_at_398[0x3];
1282 u8 log_max_tis_per_sq[0x5];
1284 u8 ext_stride_num_range[0x1];
1285 u8 reserved_at_3a1[0x2];
1286 u8 log_max_stride_sz_rq[0x5];
1287 u8 reserved_at_3a8[0x3];
1288 u8 log_min_stride_sz_rq[0x5];
1289 u8 reserved_at_3b0[0x3];
1290 u8 log_max_stride_sz_sq[0x5];
1291 u8 reserved_at_3b8[0x3];
1292 u8 log_min_stride_sz_sq[0x5];
1295 u8 reserved_at_3c1[0x2];
1296 u8 log_max_hairpin_queues[0x5];
1297 u8 reserved_at_3c8[0x3];
1298 u8 log_max_hairpin_wq_data_sz[0x5];
1299 u8 reserved_at_3d0[0x3];
1300 u8 log_max_hairpin_num_packets[0x5];
1301 u8 reserved_at_3d8[0x3];
1302 u8 log_max_wq_sz[0x5];
1304 u8 nic_vport_change_event[0x1];
1305 u8 disable_local_lb_uc[0x1];
1306 u8 disable_local_lb_mc[0x1];
1307 u8 log_min_hairpin_wq_data_sz[0x5];
1308 u8 reserved_at_3e8[0x3];
1309 u8 log_max_vlan_list[0x5];
1310 u8 reserved_at_3f0[0x3];
1311 u8 log_max_current_mc_list[0x5];
1312 u8 reserved_at_3f8[0x3];
1313 u8 log_max_current_uc_list[0x5];
1315 u8 general_obj_types[0x40];
1317 u8 reserved_at_440[0x20];
1320 u8 reserved_at_461[0x2];
1321 u8 log_max_uctx[0x5];
1322 u8 reserved_at_468[0x3];
1323 u8 log_max_umem[0x5];
1324 u8 max_num_eqs[0x10];
1326 u8 reserved_at_480[0x3];
1327 u8 log_max_l2_table[0x5];
1328 u8 reserved_at_488[0x8];
1329 u8 log_uar_page_sz[0x10];
1331 u8 reserved_at_4a0[0x20];
1332 u8 device_frequency_mhz[0x20];
1333 u8 device_frequency_khz[0x20];
1335 u8 reserved_at_500[0x20];
1336 u8 num_of_uars_per_page[0x20];
1338 u8 flex_parser_protocols[0x20];
1340 u8 max_geneve_tlv_options[0x8];
1341 u8 reserved_at_568[0x3];
1342 u8 max_geneve_tlv_option_data_len[0x5];
1343 u8 reserved_at_570[0x10];
1345 u8 reserved_at_580[0x33];
1346 u8 log_max_dek[0x5];
1347 u8 reserved_at_5b8[0x4];
1348 u8 mini_cqe_resp_stride_index[0x1];
1349 u8 cqe_128_always[0x1];
1350 u8 cqe_compression_128[0x1];
1351 u8 cqe_compression[0x1];
1353 u8 cqe_compression_timeout[0x10];
1354 u8 cqe_compression_max_num[0x10];
1356 u8 reserved_at_5e0[0x10];
1357 u8 tag_matching[0x1];
1358 u8 rndv_offload_rc[0x1];
1359 u8 rndv_offload_dc[0x1];
1360 u8 log_tag_matching_list_sz[0x5];
1361 u8 reserved_at_5f8[0x3];
1362 u8 log_max_xrq[0x5];
1364 u8 affiliate_nic_vport_criteria[0x8];
1365 u8 native_port_num[0x8];
1366 u8 num_vhca_ports[0x8];
1367 u8 reserved_at_618[0x6];
1368 u8 sw_owner_id[0x1];
1369 u8 reserved_at_61f[0x1];
1371 u8 max_num_of_monitor_counters[0x10];
1372 u8 num_ppcnt_monitor_counters[0x10];
1374 u8 reserved_at_640[0x10];
1375 u8 num_q_monitor_counters[0x10];
1377 u8 reserved_at_660[0x20];
1380 u8 sf_set_partition[0x1];
1381 u8 reserved_at_682[0x1];
1383 u8 reserved_at_688[0x8];
1384 u8 log_min_sf_size[0x8];
1385 u8 max_num_sf_partitions[0x8];
1389 u8 reserved_at_6c0[0x4];
1390 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1391 u8 reserved_at_6c8[0x28];
1392 u8 sf_base_id[0x10];
1394 u8 reserved_at_700[0x80];
1395 u8 vhca_tunnel_commands[0x40];
1396 u8 reserved_at_7c0[0x40];
1399 enum mlx5_flow_destination_type {
1400 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1401 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1402 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1404 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1405 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1406 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1409 enum mlx5_flow_table_miss_action {
1410 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1411 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1412 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1415 struct mlx5_ifc_dest_format_struct_bits {
1416 u8 destination_type[0x8];
1417 u8 destination_id[0x18];
1419 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1420 u8 packet_reformat[0x1];
1421 u8 reserved_at_22[0xe];
1422 u8 destination_eswitch_owner_vhca_id[0x10];
1425 struct mlx5_ifc_flow_counter_list_bits {
1426 u8 flow_counter_id[0x20];
1428 u8 reserved_at_20[0x20];
1431 struct mlx5_ifc_extended_dest_format_bits {
1432 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1434 u8 packet_reformat_id[0x20];
1436 u8 reserved_at_60[0x20];
1439 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1440 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1441 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1442 u8 reserved_at_0[0x40];
1445 struct mlx5_ifc_fte_match_param_bits {
1446 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1448 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1450 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1452 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1454 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1456 u8 reserved_at_a00[0x600];
1460 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1461 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1462 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1463 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1464 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1467 struct mlx5_ifc_rx_hash_field_select_bits {
1468 u8 l3_prot_type[0x1];
1469 u8 l4_prot_type[0x1];
1470 u8 selected_fields[0x1e];
1474 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1475 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1479 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1480 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1483 struct mlx5_ifc_wq_bits {
1485 u8 wq_signature[0x1];
1486 u8 end_padding_mode[0x2];
1488 u8 reserved_at_8[0x18];
1490 u8 hds_skip_first_sge[0x1];
1491 u8 log2_hds_buf_size[0x3];
1492 u8 reserved_at_24[0x7];
1493 u8 page_offset[0x5];
1496 u8 reserved_at_40[0x8];
1499 u8 reserved_at_60[0x8];
1504 u8 hw_counter[0x20];
1506 u8 sw_counter[0x20];
1508 u8 reserved_at_100[0xc];
1509 u8 log_wq_stride[0x4];
1510 u8 reserved_at_110[0x3];
1511 u8 log_wq_pg_sz[0x5];
1512 u8 reserved_at_118[0x3];
1515 u8 dbr_umem_valid[0x1];
1516 u8 wq_umem_valid[0x1];
1517 u8 reserved_at_122[0x1];
1518 u8 log_hairpin_num_packets[0x5];
1519 u8 reserved_at_128[0x3];
1520 u8 log_hairpin_data_sz[0x5];
1522 u8 reserved_at_130[0x4];
1523 u8 log_wqe_num_of_strides[0x4];
1524 u8 two_byte_shift_en[0x1];
1525 u8 reserved_at_139[0x4];
1526 u8 log_wqe_stride_size[0x3];
1528 u8 reserved_at_140[0x4c0];
1530 struct mlx5_ifc_cmd_pas_bits pas[0];
1533 struct mlx5_ifc_rq_num_bits {
1534 u8 reserved_at_0[0x8];
1538 struct mlx5_ifc_mac_address_layout_bits {
1539 u8 reserved_at_0[0x10];
1540 u8 mac_addr_47_32[0x10];
1542 u8 mac_addr_31_0[0x20];
1545 struct mlx5_ifc_vlan_layout_bits {
1546 u8 reserved_at_0[0x14];
1549 u8 reserved_at_20[0x20];
1552 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1553 u8 reserved_at_0[0xa0];
1555 u8 min_time_between_cnps[0x20];
1557 u8 reserved_at_c0[0x12];
1559 u8 reserved_at_d8[0x4];
1560 u8 cnp_prio_mode[0x1];
1561 u8 cnp_802p_prio[0x3];
1563 u8 reserved_at_e0[0x720];
1566 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1567 u8 reserved_at_0[0x60];
1569 u8 reserved_at_60[0x4];
1570 u8 clamp_tgt_rate[0x1];
1571 u8 reserved_at_65[0x3];
1572 u8 clamp_tgt_rate_after_time_inc[0x1];
1573 u8 reserved_at_69[0x17];
1575 u8 reserved_at_80[0x20];
1577 u8 rpg_time_reset[0x20];
1579 u8 rpg_byte_reset[0x20];
1581 u8 rpg_threshold[0x20];
1583 u8 rpg_max_rate[0x20];
1585 u8 rpg_ai_rate[0x20];
1587 u8 rpg_hai_rate[0x20];
1591 u8 rpg_min_dec_fac[0x20];
1593 u8 rpg_min_rate[0x20];
1595 u8 reserved_at_1c0[0xe0];
1597 u8 rate_to_set_on_first_cnp[0x20];
1601 u8 dce_tcp_rtt[0x20];
1603 u8 rate_reduce_monitor_period[0x20];
1605 u8 reserved_at_320[0x20];
1607 u8 initial_alpha_value[0x20];
1609 u8 reserved_at_360[0x4a0];
1612 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1613 u8 reserved_at_0[0x80];
1615 u8 rppp_max_rps[0x20];
1617 u8 rpg_time_reset[0x20];
1619 u8 rpg_byte_reset[0x20];
1621 u8 rpg_threshold[0x20];
1623 u8 rpg_max_rate[0x20];
1625 u8 rpg_ai_rate[0x20];
1627 u8 rpg_hai_rate[0x20];
1631 u8 rpg_min_dec_fac[0x20];
1633 u8 rpg_min_rate[0x20];
1635 u8 reserved_at_1c0[0x640];
1639 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1640 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1641 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1644 struct mlx5_ifc_resize_field_select_bits {
1645 u8 resize_field_select[0x20];
1649 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1650 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1651 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1652 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1655 struct mlx5_ifc_modify_field_select_bits {
1656 u8 modify_field_select[0x20];
1659 struct mlx5_ifc_field_select_r_roce_np_bits {
1660 u8 field_select_r_roce_np[0x20];
1663 struct mlx5_ifc_field_select_r_roce_rp_bits {
1664 u8 field_select_r_roce_rp[0x20];
1668 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1669 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1670 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1671 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1672 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1673 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1674 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1675 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1676 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1677 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1680 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1681 u8 field_select_8021qaurp[0x20];
1684 struct mlx5_ifc_phys_layer_cntrs_bits {
1685 u8 time_since_last_clear_high[0x20];
1687 u8 time_since_last_clear_low[0x20];
1689 u8 symbol_errors_high[0x20];
1691 u8 symbol_errors_low[0x20];
1693 u8 sync_headers_errors_high[0x20];
1695 u8 sync_headers_errors_low[0x20];
1697 u8 edpl_bip_errors_lane0_high[0x20];
1699 u8 edpl_bip_errors_lane0_low[0x20];
1701 u8 edpl_bip_errors_lane1_high[0x20];
1703 u8 edpl_bip_errors_lane1_low[0x20];
1705 u8 edpl_bip_errors_lane2_high[0x20];
1707 u8 edpl_bip_errors_lane2_low[0x20];
1709 u8 edpl_bip_errors_lane3_high[0x20];
1711 u8 edpl_bip_errors_lane3_low[0x20];
1713 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1715 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1717 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1719 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1721 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1723 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1725 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1727 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1729 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1731 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1733 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1735 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1737 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1739 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1741 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1743 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1745 u8 rs_fec_corrected_blocks_high[0x20];
1747 u8 rs_fec_corrected_blocks_low[0x20];
1749 u8 rs_fec_uncorrectable_blocks_high[0x20];
1751 u8 rs_fec_uncorrectable_blocks_low[0x20];
1753 u8 rs_fec_no_errors_blocks_high[0x20];
1755 u8 rs_fec_no_errors_blocks_low[0x20];
1757 u8 rs_fec_single_error_blocks_high[0x20];
1759 u8 rs_fec_single_error_blocks_low[0x20];
1761 u8 rs_fec_corrected_symbols_total_high[0x20];
1763 u8 rs_fec_corrected_symbols_total_low[0x20];
1765 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1767 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1769 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1771 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1773 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1775 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1777 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1779 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1781 u8 link_down_events[0x20];
1783 u8 successful_recovery_events[0x20];
1785 u8 reserved_at_640[0x180];
1788 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1789 u8 time_since_last_clear_high[0x20];
1791 u8 time_since_last_clear_low[0x20];
1793 u8 phy_received_bits_high[0x20];
1795 u8 phy_received_bits_low[0x20];
1797 u8 phy_symbol_errors_high[0x20];
1799 u8 phy_symbol_errors_low[0x20];
1801 u8 phy_corrected_bits_high[0x20];
1803 u8 phy_corrected_bits_low[0x20];
1805 u8 phy_corrected_bits_lane0_high[0x20];
1807 u8 phy_corrected_bits_lane0_low[0x20];
1809 u8 phy_corrected_bits_lane1_high[0x20];
1811 u8 phy_corrected_bits_lane1_low[0x20];
1813 u8 phy_corrected_bits_lane2_high[0x20];
1815 u8 phy_corrected_bits_lane2_low[0x20];
1817 u8 phy_corrected_bits_lane3_high[0x20];
1819 u8 phy_corrected_bits_lane3_low[0x20];
1821 u8 reserved_at_200[0x5c0];
1824 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1825 u8 symbol_error_counter[0x10];
1827 u8 link_error_recovery_counter[0x8];
1829 u8 link_downed_counter[0x8];
1831 u8 port_rcv_errors[0x10];
1833 u8 port_rcv_remote_physical_errors[0x10];
1835 u8 port_rcv_switch_relay_errors[0x10];
1837 u8 port_xmit_discards[0x10];
1839 u8 port_xmit_constraint_errors[0x8];
1841 u8 port_rcv_constraint_errors[0x8];
1843 u8 reserved_at_70[0x8];
1845 u8 link_overrun_errors[0x8];
1847 u8 reserved_at_80[0x10];
1849 u8 vl_15_dropped[0x10];
1851 u8 reserved_at_a0[0x80];
1853 u8 port_xmit_wait[0x20];
1856 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1857 u8 transmit_queue_high[0x20];
1859 u8 transmit_queue_low[0x20];
1861 u8 reserved_at_40[0x780];
1864 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1865 u8 rx_octets_high[0x20];
1867 u8 rx_octets_low[0x20];
1869 u8 reserved_at_40[0xc0];
1871 u8 rx_frames_high[0x20];
1873 u8 rx_frames_low[0x20];
1875 u8 tx_octets_high[0x20];
1877 u8 tx_octets_low[0x20];
1879 u8 reserved_at_180[0xc0];
1881 u8 tx_frames_high[0x20];
1883 u8 tx_frames_low[0x20];
1885 u8 rx_pause_high[0x20];
1887 u8 rx_pause_low[0x20];
1889 u8 rx_pause_duration_high[0x20];
1891 u8 rx_pause_duration_low[0x20];
1893 u8 tx_pause_high[0x20];
1895 u8 tx_pause_low[0x20];
1897 u8 tx_pause_duration_high[0x20];
1899 u8 tx_pause_duration_low[0x20];
1901 u8 rx_pause_transition_high[0x20];
1903 u8 rx_pause_transition_low[0x20];
1905 u8 reserved_at_3c0[0x40];
1907 u8 device_stall_minor_watermark_cnt_high[0x20];
1909 u8 device_stall_minor_watermark_cnt_low[0x20];
1911 u8 device_stall_critical_watermark_cnt_high[0x20];
1913 u8 device_stall_critical_watermark_cnt_low[0x20];
1915 u8 reserved_at_480[0x340];
1918 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1919 u8 port_transmit_wait_high[0x20];
1921 u8 port_transmit_wait_low[0x20];
1923 u8 reserved_at_40[0x100];
1925 u8 rx_buffer_almost_full_high[0x20];
1927 u8 rx_buffer_almost_full_low[0x20];
1929 u8 rx_buffer_full_high[0x20];
1931 u8 rx_buffer_full_low[0x20];
1933 u8 rx_icrc_encapsulated_high[0x20];
1935 u8 rx_icrc_encapsulated_low[0x20];
1937 u8 reserved_at_200[0x5c0];
1940 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1941 u8 dot3stats_alignment_errors_high[0x20];
1943 u8 dot3stats_alignment_errors_low[0x20];
1945 u8 dot3stats_fcs_errors_high[0x20];
1947 u8 dot3stats_fcs_errors_low[0x20];
1949 u8 dot3stats_single_collision_frames_high[0x20];
1951 u8 dot3stats_single_collision_frames_low[0x20];
1953 u8 dot3stats_multiple_collision_frames_high[0x20];
1955 u8 dot3stats_multiple_collision_frames_low[0x20];
1957 u8 dot3stats_sqe_test_errors_high[0x20];
1959 u8 dot3stats_sqe_test_errors_low[0x20];
1961 u8 dot3stats_deferred_transmissions_high[0x20];
1963 u8 dot3stats_deferred_transmissions_low[0x20];
1965 u8 dot3stats_late_collisions_high[0x20];
1967 u8 dot3stats_late_collisions_low[0x20];
1969 u8 dot3stats_excessive_collisions_high[0x20];
1971 u8 dot3stats_excessive_collisions_low[0x20];
1973 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1975 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1977 u8 dot3stats_carrier_sense_errors_high[0x20];
1979 u8 dot3stats_carrier_sense_errors_low[0x20];
1981 u8 dot3stats_frame_too_longs_high[0x20];
1983 u8 dot3stats_frame_too_longs_low[0x20];
1985 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1987 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1989 u8 dot3stats_symbol_errors_high[0x20];
1991 u8 dot3stats_symbol_errors_low[0x20];
1993 u8 dot3control_in_unknown_opcodes_high[0x20];
1995 u8 dot3control_in_unknown_opcodes_low[0x20];
1997 u8 dot3in_pause_frames_high[0x20];
1999 u8 dot3in_pause_frames_low[0x20];
2001 u8 dot3out_pause_frames_high[0x20];
2003 u8 dot3out_pause_frames_low[0x20];
2005 u8 reserved_at_400[0x3c0];
2008 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2009 u8 ether_stats_drop_events_high[0x20];
2011 u8 ether_stats_drop_events_low[0x20];
2013 u8 ether_stats_octets_high[0x20];
2015 u8 ether_stats_octets_low[0x20];
2017 u8 ether_stats_pkts_high[0x20];
2019 u8 ether_stats_pkts_low[0x20];
2021 u8 ether_stats_broadcast_pkts_high[0x20];
2023 u8 ether_stats_broadcast_pkts_low[0x20];
2025 u8 ether_stats_multicast_pkts_high[0x20];
2027 u8 ether_stats_multicast_pkts_low[0x20];
2029 u8 ether_stats_crc_align_errors_high[0x20];
2031 u8 ether_stats_crc_align_errors_low[0x20];
2033 u8 ether_stats_undersize_pkts_high[0x20];
2035 u8 ether_stats_undersize_pkts_low[0x20];
2037 u8 ether_stats_oversize_pkts_high[0x20];
2039 u8 ether_stats_oversize_pkts_low[0x20];
2041 u8 ether_stats_fragments_high[0x20];
2043 u8 ether_stats_fragments_low[0x20];
2045 u8 ether_stats_jabbers_high[0x20];
2047 u8 ether_stats_jabbers_low[0x20];
2049 u8 ether_stats_collisions_high[0x20];
2051 u8 ether_stats_collisions_low[0x20];
2053 u8 ether_stats_pkts64octets_high[0x20];
2055 u8 ether_stats_pkts64octets_low[0x20];
2057 u8 ether_stats_pkts65to127octets_high[0x20];
2059 u8 ether_stats_pkts65to127octets_low[0x20];
2061 u8 ether_stats_pkts128to255octets_high[0x20];
2063 u8 ether_stats_pkts128to255octets_low[0x20];
2065 u8 ether_stats_pkts256to511octets_high[0x20];
2067 u8 ether_stats_pkts256to511octets_low[0x20];
2069 u8 ether_stats_pkts512to1023octets_high[0x20];
2071 u8 ether_stats_pkts512to1023octets_low[0x20];
2073 u8 ether_stats_pkts1024to1518octets_high[0x20];
2075 u8 ether_stats_pkts1024to1518octets_low[0x20];
2077 u8 ether_stats_pkts1519to2047octets_high[0x20];
2079 u8 ether_stats_pkts1519to2047octets_low[0x20];
2081 u8 ether_stats_pkts2048to4095octets_high[0x20];
2083 u8 ether_stats_pkts2048to4095octets_low[0x20];
2085 u8 ether_stats_pkts4096to8191octets_high[0x20];
2087 u8 ether_stats_pkts4096to8191octets_low[0x20];
2089 u8 ether_stats_pkts8192to10239octets_high[0x20];
2091 u8 ether_stats_pkts8192to10239octets_low[0x20];
2093 u8 reserved_at_540[0x280];
2096 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2097 u8 if_in_octets_high[0x20];
2099 u8 if_in_octets_low[0x20];
2101 u8 if_in_ucast_pkts_high[0x20];
2103 u8 if_in_ucast_pkts_low[0x20];
2105 u8 if_in_discards_high[0x20];
2107 u8 if_in_discards_low[0x20];
2109 u8 if_in_errors_high[0x20];
2111 u8 if_in_errors_low[0x20];
2113 u8 if_in_unknown_protos_high[0x20];
2115 u8 if_in_unknown_protos_low[0x20];
2117 u8 if_out_octets_high[0x20];
2119 u8 if_out_octets_low[0x20];
2121 u8 if_out_ucast_pkts_high[0x20];
2123 u8 if_out_ucast_pkts_low[0x20];
2125 u8 if_out_discards_high[0x20];
2127 u8 if_out_discards_low[0x20];
2129 u8 if_out_errors_high[0x20];
2131 u8 if_out_errors_low[0x20];
2133 u8 if_in_multicast_pkts_high[0x20];
2135 u8 if_in_multicast_pkts_low[0x20];
2137 u8 if_in_broadcast_pkts_high[0x20];
2139 u8 if_in_broadcast_pkts_low[0x20];
2141 u8 if_out_multicast_pkts_high[0x20];
2143 u8 if_out_multicast_pkts_low[0x20];
2145 u8 if_out_broadcast_pkts_high[0x20];
2147 u8 if_out_broadcast_pkts_low[0x20];
2149 u8 reserved_at_340[0x480];
2152 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2153 u8 a_frames_transmitted_ok_high[0x20];
2155 u8 a_frames_transmitted_ok_low[0x20];
2157 u8 a_frames_received_ok_high[0x20];
2159 u8 a_frames_received_ok_low[0x20];
2161 u8 a_frame_check_sequence_errors_high[0x20];
2163 u8 a_frame_check_sequence_errors_low[0x20];
2165 u8 a_alignment_errors_high[0x20];
2167 u8 a_alignment_errors_low[0x20];
2169 u8 a_octets_transmitted_ok_high[0x20];
2171 u8 a_octets_transmitted_ok_low[0x20];
2173 u8 a_octets_received_ok_high[0x20];
2175 u8 a_octets_received_ok_low[0x20];
2177 u8 a_multicast_frames_xmitted_ok_high[0x20];
2179 u8 a_multicast_frames_xmitted_ok_low[0x20];
2181 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2183 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2185 u8 a_multicast_frames_received_ok_high[0x20];
2187 u8 a_multicast_frames_received_ok_low[0x20];
2189 u8 a_broadcast_frames_received_ok_high[0x20];
2191 u8 a_broadcast_frames_received_ok_low[0x20];
2193 u8 a_in_range_length_errors_high[0x20];
2195 u8 a_in_range_length_errors_low[0x20];
2197 u8 a_out_of_range_length_field_high[0x20];
2199 u8 a_out_of_range_length_field_low[0x20];
2201 u8 a_frame_too_long_errors_high[0x20];
2203 u8 a_frame_too_long_errors_low[0x20];
2205 u8 a_symbol_error_during_carrier_high[0x20];
2207 u8 a_symbol_error_during_carrier_low[0x20];
2209 u8 a_mac_control_frames_transmitted_high[0x20];
2211 u8 a_mac_control_frames_transmitted_low[0x20];
2213 u8 a_mac_control_frames_received_high[0x20];
2215 u8 a_mac_control_frames_received_low[0x20];
2217 u8 a_unsupported_opcodes_received_high[0x20];
2219 u8 a_unsupported_opcodes_received_low[0x20];
2221 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2223 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2225 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2227 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2229 u8 reserved_at_4c0[0x300];
2232 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2233 u8 life_time_counter_high[0x20];
2235 u8 life_time_counter_low[0x20];
2241 u8 l0_to_recovery_eieos[0x20];
2243 u8 l0_to_recovery_ts[0x20];
2245 u8 l0_to_recovery_framing[0x20];
2247 u8 l0_to_recovery_retrain[0x20];
2249 u8 crc_error_dllp[0x20];
2251 u8 crc_error_tlp[0x20];
2253 u8 tx_overflow_buffer_pkt_high[0x20];
2255 u8 tx_overflow_buffer_pkt_low[0x20];
2257 u8 outbound_stalled_reads[0x20];
2259 u8 outbound_stalled_writes[0x20];
2261 u8 outbound_stalled_reads_events[0x20];
2263 u8 outbound_stalled_writes_events[0x20];
2265 u8 reserved_at_200[0x5c0];
2268 struct mlx5_ifc_cmd_inter_comp_event_bits {
2269 u8 command_completion_vector[0x20];
2271 u8 reserved_at_20[0xc0];
2274 struct mlx5_ifc_stall_vl_event_bits {
2275 u8 reserved_at_0[0x18];
2277 u8 reserved_at_19[0x3];
2280 u8 reserved_at_20[0xa0];
2283 struct mlx5_ifc_db_bf_congestion_event_bits {
2284 u8 event_subtype[0x8];
2285 u8 reserved_at_8[0x8];
2286 u8 congestion_level[0x8];
2287 u8 reserved_at_18[0x8];
2289 u8 reserved_at_20[0xa0];
2292 struct mlx5_ifc_gpio_event_bits {
2293 u8 reserved_at_0[0x60];
2295 u8 gpio_event_hi[0x20];
2297 u8 gpio_event_lo[0x20];
2299 u8 reserved_at_a0[0x40];
2302 struct mlx5_ifc_port_state_change_event_bits {
2303 u8 reserved_at_0[0x40];
2306 u8 reserved_at_44[0x1c];
2308 u8 reserved_at_60[0x80];
2311 struct mlx5_ifc_dropped_packet_logged_bits {
2312 u8 reserved_at_0[0xe0];
2316 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2317 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2320 struct mlx5_ifc_cq_error_bits {
2321 u8 reserved_at_0[0x8];
2324 u8 reserved_at_20[0x20];
2326 u8 reserved_at_40[0x18];
2329 u8 reserved_at_60[0x80];
2332 struct mlx5_ifc_rdma_page_fault_event_bits {
2333 u8 bytes_committed[0x20];
2337 u8 reserved_at_40[0x10];
2338 u8 packet_len[0x10];
2340 u8 rdma_op_len[0x20];
2344 u8 reserved_at_c0[0x5];
2351 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2352 u8 bytes_committed[0x20];
2354 u8 reserved_at_20[0x10];
2357 u8 reserved_at_40[0x10];
2360 u8 reserved_at_60[0x60];
2362 u8 reserved_at_c0[0x5];
2369 struct mlx5_ifc_qp_events_bits {
2370 u8 reserved_at_0[0xa0];
2373 u8 reserved_at_a8[0x18];
2375 u8 reserved_at_c0[0x8];
2376 u8 qpn_rqn_sqn[0x18];
2379 struct mlx5_ifc_dct_events_bits {
2380 u8 reserved_at_0[0xc0];
2382 u8 reserved_at_c0[0x8];
2383 u8 dct_number[0x18];
2386 struct mlx5_ifc_comp_event_bits {
2387 u8 reserved_at_0[0xc0];
2389 u8 reserved_at_c0[0x8];
2394 MLX5_QPC_STATE_RST = 0x0,
2395 MLX5_QPC_STATE_INIT = 0x1,
2396 MLX5_QPC_STATE_RTR = 0x2,
2397 MLX5_QPC_STATE_RTS = 0x3,
2398 MLX5_QPC_STATE_SQER = 0x4,
2399 MLX5_QPC_STATE_ERR = 0x6,
2400 MLX5_QPC_STATE_SQD = 0x7,
2401 MLX5_QPC_STATE_SUSPENDED = 0x9,
2405 MLX5_QPC_ST_RC = 0x0,
2406 MLX5_QPC_ST_UC = 0x1,
2407 MLX5_QPC_ST_UD = 0x2,
2408 MLX5_QPC_ST_XRC = 0x3,
2409 MLX5_QPC_ST_DCI = 0x5,
2410 MLX5_QPC_ST_QP0 = 0x7,
2411 MLX5_QPC_ST_QP1 = 0x8,
2412 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2413 MLX5_QPC_ST_REG_UMR = 0xc,
2417 MLX5_QPC_PM_STATE_ARMED = 0x0,
2418 MLX5_QPC_PM_STATE_REARM = 0x1,
2419 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2420 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2424 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2428 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2429 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2433 MLX5_QPC_MTU_256_BYTES = 0x1,
2434 MLX5_QPC_MTU_512_BYTES = 0x2,
2435 MLX5_QPC_MTU_1K_BYTES = 0x3,
2436 MLX5_QPC_MTU_2K_BYTES = 0x4,
2437 MLX5_QPC_MTU_4K_BYTES = 0x5,
2438 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2442 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2443 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2444 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2445 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2446 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2447 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2448 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2449 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2453 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2454 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2455 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2459 MLX5_QPC_CS_RES_DISABLE = 0x0,
2460 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2461 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2464 struct mlx5_ifc_qpc_bits {
2466 u8 lag_tx_port_affinity[0x4];
2468 u8 reserved_at_10[0x3];
2470 u8 reserved_at_15[0x1];
2471 u8 req_e2e_credit_mode[0x2];
2472 u8 offload_type[0x4];
2473 u8 end_padding_mode[0x2];
2474 u8 reserved_at_1e[0x2];
2476 u8 wq_signature[0x1];
2477 u8 block_lb_mc[0x1];
2478 u8 atomic_like_write_en[0x1];
2479 u8 latency_sensitive[0x1];
2480 u8 reserved_at_24[0x1];
2481 u8 drain_sigerr[0x1];
2482 u8 reserved_at_26[0x2];
2486 u8 log_msg_max[0x5];
2487 u8 reserved_at_48[0x1];
2488 u8 log_rq_size[0x4];
2489 u8 log_rq_stride[0x3];
2491 u8 log_sq_size[0x4];
2492 u8 reserved_at_55[0x6];
2494 u8 ulp_stateless_offload_mode[0x4];
2496 u8 counter_set_id[0x8];
2499 u8 reserved_at_80[0x8];
2500 u8 user_index[0x18];
2502 u8 reserved_at_a0[0x3];
2503 u8 log_page_size[0x5];
2504 u8 remote_qpn[0x18];
2506 struct mlx5_ifc_ads_bits primary_address_path;
2508 struct mlx5_ifc_ads_bits secondary_address_path;
2510 u8 log_ack_req_freq[0x4];
2511 u8 reserved_at_384[0x4];
2512 u8 log_sra_max[0x3];
2513 u8 reserved_at_38b[0x2];
2514 u8 retry_count[0x3];
2516 u8 reserved_at_393[0x1];
2518 u8 cur_rnr_retry[0x3];
2519 u8 cur_retry_count[0x3];
2520 u8 reserved_at_39b[0x5];
2522 u8 reserved_at_3a0[0x20];
2524 u8 reserved_at_3c0[0x8];
2525 u8 next_send_psn[0x18];
2527 u8 reserved_at_3e0[0x8];
2530 u8 reserved_at_400[0x8];
2533 u8 reserved_at_420[0x20];
2535 u8 reserved_at_440[0x8];
2536 u8 last_acked_psn[0x18];
2538 u8 reserved_at_460[0x8];
2541 u8 reserved_at_480[0x8];
2542 u8 log_rra_max[0x3];
2543 u8 reserved_at_48b[0x1];
2544 u8 atomic_mode[0x4];
2548 u8 reserved_at_493[0x1];
2549 u8 page_offset[0x6];
2550 u8 reserved_at_49a[0x3];
2551 u8 cd_slave_receive[0x1];
2552 u8 cd_slave_send[0x1];
2555 u8 reserved_at_4a0[0x3];
2556 u8 min_rnr_nak[0x5];
2557 u8 next_rcv_psn[0x18];
2559 u8 reserved_at_4c0[0x8];
2562 u8 reserved_at_4e0[0x8];
2569 u8 reserved_at_560[0x5];
2571 u8 srqn_rmpn_xrqn[0x18];
2573 u8 reserved_at_580[0x8];
2576 u8 hw_sq_wqebb_counter[0x10];
2577 u8 sw_sq_wqebb_counter[0x10];
2579 u8 hw_rq_counter[0x20];
2581 u8 sw_rq_counter[0x20];
2583 u8 reserved_at_600[0x20];
2585 u8 reserved_at_620[0xf];
2590 u8 dc_access_key[0x40];
2592 u8 reserved_at_680[0x3];
2593 u8 dbr_umem_valid[0x1];
2595 u8 reserved_at_684[0xbc];
2598 struct mlx5_ifc_roce_addr_layout_bits {
2599 u8 source_l3_address[16][0x8];
2601 u8 reserved_at_80[0x3];
2604 u8 source_mac_47_32[0x10];
2606 u8 source_mac_31_0[0x20];
2608 u8 reserved_at_c0[0x14];
2609 u8 roce_l3_type[0x4];
2610 u8 roce_version[0x8];
2612 u8 reserved_at_e0[0x20];
2615 union mlx5_ifc_hca_cap_union_bits {
2616 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2617 struct mlx5_ifc_odp_cap_bits odp_cap;
2618 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2619 struct mlx5_ifc_roce_cap_bits roce_cap;
2620 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2621 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2622 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2623 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2624 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2625 struct mlx5_ifc_qos_cap_bits qos_cap;
2626 struct mlx5_ifc_debug_cap_bits debug_cap;
2627 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2628 struct mlx5_ifc_tls_cap_bits tls_cap;
2629 u8 reserved_at_0[0x8000];
2633 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2634 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2635 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2636 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2637 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2638 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2639 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2640 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2641 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2642 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2643 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2647 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2648 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2649 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2652 struct mlx5_ifc_vlan_bits {
2659 struct mlx5_ifc_flow_context_bits {
2660 struct mlx5_ifc_vlan_bits push_vlan;
2664 u8 reserved_at_40[0x8];
2667 u8 reserved_at_60[0x10];
2670 u8 extended_destination[0x1];
2671 u8 reserved_at_81[0x1];
2672 u8 flow_source[0x2];
2673 u8 reserved_at_84[0x4];
2674 u8 destination_list_size[0x18];
2676 u8 reserved_at_a0[0x8];
2677 u8 flow_counter_list_size[0x18];
2679 u8 packet_reformat_id[0x20];
2681 u8 modify_header_id[0x20];
2683 struct mlx5_ifc_vlan_bits push_vlan_2;
2685 u8 reserved_at_120[0xe0];
2687 struct mlx5_ifc_fte_match_param_bits match_value;
2689 u8 reserved_at_1200[0x600];
2691 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2695 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2696 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2699 struct mlx5_ifc_xrc_srqc_bits {
2701 u8 log_xrc_srq_size[0x4];
2702 u8 reserved_at_8[0x18];
2704 u8 wq_signature[0x1];
2706 u8 reserved_at_22[0x1];
2708 u8 basic_cyclic_rcv_wqe[0x1];
2709 u8 log_rq_stride[0x3];
2712 u8 page_offset[0x6];
2713 u8 reserved_at_46[0x1];
2714 u8 dbr_umem_valid[0x1];
2717 u8 reserved_at_60[0x20];
2719 u8 user_index_equal_xrc_srqn[0x1];
2720 u8 reserved_at_81[0x1];
2721 u8 log_page_size[0x6];
2722 u8 user_index[0x18];
2724 u8 reserved_at_a0[0x20];
2726 u8 reserved_at_c0[0x8];
2732 u8 reserved_at_100[0x40];
2734 u8 db_record_addr_h[0x20];
2736 u8 db_record_addr_l[0x1e];
2737 u8 reserved_at_17e[0x2];
2739 u8 reserved_at_180[0x80];
2742 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2743 u8 counter_error_queues[0x20];
2745 u8 total_error_queues[0x20];
2747 u8 send_queue_priority_update_flow[0x20];
2749 u8 reserved_at_60[0x20];
2751 u8 nic_receive_steering_discard[0x40];
2753 u8 receive_discard_vport_down[0x40];
2755 u8 transmit_discard_vport_down[0x40];
2757 u8 reserved_at_140[0xec0];
2760 struct mlx5_ifc_traffic_counter_bits {
2766 struct mlx5_ifc_tisc_bits {
2767 u8 strict_lag_tx_port_affinity[0x1];
2769 u8 reserved_at_1[0x2];
2770 u8 lag_tx_port_affinity[0x04];
2772 u8 reserved_at_8[0x4];
2774 u8 reserved_at_10[0x10];
2776 u8 reserved_at_20[0x100];
2778 u8 reserved_at_120[0x8];
2779 u8 transport_domain[0x18];
2781 u8 reserved_at_140[0x8];
2782 u8 underlay_qpn[0x18];
2784 u8 reserved_at_160[0x8];
2787 u8 reserved_at_180[0x380];
2791 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2792 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2796 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2797 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2801 MLX5_RX_HASH_FN_NONE = 0x0,
2802 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2803 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
2807 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
2808 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
2811 struct mlx5_ifc_tirc_bits {
2812 u8 reserved_at_0[0x20];
2815 u8 reserved_at_24[0x1c];
2817 u8 reserved_at_40[0x40];
2819 u8 reserved_at_80[0x4];
2820 u8 lro_timeout_period_usecs[0x10];
2821 u8 lro_enable_mask[0x4];
2822 u8 lro_max_ip_payload_size[0x8];
2824 u8 reserved_at_a0[0x40];
2826 u8 reserved_at_e0[0x8];
2827 u8 inline_rqn[0x18];
2829 u8 rx_hash_symmetric[0x1];
2830 u8 reserved_at_101[0x1];
2831 u8 tunneled_offload_en[0x1];
2832 u8 reserved_at_103[0x5];
2833 u8 indirect_table[0x18];
2836 u8 reserved_at_124[0x2];
2837 u8 self_lb_block[0x2];
2838 u8 transport_domain[0x18];
2840 u8 rx_hash_toeplitz_key[10][0x20];
2842 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2844 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2846 u8 reserved_at_2c0[0x4c0];
2850 MLX5_SRQC_STATE_GOOD = 0x0,
2851 MLX5_SRQC_STATE_ERROR = 0x1,
2854 struct mlx5_ifc_srqc_bits {
2856 u8 log_srq_size[0x4];
2857 u8 reserved_at_8[0x18];
2859 u8 wq_signature[0x1];
2861 u8 reserved_at_22[0x1];
2863 u8 reserved_at_24[0x1];
2864 u8 log_rq_stride[0x3];
2867 u8 page_offset[0x6];
2868 u8 reserved_at_46[0x2];
2871 u8 reserved_at_60[0x20];
2873 u8 reserved_at_80[0x2];
2874 u8 log_page_size[0x6];
2875 u8 reserved_at_88[0x18];
2877 u8 reserved_at_a0[0x20];
2879 u8 reserved_at_c0[0x8];
2885 u8 reserved_at_100[0x40];
2889 u8 reserved_at_180[0x80];
2893 MLX5_SQC_STATE_RST = 0x0,
2894 MLX5_SQC_STATE_RDY = 0x1,
2895 MLX5_SQC_STATE_ERR = 0x3,
2898 struct mlx5_ifc_sqc_bits {
2902 u8 flush_in_error_en[0x1];
2903 u8 allow_multi_pkt_send_wqe[0x1];
2904 u8 min_wqe_inline_mode[0x3];
2909 u8 reserved_at_f[0x11];
2911 u8 reserved_at_20[0x8];
2912 u8 user_index[0x18];
2914 u8 reserved_at_40[0x8];
2917 u8 reserved_at_60[0x8];
2918 u8 hairpin_peer_rq[0x18];
2920 u8 reserved_at_80[0x10];
2921 u8 hairpin_peer_vhca[0x10];
2923 u8 reserved_at_a0[0x50];
2925 u8 packet_pacing_rate_limit_index[0x10];
2926 u8 tis_lst_sz[0x10];
2927 u8 reserved_at_110[0x10];
2929 u8 reserved_at_120[0x40];
2931 u8 reserved_at_160[0x8];
2934 struct mlx5_ifc_wq_bits wq;
2938 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2939 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2940 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2941 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2944 struct mlx5_ifc_scheduling_context_bits {
2945 u8 element_type[0x8];
2946 u8 reserved_at_8[0x18];
2948 u8 element_attributes[0x20];
2950 u8 parent_element_id[0x20];
2952 u8 reserved_at_60[0x40];
2956 u8 max_average_bw[0x20];
2958 u8 reserved_at_e0[0x120];
2961 struct mlx5_ifc_rqtc_bits {
2962 u8 reserved_at_0[0xa0];
2964 u8 reserved_at_a0[0x10];
2965 u8 rqt_max_size[0x10];
2967 u8 reserved_at_c0[0x10];
2968 u8 rqt_actual_size[0x10];
2970 u8 reserved_at_e0[0x6a0];
2972 struct mlx5_ifc_rq_num_bits rq_num[0];
2976 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2977 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2981 MLX5_RQC_STATE_RST = 0x0,
2982 MLX5_RQC_STATE_RDY = 0x1,
2983 MLX5_RQC_STATE_ERR = 0x3,
2986 struct mlx5_ifc_rqc_bits {
2988 u8 delay_drop_en[0x1];
2989 u8 scatter_fcs[0x1];
2991 u8 mem_rq_type[0x4];
2993 u8 reserved_at_c[0x1];
2994 u8 flush_in_error_en[0x1];
2996 u8 reserved_at_f[0x11];
2998 u8 reserved_at_20[0x8];
2999 u8 user_index[0x18];
3001 u8 reserved_at_40[0x8];
3004 u8 counter_set_id[0x8];
3005 u8 reserved_at_68[0x18];
3007 u8 reserved_at_80[0x8];
3010 u8 reserved_at_a0[0x8];
3011 u8 hairpin_peer_sq[0x18];
3013 u8 reserved_at_c0[0x10];
3014 u8 hairpin_peer_vhca[0x10];
3016 u8 reserved_at_e0[0xa0];
3018 struct mlx5_ifc_wq_bits wq;
3022 MLX5_RMPC_STATE_RDY = 0x1,
3023 MLX5_RMPC_STATE_ERR = 0x3,
3026 struct mlx5_ifc_rmpc_bits {
3027 u8 reserved_at_0[0x8];
3029 u8 reserved_at_c[0x14];
3031 u8 basic_cyclic_rcv_wqe[0x1];
3032 u8 reserved_at_21[0x1f];
3034 u8 reserved_at_40[0x140];
3036 struct mlx5_ifc_wq_bits wq;
3039 struct mlx5_ifc_nic_vport_context_bits {
3040 u8 reserved_at_0[0x5];
3041 u8 min_wqe_inline_mode[0x3];
3042 u8 reserved_at_8[0x15];
3043 u8 disable_mc_local_lb[0x1];
3044 u8 disable_uc_local_lb[0x1];
3047 u8 arm_change_event[0x1];
3048 u8 reserved_at_21[0x1a];
3049 u8 event_on_mtu[0x1];
3050 u8 event_on_promisc_change[0x1];
3051 u8 event_on_vlan_change[0x1];
3052 u8 event_on_mc_address_change[0x1];
3053 u8 event_on_uc_address_change[0x1];
3055 u8 reserved_at_40[0xc];
3057 u8 affiliation_criteria[0x4];
3058 u8 affiliated_vhca_id[0x10];
3060 u8 reserved_at_60[0xd0];
3064 u8 system_image_guid[0x40];
3068 u8 reserved_at_200[0x140];
3069 u8 qkey_violation_counter[0x10];
3070 u8 reserved_at_350[0x430];
3074 u8 promisc_all[0x1];
3075 u8 reserved_at_783[0x2];
3076 u8 allowed_list_type[0x3];
3077 u8 reserved_at_788[0xc];
3078 u8 allowed_list_size[0xc];
3080 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3082 u8 reserved_at_7e0[0x20];
3084 u8 current_uc_mac_address[0][0x40];
3088 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3089 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3090 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3091 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3092 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3093 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3096 struct mlx5_ifc_mkc_bits {
3097 u8 reserved_at_0[0x1];
3099 u8 reserved_at_2[0x1];
3100 u8 access_mode_4_2[0x3];
3101 u8 reserved_at_6[0x7];
3102 u8 relaxed_ordering_write[0x1];
3103 u8 reserved_at_e[0x1];
3104 u8 small_fence_on_rdma_read_response[0x1];
3111 u8 access_mode_1_0[0x2];
3112 u8 reserved_at_18[0x8];
3117 u8 reserved_at_40[0x20];
3122 u8 reserved_at_63[0x2];
3123 u8 expected_sigerr_count[0x1];
3124 u8 reserved_at_66[0x1];
3128 u8 start_addr[0x40];
3132 u8 bsf_octword_size[0x20];
3134 u8 reserved_at_120[0x80];
3136 u8 translations_octword_size[0x20];
3138 u8 reserved_at_1c0[0x1b];
3139 u8 log_page_size[0x5];
3141 u8 reserved_at_1e0[0x20];
3144 struct mlx5_ifc_pkey_bits {
3145 u8 reserved_at_0[0x10];
3149 struct mlx5_ifc_array128_auto_bits {
3150 u8 array128_auto[16][0x8];
3153 struct mlx5_ifc_hca_vport_context_bits {
3154 u8 field_select[0x20];
3156 u8 reserved_at_20[0xe0];
3158 u8 sm_virt_aware[0x1];
3161 u8 grh_required[0x1];
3162 u8 reserved_at_104[0xc];
3163 u8 port_physical_state[0x4];
3164 u8 vport_state_policy[0x4];
3166 u8 vport_state[0x4];
3168 u8 reserved_at_120[0x20];
3170 u8 system_image_guid[0x40];
3178 u8 cap_mask1_field_select[0x20];
3182 u8 cap_mask2_field_select[0x20];
3184 u8 reserved_at_280[0x80];
3187 u8 reserved_at_310[0x4];
3188 u8 init_type_reply[0x4];
3190 u8 subnet_timeout[0x5];
3194 u8 reserved_at_334[0xc];
3196 u8 qkey_violation_counter[0x10];
3197 u8 pkey_violation_counter[0x10];
3199 u8 reserved_at_360[0xca0];
3202 struct mlx5_ifc_esw_vport_context_bits {
3203 u8 fdb_to_vport_reg_c[0x1];
3204 u8 reserved_at_1[0x2];
3205 u8 vport_svlan_strip[0x1];
3206 u8 vport_cvlan_strip[0x1];
3207 u8 vport_svlan_insert[0x1];
3208 u8 vport_cvlan_insert[0x2];
3209 u8 fdb_to_vport_reg_c_id[0x8];
3210 u8 reserved_at_10[0x10];
3212 u8 reserved_at_20[0x20];
3221 u8 reserved_at_60[0x7a0];
3225 MLX5_EQC_STATUS_OK = 0x0,
3226 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3230 MLX5_EQC_ST_ARMED = 0x9,
3231 MLX5_EQC_ST_FIRED = 0xa,
3234 struct mlx5_ifc_eqc_bits {
3236 u8 reserved_at_4[0x9];
3239 u8 reserved_at_f[0x5];
3241 u8 reserved_at_18[0x8];
3243 u8 reserved_at_20[0x20];
3245 u8 reserved_at_40[0x14];
3246 u8 page_offset[0x6];
3247 u8 reserved_at_5a[0x6];
3249 u8 reserved_at_60[0x3];
3250 u8 log_eq_size[0x5];
3253 u8 reserved_at_80[0x20];
3255 u8 reserved_at_a0[0x18];
3258 u8 reserved_at_c0[0x3];
3259 u8 log_page_size[0x5];
3260 u8 reserved_at_c8[0x18];
3262 u8 reserved_at_e0[0x60];
3264 u8 reserved_at_140[0x8];
3265 u8 consumer_counter[0x18];
3267 u8 reserved_at_160[0x8];
3268 u8 producer_counter[0x18];
3270 u8 reserved_at_180[0x80];
3274 MLX5_DCTC_STATE_ACTIVE = 0x0,
3275 MLX5_DCTC_STATE_DRAINING = 0x1,
3276 MLX5_DCTC_STATE_DRAINED = 0x2,
3280 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3281 MLX5_DCTC_CS_RES_NA = 0x1,
3282 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3286 MLX5_DCTC_MTU_256_BYTES = 0x1,
3287 MLX5_DCTC_MTU_512_BYTES = 0x2,
3288 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3289 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3290 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3293 struct mlx5_ifc_dctc_bits {
3294 u8 reserved_at_0[0x4];
3296 u8 reserved_at_8[0x18];
3298 u8 reserved_at_20[0x8];
3299 u8 user_index[0x18];
3301 u8 reserved_at_40[0x8];
3304 u8 counter_set_id[0x8];
3305 u8 atomic_mode[0x4];
3309 u8 atomic_like_write_en[0x1];
3310 u8 latency_sensitive[0x1];
3313 u8 reserved_at_73[0xd];
3315 u8 reserved_at_80[0x8];
3317 u8 reserved_at_90[0x3];
3318 u8 min_rnr_nak[0x5];
3319 u8 reserved_at_98[0x8];
3321 u8 reserved_at_a0[0x8];
3324 u8 reserved_at_c0[0x8];
3328 u8 reserved_at_e8[0x4];
3329 u8 flow_label[0x14];
3331 u8 dc_access_key[0x40];
3333 u8 reserved_at_140[0x5];
3336 u8 pkey_index[0x10];
3338 u8 reserved_at_160[0x8];
3339 u8 my_addr_index[0x8];
3340 u8 reserved_at_170[0x8];
3343 u8 dc_access_key_violation_count[0x20];
3345 u8 reserved_at_1a0[0x14];
3351 u8 reserved_at_1c0[0x40];
3355 MLX5_CQC_STATUS_OK = 0x0,
3356 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3357 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3361 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3362 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3366 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3367 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3368 MLX5_CQC_ST_FIRED = 0xa,
3372 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3373 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3374 MLX5_CQ_PERIOD_NUM_MODES
3377 struct mlx5_ifc_cqc_bits {
3379 u8 reserved_at_4[0x2];
3380 u8 dbr_umem_valid[0x1];
3381 u8 reserved_at_7[0x1];
3384 u8 reserved_at_c[0x1];
3385 u8 scqe_break_moderation_en[0x1];
3387 u8 cq_period_mode[0x2];
3388 u8 cqe_comp_en[0x1];
3389 u8 mini_cqe_res_format[0x2];
3391 u8 reserved_at_18[0x8];
3393 u8 reserved_at_20[0x20];
3395 u8 reserved_at_40[0x14];
3396 u8 page_offset[0x6];
3397 u8 reserved_at_5a[0x6];
3399 u8 reserved_at_60[0x3];
3400 u8 log_cq_size[0x5];
3403 u8 reserved_at_80[0x4];
3405 u8 cq_max_count[0x10];
3407 u8 reserved_at_a0[0x18];
3410 u8 reserved_at_c0[0x3];
3411 u8 log_page_size[0x5];
3412 u8 reserved_at_c8[0x18];
3414 u8 reserved_at_e0[0x20];
3416 u8 reserved_at_100[0x8];
3417 u8 last_notified_index[0x18];
3419 u8 reserved_at_120[0x8];
3420 u8 last_solicit_index[0x18];
3422 u8 reserved_at_140[0x8];
3423 u8 consumer_counter[0x18];
3425 u8 reserved_at_160[0x8];
3426 u8 producer_counter[0x18];
3428 u8 reserved_at_180[0x40];
3433 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3434 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3435 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3436 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3437 u8 reserved_at_0[0x800];
3440 struct mlx5_ifc_query_adapter_param_block_bits {
3441 u8 reserved_at_0[0xc0];
3443 u8 reserved_at_c0[0x8];
3444 u8 ieee_vendor_id[0x18];
3446 u8 reserved_at_e0[0x10];
3447 u8 vsd_vendor_id[0x10];
3451 u8 vsd_contd_psid[16][0x8];
3455 MLX5_XRQC_STATE_GOOD = 0x0,
3456 MLX5_XRQC_STATE_ERROR = 0x1,
3460 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3461 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3465 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3468 struct mlx5_ifc_tag_matching_topology_context_bits {
3469 u8 log_matching_list_sz[0x4];
3470 u8 reserved_at_4[0xc];
3471 u8 append_next_index[0x10];
3473 u8 sw_phase_cnt[0x10];
3474 u8 hw_phase_cnt[0x10];
3476 u8 reserved_at_40[0x40];
3479 struct mlx5_ifc_xrqc_bits {
3482 u8 reserved_at_5[0xf];
3484 u8 reserved_at_18[0x4];
3487 u8 reserved_at_20[0x8];
3488 u8 user_index[0x18];
3490 u8 reserved_at_40[0x8];
3493 u8 reserved_at_60[0xa0];
3495 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3497 u8 reserved_at_180[0x280];
3499 struct mlx5_ifc_wq_bits wq;
3502 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3503 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3504 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3505 u8 reserved_at_0[0x20];
3508 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3509 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3510 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3511 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3512 u8 reserved_at_0[0x20];
3515 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3516 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3517 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3518 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3519 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3520 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3521 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3522 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3523 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3524 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3525 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3526 u8 reserved_at_0[0x7c0];
3529 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3530 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3531 u8 reserved_at_0[0x7c0];
3534 union mlx5_ifc_event_auto_bits {
3535 struct mlx5_ifc_comp_event_bits comp_event;
3536 struct mlx5_ifc_dct_events_bits dct_events;
3537 struct mlx5_ifc_qp_events_bits qp_events;
3538 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3539 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3540 struct mlx5_ifc_cq_error_bits cq_error;
3541 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3542 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3543 struct mlx5_ifc_gpio_event_bits gpio_event;
3544 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3545 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3546 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3547 u8 reserved_at_0[0xe0];
3550 struct mlx5_ifc_health_buffer_bits {
3551 u8 reserved_at_0[0x100];
3553 u8 assert_existptr[0x20];
3555 u8 assert_callra[0x20];
3557 u8 reserved_at_140[0x40];
3559 u8 fw_version[0x20];
3563 u8 reserved_at_1c0[0x20];
3565 u8 irisc_index[0x8];
3570 struct mlx5_ifc_register_loopback_control_bits {
3572 u8 reserved_at_1[0x7];
3574 u8 reserved_at_10[0x10];
3576 u8 reserved_at_20[0x60];
3579 struct mlx5_ifc_vport_tc_element_bits {
3580 u8 traffic_class[0x4];
3581 u8 reserved_at_4[0xc];
3582 u8 vport_number[0x10];
3585 struct mlx5_ifc_vport_element_bits {
3586 u8 reserved_at_0[0x10];
3587 u8 vport_number[0x10];
3591 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3592 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3593 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3596 struct mlx5_ifc_tsar_element_bits {
3597 u8 reserved_at_0[0x8];
3599 u8 reserved_at_10[0x10];
3603 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3604 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3607 struct mlx5_ifc_teardown_hca_out_bits {
3609 u8 reserved_at_8[0x18];
3613 u8 reserved_at_40[0x3f];
3619 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3620 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3621 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3624 struct mlx5_ifc_teardown_hca_in_bits {
3626 u8 reserved_at_10[0x10];
3628 u8 reserved_at_20[0x10];
3631 u8 reserved_at_40[0x10];
3634 u8 reserved_at_60[0x20];
3637 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3639 u8 reserved_at_8[0x18];
3643 u8 reserved_at_40[0x40];
3646 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3650 u8 reserved_at_20[0x10];
3653 u8 reserved_at_40[0x8];
3656 u8 reserved_at_60[0x20];
3658 u8 opt_param_mask[0x20];
3660 u8 reserved_at_a0[0x20];
3662 struct mlx5_ifc_qpc_bits qpc;
3664 u8 reserved_at_800[0x80];
3667 struct mlx5_ifc_sqd2rts_qp_out_bits {
3669 u8 reserved_at_8[0x18];
3673 u8 reserved_at_40[0x40];
3676 struct mlx5_ifc_sqd2rts_qp_in_bits {
3680 u8 reserved_at_20[0x10];
3683 u8 reserved_at_40[0x8];
3686 u8 reserved_at_60[0x20];
3688 u8 opt_param_mask[0x20];
3690 u8 reserved_at_a0[0x20];
3692 struct mlx5_ifc_qpc_bits qpc;
3694 u8 reserved_at_800[0x80];
3697 struct mlx5_ifc_set_roce_address_out_bits {
3699 u8 reserved_at_8[0x18];
3703 u8 reserved_at_40[0x40];
3706 struct mlx5_ifc_set_roce_address_in_bits {
3708 u8 reserved_at_10[0x10];
3710 u8 reserved_at_20[0x10];
3713 u8 roce_address_index[0x10];
3714 u8 reserved_at_50[0xc];
3715 u8 vhca_port_num[0x4];
3717 u8 reserved_at_60[0x20];
3719 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3722 struct mlx5_ifc_set_mad_demux_out_bits {
3724 u8 reserved_at_8[0x18];
3728 u8 reserved_at_40[0x40];
3732 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3733 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3736 struct mlx5_ifc_set_mad_demux_in_bits {
3738 u8 reserved_at_10[0x10];
3740 u8 reserved_at_20[0x10];
3743 u8 reserved_at_40[0x20];
3745 u8 reserved_at_60[0x6];
3747 u8 reserved_at_68[0x18];
3750 struct mlx5_ifc_set_l2_table_entry_out_bits {
3752 u8 reserved_at_8[0x18];
3756 u8 reserved_at_40[0x40];
3759 struct mlx5_ifc_set_l2_table_entry_in_bits {
3761 u8 reserved_at_10[0x10];
3763 u8 reserved_at_20[0x10];
3766 u8 reserved_at_40[0x60];
3768 u8 reserved_at_a0[0x8];
3769 u8 table_index[0x18];
3771 u8 reserved_at_c0[0x20];
3773 u8 reserved_at_e0[0x13];
3777 struct mlx5_ifc_mac_address_layout_bits mac_address;
3779 u8 reserved_at_140[0xc0];
3782 struct mlx5_ifc_set_issi_out_bits {
3784 u8 reserved_at_8[0x18];
3788 u8 reserved_at_40[0x40];
3791 struct mlx5_ifc_set_issi_in_bits {
3793 u8 reserved_at_10[0x10];
3795 u8 reserved_at_20[0x10];
3798 u8 reserved_at_40[0x10];
3799 u8 current_issi[0x10];
3801 u8 reserved_at_60[0x20];
3804 struct mlx5_ifc_set_hca_cap_out_bits {
3806 u8 reserved_at_8[0x18];
3810 u8 reserved_at_40[0x40];
3813 struct mlx5_ifc_set_hca_cap_in_bits {
3815 u8 reserved_at_10[0x10];
3817 u8 reserved_at_20[0x10];
3820 u8 reserved_at_40[0x40];
3822 union mlx5_ifc_hca_cap_union_bits capability;
3826 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3827 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3828 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3829 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3832 struct mlx5_ifc_set_fte_out_bits {
3834 u8 reserved_at_8[0x18];
3838 u8 reserved_at_40[0x40];
3841 struct mlx5_ifc_set_fte_in_bits {
3843 u8 reserved_at_10[0x10];
3845 u8 reserved_at_20[0x10];
3848 u8 other_vport[0x1];
3849 u8 reserved_at_41[0xf];
3850 u8 vport_number[0x10];
3852 u8 reserved_at_60[0x20];
3855 u8 reserved_at_88[0x18];
3857 u8 reserved_at_a0[0x8];
3860 u8 reserved_at_c0[0x18];
3861 u8 modify_enable_mask[0x8];
3863 u8 reserved_at_e0[0x20];
3865 u8 flow_index[0x20];
3867 u8 reserved_at_120[0xe0];
3869 struct mlx5_ifc_flow_context_bits flow_context;
3872 struct mlx5_ifc_rts2rts_qp_out_bits {
3874 u8 reserved_at_8[0x18];
3878 u8 reserved_at_40[0x40];
3881 struct mlx5_ifc_rts2rts_qp_in_bits {
3885 u8 reserved_at_20[0x10];
3888 u8 reserved_at_40[0x8];
3891 u8 reserved_at_60[0x20];
3893 u8 opt_param_mask[0x20];
3895 u8 reserved_at_a0[0x20];
3897 struct mlx5_ifc_qpc_bits qpc;
3899 u8 reserved_at_800[0x80];
3902 struct mlx5_ifc_rtr2rts_qp_out_bits {
3904 u8 reserved_at_8[0x18];
3908 u8 reserved_at_40[0x40];
3911 struct mlx5_ifc_rtr2rts_qp_in_bits {
3915 u8 reserved_at_20[0x10];
3918 u8 reserved_at_40[0x8];
3921 u8 reserved_at_60[0x20];
3923 u8 opt_param_mask[0x20];
3925 u8 reserved_at_a0[0x20];
3927 struct mlx5_ifc_qpc_bits qpc;
3929 u8 reserved_at_800[0x80];
3932 struct mlx5_ifc_rst2init_qp_out_bits {
3934 u8 reserved_at_8[0x18];
3938 u8 reserved_at_40[0x40];
3941 struct mlx5_ifc_rst2init_qp_in_bits {
3945 u8 reserved_at_20[0x10];
3948 u8 reserved_at_40[0x8];
3951 u8 reserved_at_60[0x20];
3953 u8 opt_param_mask[0x20];
3955 u8 reserved_at_a0[0x20];
3957 struct mlx5_ifc_qpc_bits qpc;
3959 u8 reserved_at_800[0x80];
3962 struct mlx5_ifc_query_xrq_out_bits {
3964 u8 reserved_at_8[0x18];
3968 u8 reserved_at_40[0x40];
3970 struct mlx5_ifc_xrqc_bits xrq_context;
3973 struct mlx5_ifc_query_xrq_in_bits {
3975 u8 reserved_at_10[0x10];
3977 u8 reserved_at_20[0x10];
3980 u8 reserved_at_40[0x8];
3983 u8 reserved_at_60[0x20];
3986 struct mlx5_ifc_query_xrc_srq_out_bits {
3988 u8 reserved_at_8[0x18];
3992 u8 reserved_at_40[0x40];
3994 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3996 u8 reserved_at_280[0x600];
4001 struct mlx5_ifc_query_xrc_srq_in_bits {
4003 u8 reserved_at_10[0x10];
4005 u8 reserved_at_20[0x10];
4008 u8 reserved_at_40[0x8];
4011 u8 reserved_at_60[0x20];
4015 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4016 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4019 struct mlx5_ifc_query_vport_state_out_bits {
4021 u8 reserved_at_8[0x18];
4025 u8 reserved_at_40[0x20];
4027 u8 reserved_at_60[0x18];
4028 u8 admin_state[0x4];
4033 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4034 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4037 struct mlx5_ifc_arm_monitor_counter_in_bits {
4041 u8 reserved_at_20[0x10];
4044 u8 reserved_at_40[0x20];
4046 u8 reserved_at_60[0x20];
4049 struct mlx5_ifc_arm_monitor_counter_out_bits {
4051 u8 reserved_at_8[0x18];
4055 u8 reserved_at_40[0x40];
4059 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4060 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4063 enum mlx5_monitor_counter_ppcnt {
4064 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4065 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4066 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4067 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4068 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4069 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4073 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4076 struct mlx5_ifc_monitor_counter_output_bits {
4077 u8 reserved_at_0[0x4];
4079 u8 reserved_at_8[0x8];
4082 u8 counter_group_id[0x20];
4085 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4086 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4087 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4088 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4090 struct mlx5_ifc_set_monitor_counter_in_bits {
4094 u8 reserved_at_20[0x10];
4097 u8 reserved_at_40[0x10];
4098 u8 num_of_counters[0x10];
4100 u8 reserved_at_60[0x20];
4102 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4105 struct mlx5_ifc_set_monitor_counter_out_bits {
4107 u8 reserved_at_8[0x18];
4111 u8 reserved_at_40[0x40];
4114 struct mlx5_ifc_query_vport_state_in_bits {
4116 u8 reserved_at_10[0x10];
4118 u8 reserved_at_20[0x10];
4121 u8 other_vport[0x1];
4122 u8 reserved_at_41[0xf];
4123 u8 vport_number[0x10];
4125 u8 reserved_at_60[0x20];
4128 struct mlx5_ifc_query_vnic_env_out_bits {
4130 u8 reserved_at_8[0x18];
4134 u8 reserved_at_40[0x40];
4136 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4140 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4143 struct mlx5_ifc_query_vnic_env_in_bits {
4145 u8 reserved_at_10[0x10];
4147 u8 reserved_at_20[0x10];
4150 u8 other_vport[0x1];
4151 u8 reserved_at_41[0xf];
4152 u8 vport_number[0x10];
4154 u8 reserved_at_60[0x20];
4157 struct mlx5_ifc_query_vport_counter_out_bits {
4159 u8 reserved_at_8[0x18];
4163 u8 reserved_at_40[0x40];
4165 struct mlx5_ifc_traffic_counter_bits received_errors;
4167 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4169 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4171 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4173 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4175 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4177 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4179 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4181 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4183 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4185 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4187 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4189 u8 reserved_at_680[0xa00];
4193 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4196 struct mlx5_ifc_query_vport_counter_in_bits {
4198 u8 reserved_at_10[0x10];
4200 u8 reserved_at_20[0x10];
4203 u8 other_vport[0x1];
4204 u8 reserved_at_41[0xb];
4206 u8 vport_number[0x10];
4208 u8 reserved_at_60[0x60];
4211 u8 reserved_at_c1[0x1f];
4213 u8 reserved_at_e0[0x20];
4216 struct mlx5_ifc_query_tis_out_bits {
4218 u8 reserved_at_8[0x18];
4222 u8 reserved_at_40[0x40];
4224 struct mlx5_ifc_tisc_bits tis_context;
4227 struct mlx5_ifc_query_tis_in_bits {
4229 u8 reserved_at_10[0x10];
4231 u8 reserved_at_20[0x10];
4234 u8 reserved_at_40[0x8];
4237 u8 reserved_at_60[0x20];
4240 struct mlx5_ifc_query_tir_out_bits {
4242 u8 reserved_at_8[0x18];
4246 u8 reserved_at_40[0xc0];
4248 struct mlx5_ifc_tirc_bits tir_context;
4251 struct mlx5_ifc_query_tir_in_bits {
4253 u8 reserved_at_10[0x10];
4255 u8 reserved_at_20[0x10];
4258 u8 reserved_at_40[0x8];
4261 u8 reserved_at_60[0x20];
4264 struct mlx5_ifc_query_srq_out_bits {
4266 u8 reserved_at_8[0x18];
4270 u8 reserved_at_40[0x40];
4272 struct mlx5_ifc_srqc_bits srq_context_entry;
4274 u8 reserved_at_280[0x600];
4279 struct mlx5_ifc_query_srq_in_bits {
4281 u8 reserved_at_10[0x10];
4283 u8 reserved_at_20[0x10];
4286 u8 reserved_at_40[0x8];
4289 u8 reserved_at_60[0x20];
4292 struct mlx5_ifc_query_sq_out_bits {
4294 u8 reserved_at_8[0x18];
4298 u8 reserved_at_40[0xc0];
4300 struct mlx5_ifc_sqc_bits sq_context;
4303 struct mlx5_ifc_query_sq_in_bits {
4305 u8 reserved_at_10[0x10];
4307 u8 reserved_at_20[0x10];
4310 u8 reserved_at_40[0x8];
4313 u8 reserved_at_60[0x20];
4316 struct mlx5_ifc_query_special_contexts_out_bits {
4318 u8 reserved_at_8[0x18];
4322 u8 dump_fill_mkey[0x20];
4328 u8 reserved_at_a0[0x60];
4331 struct mlx5_ifc_query_special_contexts_in_bits {
4333 u8 reserved_at_10[0x10];
4335 u8 reserved_at_20[0x10];
4338 u8 reserved_at_40[0x40];
4341 struct mlx5_ifc_query_scheduling_element_out_bits {
4343 u8 reserved_at_10[0x10];
4345 u8 reserved_at_20[0x10];
4348 u8 reserved_at_40[0xc0];
4350 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4352 u8 reserved_at_300[0x100];
4356 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4359 struct mlx5_ifc_query_scheduling_element_in_bits {
4361 u8 reserved_at_10[0x10];
4363 u8 reserved_at_20[0x10];
4366 u8 scheduling_hierarchy[0x8];
4367 u8 reserved_at_48[0x18];
4369 u8 scheduling_element_id[0x20];
4371 u8 reserved_at_80[0x180];
4374 struct mlx5_ifc_query_rqt_out_bits {
4376 u8 reserved_at_8[0x18];
4380 u8 reserved_at_40[0xc0];
4382 struct mlx5_ifc_rqtc_bits rqt_context;
4385 struct mlx5_ifc_query_rqt_in_bits {
4387 u8 reserved_at_10[0x10];
4389 u8 reserved_at_20[0x10];
4392 u8 reserved_at_40[0x8];
4395 u8 reserved_at_60[0x20];
4398 struct mlx5_ifc_query_rq_out_bits {
4400 u8 reserved_at_8[0x18];
4404 u8 reserved_at_40[0xc0];
4406 struct mlx5_ifc_rqc_bits rq_context;
4409 struct mlx5_ifc_query_rq_in_bits {
4411 u8 reserved_at_10[0x10];
4413 u8 reserved_at_20[0x10];
4416 u8 reserved_at_40[0x8];
4419 u8 reserved_at_60[0x20];
4422 struct mlx5_ifc_query_roce_address_out_bits {
4424 u8 reserved_at_8[0x18];
4428 u8 reserved_at_40[0x40];
4430 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4433 struct mlx5_ifc_query_roce_address_in_bits {
4435 u8 reserved_at_10[0x10];
4437 u8 reserved_at_20[0x10];
4440 u8 roce_address_index[0x10];
4441 u8 reserved_at_50[0xc];
4442 u8 vhca_port_num[0x4];
4444 u8 reserved_at_60[0x20];
4447 struct mlx5_ifc_query_rmp_out_bits {
4449 u8 reserved_at_8[0x18];
4453 u8 reserved_at_40[0xc0];
4455 struct mlx5_ifc_rmpc_bits rmp_context;
4458 struct mlx5_ifc_query_rmp_in_bits {
4460 u8 reserved_at_10[0x10];
4462 u8 reserved_at_20[0x10];
4465 u8 reserved_at_40[0x8];
4468 u8 reserved_at_60[0x20];
4471 struct mlx5_ifc_query_qp_out_bits {
4473 u8 reserved_at_8[0x18];
4477 u8 reserved_at_40[0x40];
4479 u8 opt_param_mask[0x20];
4481 u8 reserved_at_a0[0x20];
4483 struct mlx5_ifc_qpc_bits qpc;
4485 u8 reserved_at_800[0x80];
4490 struct mlx5_ifc_query_qp_in_bits {
4492 u8 reserved_at_10[0x10];
4494 u8 reserved_at_20[0x10];
4497 u8 reserved_at_40[0x8];
4500 u8 reserved_at_60[0x20];
4503 struct mlx5_ifc_query_q_counter_out_bits {
4505 u8 reserved_at_8[0x18];
4509 u8 reserved_at_40[0x40];
4511 u8 rx_write_requests[0x20];
4513 u8 reserved_at_a0[0x20];
4515 u8 rx_read_requests[0x20];
4517 u8 reserved_at_e0[0x20];
4519 u8 rx_atomic_requests[0x20];
4521 u8 reserved_at_120[0x20];
4523 u8 rx_dct_connect[0x20];
4525 u8 reserved_at_160[0x20];
4527 u8 out_of_buffer[0x20];
4529 u8 reserved_at_1a0[0x20];
4531 u8 out_of_sequence[0x20];
4533 u8 reserved_at_1e0[0x20];
4535 u8 duplicate_request[0x20];
4537 u8 reserved_at_220[0x20];
4539 u8 rnr_nak_retry_err[0x20];
4541 u8 reserved_at_260[0x20];
4543 u8 packet_seq_err[0x20];
4545 u8 reserved_at_2a0[0x20];
4547 u8 implied_nak_seq_err[0x20];
4549 u8 reserved_at_2e0[0x20];
4551 u8 local_ack_timeout_err[0x20];
4553 u8 reserved_at_320[0xa0];
4555 u8 resp_local_length_error[0x20];
4557 u8 req_local_length_error[0x20];
4559 u8 resp_local_qp_error[0x20];
4561 u8 local_operation_error[0x20];
4563 u8 resp_local_protection[0x20];
4565 u8 req_local_protection[0x20];
4567 u8 resp_cqe_error[0x20];
4569 u8 req_cqe_error[0x20];
4571 u8 req_mw_binding[0x20];
4573 u8 req_bad_response[0x20];
4575 u8 req_remote_invalid_request[0x20];
4577 u8 resp_remote_invalid_request[0x20];
4579 u8 req_remote_access_errors[0x20];
4581 u8 resp_remote_access_errors[0x20];
4583 u8 req_remote_operation_errors[0x20];
4585 u8 req_transport_retries_exceeded[0x20];
4587 u8 cq_overflow[0x20];
4589 u8 resp_cqe_flush_error[0x20];
4591 u8 req_cqe_flush_error[0x20];
4593 u8 reserved_at_620[0x1e0];
4596 struct mlx5_ifc_query_q_counter_in_bits {
4598 u8 reserved_at_10[0x10];
4600 u8 reserved_at_20[0x10];
4603 u8 reserved_at_40[0x80];
4606 u8 reserved_at_c1[0x1f];
4608 u8 reserved_at_e0[0x18];
4609 u8 counter_set_id[0x8];
4612 struct mlx5_ifc_query_pages_out_bits {
4614 u8 reserved_at_8[0x18];
4618 u8 embedded_cpu_function[0x1];
4619 u8 reserved_at_41[0xf];
4620 u8 function_id[0x10];
4626 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4627 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4628 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4631 struct mlx5_ifc_query_pages_in_bits {
4633 u8 reserved_at_10[0x10];
4635 u8 reserved_at_20[0x10];
4638 u8 embedded_cpu_function[0x1];
4639 u8 reserved_at_41[0xf];
4640 u8 function_id[0x10];
4642 u8 reserved_at_60[0x20];
4645 struct mlx5_ifc_query_nic_vport_context_out_bits {
4647 u8 reserved_at_8[0x18];
4651 u8 reserved_at_40[0x40];
4653 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4656 struct mlx5_ifc_query_nic_vport_context_in_bits {
4658 u8 reserved_at_10[0x10];
4660 u8 reserved_at_20[0x10];
4663 u8 other_vport[0x1];
4664 u8 reserved_at_41[0xf];
4665 u8 vport_number[0x10];
4667 u8 reserved_at_60[0x5];
4668 u8 allowed_list_type[0x3];
4669 u8 reserved_at_68[0x18];
4672 struct mlx5_ifc_query_mkey_out_bits {
4674 u8 reserved_at_8[0x18];
4678 u8 reserved_at_40[0x40];
4680 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4682 u8 reserved_at_280[0x600];
4684 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4686 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4689 struct mlx5_ifc_query_mkey_in_bits {
4691 u8 reserved_at_10[0x10];
4693 u8 reserved_at_20[0x10];
4696 u8 reserved_at_40[0x8];
4697 u8 mkey_index[0x18];
4700 u8 reserved_at_61[0x1f];
4703 struct mlx5_ifc_query_mad_demux_out_bits {
4705 u8 reserved_at_8[0x18];
4709 u8 reserved_at_40[0x40];
4711 u8 mad_dumux_parameters_block[0x20];
4714 struct mlx5_ifc_query_mad_demux_in_bits {
4716 u8 reserved_at_10[0x10];
4718 u8 reserved_at_20[0x10];
4721 u8 reserved_at_40[0x40];
4724 struct mlx5_ifc_query_l2_table_entry_out_bits {
4726 u8 reserved_at_8[0x18];
4730 u8 reserved_at_40[0xa0];
4732 u8 reserved_at_e0[0x13];
4736 struct mlx5_ifc_mac_address_layout_bits mac_address;
4738 u8 reserved_at_140[0xc0];
4741 struct mlx5_ifc_query_l2_table_entry_in_bits {
4743 u8 reserved_at_10[0x10];
4745 u8 reserved_at_20[0x10];
4748 u8 reserved_at_40[0x60];
4750 u8 reserved_at_a0[0x8];
4751 u8 table_index[0x18];
4753 u8 reserved_at_c0[0x140];
4756 struct mlx5_ifc_query_issi_out_bits {
4758 u8 reserved_at_8[0x18];
4762 u8 reserved_at_40[0x10];
4763 u8 current_issi[0x10];
4765 u8 reserved_at_60[0xa0];
4767 u8 reserved_at_100[76][0x8];
4768 u8 supported_issi_dw0[0x20];
4771 struct mlx5_ifc_query_issi_in_bits {
4773 u8 reserved_at_10[0x10];
4775 u8 reserved_at_20[0x10];
4778 u8 reserved_at_40[0x40];
4781 struct mlx5_ifc_set_driver_version_out_bits {
4783 u8 reserved_0[0x18];
4786 u8 reserved_1[0x40];
4789 struct mlx5_ifc_set_driver_version_in_bits {
4791 u8 reserved_0[0x10];
4793 u8 reserved_1[0x10];
4796 u8 reserved_2[0x40];
4797 u8 driver_version[64][0x8];
4800 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4802 u8 reserved_at_8[0x18];
4806 u8 reserved_at_40[0x40];
4808 struct mlx5_ifc_pkey_bits pkey[0];
4811 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4813 u8 reserved_at_10[0x10];
4815 u8 reserved_at_20[0x10];
4818 u8 other_vport[0x1];
4819 u8 reserved_at_41[0xb];
4821 u8 vport_number[0x10];
4823 u8 reserved_at_60[0x10];
4824 u8 pkey_index[0x10];
4828 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4829 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4830 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4833 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4835 u8 reserved_at_8[0x18];
4839 u8 reserved_at_40[0x20];
4842 u8 reserved_at_70[0x10];
4844 struct mlx5_ifc_array128_auto_bits gid[0];
4847 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4849 u8 reserved_at_10[0x10];
4851 u8 reserved_at_20[0x10];
4854 u8 other_vport[0x1];
4855 u8 reserved_at_41[0xb];
4857 u8 vport_number[0x10];
4859 u8 reserved_at_60[0x10];
4863 struct mlx5_ifc_query_hca_vport_context_out_bits {
4865 u8 reserved_at_8[0x18];
4869 u8 reserved_at_40[0x40];
4871 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4874 struct mlx5_ifc_query_hca_vport_context_in_bits {
4876 u8 reserved_at_10[0x10];
4878 u8 reserved_at_20[0x10];
4881 u8 other_vport[0x1];
4882 u8 reserved_at_41[0xb];
4884 u8 vport_number[0x10];
4886 u8 reserved_at_60[0x20];
4889 struct mlx5_ifc_query_hca_cap_out_bits {
4891 u8 reserved_at_8[0x18];
4895 u8 reserved_at_40[0x40];
4897 union mlx5_ifc_hca_cap_union_bits capability;
4900 struct mlx5_ifc_query_hca_cap_in_bits {
4902 u8 reserved_at_10[0x10];
4904 u8 reserved_at_20[0x10];
4907 u8 reserved_at_40[0x40];
4910 struct mlx5_ifc_query_flow_table_out_bits {
4912 u8 reserved_at_8[0x18];
4916 u8 reserved_at_40[0x80];
4918 u8 reserved_at_c0[0x8];
4920 u8 reserved_at_d0[0x8];
4923 u8 reserved_at_e0[0x120];
4926 struct mlx5_ifc_query_flow_table_in_bits {
4928 u8 reserved_at_10[0x10];
4930 u8 reserved_at_20[0x10];
4933 u8 reserved_at_40[0x40];
4936 u8 reserved_at_88[0x18];
4938 u8 reserved_at_a0[0x8];
4941 u8 reserved_at_c0[0x140];
4944 struct mlx5_ifc_query_fte_out_bits {
4946 u8 reserved_at_8[0x18];
4950 u8 reserved_at_40[0x1c0];
4952 struct mlx5_ifc_flow_context_bits flow_context;
4955 struct mlx5_ifc_query_fte_in_bits {
4957 u8 reserved_at_10[0x10];
4959 u8 reserved_at_20[0x10];
4962 u8 reserved_at_40[0x40];
4965 u8 reserved_at_88[0x18];
4967 u8 reserved_at_a0[0x8];
4970 u8 reserved_at_c0[0x40];
4972 u8 flow_index[0x20];
4974 u8 reserved_at_120[0xe0];
4978 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4979 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4980 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4981 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
4982 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
4985 struct mlx5_ifc_query_flow_group_out_bits {
4987 u8 reserved_at_8[0x18];
4991 u8 reserved_at_40[0xa0];
4993 u8 start_flow_index[0x20];
4995 u8 reserved_at_100[0x20];
4997 u8 end_flow_index[0x20];
4999 u8 reserved_at_140[0xa0];
5001 u8 reserved_at_1e0[0x18];
5002 u8 match_criteria_enable[0x8];
5004 struct mlx5_ifc_fte_match_param_bits match_criteria;
5006 u8 reserved_at_1200[0xe00];
5009 struct mlx5_ifc_query_flow_group_in_bits {
5011 u8 reserved_at_10[0x10];
5013 u8 reserved_at_20[0x10];
5016 u8 reserved_at_40[0x40];
5019 u8 reserved_at_88[0x18];
5021 u8 reserved_at_a0[0x8];
5026 u8 reserved_at_e0[0x120];
5029 struct mlx5_ifc_query_flow_counter_out_bits {
5031 u8 reserved_at_8[0x18];
5035 u8 reserved_at_40[0x40];
5037 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5040 struct mlx5_ifc_query_flow_counter_in_bits {
5042 u8 reserved_at_10[0x10];
5044 u8 reserved_at_20[0x10];
5047 u8 reserved_at_40[0x80];
5050 u8 reserved_at_c1[0xf];
5051 u8 num_of_counters[0x10];
5053 u8 flow_counter_id[0x20];
5056 struct mlx5_ifc_query_esw_vport_context_out_bits {
5058 u8 reserved_at_8[0x18];
5062 u8 reserved_at_40[0x40];
5064 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5067 struct mlx5_ifc_query_esw_vport_context_in_bits {
5069 u8 reserved_at_10[0x10];
5071 u8 reserved_at_20[0x10];
5074 u8 other_vport[0x1];
5075 u8 reserved_at_41[0xf];
5076 u8 vport_number[0x10];
5078 u8 reserved_at_60[0x20];
5081 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5083 u8 reserved_at_8[0x18];
5087 u8 reserved_at_40[0x40];
5090 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5091 u8 reserved_at_0[0x1b];
5092 u8 fdb_to_vport_reg_c_id[0x1];
5093 u8 vport_cvlan_insert[0x1];
5094 u8 vport_svlan_insert[0x1];
5095 u8 vport_cvlan_strip[0x1];
5096 u8 vport_svlan_strip[0x1];
5099 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5101 u8 reserved_at_10[0x10];
5103 u8 reserved_at_20[0x10];
5106 u8 other_vport[0x1];
5107 u8 reserved_at_41[0xf];
5108 u8 vport_number[0x10];
5110 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5112 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5115 struct mlx5_ifc_query_eq_out_bits {
5117 u8 reserved_at_8[0x18];
5121 u8 reserved_at_40[0x40];
5123 struct mlx5_ifc_eqc_bits eq_context_entry;
5125 u8 reserved_at_280[0x40];
5127 u8 event_bitmask[0x40];
5129 u8 reserved_at_300[0x580];
5134 struct mlx5_ifc_query_eq_in_bits {
5136 u8 reserved_at_10[0x10];
5138 u8 reserved_at_20[0x10];
5141 u8 reserved_at_40[0x18];
5144 u8 reserved_at_60[0x20];
5147 struct mlx5_ifc_packet_reformat_context_in_bits {
5148 u8 reserved_at_0[0x5];
5149 u8 reformat_type[0x3];
5150 u8 reserved_at_8[0xe];
5151 u8 reformat_data_size[0xa];
5153 u8 reserved_at_20[0x10];
5154 u8 reformat_data[2][0x8];
5156 u8 more_reformat_data[0][0x8];
5159 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5161 u8 reserved_at_8[0x18];
5165 u8 reserved_at_40[0xa0];
5167 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5170 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5172 u8 reserved_at_10[0x10];
5174 u8 reserved_at_20[0x10];
5177 u8 packet_reformat_id[0x20];
5179 u8 reserved_at_60[0xa0];
5182 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5184 u8 reserved_at_8[0x18];
5188 u8 packet_reformat_id[0x20];
5190 u8 reserved_at_60[0x20];
5194 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5195 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5196 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5197 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5198 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5201 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5203 u8 reserved_at_10[0x10];
5205 u8 reserved_at_20[0x10];
5208 u8 reserved_at_40[0xa0];
5210 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5213 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5215 u8 reserved_at_8[0x18];
5219 u8 reserved_at_40[0x40];
5222 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5224 u8 reserved_at_10[0x10];
5226 u8 reserved_20[0x10];
5229 u8 packet_reformat_id[0x20];
5231 u8 reserved_60[0x20];
5234 struct mlx5_ifc_set_action_in_bits {
5235 u8 action_type[0x4];
5237 u8 reserved_at_10[0x3];
5239 u8 reserved_at_18[0x3];
5245 struct mlx5_ifc_add_action_in_bits {
5246 u8 action_type[0x4];
5248 u8 reserved_at_10[0x10];
5253 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5254 struct mlx5_ifc_set_action_in_bits set_action_in;
5255 struct mlx5_ifc_add_action_in_bits add_action_in;
5256 u8 reserved_at_0[0x40];
5260 MLX5_ACTION_TYPE_SET = 0x1,
5261 MLX5_ACTION_TYPE_ADD = 0x2,
5265 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5266 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5267 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5268 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5269 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5270 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5271 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5272 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5273 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5274 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5275 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5276 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5277 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5278 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5279 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5280 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5281 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5282 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5283 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5284 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5285 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5286 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5287 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5288 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5289 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5292 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5294 u8 reserved_at_8[0x18];
5298 u8 modify_header_id[0x20];
5300 u8 reserved_at_60[0x20];
5303 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5305 u8 reserved_at_10[0x10];
5307 u8 reserved_at_20[0x10];
5310 u8 reserved_at_40[0x20];
5313 u8 reserved_at_68[0x10];
5314 u8 num_of_actions[0x8];
5316 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5319 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5321 u8 reserved_at_8[0x18];
5325 u8 reserved_at_40[0x40];
5328 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5330 u8 reserved_at_10[0x10];
5332 u8 reserved_at_20[0x10];
5335 u8 modify_header_id[0x20];
5337 u8 reserved_at_60[0x20];
5340 struct mlx5_ifc_query_dct_out_bits {
5342 u8 reserved_at_8[0x18];
5346 u8 reserved_at_40[0x40];
5348 struct mlx5_ifc_dctc_bits dct_context_entry;
5350 u8 reserved_at_280[0x180];
5353 struct mlx5_ifc_query_dct_in_bits {
5355 u8 reserved_at_10[0x10];
5357 u8 reserved_at_20[0x10];
5360 u8 reserved_at_40[0x8];
5363 u8 reserved_at_60[0x20];
5366 struct mlx5_ifc_query_cq_out_bits {
5368 u8 reserved_at_8[0x18];
5372 u8 reserved_at_40[0x40];
5374 struct mlx5_ifc_cqc_bits cq_context;
5376 u8 reserved_at_280[0x600];
5381 struct mlx5_ifc_query_cq_in_bits {
5383 u8 reserved_at_10[0x10];
5385 u8 reserved_at_20[0x10];
5388 u8 reserved_at_40[0x8];
5391 u8 reserved_at_60[0x20];
5394 struct mlx5_ifc_query_cong_status_out_bits {
5396 u8 reserved_at_8[0x18];
5400 u8 reserved_at_40[0x20];
5404 u8 reserved_at_62[0x1e];
5407 struct mlx5_ifc_query_cong_status_in_bits {
5409 u8 reserved_at_10[0x10];
5411 u8 reserved_at_20[0x10];
5414 u8 reserved_at_40[0x18];
5416 u8 cong_protocol[0x4];
5418 u8 reserved_at_60[0x20];
5421 struct mlx5_ifc_query_cong_statistics_out_bits {
5423 u8 reserved_at_8[0x18];
5427 u8 reserved_at_40[0x40];
5429 u8 rp_cur_flows[0x20];
5433 u8 rp_cnp_ignored_high[0x20];
5435 u8 rp_cnp_ignored_low[0x20];
5437 u8 rp_cnp_handled_high[0x20];
5439 u8 rp_cnp_handled_low[0x20];
5441 u8 reserved_at_140[0x100];
5443 u8 time_stamp_high[0x20];
5445 u8 time_stamp_low[0x20];
5447 u8 accumulators_period[0x20];
5449 u8 np_ecn_marked_roce_packets_high[0x20];
5451 u8 np_ecn_marked_roce_packets_low[0x20];
5453 u8 np_cnp_sent_high[0x20];
5455 u8 np_cnp_sent_low[0x20];
5457 u8 reserved_at_320[0x560];
5460 struct mlx5_ifc_query_cong_statistics_in_bits {
5462 u8 reserved_at_10[0x10];
5464 u8 reserved_at_20[0x10];
5468 u8 reserved_at_41[0x1f];
5470 u8 reserved_at_60[0x20];
5473 struct mlx5_ifc_query_cong_params_out_bits {
5475 u8 reserved_at_8[0x18];
5479 u8 reserved_at_40[0x40];
5481 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5484 struct mlx5_ifc_query_cong_params_in_bits {
5486 u8 reserved_at_10[0x10];
5488 u8 reserved_at_20[0x10];
5491 u8 reserved_at_40[0x1c];
5492 u8 cong_protocol[0x4];
5494 u8 reserved_at_60[0x20];
5497 struct mlx5_ifc_query_adapter_out_bits {
5499 u8 reserved_at_8[0x18];
5503 u8 reserved_at_40[0x40];
5505 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5508 struct mlx5_ifc_query_adapter_in_bits {
5510 u8 reserved_at_10[0x10];
5512 u8 reserved_at_20[0x10];
5515 u8 reserved_at_40[0x40];
5518 struct mlx5_ifc_qp_2rst_out_bits {
5520 u8 reserved_at_8[0x18];
5524 u8 reserved_at_40[0x40];
5527 struct mlx5_ifc_qp_2rst_in_bits {
5531 u8 reserved_at_20[0x10];
5534 u8 reserved_at_40[0x8];
5537 u8 reserved_at_60[0x20];
5540 struct mlx5_ifc_qp_2err_out_bits {
5542 u8 reserved_at_8[0x18];
5546 u8 reserved_at_40[0x40];
5549 struct mlx5_ifc_qp_2err_in_bits {
5553 u8 reserved_at_20[0x10];
5556 u8 reserved_at_40[0x8];
5559 u8 reserved_at_60[0x20];
5562 struct mlx5_ifc_page_fault_resume_out_bits {
5564 u8 reserved_at_8[0x18];
5568 u8 reserved_at_40[0x40];
5571 struct mlx5_ifc_page_fault_resume_in_bits {
5573 u8 reserved_at_10[0x10];
5575 u8 reserved_at_20[0x10];
5579 u8 reserved_at_41[0x4];
5580 u8 page_fault_type[0x3];
5583 u8 reserved_at_60[0x8];
5587 struct mlx5_ifc_nop_out_bits {
5589 u8 reserved_at_8[0x18];
5593 u8 reserved_at_40[0x40];
5596 struct mlx5_ifc_nop_in_bits {
5598 u8 reserved_at_10[0x10];
5600 u8 reserved_at_20[0x10];
5603 u8 reserved_at_40[0x40];
5606 struct mlx5_ifc_modify_vport_state_out_bits {
5608 u8 reserved_at_8[0x18];
5612 u8 reserved_at_40[0x40];
5615 struct mlx5_ifc_modify_vport_state_in_bits {
5617 u8 reserved_at_10[0x10];
5619 u8 reserved_at_20[0x10];
5622 u8 other_vport[0x1];
5623 u8 reserved_at_41[0xf];
5624 u8 vport_number[0x10];
5626 u8 reserved_at_60[0x18];
5627 u8 admin_state[0x4];
5628 u8 reserved_at_7c[0x4];
5631 struct mlx5_ifc_modify_tis_out_bits {
5633 u8 reserved_at_8[0x18];
5637 u8 reserved_at_40[0x40];
5640 struct mlx5_ifc_modify_tis_bitmask_bits {
5641 u8 reserved_at_0[0x20];
5643 u8 reserved_at_20[0x1d];
5644 u8 lag_tx_port_affinity[0x1];
5645 u8 strict_lag_tx_port_affinity[0x1];
5649 struct mlx5_ifc_modify_tis_in_bits {
5653 u8 reserved_at_20[0x10];
5656 u8 reserved_at_40[0x8];
5659 u8 reserved_at_60[0x20];
5661 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5663 u8 reserved_at_c0[0x40];
5665 struct mlx5_ifc_tisc_bits ctx;
5668 struct mlx5_ifc_modify_tir_bitmask_bits {
5669 u8 reserved_at_0[0x20];
5671 u8 reserved_at_20[0x1b];
5673 u8 reserved_at_3c[0x1];
5675 u8 reserved_at_3e[0x1];
5679 struct mlx5_ifc_modify_tir_out_bits {
5681 u8 reserved_at_8[0x18];
5685 u8 reserved_at_40[0x40];
5688 struct mlx5_ifc_modify_tir_in_bits {
5692 u8 reserved_at_20[0x10];
5695 u8 reserved_at_40[0x8];
5698 u8 reserved_at_60[0x20];
5700 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5702 u8 reserved_at_c0[0x40];
5704 struct mlx5_ifc_tirc_bits ctx;
5707 struct mlx5_ifc_modify_sq_out_bits {
5709 u8 reserved_at_8[0x18];
5713 u8 reserved_at_40[0x40];
5716 struct mlx5_ifc_modify_sq_in_bits {
5720 u8 reserved_at_20[0x10];
5724 u8 reserved_at_44[0x4];
5727 u8 reserved_at_60[0x20];
5729 u8 modify_bitmask[0x40];
5731 u8 reserved_at_c0[0x40];
5733 struct mlx5_ifc_sqc_bits ctx;
5736 struct mlx5_ifc_modify_scheduling_element_out_bits {
5738 u8 reserved_at_8[0x18];
5742 u8 reserved_at_40[0x1c0];
5746 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5747 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5750 struct mlx5_ifc_modify_scheduling_element_in_bits {
5752 u8 reserved_at_10[0x10];
5754 u8 reserved_at_20[0x10];
5757 u8 scheduling_hierarchy[0x8];
5758 u8 reserved_at_48[0x18];
5760 u8 scheduling_element_id[0x20];
5762 u8 reserved_at_80[0x20];
5764 u8 modify_bitmask[0x20];
5766 u8 reserved_at_c0[0x40];
5768 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5770 u8 reserved_at_300[0x100];
5773 struct mlx5_ifc_modify_rqt_out_bits {
5775 u8 reserved_at_8[0x18];
5779 u8 reserved_at_40[0x40];
5782 struct mlx5_ifc_rqt_bitmask_bits {
5783 u8 reserved_at_0[0x20];
5785 u8 reserved_at_20[0x1f];
5789 struct mlx5_ifc_modify_rqt_in_bits {
5793 u8 reserved_at_20[0x10];
5796 u8 reserved_at_40[0x8];
5799 u8 reserved_at_60[0x20];
5801 struct mlx5_ifc_rqt_bitmask_bits bitmask;
5803 u8 reserved_at_c0[0x40];
5805 struct mlx5_ifc_rqtc_bits ctx;
5808 struct mlx5_ifc_modify_rq_out_bits {
5810 u8 reserved_at_8[0x18];
5814 u8 reserved_at_40[0x40];
5818 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5819 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5820 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5823 struct mlx5_ifc_modify_rq_in_bits {
5827 u8 reserved_at_20[0x10];
5831 u8 reserved_at_44[0x4];
5834 u8 reserved_at_60[0x20];
5836 u8 modify_bitmask[0x40];
5838 u8 reserved_at_c0[0x40];
5840 struct mlx5_ifc_rqc_bits ctx;
5843 struct mlx5_ifc_modify_rmp_out_bits {
5845 u8 reserved_at_8[0x18];
5849 u8 reserved_at_40[0x40];
5852 struct mlx5_ifc_rmp_bitmask_bits {
5853 u8 reserved_at_0[0x20];
5855 u8 reserved_at_20[0x1f];
5859 struct mlx5_ifc_modify_rmp_in_bits {
5863 u8 reserved_at_20[0x10];
5867 u8 reserved_at_44[0x4];
5870 u8 reserved_at_60[0x20];
5872 struct mlx5_ifc_rmp_bitmask_bits bitmask;
5874 u8 reserved_at_c0[0x40];
5876 struct mlx5_ifc_rmpc_bits ctx;
5879 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5881 u8 reserved_at_8[0x18];
5885 u8 reserved_at_40[0x40];
5888 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5889 u8 reserved_at_0[0x12];
5890 u8 affiliation[0x1];
5891 u8 reserved_at_13[0x1];
5892 u8 disable_uc_local_lb[0x1];
5893 u8 disable_mc_local_lb[0x1];
5898 u8 change_event[0x1];
5900 u8 permanent_address[0x1];
5901 u8 addresses_list[0x1];
5903 u8 reserved_at_1f[0x1];
5906 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5908 u8 reserved_at_10[0x10];
5910 u8 reserved_at_20[0x10];
5913 u8 other_vport[0x1];
5914 u8 reserved_at_41[0xf];
5915 u8 vport_number[0x10];
5917 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5919 u8 reserved_at_80[0x780];
5921 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5924 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5926 u8 reserved_at_8[0x18];
5930 u8 reserved_at_40[0x40];
5933 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5935 u8 reserved_at_10[0x10];
5937 u8 reserved_at_20[0x10];
5940 u8 other_vport[0x1];
5941 u8 reserved_at_41[0xb];
5943 u8 vport_number[0x10];
5945 u8 reserved_at_60[0x20];
5947 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5950 struct mlx5_ifc_modify_cq_out_bits {
5952 u8 reserved_at_8[0x18];
5956 u8 reserved_at_40[0x40];
5960 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5961 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5964 struct mlx5_ifc_modify_cq_in_bits {
5968 u8 reserved_at_20[0x10];
5971 u8 reserved_at_40[0x8];
5974 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5976 struct mlx5_ifc_cqc_bits cq_context;
5978 u8 reserved_at_280[0x40];
5980 u8 cq_umem_valid[0x1];
5981 u8 reserved_at_2c1[0x5bf];
5986 struct mlx5_ifc_modify_cong_status_out_bits {
5988 u8 reserved_at_8[0x18];
5992 u8 reserved_at_40[0x40];
5995 struct mlx5_ifc_modify_cong_status_in_bits {
5997 u8 reserved_at_10[0x10];
5999 u8 reserved_at_20[0x10];
6002 u8 reserved_at_40[0x18];
6004 u8 cong_protocol[0x4];
6008 u8 reserved_at_62[0x1e];
6011 struct mlx5_ifc_modify_cong_params_out_bits {
6013 u8 reserved_at_8[0x18];
6017 u8 reserved_at_40[0x40];
6020 struct mlx5_ifc_modify_cong_params_in_bits {
6022 u8 reserved_at_10[0x10];
6024 u8 reserved_at_20[0x10];
6027 u8 reserved_at_40[0x1c];
6028 u8 cong_protocol[0x4];
6030 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6032 u8 reserved_at_80[0x80];
6034 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6037 struct mlx5_ifc_manage_pages_out_bits {
6039 u8 reserved_at_8[0x18];
6043 u8 output_num_entries[0x20];
6045 u8 reserved_at_60[0x20];
6051 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6052 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6053 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6056 struct mlx5_ifc_manage_pages_in_bits {
6058 u8 reserved_at_10[0x10];
6060 u8 reserved_at_20[0x10];
6063 u8 embedded_cpu_function[0x1];
6064 u8 reserved_at_41[0xf];
6065 u8 function_id[0x10];
6067 u8 input_num_entries[0x20];
6072 struct mlx5_ifc_mad_ifc_out_bits {
6074 u8 reserved_at_8[0x18];
6078 u8 reserved_at_40[0x40];
6080 u8 response_mad_packet[256][0x8];
6083 struct mlx5_ifc_mad_ifc_in_bits {
6085 u8 reserved_at_10[0x10];
6087 u8 reserved_at_20[0x10];
6090 u8 remote_lid[0x10];
6091 u8 reserved_at_50[0x8];
6094 u8 reserved_at_60[0x20];
6099 struct mlx5_ifc_init_hca_out_bits {
6101 u8 reserved_at_8[0x18];
6105 u8 reserved_at_40[0x40];
6108 struct mlx5_ifc_init_hca_in_bits {
6110 u8 reserved_at_10[0x10];
6112 u8 reserved_at_20[0x10];
6115 u8 reserved_at_40[0x40];
6116 u8 sw_owner_id[4][0x20];
6119 struct mlx5_ifc_init2rtr_qp_out_bits {
6121 u8 reserved_at_8[0x18];
6125 u8 reserved_at_40[0x40];
6128 struct mlx5_ifc_init2rtr_qp_in_bits {
6132 u8 reserved_at_20[0x10];
6135 u8 reserved_at_40[0x8];
6138 u8 reserved_at_60[0x20];
6140 u8 opt_param_mask[0x20];
6142 u8 reserved_at_a0[0x20];
6144 struct mlx5_ifc_qpc_bits qpc;
6146 u8 reserved_at_800[0x80];
6149 struct mlx5_ifc_init2init_qp_out_bits {
6151 u8 reserved_at_8[0x18];
6155 u8 reserved_at_40[0x40];
6158 struct mlx5_ifc_init2init_qp_in_bits {
6162 u8 reserved_at_20[0x10];
6165 u8 reserved_at_40[0x8];
6168 u8 reserved_at_60[0x20];
6170 u8 opt_param_mask[0x20];
6172 u8 reserved_at_a0[0x20];
6174 struct mlx5_ifc_qpc_bits qpc;
6176 u8 reserved_at_800[0x80];
6179 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6181 u8 reserved_at_8[0x18];
6185 u8 reserved_at_40[0x40];
6187 u8 packet_headers_log[128][0x8];
6189 u8 packet_syndrome[64][0x8];
6192 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6194 u8 reserved_at_10[0x10];
6196 u8 reserved_at_20[0x10];
6199 u8 reserved_at_40[0x40];
6202 struct mlx5_ifc_gen_eqe_in_bits {
6204 u8 reserved_at_10[0x10];
6206 u8 reserved_at_20[0x10];
6209 u8 reserved_at_40[0x18];
6212 u8 reserved_at_60[0x20];
6217 struct mlx5_ifc_gen_eq_out_bits {
6219 u8 reserved_at_8[0x18];
6223 u8 reserved_at_40[0x40];
6226 struct mlx5_ifc_enable_hca_out_bits {
6228 u8 reserved_at_8[0x18];
6232 u8 reserved_at_40[0x20];
6235 struct mlx5_ifc_enable_hca_in_bits {
6237 u8 reserved_at_10[0x10];
6239 u8 reserved_at_20[0x10];
6242 u8 embedded_cpu_function[0x1];
6243 u8 reserved_at_41[0xf];
6244 u8 function_id[0x10];
6246 u8 reserved_at_60[0x20];
6249 struct mlx5_ifc_drain_dct_out_bits {
6251 u8 reserved_at_8[0x18];
6255 u8 reserved_at_40[0x40];
6258 struct mlx5_ifc_drain_dct_in_bits {
6262 u8 reserved_at_20[0x10];
6265 u8 reserved_at_40[0x8];
6268 u8 reserved_at_60[0x20];
6271 struct mlx5_ifc_disable_hca_out_bits {
6273 u8 reserved_at_8[0x18];
6277 u8 reserved_at_40[0x20];
6280 struct mlx5_ifc_disable_hca_in_bits {
6282 u8 reserved_at_10[0x10];
6284 u8 reserved_at_20[0x10];
6287 u8 embedded_cpu_function[0x1];
6288 u8 reserved_at_41[0xf];
6289 u8 function_id[0x10];
6291 u8 reserved_at_60[0x20];
6294 struct mlx5_ifc_detach_from_mcg_out_bits {
6296 u8 reserved_at_8[0x18];
6300 u8 reserved_at_40[0x40];
6303 struct mlx5_ifc_detach_from_mcg_in_bits {
6307 u8 reserved_at_20[0x10];
6310 u8 reserved_at_40[0x8];
6313 u8 reserved_at_60[0x20];
6315 u8 multicast_gid[16][0x8];
6318 struct mlx5_ifc_destroy_xrq_out_bits {
6320 u8 reserved_at_8[0x18];
6324 u8 reserved_at_40[0x40];
6327 struct mlx5_ifc_destroy_xrq_in_bits {
6331 u8 reserved_at_20[0x10];
6334 u8 reserved_at_40[0x8];
6337 u8 reserved_at_60[0x20];
6340 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6342 u8 reserved_at_8[0x18];
6346 u8 reserved_at_40[0x40];
6349 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6353 u8 reserved_at_20[0x10];
6356 u8 reserved_at_40[0x8];
6359 u8 reserved_at_60[0x20];
6362 struct mlx5_ifc_destroy_tis_out_bits {
6364 u8 reserved_at_8[0x18];
6368 u8 reserved_at_40[0x40];
6371 struct mlx5_ifc_destroy_tis_in_bits {
6375 u8 reserved_at_20[0x10];
6378 u8 reserved_at_40[0x8];
6381 u8 reserved_at_60[0x20];
6384 struct mlx5_ifc_destroy_tir_out_bits {
6386 u8 reserved_at_8[0x18];
6390 u8 reserved_at_40[0x40];
6393 struct mlx5_ifc_destroy_tir_in_bits {
6397 u8 reserved_at_20[0x10];
6400 u8 reserved_at_40[0x8];
6403 u8 reserved_at_60[0x20];
6406 struct mlx5_ifc_destroy_srq_out_bits {
6408 u8 reserved_at_8[0x18];
6412 u8 reserved_at_40[0x40];
6415 struct mlx5_ifc_destroy_srq_in_bits {
6419 u8 reserved_at_20[0x10];
6422 u8 reserved_at_40[0x8];
6425 u8 reserved_at_60[0x20];
6428 struct mlx5_ifc_destroy_sq_out_bits {
6430 u8 reserved_at_8[0x18];
6434 u8 reserved_at_40[0x40];
6437 struct mlx5_ifc_destroy_sq_in_bits {
6441 u8 reserved_at_20[0x10];
6444 u8 reserved_at_40[0x8];
6447 u8 reserved_at_60[0x20];
6450 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6452 u8 reserved_at_8[0x18];
6456 u8 reserved_at_40[0x1c0];
6459 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6461 u8 reserved_at_10[0x10];
6463 u8 reserved_at_20[0x10];
6466 u8 scheduling_hierarchy[0x8];
6467 u8 reserved_at_48[0x18];
6469 u8 scheduling_element_id[0x20];
6471 u8 reserved_at_80[0x180];
6474 struct mlx5_ifc_destroy_rqt_out_bits {
6476 u8 reserved_at_8[0x18];
6480 u8 reserved_at_40[0x40];
6483 struct mlx5_ifc_destroy_rqt_in_bits {
6487 u8 reserved_at_20[0x10];
6490 u8 reserved_at_40[0x8];
6493 u8 reserved_at_60[0x20];
6496 struct mlx5_ifc_destroy_rq_out_bits {
6498 u8 reserved_at_8[0x18];
6502 u8 reserved_at_40[0x40];
6505 struct mlx5_ifc_destroy_rq_in_bits {
6509 u8 reserved_at_20[0x10];
6512 u8 reserved_at_40[0x8];
6515 u8 reserved_at_60[0x20];
6518 struct mlx5_ifc_set_delay_drop_params_in_bits {
6520 u8 reserved_at_10[0x10];
6522 u8 reserved_at_20[0x10];
6525 u8 reserved_at_40[0x20];
6527 u8 reserved_at_60[0x10];
6528 u8 delay_drop_timeout[0x10];
6531 struct mlx5_ifc_set_delay_drop_params_out_bits {
6533 u8 reserved_at_8[0x18];
6537 u8 reserved_at_40[0x40];
6540 struct mlx5_ifc_destroy_rmp_out_bits {
6542 u8 reserved_at_8[0x18];
6546 u8 reserved_at_40[0x40];
6549 struct mlx5_ifc_destroy_rmp_in_bits {
6553 u8 reserved_at_20[0x10];
6556 u8 reserved_at_40[0x8];
6559 u8 reserved_at_60[0x20];
6562 struct mlx5_ifc_destroy_qp_out_bits {
6564 u8 reserved_at_8[0x18];
6568 u8 reserved_at_40[0x40];
6571 struct mlx5_ifc_destroy_qp_in_bits {
6575 u8 reserved_at_20[0x10];
6578 u8 reserved_at_40[0x8];
6581 u8 reserved_at_60[0x20];
6584 struct mlx5_ifc_destroy_psv_out_bits {
6586 u8 reserved_at_8[0x18];
6590 u8 reserved_at_40[0x40];
6593 struct mlx5_ifc_destroy_psv_in_bits {
6595 u8 reserved_at_10[0x10];
6597 u8 reserved_at_20[0x10];
6600 u8 reserved_at_40[0x8];
6603 u8 reserved_at_60[0x20];
6606 struct mlx5_ifc_destroy_mkey_out_bits {
6608 u8 reserved_at_8[0x18];
6612 u8 reserved_at_40[0x40];
6615 struct mlx5_ifc_destroy_mkey_in_bits {
6617 u8 reserved_at_10[0x10];
6619 u8 reserved_at_20[0x10];
6622 u8 reserved_at_40[0x8];
6623 u8 mkey_index[0x18];
6625 u8 reserved_at_60[0x20];
6628 struct mlx5_ifc_destroy_flow_table_out_bits {
6630 u8 reserved_at_8[0x18];
6634 u8 reserved_at_40[0x40];
6637 struct mlx5_ifc_destroy_flow_table_in_bits {
6639 u8 reserved_at_10[0x10];
6641 u8 reserved_at_20[0x10];
6644 u8 other_vport[0x1];
6645 u8 reserved_at_41[0xf];
6646 u8 vport_number[0x10];
6648 u8 reserved_at_60[0x20];
6651 u8 reserved_at_88[0x18];
6653 u8 reserved_at_a0[0x8];
6656 u8 reserved_at_c0[0x140];
6659 struct mlx5_ifc_destroy_flow_group_out_bits {
6661 u8 reserved_at_8[0x18];
6665 u8 reserved_at_40[0x40];
6668 struct mlx5_ifc_destroy_flow_group_in_bits {
6670 u8 reserved_at_10[0x10];
6672 u8 reserved_at_20[0x10];
6675 u8 other_vport[0x1];
6676 u8 reserved_at_41[0xf];
6677 u8 vport_number[0x10];
6679 u8 reserved_at_60[0x20];
6682 u8 reserved_at_88[0x18];
6684 u8 reserved_at_a0[0x8];
6689 u8 reserved_at_e0[0x120];
6692 struct mlx5_ifc_destroy_eq_out_bits {
6694 u8 reserved_at_8[0x18];
6698 u8 reserved_at_40[0x40];
6701 struct mlx5_ifc_destroy_eq_in_bits {
6703 u8 reserved_at_10[0x10];
6705 u8 reserved_at_20[0x10];
6708 u8 reserved_at_40[0x18];
6711 u8 reserved_at_60[0x20];
6714 struct mlx5_ifc_destroy_dct_out_bits {
6716 u8 reserved_at_8[0x18];
6720 u8 reserved_at_40[0x40];
6723 struct mlx5_ifc_destroy_dct_in_bits {
6727 u8 reserved_at_20[0x10];
6730 u8 reserved_at_40[0x8];
6733 u8 reserved_at_60[0x20];
6736 struct mlx5_ifc_destroy_cq_out_bits {
6738 u8 reserved_at_8[0x18];
6742 u8 reserved_at_40[0x40];
6745 struct mlx5_ifc_destroy_cq_in_bits {
6749 u8 reserved_at_20[0x10];
6752 u8 reserved_at_40[0x8];
6755 u8 reserved_at_60[0x20];
6758 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6760 u8 reserved_at_8[0x18];
6764 u8 reserved_at_40[0x40];
6767 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6769 u8 reserved_at_10[0x10];
6771 u8 reserved_at_20[0x10];
6774 u8 reserved_at_40[0x20];
6776 u8 reserved_at_60[0x10];
6777 u8 vxlan_udp_port[0x10];
6780 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6782 u8 reserved_at_8[0x18];
6786 u8 reserved_at_40[0x40];
6789 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6791 u8 reserved_at_10[0x10];
6793 u8 reserved_at_20[0x10];
6796 u8 reserved_at_40[0x60];
6798 u8 reserved_at_a0[0x8];
6799 u8 table_index[0x18];
6801 u8 reserved_at_c0[0x140];
6804 struct mlx5_ifc_delete_fte_out_bits {
6806 u8 reserved_at_8[0x18];
6810 u8 reserved_at_40[0x40];
6813 struct mlx5_ifc_delete_fte_in_bits {
6815 u8 reserved_at_10[0x10];
6817 u8 reserved_at_20[0x10];
6820 u8 other_vport[0x1];
6821 u8 reserved_at_41[0xf];
6822 u8 vport_number[0x10];
6824 u8 reserved_at_60[0x20];
6827 u8 reserved_at_88[0x18];
6829 u8 reserved_at_a0[0x8];
6832 u8 reserved_at_c0[0x40];
6834 u8 flow_index[0x20];
6836 u8 reserved_at_120[0xe0];
6839 struct mlx5_ifc_dealloc_xrcd_out_bits {
6841 u8 reserved_at_8[0x18];
6845 u8 reserved_at_40[0x40];
6848 struct mlx5_ifc_dealloc_xrcd_in_bits {
6852 u8 reserved_at_20[0x10];
6855 u8 reserved_at_40[0x8];
6858 u8 reserved_at_60[0x20];
6861 struct mlx5_ifc_dealloc_uar_out_bits {
6863 u8 reserved_at_8[0x18];
6867 u8 reserved_at_40[0x40];
6870 struct mlx5_ifc_dealloc_uar_in_bits {
6872 u8 reserved_at_10[0x10];
6874 u8 reserved_at_20[0x10];
6877 u8 reserved_at_40[0x8];
6880 u8 reserved_at_60[0x20];
6883 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6885 u8 reserved_at_8[0x18];
6889 u8 reserved_at_40[0x40];
6892 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6896 u8 reserved_at_20[0x10];
6899 u8 reserved_at_40[0x8];
6900 u8 transport_domain[0x18];
6902 u8 reserved_at_60[0x20];
6905 struct mlx5_ifc_dealloc_q_counter_out_bits {
6907 u8 reserved_at_8[0x18];
6911 u8 reserved_at_40[0x40];
6914 struct mlx5_ifc_dealloc_q_counter_in_bits {
6916 u8 reserved_at_10[0x10];
6918 u8 reserved_at_20[0x10];
6921 u8 reserved_at_40[0x18];
6922 u8 counter_set_id[0x8];
6924 u8 reserved_at_60[0x20];
6927 struct mlx5_ifc_dealloc_pd_out_bits {
6929 u8 reserved_at_8[0x18];
6933 u8 reserved_at_40[0x40];
6936 struct mlx5_ifc_dealloc_pd_in_bits {
6940 u8 reserved_at_20[0x10];
6943 u8 reserved_at_40[0x8];
6946 u8 reserved_at_60[0x20];
6949 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6951 u8 reserved_at_8[0x18];
6955 u8 reserved_at_40[0x40];
6958 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6960 u8 reserved_at_10[0x10];
6962 u8 reserved_at_20[0x10];
6965 u8 flow_counter_id[0x20];
6967 u8 reserved_at_60[0x20];
6970 struct mlx5_ifc_create_xrq_out_bits {
6972 u8 reserved_at_8[0x18];
6976 u8 reserved_at_40[0x8];
6979 u8 reserved_at_60[0x20];
6982 struct mlx5_ifc_create_xrq_in_bits {
6986 u8 reserved_at_20[0x10];
6989 u8 reserved_at_40[0x40];
6991 struct mlx5_ifc_xrqc_bits xrq_context;
6994 struct mlx5_ifc_create_xrc_srq_out_bits {
6996 u8 reserved_at_8[0x18];
7000 u8 reserved_at_40[0x8];
7003 u8 reserved_at_60[0x20];
7006 struct mlx5_ifc_create_xrc_srq_in_bits {
7010 u8 reserved_at_20[0x10];
7013 u8 reserved_at_40[0x40];
7015 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7017 u8 reserved_at_280[0x60];
7019 u8 xrc_srq_umem_valid[0x1];
7020 u8 reserved_at_2e1[0x1f];
7022 u8 reserved_at_300[0x580];
7027 struct mlx5_ifc_create_tis_out_bits {
7029 u8 reserved_at_8[0x18];
7033 u8 reserved_at_40[0x8];
7036 u8 reserved_at_60[0x20];
7039 struct mlx5_ifc_create_tis_in_bits {
7043 u8 reserved_at_20[0x10];
7046 u8 reserved_at_40[0xc0];
7048 struct mlx5_ifc_tisc_bits ctx;
7051 struct mlx5_ifc_create_tir_out_bits {
7053 u8 icm_address_63_40[0x18];
7057 u8 icm_address_39_32[0x8];
7060 u8 icm_address_31_0[0x20];
7063 struct mlx5_ifc_create_tir_in_bits {
7067 u8 reserved_at_20[0x10];
7070 u8 reserved_at_40[0xc0];
7072 struct mlx5_ifc_tirc_bits ctx;
7075 struct mlx5_ifc_create_srq_out_bits {
7077 u8 reserved_at_8[0x18];
7081 u8 reserved_at_40[0x8];
7084 u8 reserved_at_60[0x20];
7087 struct mlx5_ifc_create_srq_in_bits {
7091 u8 reserved_at_20[0x10];
7094 u8 reserved_at_40[0x40];
7096 struct mlx5_ifc_srqc_bits srq_context_entry;
7098 u8 reserved_at_280[0x600];
7103 struct mlx5_ifc_create_sq_out_bits {
7105 u8 reserved_at_8[0x18];
7109 u8 reserved_at_40[0x8];
7112 u8 reserved_at_60[0x20];
7115 struct mlx5_ifc_create_sq_in_bits {
7119 u8 reserved_at_20[0x10];
7122 u8 reserved_at_40[0xc0];
7124 struct mlx5_ifc_sqc_bits ctx;
7127 struct mlx5_ifc_create_scheduling_element_out_bits {
7129 u8 reserved_at_8[0x18];
7133 u8 reserved_at_40[0x40];
7135 u8 scheduling_element_id[0x20];
7137 u8 reserved_at_a0[0x160];
7140 struct mlx5_ifc_create_scheduling_element_in_bits {
7142 u8 reserved_at_10[0x10];
7144 u8 reserved_at_20[0x10];
7147 u8 scheduling_hierarchy[0x8];
7148 u8 reserved_at_48[0x18];
7150 u8 reserved_at_60[0xa0];
7152 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7154 u8 reserved_at_300[0x100];
7157 struct mlx5_ifc_create_rqt_out_bits {
7159 u8 reserved_at_8[0x18];
7163 u8 reserved_at_40[0x8];
7166 u8 reserved_at_60[0x20];
7169 struct mlx5_ifc_create_rqt_in_bits {
7173 u8 reserved_at_20[0x10];
7176 u8 reserved_at_40[0xc0];
7178 struct mlx5_ifc_rqtc_bits rqt_context;
7181 struct mlx5_ifc_create_rq_out_bits {
7183 u8 reserved_at_8[0x18];
7187 u8 reserved_at_40[0x8];
7190 u8 reserved_at_60[0x20];
7193 struct mlx5_ifc_create_rq_in_bits {
7197 u8 reserved_at_20[0x10];
7200 u8 reserved_at_40[0xc0];
7202 struct mlx5_ifc_rqc_bits ctx;
7205 struct mlx5_ifc_create_rmp_out_bits {
7207 u8 reserved_at_8[0x18];
7211 u8 reserved_at_40[0x8];
7214 u8 reserved_at_60[0x20];
7217 struct mlx5_ifc_create_rmp_in_bits {
7221 u8 reserved_at_20[0x10];
7224 u8 reserved_at_40[0xc0];
7226 struct mlx5_ifc_rmpc_bits ctx;
7229 struct mlx5_ifc_create_qp_out_bits {
7231 u8 reserved_at_8[0x18];
7235 u8 reserved_at_40[0x8];
7238 u8 reserved_at_60[0x20];
7241 struct mlx5_ifc_create_qp_in_bits {
7245 u8 reserved_at_20[0x10];
7248 u8 reserved_at_40[0x40];
7250 u8 opt_param_mask[0x20];
7252 u8 reserved_at_a0[0x20];
7254 struct mlx5_ifc_qpc_bits qpc;
7256 u8 reserved_at_800[0x60];
7258 u8 wq_umem_valid[0x1];
7259 u8 reserved_at_861[0x1f];
7264 struct mlx5_ifc_create_psv_out_bits {
7266 u8 reserved_at_8[0x18];
7270 u8 reserved_at_40[0x40];
7272 u8 reserved_at_80[0x8];
7273 u8 psv0_index[0x18];
7275 u8 reserved_at_a0[0x8];
7276 u8 psv1_index[0x18];
7278 u8 reserved_at_c0[0x8];
7279 u8 psv2_index[0x18];
7281 u8 reserved_at_e0[0x8];
7282 u8 psv3_index[0x18];
7285 struct mlx5_ifc_create_psv_in_bits {
7287 u8 reserved_at_10[0x10];
7289 u8 reserved_at_20[0x10];
7293 u8 reserved_at_44[0x4];
7296 u8 reserved_at_60[0x20];
7299 struct mlx5_ifc_create_mkey_out_bits {
7301 u8 reserved_at_8[0x18];
7305 u8 reserved_at_40[0x8];
7306 u8 mkey_index[0x18];
7308 u8 reserved_at_60[0x20];
7311 struct mlx5_ifc_create_mkey_in_bits {
7313 u8 reserved_at_10[0x10];
7315 u8 reserved_at_20[0x10];
7318 u8 reserved_at_40[0x20];
7321 u8 mkey_umem_valid[0x1];
7322 u8 reserved_at_62[0x1e];
7324 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7326 u8 reserved_at_280[0x80];
7328 u8 translations_octword_actual_size[0x20];
7330 u8 reserved_at_320[0x560];
7332 u8 klm_pas_mtt[0][0x20];
7335 struct mlx5_ifc_create_flow_table_out_bits {
7337 u8 reserved_at_8[0x18];
7341 u8 reserved_at_40[0x8];
7344 u8 reserved_at_60[0x20];
7347 struct mlx5_ifc_flow_table_context_bits {
7348 u8 reformat_en[0x1];
7350 u8 reserved_at_2[0x1];
7351 u8 termination_table[0x1];
7352 u8 table_miss_action[0x4];
7354 u8 reserved_at_10[0x8];
7357 u8 reserved_at_20[0x8];
7358 u8 table_miss_id[0x18];
7360 u8 reserved_at_40[0x8];
7361 u8 lag_master_next_table_id[0x18];
7363 u8 reserved_at_60[0xe0];
7366 struct mlx5_ifc_create_flow_table_in_bits {
7368 u8 reserved_at_10[0x10];
7370 u8 reserved_at_20[0x10];
7373 u8 other_vport[0x1];
7374 u8 reserved_at_41[0xf];
7375 u8 vport_number[0x10];
7377 u8 reserved_at_60[0x20];
7380 u8 reserved_at_88[0x18];
7382 u8 reserved_at_a0[0x20];
7384 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7387 struct mlx5_ifc_create_flow_group_out_bits {
7389 u8 reserved_at_8[0x18];
7393 u8 reserved_at_40[0x8];
7396 u8 reserved_at_60[0x20];
7400 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7401 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7402 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7403 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7406 struct mlx5_ifc_create_flow_group_in_bits {
7408 u8 reserved_at_10[0x10];
7410 u8 reserved_at_20[0x10];
7413 u8 other_vport[0x1];
7414 u8 reserved_at_41[0xf];
7415 u8 vport_number[0x10];
7417 u8 reserved_at_60[0x20];
7420 u8 reserved_at_88[0x18];
7422 u8 reserved_at_a0[0x8];
7425 u8 source_eswitch_owner_vhca_id_valid[0x1];
7427 u8 reserved_at_c1[0x1f];
7429 u8 start_flow_index[0x20];
7431 u8 reserved_at_100[0x20];
7433 u8 end_flow_index[0x20];
7435 u8 reserved_at_140[0xa0];
7437 u8 reserved_at_1e0[0x18];
7438 u8 match_criteria_enable[0x8];
7440 struct mlx5_ifc_fte_match_param_bits match_criteria;
7442 u8 reserved_at_1200[0xe00];
7445 struct mlx5_ifc_create_eq_out_bits {
7447 u8 reserved_at_8[0x18];
7451 u8 reserved_at_40[0x18];
7454 u8 reserved_at_60[0x20];
7457 struct mlx5_ifc_create_eq_in_bits {
7461 u8 reserved_at_20[0x10];
7464 u8 reserved_at_40[0x40];
7466 struct mlx5_ifc_eqc_bits eq_context_entry;
7468 u8 reserved_at_280[0x40];
7470 u8 event_bitmask[4][0x40];
7472 u8 reserved_at_3c0[0x4c0];
7477 struct mlx5_ifc_create_dct_out_bits {
7479 u8 reserved_at_8[0x18];
7483 u8 reserved_at_40[0x8];
7486 u8 reserved_at_60[0x20];
7489 struct mlx5_ifc_create_dct_in_bits {
7493 u8 reserved_at_20[0x10];
7496 u8 reserved_at_40[0x40];
7498 struct mlx5_ifc_dctc_bits dct_context_entry;
7500 u8 reserved_at_280[0x180];
7503 struct mlx5_ifc_create_cq_out_bits {
7505 u8 reserved_at_8[0x18];
7509 u8 reserved_at_40[0x8];
7512 u8 reserved_at_60[0x20];
7515 struct mlx5_ifc_create_cq_in_bits {
7519 u8 reserved_at_20[0x10];
7522 u8 reserved_at_40[0x40];
7524 struct mlx5_ifc_cqc_bits cq_context;
7526 u8 reserved_at_280[0x60];
7528 u8 cq_umem_valid[0x1];
7529 u8 reserved_at_2e1[0x59f];
7534 struct mlx5_ifc_config_int_moderation_out_bits {
7536 u8 reserved_at_8[0x18];
7540 u8 reserved_at_40[0x4];
7542 u8 int_vector[0x10];
7544 u8 reserved_at_60[0x20];
7548 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7549 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7552 struct mlx5_ifc_config_int_moderation_in_bits {
7554 u8 reserved_at_10[0x10];
7556 u8 reserved_at_20[0x10];
7559 u8 reserved_at_40[0x4];
7561 u8 int_vector[0x10];
7563 u8 reserved_at_60[0x20];
7566 struct mlx5_ifc_attach_to_mcg_out_bits {
7568 u8 reserved_at_8[0x18];
7572 u8 reserved_at_40[0x40];
7575 struct mlx5_ifc_attach_to_mcg_in_bits {
7579 u8 reserved_at_20[0x10];
7582 u8 reserved_at_40[0x8];
7585 u8 reserved_at_60[0x20];
7587 u8 multicast_gid[16][0x8];
7590 struct mlx5_ifc_arm_xrq_out_bits {
7592 u8 reserved_at_8[0x18];
7596 u8 reserved_at_40[0x40];
7599 struct mlx5_ifc_arm_xrq_in_bits {
7601 u8 reserved_at_10[0x10];
7603 u8 reserved_at_20[0x10];
7606 u8 reserved_at_40[0x8];
7609 u8 reserved_at_60[0x10];
7613 struct mlx5_ifc_arm_xrc_srq_out_bits {
7615 u8 reserved_at_8[0x18];
7619 u8 reserved_at_40[0x40];
7623 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7626 struct mlx5_ifc_arm_xrc_srq_in_bits {
7630 u8 reserved_at_20[0x10];
7633 u8 reserved_at_40[0x8];
7636 u8 reserved_at_60[0x10];
7640 struct mlx5_ifc_arm_rq_out_bits {
7642 u8 reserved_at_8[0x18];
7646 u8 reserved_at_40[0x40];
7650 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7651 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7654 struct mlx5_ifc_arm_rq_in_bits {
7658 u8 reserved_at_20[0x10];
7661 u8 reserved_at_40[0x8];
7662 u8 srq_number[0x18];
7664 u8 reserved_at_60[0x10];
7668 struct mlx5_ifc_arm_dct_out_bits {
7670 u8 reserved_at_8[0x18];
7674 u8 reserved_at_40[0x40];
7677 struct mlx5_ifc_arm_dct_in_bits {
7679 u8 reserved_at_10[0x10];
7681 u8 reserved_at_20[0x10];
7684 u8 reserved_at_40[0x8];
7685 u8 dct_number[0x18];
7687 u8 reserved_at_60[0x20];
7690 struct mlx5_ifc_alloc_xrcd_out_bits {
7692 u8 reserved_at_8[0x18];
7696 u8 reserved_at_40[0x8];
7699 u8 reserved_at_60[0x20];
7702 struct mlx5_ifc_alloc_xrcd_in_bits {
7706 u8 reserved_at_20[0x10];
7709 u8 reserved_at_40[0x40];
7712 struct mlx5_ifc_alloc_uar_out_bits {
7714 u8 reserved_at_8[0x18];
7718 u8 reserved_at_40[0x8];
7721 u8 reserved_at_60[0x20];
7724 struct mlx5_ifc_alloc_uar_in_bits {
7726 u8 reserved_at_10[0x10];
7728 u8 reserved_at_20[0x10];
7731 u8 reserved_at_40[0x40];
7734 struct mlx5_ifc_alloc_transport_domain_out_bits {
7736 u8 reserved_at_8[0x18];
7740 u8 reserved_at_40[0x8];
7741 u8 transport_domain[0x18];
7743 u8 reserved_at_60[0x20];
7746 struct mlx5_ifc_alloc_transport_domain_in_bits {
7750 u8 reserved_at_20[0x10];
7753 u8 reserved_at_40[0x40];
7756 struct mlx5_ifc_alloc_q_counter_out_bits {
7758 u8 reserved_at_8[0x18];
7762 u8 reserved_at_40[0x18];
7763 u8 counter_set_id[0x8];
7765 u8 reserved_at_60[0x20];
7768 struct mlx5_ifc_alloc_q_counter_in_bits {
7772 u8 reserved_at_20[0x10];
7775 u8 reserved_at_40[0x40];
7778 struct mlx5_ifc_alloc_pd_out_bits {
7780 u8 reserved_at_8[0x18];
7784 u8 reserved_at_40[0x8];
7787 u8 reserved_at_60[0x20];
7790 struct mlx5_ifc_alloc_pd_in_bits {
7794 u8 reserved_at_20[0x10];
7797 u8 reserved_at_40[0x40];
7800 struct mlx5_ifc_alloc_flow_counter_out_bits {
7802 u8 reserved_at_8[0x18];
7806 u8 flow_counter_id[0x20];
7808 u8 reserved_at_60[0x20];
7811 struct mlx5_ifc_alloc_flow_counter_in_bits {
7813 u8 reserved_at_10[0x10];
7815 u8 reserved_at_20[0x10];
7818 u8 reserved_at_40[0x40];
7821 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7823 u8 reserved_at_8[0x18];
7827 u8 reserved_at_40[0x40];
7830 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7832 u8 reserved_at_10[0x10];
7834 u8 reserved_at_20[0x10];
7837 u8 reserved_at_40[0x20];
7839 u8 reserved_at_60[0x10];
7840 u8 vxlan_udp_port[0x10];
7843 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7845 u8 reserved_at_8[0x18];
7849 u8 reserved_at_40[0x40];
7852 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7854 u8 reserved_at_10[0x10];
7856 u8 reserved_at_20[0x10];
7859 u8 reserved_at_40[0x10];
7860 u8 rate_limit_index[0x10];
7862 u8 reserved_at_60[0x20];
7864 u8 rate_limit[0x20];
7866 u8 burst_upper_bound[0x20];
7868 u8 reserved_at_c0[0x10];
7869 u8 typical_packet_size[0x10];
7871 u8 reserved_at_e0[0x120];
7874 struct mlx5_ifc_access_register_out_bits {
7876 u8 reserved_at_8[0x18];
7880 u8 reserved_at_40[0x40];
7882 u8 register_data[0][0x20];
7886 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7887 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7890 struct mlx5_ifc_access_register_in_bits {
7892 u8 reserved_at_10[0x10];
7894 u8 reserved_at_20[0x10];
7897 u8 reserved_at_40[0x10];
7898 u8 register_id[0x10];
7902 u8 register_data[0][0x20];
7905 struct mlx5_ifc_sltp_reg_bits {
7910 u8 reserved_at_12[0x2];
7912 u8 reserved_at_18[0x8];
7914 u8 reserved_at_20[0x20];
7916 u8 reserved_at_40[0x7];
7922 u8 reserved_at_60[0xc];
7923 u8 ob_preemp_mode[0x4];
7927 u8 reserved_at_80[0x20];
7930 struct mlx5_ifc_slrg_reg_bits {
7935 u8 reserved_at_12[0x2];
7937 u8 reserved_at_18[0x8];
7939 u8 time_to_link_up[0x10];
7940 u8 reserved_at_30[0xc];
7941 u8 grade_lane_speed[0x4];
7943 u8 grade_version[0x8];
7946 u8 reserved_at_60[0x4];
7947 u8 height_grade_type[0x4];
7948 u8 height_grade[0x18];
7953 u8 reserved_at_a0[0x10];
7954 u8 height_sigma[0x10];
7956 u8 reserved_at_c0[0x20];
7958 u8 reserved_at_e0[0x4];
7959 u8 phase_grade_type[0x4];
7960 u8 phase_grade[0x18];
7962 u8 reserved_at_100[0x8];
7963 u8 phase_eo_pos[0x8];
7964 u8 reserved_at_110[0x8];
7965 u8 phase_eo_neg[0x8];
7967 u8 ffe_set_tested[0x10];
7968 u8 test_errors_per_lane[0x10];
7971 struct mlx5_ifc_pvlc_reg_bits {
7972 u8 reserved_at_0[0x8];
7974 u8 reserved_at_10[0x10];
7976 u8 reserved_at_20[0x1c];
7979 u8 reserved_at_40[0x1c];
7982 u8 reserved_at_60[0x1c];
7983 u8 vl_operational[0x4];
7986 struct mlx5_ifc_pude_reg_bits {
7989 u8 reserved_at_10[0x4];
7990 u8 admin_status[0x4];
7991 u8 reserved_at_18[0x4];
7992 u8 oper_status[0x4];
7994 u8 reserved_at_20[0x60];
7997 struct mlx5_ifc_ptys_reg_bits {
7998 u8 reserved_at_0[0x1];
7999 u8 an_disable_admin[0x1];
8000 u8 an_disable_cap[0x1];
8001 u8 reserved_at_3[0x5];
8003 u8 reserved_at_10[0xd];
8007 u8 reserved_at_24[0x1c];
8009 u8 ext_eth_proto_capability[0x20];
8011 u8 eth_proto_capability[0x20];
8013 u8 ib_link_width_capability[0x10];
8014 u8 ib_proto_capability[0x10];
8016 u8 ext_eth_proto_admin[0x20];
8018 u8 eth_proto_admin[0x20];
8020 u8 ib_link_width_admin[0x10];
8021 u8 ib_proto_admin[0x10];
8023 u8 ext_eth_proto_oper[0x20];
8025 u8 eth_proto_oper[0x20];
8027 u8 ib_link_width_oper[0x10];
8028 u8 ib_proto_oper[0x10];
8030 u8 reserved_at_160[0x1c];
8031 u8 connector_type[0x4];
8033 u8 eth_proto_lp_advertise[0x20];
8035 u8 reserved_at_1a0[0x60];
8038 struct mlx5_ifc_mlcr_reg_bits {
8039 u8 reserved_at_0[0x8];
8041 u8 reserved_at_10[0x20];
8043 u8 beacon_duration[0x10];
8044 u8 reserved_at_40[0x10];
8046 u8 beacon_remain[0x10];
8049 struct mlx5_ifc_ptas_reg_bits {
8050 u8 reserved_at_0[0x20];
8052 u8 algorithm_options[0x10];
8053 u8 reserved_at_30[0x4];
8054 u8 repetitions_mode[0x4];
8055 u8 num_of_repetitions[0x8];
8057 u8 grade_version[0x8];
8058 u8 height_grade_type[0x4];
8059 u8 phase_grade_type[0x4];
8060 u8 height_grade_weight[0x8];
8061 u8 phase_grade_weight[0x8];
8063 u8 gisim_measure_bits[0x10];
8064 u8 adaptive_tap_measure_bits[0x10];
8066 u8 ber_bath_high_error_threshold[0x10];
8067 u8 ber_bath_mid_error_threshold[0x10];
8069 u8 ber_bath_low_error_threshold[0x10];
8070 u8 one_ratio_high_threshold[0x10];
8072 u8 one_ratio_high_mid_threshold[0x10];
8073 u8 one_ratio_low_mid_threshold[0x10];
8075 u8 one_ratio_low_threshold[0x10];
8076 u8 ndeo_error_threshold[0x10];
8078 u8 mixer_offset_step_size[0x10];
8079 u8 reserved_at_110[0x8];
8080 u8 mix90_phase_for_voltage_bath[0x8];
8082 u8 mixer_offset_start[0x10];
8083 u8 mixer_offset_end[0x10];
8085 u8 reserved_at_140[0x15];
8086 u8 ber_test_time[0xb];
8089 struct mlx5_ifc_pspa_reg_bits {
8093 u8 reserved_at_18[0x8];
8095 u8 reserved_at_20[0x20];
8098 struct mlx5_ifc_pqdr_reg_bits {
8099 u8 reserved_at_0[0x8];
8101 u8 reserved_at_10[0x5];
8103 u8 reserved_at_18[0x6];
8106 u8 reserved_at_20[0x20];
8108 u8 reserved_at_40[0x10];
8109 u8 min_threshold[0x10];
8111 u8 reserved_at_60[0x10];
8112 u8 max_threshold[0x10];
8114 u8 reserved_at_80[0x10];
8115 u8 mark_probability_denominator[0x10];
8117 u8 reserved_at_a0[0x60];
8120 struct mlx5_ifc_ppsc_reg_bits {
8121 u8 reserved_at_0[0x8];
8123 u8 reserved_at_10[0x10];
8125 u8 reserved_at_20[0x60];
8127 u8 reserved_at_80[0x1c];
8130 u8 reserved_at_a0[0x1c];
8131 u8 wrps_status[0x4];
8133 u8 reserved_at_c0[0x8];
8134 u8 up_threshold[0x8];
8135 u8 reserved_at_d0[0x8];
8136 u8 down_threshold[0x8];
8138 u8 reserved_at_e0[0x20];
8140 u8 reserved_at_100[0x1c];
8143 u8 reserved_at_120[0x1c];
8144 u8 srps_status[0x4];
8146 u8 reserved_at_140[0x40];
8149 struct mlx5_ifc_pplr_reg_bits {
8150 u8 reserved_at_0[0x8];
8152 u8 reserved_at_10[0x10];
8154 u8 reserved_at_20[0x8];
8156 u8 reserved_at_30[0x8];
8160 struct mlx5_ifc_pplm_reg_bits {
8161 u8 reserved_at_0[0x8];
8163 u8 reserved_at_10[0x10];
8165 u8 reserved_at_20[0x20];
8167 u8 port_profile_mode[0x8];
8168 u8 static_port_profile[0x8];
8169 u8 active_port_profile[0x8];
8170 u8 reserved_at_58[0x8];
8172 u8 retransmission_active[0x8];
8173 u8 fec_mode_active[0x18];
8175 u8 rs_fec_correction_bypass_cap[0x4];
8176 u8 reserved_at_84[0x8];
8177 u8 fec_override_cap_56g[0x4];
8178 u8 fec_override_cap_100g[0x4];
8179 u8 fec_override_cap_50g[0x4];
8180 u8 fec_override_cap_25g[0x4];
8181 u8 fec_override_cap_10g_40g[0x4];
8183 u8 rs_fec_correction_bypass_admin[0x4];
8184 u8 reserved_at_a4[0x8];
8185 u8 fec_override_admin_56g[0x4];
8186 u8 fec_override_admin_100g[0x4];
8187 u8 fec_override_admin_50g[0x4];
8188 u8 fec_override_admin_25g[0x4];
8189 u8 fec_override_admin_10g_40g[0x4];
8192 struct mlx5_ifc_ppcnt_reg_bits {
8196 u8 reserved_at_12[0x8];
8200 u8 reserved_at_21[0x1c];
8203 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8206 struct mlx5_ifc_mpein_reg_bits {
8207 u8 reserved_at_0[0x2];
8211 u8 reserved_at_18[0x8];
8213 u8 capability_mask[0x20];
8215 u8 reserved_at_40[0x8];
8216 u8 link_width_enabled[0x8];
8217 u8 link_speed_enabled[0x10];
8219 u8 lane0_physical_position[0x8];
8220 u8 link_width_active[0x8];
8221 u8 link_speed_active[0x10];
8223 u8 num_of_pfs[0x10];
8224 u8 num_of_vfs[0x10];
8227 u8 reserved_at_b0[0x10];
8229 u8 max_read_request_size[0x4];
8230 u8 max_payload_size[0x4];
8231 u8 reserved_at_c8[0x5];
8234 u8 reserved_at_d4[0xb];
8235 u8 lane_reversal[0x1];
8237 u8 reserved_at_e0[0x14];
8240 u8 reserved_at_100[0x20];
8242 u8 device_status[0x10];
8244 u8 reserved_at_138[0x8];
8246 u8 reserved_at_140[0x10];
8247 u8 receiver_detect_result[0x10];
8249 u8 reserved_at_160[0x20];
8252 struct mlx5_ifc_mpcnt_reg_bits {
8253 u8 reserved_at_0[0x8];
8255 u8 reserved_at_10[0xa];
8259 u8 reserved_at_21[0x1f];
8261 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8264 struct mlx5_ifc_ppad_reg_bits {
8265 u8 reserved_at_0[0x3];
8267 u8 reserved_at_4[0x4];
8273 u8 reserved_at_40[0x40];
8276 struct mlx5_ifc_pmtu_reg_bits {
8277 u8 reserved_at_0[0x8];
8279 u8 reserved_at_10[0x10];
8282 u8 reserved_at_30[0x10];
8285 u8 reserved_at_50[0x10];
8288 u8 reserved_at_70[0x10];
8291 struct mlx5_ifc_pmpr_reg_bits {
8292 u8 reserved_at_0[0x8];
8294 u8 reserved_at_10[0x10];
8296 u8 reserved_at_20[0x18];
8297 u8 attenuation_5g[0x8];
8299 u8 reserved_at_40[0x18];
8300 u8 attenuation_7g[0x8];
8302 u8 reserved_at_60[0x18];
8303 u8 attenuation_12g[0x8];
8306 struct mlx5_ifc_pmpe_reg_bits {
8307 u8 reserved_at_0[0x8];
8309 u8 reserved_at_10[0xc];
8310 u8 module_status[0x4];
8312 u8 reserved_at_20[0x60];
8315 struct mlx5_ifc_pmpc_reg_bits {
8316 u8 module_state_updated[32][0x8];
8319 struct mlx5_ifc_pmlpn_reg_bits {
8320 u8 reserved_at_0[0x4];
8321 u8 mlpn_status[0x4];
8323 u8 reserved_at_10[0x10];
8326 u8 reserved_at_21[0x1f];
8329 struct mlx5_ifc_pmlp_reg_bits {
8331 u8 reserved_at_1[0x7];
8333 u8 reserved_at_10[0x8];
8336 u8 lane0_module_mapping[0x20];
8338 u8 lane1_module_mapping[0x20];
8340 u8 lane2_module_mapping[0x20];
8342 u8 lane3_module_mapping[0x20];
8344 u8 reserved_at_a0[0x160];
8347 struct mlx5_ifc_pmaos_reg_bits {
8348 u8 reserved_at_0[0x8];
8350 u8 reserved_at_10[0x4];
8351 u8 admin_status[0x4];
8352 u8 reserved_at_18[0x4];
8353 u8 oper_status[0x4];
8357 u8 reserved_at_22[0x1c];
8360 u8 reserved_at_40[0x40];
8363 struct mlx5_ifc_plpc_reg_bits {
8364 u8 reserved_at_0[0x4];
8366 u8 reserved_at_10[0x4];
8368 u8 reserved_at_18[0x8];
8370 u8 reserved_at_20[0x10];
8371 u8 lane_speed[0x10];
8373 u8 reserved_at_40[0x17];
8375 u8 fec_mode_policy[0x8];
8377 u8 retransmission_capability[0x8];
8378 u8 fec_mode_capability[0x18];
8380 u8 retransmission_support_admin[0x8];
8381 u8 fec_mode_support_admin[0x18];
8383 u8 retransmission_request_admin[0x8];
8384 u8 fec_mode_request_admin[0x18];
8386 u8 reserved_at_c0[0x80];
8389 struct mlx5_ifc_plib_reg_bits {
8390 u8 reserved_at_0[0x8];
8392 u8 reserved_at_10[0x8];
8395 u8 reserved_at_20[0x60];
8398 struct mlx5_ifc_plbf_reg_bits {
8399 u8 reserved_at_0[0x8];
8401 u8 reserved_at_10[0xd];
8404 u8 reserved_at_20[0x20];
8407 struct mlx5_ifc_pipg_reg_bits {
8408 u8 reserved_at_0[0x8];
8410 u8 reserved_at_10[0x10];
8413 u8 reserved_at_21[0x19];
8415 u8 reserved_at_3e[0x2];
8418 struct mlx5_ifc_pifr_reg_bits {
8419 u8 reserved_at_0[0x8];
8421 u8 reserved_at_10[0x10];
8423 u8 reserved_at_20[0xe0];
8425 u8 port_filter[8][0x20];
8427 u8 port_filter_update_en[8][0x20];
8430 struct mlx5_ifc_pfcc_reg_bits {
8431 u8 reserved_at_0[0x8];
8433 u8 reserved_at_10[0xb];
8434 u8 ppan_mask_n[0x1];
8435 u8 minor_stall_mask[0x1];
8436 u8 critical_stall_mask[0x1];
8437 u8 reserved_at_1e[0x2];
8440 u8 reserved_at_24[0x4];
8441 u8 prio_mask_tx[0x8];
8442 u8 reserved_at_30[0x8];
8443 u8 prio_mask_rx[0x8];
8447 u8 pptx_mask_n[0x1];
8448 u8 reserved_at_43[0x5];
8450 u8 reserved_at_50[0x10];
8454 u8 pprx_mask_n[0x1];
8455 u8 reserved_at_63[0x5];
8457 u8 reserved_at_70[0x10];
8459 u8 device_stall_minor_watermark[0x10];
8460 u8 device_stall_critical_watermark[0x10];
8462 u8 reserved_at_a0[0x60];
8465 struct mlx5_ifc_pelc_reg_bits {
8467 u8 reserved_at_4[0x4];
8469 u8 reserved_at_10[0x10];
8472 u8 op_capability[0x8];
8478 u8 capability[0x40];
8484 u8 reserved_at_140[0x80];
8487 struct mlx5_ifc_peir_reg_bits {
8488 u8 reserved_at_0[0x8];
8490 u8 reserved_at_10[0x10];
8492 u8 reserved_at_20[0xc];
8493 u8 error_count[0x4];
8494 u8 reserved_at_30[0x10];
8496 u8 reserved_at_40[0xc];
8498 u8 reserved_at_50[0x8];
8502 struct mlx5_ifc_mpegc_reg_bits {
8503 u8 reserved_at_0[0x30];
8504 u8 field_select[0x10];
8506 u8 tx_overflow_sense[0x1];
8509 u8 reserved_at_43[0x1b];
8510 u8 tx_lossy_overflow_oper[0x2];
8512 u8 reserved_at_60[0x100];
8515 struct mlx5_ifc_pcam_enhanced_features_bits {
8516 u8 reserved_at_0[0x6d];
8517 u8 rx_icrc_encapsulated_counter[0x1];
8518 u8 reserved_at_6e[0x4];
8519 u8 ptys_extended_ethernet[0x1];
8520 u8 reserved_at_73[0x3];
8522 u8 reserved_at_77[0x3];
8523 u8 per_lane_error_counters[0x1];
8524 u8 rx_buffer_fullness_counters[0x1];
8525 u8 ptys_connector_type[0x1];
8526 u8 reserved_at_7d[0x1];
8527 u8 ppcnt_discard_group[0x1];
8528 u8 ppcnt_statistical_group[0x1];
8531 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8532 u8 port_access_reg_cap_mask_127_to_96[0x20];
8533 u8 port_access_reg_cap_mask_95_to_64[0x20];
8535 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8537 u8 port_access_reg_cap_mask_34_to_32[0x3];
8539 u8 port_access_reg_cap_mask_31_to_13[0x13];
8542 u8 port_access_reg_cap_mask_10_to_09[0x2];
8544 u8 port_access_reg_cap_mask_07_to_00[0x8];
8547 struct mlx5_ifc_pcam_reg_bits {
8548 u8 reserved_at_0[0x8];
8549 u8 feature_group[0x8];
8550 u8 reserved_at_10[0x8];
8551 u8 access_reg_group[0x8];
8553 u8 reserved_at_20[0x20];
8556 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8557 u8 reserved_at_0[0x80];
8558 } port_access_reg_cap_mask;
8560 u8 reserved_at_c0[0x80];
8563 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8564 u8 reserved_at_0[0x80];
8567 u8 reserved_at_1c0[0xc0];
8570 struct mlx5_ifc_mcam_enhanced_features_bits {
8571 u8 reserved_at_0[0x6e];
8572 u8 pci_status_and_power[0x1];
8573 u8 reserved_at_6f[0x5];
8574 u8 mark_tx_action_cnp[0x1];
8575 u8 mark_tx_action_cqe[0x1];
8576 u8 dynamic_tx_overflow[0x1];
8577 u8 reserved_at_77[0x4];
8578 u8 pcie_outbound_stalled[0x1];
8579 u8 tx_overflow_buffer_pkt[0x1];
8580 u8 mtpps_enh_out_per_adj[0x1];
8582 u8 pcie_performance_group[0x1];
8585 struct mlx5_ifc_mcam_access_reg_bits {
8586 u8 reserved_at_0[0x1c];
8592 u8 regs_95_to_87[0x9];
8594 u8 regs_85_to_68[0x12];
8595 u8 tracer_registers[0x4];
8597 u8 regs_63_to_32[0x20];
8598 u8 regs_31_to_0[0x20];
8601 struct mlx5_ifc_mcam_reg_bits {
8602 u8 reserved_at_0[0x8];
8603 u8 feature_group[0x8];
8604 u8 reserved_at_10[0x8];
8605 u8 access_reg_group[0x8];
8607 u8 reserved_at_20[0x20];
8610 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8611 u8 reserved_at_0[0x80];
8612 } mng_access_reg_cap_mask;
8614 u8 reserved_at_c0[0x80];
8617 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8618 u8 reserved_at_0[0x80];
8619 } mng_feature_cap_mask;
8621 u8 reserved_at_1c0[0x80];
8624 struct mlx5_ifc_qcam_access_reg_cap_mask {
8625 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
8627 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
8631 u8 qcam_access_reg_cap_mask_0[0x1];
8634 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8635 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
8636 u8 qpts_trust_both[0x1];
8639 struct mlx5_ifc_qcam_reg_bits {
8640 u8 reserved_at_0[0x8];
8641 u8 feature_group[0x8];
8642 u8 reserved_at_10[0x8];
8643 u8 access_reg_group[0x8];
8644 u8 reserved_at_20[0x20];
8647 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8648 u8 reserved_at_0[0x80];
8649 } qos_access_reg_cap_mask;
8651 u8 reserved_at_c0[0x80];
8654 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8655 u8 reserved_at_0[0x80];
8656 } qos_feature_cap_mask;
8658 u8 reserved_at_1c0[0x80];
8661 struct mlx5_ifc_core_dump_reg_bits {
8662 u8 reserved_at_0[0x18];
8663 u8 core_dump_type[0x8];
8665 u8 reserved_at_20[0x30];
8668 u8 reserved_at_60[0x8];
8670 u8 reserved_at_80[0x180];
8673 struct mlx5_ifc_pcap_reg_bits {
8674 u8 reserved_at_0[0x8];
8676 u8 reserved_at_10[0x10];
8678 u8 port_capability_mask[4][0x20];
8681 struct mlx5_ifc_paos_reg_bits {
8684 u8 reserved_at_10[0x4];
8685 u8 admin_status[0x4];
8686 u8 reserved_at_18[0x4];
8687 u8 oper_status[0x4];
8691 u8 reserved_at_22[0x1c];
8694 u8 reserved_at_40[0x40];
8697 struct mlx5_ifc_pamp_reg_bits {
8698 u8 reserved_at_0[0x8];
8699 u8 opamp_group[0x8];
8700 u8 reserved_at_10[0xc];
8701 u8 opamp_group_type[0x4];
8703 u8 start_index[0x10];
8704 u8 reserved_at_30[0x4];
8705 u8 num_of_indices[0xc];
8707 u8 index_data[18][0x10];
8710 struct mlx5_ifc_pcmr_reg_bits {
8711 u8 reserved_at_0[0x8];
8713 u8 reserved_at_10[0x10];
8714 u8 entropy_force_cap[0x1];
8715 u8 entropy_calc_cap[0x1];
8716 u8 entropy_gre_calc_cap[0x1];
8717 u8 reserved_at_23[0x1b];
8719 u8 reserved_at_3f[0x1];
8720 u8 entropy_force[0x1];
8721 u8 entropy_calc[0x1];
8722 u8 entropy_gre_calc[0x1];
8723 u8 reserved_at_43[0x1b];
8725 u8 reserved_at_5f[0x1];
8728 struct mlx5_ifc_lane_2_module_mapping_bits {
8729 u8 reserved_at_0[0x6];
8731 u8 reserved_at_8[0x6];
8733 u8 reserved_at_10[0x8];
8737 struct mlx5_ifc_bufferx_reg_bits {
8738 u8 reserved_at_0[0x6];
8741 u8 reserved_at_8[0xc];
8744 u8 xoff_threshold[0x10];
8745 u8 xon_threshold[0x10];
8748 struct mlx5_ifc_set_node_in_bits {
8749 u8 node_description[64][0x8];
8752 struct mlx5_ifc_register_power_settings_bits {
8753 u8 reserved_at_0[0x18];
8754 u8 power_settings_level[0x8];
8756 u8 reserved_at_20[0x60];
8759 struct mlx5_ifc_register_host_endianness_bits {
8761 u8 reserved_at_1[0x1f];
8763 u8 reserved_at_20[0x60];
8766 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8767 u8 reserved_at_0[0x20];
8771 u8 addressh_63_32[0x20];
8773 u8 addressl_31_0[0x20];
8776 struct mlx5_ifc_ud_adrs_vector_bits {
8780 u8 reserved_at_41[0x7];
8781 u8 destination_qp_dct[0x18];
8783 u8 static_rate[0x4];
8784 u8 sl_eth_prio[0x4];
8787 u8 rlid_udp_sport[0x10];
8789 u8 reserved_at_80[0x20];
8791 u8 rmac_47_16[0x20];
8797 u8 reserved_at_e0[0x1];
8799 u8 reserved_at_e2[0x2];
8800 u8 src_addr_index[0x8];
8801 u8 flow_label[0x14];
8803 u8 rgid_rip[16][0x8];
8806 struct mlx5_ifc_pages_req_event_bits {
8807 u8 reserved_at_0[0x10];
8808 u8 function_id[0x10];
8812 u8 reserved_at_40[0xa0];
8815 struct mlx5_ifc_eqe_bits {
8816 u8 reserved_at_0[0x8];
8818 u8 reserved_at_10[0x8];
8819 u8 event_sub_type[0x8];
8821 u8 reserved_at_20[0xe0];
8823 union mlx5_ifc_event_auto_bits event_data;
8825 u8 reserved_at_1e0[0x10];
8827 u8 reserved_at_1f8[0x7];
8832 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8835 struct mlx5_ifc_cmd_queue_entry_bits {
8837 u8 reserved_at_8[0x18];
8839 u8 input_length[0x20];
8841 u8 input_mailbox_pointer_63_32[0x20];
8843 u8 input_mailbox_pointer_31_9[0x17];
8844 u8 reserved_at_77[0x9];
8846 u8 command_input_inline_data[16][0x8];
8848 u8 command_output_inline_data[16][0x8];
8850 u8 output_mailbox_pointer_63_32[0x20];
8852 u8 output_mailbox_pointer_31_9[0x17];
8853 u8 reserved_at_1b7[0x9];
8855 u8 output_length[0x20];
8859 u8 reserved_at_1f0[0x8];
8864 struct mlx5_ifc_cmd_out_bits {
8866 u8 reserved_at_8[0x18];
8870 u8 command_output[0x20];
8873 struct mlx5_ifc_cmd_in_bits {
8875 u8 reserved_at_10[0x10];
8877 u8 reserved_at_20[0x10];
8880 u8 command[0][0x20];
8883 struct mlx5_ifc_cmd_if_box_bits {
8884 u8 mailbox_data[512][0x8];
8886 u8 reserved_at_1000[0x180];
8888 u8 next_pointer_63_32[0x20];
8890 u8 next_pointer_31_10[0x16];
8891 u8 reserved_at_11b6[0xa];
8893 u8 block_number[0x20];
8895 u8 reserved_at_11e0[0x8];
8897 u8 ctrl_signature[0x8];
8901 struct mlx5_ifc_mtt_bits {
8902 u8 ptag_63_32[0x20];
8905 u8 reserved_at_38[0x6];
8910 struct mlx5_ifc_query_wol_rol_out_bits {
8912 u8 reserved_at_8[0x18];
8916 u8 reserved_at_40[0x10];
8920 u8 reserved_at_60[0x20];
8923 struct mlx5_ifc_query_wol_rol_in_bits {
8925 u8 reserved_at_10[0x10];
8927 u8 reserved_at_20[0x10];
8930 u8 reserved_at_40[0x40];
8933 struct mlx5_ifc_set_wol_rol_out_bits {
8935 u8 reserved_at_8[0x18];
8939 u8 reserved_at_40[0x40];
8942 struct mlx5_ifc_set_wol_rol_in_bits {
8944 u8 reserved_at_10[0x10];
8946 u8 reserved_at_20[0x10];
8949 u8 rol_mode_valid[0x1];
8950 u8 wol_mode_valid[0x1];
8951 u8 reserved_at_42[0xe];
8955 u8 reserved_at_60[0x20];
8959 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8960 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8961 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8965 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8966 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8967 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8971 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8972 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8973 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8974 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8975 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8976 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8977 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8978 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8979 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8980 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8981 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8984 struct mlx5_ifc_initial_seg_bits {
8985 u8 fw_rev_minor[0x10];
8986 u8 fw_rev_major[0x10];
8988 u8 cmd_interface_rev[0x10];
8989 u8 fw_rev_subminor[0x10];
8991 u8 reserved_at_40[0x40];
8993 u8 cmdq_phy_addr_63_32[0x20];
8995 u8 cmdq_phy_addr_31_12[0x14];
8996 u8 reserved_at_b4[0x2];
8997 u8 nic_interface[0x2];
8998 u8 log_cmdq_size[0x4];
8999 u8 log_cmdq_stride[0x4];
9001 u8 command_doorbell_vector[0x20];
9003 u8 reserved_at_e0[0xf00];
9005 u8 initializing[0x1];
9006 u8 reserved_at_fe1[0x4];
9007 u8 nic_interface_supported[0x3];
9008 u8 embedded_cpu[0x1];
9009 u8 reserved_at_fe9[0x17];
9011 struct mlx5_ifc_health_buffer_bits health_buffer;
9013 u8 no_dram_nic_offset[0x20];
9015 u8 reserved_at_1220[0x6e40];
9017 u8 reserved_at_8060[0x1f];
9020 u8 health_syndrome[0x8];
9021 u8 health_counter[0x18];
9023 u8 reserved_at_80a0[0x17fc0];
9026 struct mlx5_ifc_mtpps_reg_bits {
9027 u8 reserved_at_0[0xc];
9028 u8 cap_number_of_pps_pins[0x4];
9029 u8 reserved_at_10[0x4];
9030 u8 cap_max_num_of_pps_in_pins[0x4];
9031 u8 reserved_at_18[0x4];
9032 u8 cap_max_num_of_pps_out_pins[0x4];
9034 u8 reserved_at_20[0x24];
9035 u8 cap_pin_3_mode[0x4];
9036 u8 reserved_at_48[0x4];
9037 u8 cap_pin_2_mode[0x4];
9038 u8 reserved_at_50[0x4];
9039 u8 cap_pin_1_mode[0x4];
9040 u8 reserved_at_58[0x4];
9041 u8 cap_pin_0_mode[0x4];
9043 u8 reserved_at_60[0x4];
9044 u8 cap_pin_7_mode[0x4];
9045 u8 reserved_at_68[0x4];
9046 u8 cap_pin_6_mode[0x4];
9047 u8 reserved_at_70[0x4];
9048 u8 cap_pin_5_mode[0x4];
9049 u8 reserved_at_78[0x4];
9050 u8 cap_pin_4_mode[0x4];
9052 u8 field_select[0x20];
9053 u8 reserved_at_a0[0x60];
9056 u8 reserved_at_101[0xb];
9058 u8 reserved_at_110[0x4];
9062 u8 reserved_at_120[0x20];
9064 u8 time_stamp[0x40];
9066 u8 out_pulse_duration[0x10];
9067 u8 out_periodic_adjustment[0x10];
9068 u8 enhanced_out_periodic_adjustment[0x20];
9070 u8 reserved_at_1c0[0x20];
9073 struct mlx5_ifc_mtppse_reg_bits {
9074 u8 reserved_at_0[0x18];
9077 u8 reserved_at_21[0x1b];
9078 u8 event_generation_mode[0x4];
9079 u8 reserved_at_40[0x40];
9082 struct mlx5_ifc_mcqs_reg_bits {
9083 u8 last_index_flag[0x1];
9084 u8 reserved_at_1[0x7];
9086 u8 component_index[0x10];
9088 u8 reserved_at_20[0x10];
9089 u8 identifier[0x10];
9091 u8 reserved_at_40[0x17];
9092 u8 component_status[0x5];
9093 u8 component_update_state[0x4];
9095 u8 last_update_state_changer_type[0x4];
9096 u8 last_update_state_changer_host_id[0x4];
9097 u8 reserved_at_68[0x18];
9100 struct mlx5_ifc_mcqi_cap_bits {
9101 u8 supported_info_bitmask[0x20];
9103 u8 component_size[0x20];
9105 u8 max_component_size[0x20];
9107 u8 log_mcda_word_size[0x4];
9108 u8 reserved_at_64[0xc];
9109 u8 mcda_max_write_size[0x10];
9112 u8 reserved_at_81[0x1];
9113 u8 match_chip_id[0x1];
9115 u8 check_user_timestamp[0x1];
9116 u8 match_base_guid_mac[0x1];
9117 u8 reserved_at_86[0x1a];
9120 struct mlx5_ifc_mcqi_version_bits {
9121 u8 reserved_at_0[0x2];
9122 u8 build_time_valid[0x1];
9123 u8 user_defined_time_valid[0x1];
9124 u8 reserved_at_4[0x14];
9125 u8 version_string_length[0x8];
9129 u8 build_time[0x40];
9131 u8 user_defined_time[0x40];
9133 u8 build_tool_version[0x20];
9135 u8 reserved_at_e0[0x20];
9137 u8 version_string[92][0x8];
9140 struct mlx5_ifc_mcqi_activation_method_bits {
9141 u8 pending_server_ac_power_cycle[0x1];
9142 u8 pending_server_dc_power_cycle[0x1];
9143 u8 pending_server_reboot[0x1];
9144 u8 pending_fw_reset[0x1];
9145 u8 auto_activate[0x1];
9146 u8 all_hosts_sync[0x1];
9147 u8 device_hw_reset[0x1];
9148 u8 reserved_at_7[0x19];
9151 union mlx5_ifc_mcqi_reg_data_bits {
9152 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9153 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9154 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9157 struct mlx5_ifc_mcqi_reg_bits {
9158 u8 read_pending_component[0x1];
9159 u8 reserved_at_1[0xf];
9160 u8 component_index[0x10];
9162 u8 reserved_at_20[0x20];
9164 u8 reserved_at_40[0x1b];
9171 u8 reserved_at_a0[0x10];
9174 union mlx5_ifc_mcqi_reg_data_bits data[0];
9177 struct mlx5_ifc_mcc_reg_bits {
9178 u8 reserved_at_0[0x4];
9179 u8 time_elapsed_since_last_cmd[0xc];
9180 u8 reserved_at_10[0x8];
9181 u8 instruction[0x8];
9183 u8 reserved_at_20[0x10];
9184 u8 component_index[0x10];
9186 u8 reserved_at_40[0x8];
9187 u8 update_handle[0x18];
9189 u8 handle_owner_type[0x4];
9190 u8 handle_owner_host_id[0x4];
9191 u8 reserved_at_68[0x1];
9192 u8 control_progress[0x7];
9194 u8 reserved_at_78[0x4];
9195 u8 control_state[0x4];
9197 u8 component_size[0x20];
9199 u8 reserved_at_a0[0x60];
9202 struct mlx5_ifc_mcda_reg_bits {
9203 u8 reserved_at_0[0x8];
9204 u8 update_handle[0x18];
9208 u8 reserved_at_40[0x10];
9211 u8 reserved_at_60[0x20];
9216 union mlx5_ifc_ports_control_registers_document_bits {
9217 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9218 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9219 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9220 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9221 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9222 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9223 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9224 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9225 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9226 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9227 struct mlx5_ifc_paos_reg_bits paos_reg;
9228 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9229 struct mlx5_ifc_peir_reg_bits peir_reg;
9230 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9231 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9232 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9233 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9234 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9235 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9236 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9237 struct mlx5_ifc_plib_reg_bits plib_reg;
9238 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9239 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9240 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9241 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9242 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9243 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9244 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9245 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9246 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9247 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9248 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9249 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9250 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9251 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9252 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9253 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9254 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9255 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9256 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9257 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9258 struct mlx5_ifc_pude_reg_bits pude_reg;
9259 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9260 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9261 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9262 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9263 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9264 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9265 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9266 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9267 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9268 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9269 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9270 u8 reserved_at_0[0x60e0];
9273 union mlx5_ifc_debug_enhancements_document_bits {
9274 struct mlx5_ifc_health_buffer_bits health_buffer;
9275 u8 reserved_at_0[0x200];
9278 union mlx5_ifc_uplink_pci_interface_document_bits {
9279 struct mlx5_ifc_initial_seg_bits initial_seg;
9280 u8 reserved_at_0[0x20060];
9283 struct mlx5_ifc_set_flow_table_root_out_bits {
9285 u8 reserved_at_8[0x18];
9289 u8 reserved_at_40[0x40];
9292 struct mlx5_ifc_set_flow_table_root_in_bits {
9294 u8 reserved_at_10[0x10];
9296 u8 reserved_at_20[0x10];
9299 u8 other_vport[0x1];
9300 u8 reserved_at_41[0xf];
9301 u8 vport_number[0x10];
9303 u8 reserved_at_60[0x20];
9306 u8 reserved_at_88[0x18];
9308 u8 reserved_at_a0[0x8];
9311 u8 reserved_at_c0[0x8];
9312 u8 underlay_qpn[0x18];
9313 u8 reserved_at_e0[0x120];
9317 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9318 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9321 struct mlx5_ifc_modify_flow_table_out_bits {
9323 u8 reserved_at_8[0x18];
9327 u8 reserved_at_40[0x40];
9330 struct mlx5_ifc_modify_flow_table_in_bits {
9332 u8 reserved_at_10[0x10];
9334 u8 reserved_at_20[0x10];
9337 u8 other_vport[0x1];
9338 u8 reserved_at_41[0xf];
9339 u8 vport_number[0x10];
9341 u8 reserved_at_60[0x10];
9342 u8 modify_field_select[0x10];
9345 u8 reserved_at_88[0x18];
9347 u8 reserved_at_a0[0x8];
9350 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9353 struct mlx5_ifc_ets_tcn_config_reg_bits {
9357 u8 reserved_at_3[0x9];
9359 u8 reserved_at_10[0x9];
9360 u8 bw_allocation[0x7];
9362 u8 reserved_at_20[0xc];
9363 u8 max_bw_units[0x4];
9364 u8 reserved_at_30[0x8];
9365 u8 max_bw_value[0x8];
9368 struct mlx5_ifc_ets_global_config_reg_bits {
9369 u8 reserved_at_0[0x2];
9371 u8 reserved_at_3[0x1d];
9373 u8 reserved_at_20[0xc];
9374 u8 max_bw_units[0x4];
9375 u8 reserved_at_30[0x8];
9376 u8 max_bw_value[0x8];
9379 struct mlx5_ifc_qetc_reg_bits {
9380 u8 reserved_at_0[0x8];
9381 u8 port_number[0x8];
9382 u8 reserved_at_10[0x30];
9384 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9385 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9388 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9390 u8 reserved_at_01[0x0b];
9394 struct mlx5_ifc_qpdpm_reg_bits {
9395 u8 reserved_at_0[0x8];
9397 u8 reserved_at_10[0x10];
9398 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9401 struct mlx5_ifc_qpts_reg_bits {
9402 u8 reserved_at_0[0x8];
9404 u8 reserved_at_10[0x2d];
9405 u8 trust_state[0x3];
9408 struct mlx5_ifc_pptb_reg_bits {
9409 u8 reserved_at_0[0x2];
9411 u8 reserved_at_4[0x4];
9413 u8 reserved_at_10[0x6];
9418 u8 prio_x_buff[0x20];
9421 u8 reserved_at_48[0x10];
9423 u8 untagged_buff[0x4];
9426 struct mlx5_ifc_pbmc_reg_bits {
9427 u8 reserved_at_0[0x8];
9429 u8 reserved_at_10[0x10];
9431 u8 xoff_timer_value[0x10];
9432 u8 xoff_refresh[0x10];
9434 u8 reserved_at_40[0x9];
9435 u8 fullness_threshold[0x7];
9436 u8 port_buffer_size[0x10];
9438 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9440 u8 reserved_at_2e0[0x40];
9443 struct mlx5_ifc_qtct_reg_bits {
9444 u8 reserved_at_0[0x8];
9445 u8 port_number[0x8];
9446 u8 reserved_at_10[0xd];
9449 u8 reserved_at_20[0x1d];
9453 struct mlx5_ifc_mcia_reg_bits {
9455 u8 reserved_at_1[0x7];
9457 u8 reserved_at_10[0x8];
9460 u8 i2c_device_address[0x8];
9461 u8 page_number[0x8];
9462 u8 device_address[0x10];
9464 u8 reserved_at_40[0x10];
9467 u8 reserved_at_60[0x20];
9483 struct mlx5_ifc_dcbx_param_bits {
9484 u8 dcbx_cee_cap[0x1];
9485 u8 dcbx_ieee_cap[0x1];
9486 u8 dcbx_standby_cap[0x1];
9487 u8 reserved_at_3[0x5];
9488 u8 port_number[0x8];
9489 u8 reserved_at_10[0xa];
9490 u8 max_application_table_size[6];
9491 u8 reserved_at_20[0x15];
9492 u8 version_oper[0x3];
9493 u8 reserved_at_38[5];
9494 u8 version_admin[0x3];
9495 u8 willing_admin[0x1];
9496 u8 reserved_at_41[0x3];
9497 u8 pfc_cap_oper[0x4];
9498 u8 reserved_at_48[0x4];
9499 u8 pfc_cap_admin[0x4];
9500 u8 reserved_at_50[0x4];
9501 u8 num_of_tc_oper[0x4];
9502 u8 reserved_at_58[0x4];
9503 u8 num_of_tc_admin[0x4];
9504 u8 remote_willing[0x1];
9505 u8 reserved_at_61[3];
9506 u8 remote_pfc_cap[4];
9507 u8 reserved_at_68[0x14];
9508 u8 remote_num_of_tc[0x4];
9509 u8 reserved_at_80[0x18];
9511 u8 reserved_at_a0[0x160];
9514 struct mlx5_ifc_lagc_bits {
9515 u8 reserved_at_0[0x1d];
9518 u8 reserved_at_20[0x14];
9519 u8 tx_remap_affinity_2[0x4];
9520 u8 reserved_at_38[0x4];
9521 u8 tx_remap_affinity_1[0x4];
9524 struct mlx5_ifc_create_lag_out_bits {
9526 u8 reserved_at_8[0x18];
9530 u8 reserved_at_40[0x40];
9533 struct mlx5_ifc_create_lag_in_bits {
9535 u8 reserved_at_10[0x10];
9537 u8 reserved_at_20[0x10];
9540 struct mlx5_ifc_lagc_bits ctx;
9543 struct mlx5_ifc_modify_lag_out_bits {
9545 u8 reserved_at_8[0x18];
9549 u8 reserved_at_40[0x40];
9552 struct mlx5_ifc_modify_lag_in_bits {
9554 u8 reserved_at_10[0x10];
9556 u8 reserved_at_20[0x10];
9559 u8 reserved_at_40[0x20];
9560 u8 field_select[0x20];
9562 struct mlx5_ifc_lagc_bits ctx;
9565 struct mlx5_ifc_query_lag_out_bits {
9567 u8 reserved_at_8[0x18];
9571 u8 reserved_at_40[0x40];
9573 struct mlx5_ifc_lagc_bits ctx;
9576 struct mlx5_ifc_query_lag_in_bits {
9578 u8 reserved_at_10[0x10];
9580 u8 reserved_at_20[0x10];
9583 u8 reserved_at_40[0x40];
9586 struct mlx5_ifc_destroy_lag_out_bits {
9588 u8 reserved_at_8[0x18];
9592 u8 reserved_at_40[0x40];
9595 struct mlx5_ifc_destroy_lag_in_bits {
9597 u8 reserved_at_10[0x10];
9599 u8 reserved_at_20[0x10];
9602 u8 reserved_at_40[0x40];
9605 struct mlx5_ifc_create_vport_lag_out_bits {
9607 u8 reserved_at_8[0x18];
9611 u8 reserved_at_40[0x40];
9614 struct mlx5_ifc_create_vport_lag_in_bits {
9616 u8 reserved_at_10[0x10];
9618 u8 reserved_at_20[0x10];
9621 u8 reserved_at_40[0x40];
9624 struct mlx5_ifc_destroy_vport_lag_out_bits {
9626 u8 reserved_at_8[0x18];
9630 u8 reserved_at_40[0x40];
9633 struct mlx5_ifc_destroy_vport_lag_in_bits {
9635 u8 reserved_at_10[0x10];
9637 u8 reserved_at_20[0x10];
9640 u8 reserved_at_40[0x40];
9643 struct mlx5_ifc_alloc_memic_in_bits {
9645 u8 reserved_at_10[0x10];
9647 u8 reserved_at_20[0x10];
9650 u8 reserved_at_30[0x20];
9652 u8 reserved_at_40[0x18];
9653 u8 log_memic_addr_alignment[0x8];
9655 u8 range_start_addr[0x40];
9657 u8 range_size[0x20];
9659 u8 memic_size[0x20];
9662 struct mlx5_ifc_alloc_memic_out_bits {
9664 u8 reserved_at_8[0x18];
9668 u8 memic_start_addr[0x40];
9671 struct mlx5_ifc_dealloc_memic_in_bits {
9673 u8 reserved_at_10[0x10];
9675 u8 reserved_at_20[0x10];
9678 u8 reserved_at_40[0x40];
9680 u8 memic_start_addr[0x40];
9682 u8 memic_size[0x20];
9684 u8 reserved_at_e0[0x20];
9687 struct mlx5_ifc_dealloc_memic_out_bits {
9689 u8 reserved_at_8[0x18];
9693 u8 reserved_at_40[0x40];
9696 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9700 u8 vhca_tunnel_id[0x10];
9705 u8 reserved_at_60[0x20];
9708 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9710 u8 reserved_at_8[0x18];
9716 u8 reserved_at_60[0x20];
9719 struct mlx5_ifc_umem_bits {
9720 u8 reserved_at_0[0x80];
9722 u8 reserved_at_80[0x1b];
9723 u8 log_page_size[0x5];
9725 u8 page_offset[0x20];
9727 u8 num_of_mtt[0x40];
9729 struct mlx5_ifc_mtt_bits mtt[0];
9732 struct mlx5_ifc_uctx_bits {
9735 u8 reserved_at_20[0x160];
9738 struct mlx5_ifc_sw_icm_bits {
9739 u8 modify_field_select[0x40];
9741 u8 reserved_at_40[0x18];
9742 u8 log_sw_icm_size[0x8];
9744 u8 reserved_at_60[0x20];
9746 u8 sw_icm_start_addr[0x40];
9748 u8 reserved_at_c0[0x140];
9751 struct mlx5_ifc_geneve_tlv_option_bits {
9752 u8 modify_field_select[0x40];
9754 u8 reserved_at_40[0x18];
9755 u8 geneve_option_fte_index[0x8];
9757 u8 option_class[0x10];
9758 u8 option_type[0x8];
9759 u8 reserved_at_78[0x3];
9760 u8 option_data_length[0x5];
9762 u8 reserved_at_80[0x180];
9765 struct mlx5_ifc_create_umem_in_bits {
9769 u8 reserved_at_20[0x10];
9772 u8 reserved_at_40[0x40];
9774 struct mlx5_ifc_umem_bits umem;
9777 struct mlx5_ifc_create_uctx_in_bits {
9779 u8 reserved_at_10[0x10];
9781 u8 reserved_at_20[0x10];
9784 u8 reserved_at_40[0x40];
9786 struct mlx5_ifc_uctx_bits uctx;
9789 struct mlx5_ifc_destroy_uctx_in_bits {
9791 u8 reserved_at_10[0x10];
9793 u8 reserved_at_20[0x10];
9796 u8 reserved_at_40[0x10];
9799 u8 reserved_at_60[0x20];
9802 struct mlx5_ifc_create_sw_icm_in_bits {
9803 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9804 struct mlx5_ifc_sw_icm_bits sw_icm;
9807 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9808 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
9809 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
9812 struct mlx5_ifc_mtrc_string_db_param_bits {
9813 u8 string_db_base_address[0x20];
9815 u8 reserved_at_20[0x8];
9816 u8 string_db_size[0x18];
9819 struct mlx5_ifc_mtrc_cap_bits {
9820 u8 trace_owner[0x1];
9821 u8 trace_to_memory[0x1];
9822 u8 reserved_at_2[0x4];
9824 u8 reserved_at_8[0x14];
9825 u8 num_string_db[0x4];
9827 u8 first_string_trace[0x8];
9828 u8 num_string_trace[0x8];
9829 u8 reserved_at_30[0x28];
9831 u8 log_max_trace_buffer_size[0x8];
9833 u8 reserved_at_60[0x20];
9835 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9837 u8 reserved_at_280[0x180];
9840 struct mlx5_ifc_mtrc_conf_bits {
9841 u8 reserved_at_0[0x1c];
9843 u8 reserved_at_20[0x18];
9844 u8 log_trace_buffer_size[0x8];
9845 u8 trace_mkey[0x20];
9846 u8 reserved_at_60[0x3a0];
9849 struct mlx5_ifc_mtrc_stdb_bits {
9850 u8 string_db_index[0x4];
9851 u8 reserved_at_4[0x4];
9853 u8 start_offset[0x20];
9854 u8 string_db_data[0];
9857 struct mlx5_ifc_mtrc_ctrl_bits {
9858 u8 trace_status[0x2];
9859 u8 reserved_at_2[0x2];
9861 u8 reserved_at_5[0xb];
9862 u8 modify_field_select[0x10];
9863 u8 reserved_at_20[0x2b];
9864 u8 current_timestamp52_32[0x15];
9865 u8 current_timestamp31_0[0x20];
9866 u8 reserved_at_80[0x180];
9869 struct mlx5_ifc_host_params_context_bits {
9870 u8 host_number[0x8];
9871 u8 reserved_at_8[0x7];
9872 u8 host_pf_disabled[0x1];
9873 u8 host_num_of_vfs[0x10];
9875 u8 host_total_vfs[0x10];
9876 u8 host_pci_bus[0x10];
9878 u8 reserved_at_40[0x10];
9879 u8 host_pci_device[0x10];
9881 u8 reserved_at_60[0x10];
9882 u8 host_pci_function[0x10];
9884 u8 reserved_at_80[0x180];
9887 struct mlx5_ifc_query_esw_functions_in_bits {
9889 u8 reserved_at_10[0x10];
9891 u8 reserved_at_20[0x10];
9894 u8 reserved_at_40[0x40];
9897 struct mlx5_ifc_query_esw_functions_out_bits {
9899 u8 reserved_at_8[0x18];
9903 u8 reserved_at_40[0x40];
9905 struct mlx5_ifc_host_params_context_bits host_params_context;
9907 u8 reserved_at_280[0x180];
9908 u8 host_sf_enable[0][0x40];
9911 struct mlx5_ifc_sf_partition_bits {
9912 u8 reserved_at_0[0x10];
9914 u8 log_sf_bar_size[0x8];
9917 struct mlx5_ifc_query_sf_partitions_out_bits {
9919 u8 reserved_at_8[0x18];
9923 u8 reserved_at_40[0x18];
9924 u8 num_sf_partitions[0x8];
9926 u8 reserved_at_60[0x20];
9928 struct mlx5_ifc_sf_partition_bits sf_partition[0];
9931 struct mlx5_ifc_query_sf_partitions_in_bits {
9933 u8 reserved_at_10[0x10];
9935 u8 reserved_at_20[0x10];
9938 u8 reserved_at_40[0x40];
9941 struct mlx5_ifc_dealloc_sf_out_bits {
9943 u8 reserved_at_8[0x18];
9947 u8 reserved_at_40[0x40];
9950 struct mlx5_ifc_dealloc_sf_in_bits {
9952 u8 reserved_at_10[0x10];
9954 u8 reserved_at_20[0x10];
9957 u8 reserved_at_40[0x10];
9958 u8 function_id[0x10];
9960 u8 reserved_at_60[0x20];
9963 struct mlx5_ifc_alloc_sf_out_bits {
9965 u8 reserved_at_8[0x18];
9969 u8 reserved_at_40[0x40];
9972 struct mlx5_ifc_alloc_sf_in_bits {
9974 u8 reserved_at_10[0x10];
9976 u8 reserved_at_20[0x10];
9979 u8 reserved_at_40[0x10];
9980 u8 function_id[0x10];
9982 u8 reserved_at_60[0x20];
9985 struct mlx5_ifc_affiliated_event_header_bits {
9986 u8 reserved_at_0[0x10];
9993 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
9997 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10000 struct mlx5_ifc_encryption_key_obj_bits {
10001 u8 modify_field_select[0x40];
10003 u8 reserved_at_40[0x14];
10005 u8 reserved_at_58[0x4];
10008 u8 reserved_at_60[0x8];
10011 u8 reserved_at_80[0x180];
10014 u8 reserved_at_300[0x500];
10017 struct mlx5_ifc_create_encryption_key_in_bits {
10018 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10019 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10023 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10024 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10028 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10031 struct mlx5_ifc_tls_static_params_bits {
10033 u8 tls_version[0x4];
10035 u8 reserved_at_8[0x14];
10036 u8 encryption_standard[0x4];
10038 u8 reserved_at_20[0x20];
10040 u8 initial_record_number[0x40];
10042 u8 resync_tcp_sn[0x20];
10046 u8 implicit_iv[0x40];
10048 u8 reserved_at_100[0x8];
10049 u8 dek_index[0x18];
10051 u8 reserved_at_120[0xe0];
10054 struct mlx5_ifc_tls_progress_params_bits {
10056 u8 reserved_at_1[0x7];
10059 u8 next_record_tcp_sn[0x20];
10061 u8 hw_resync_tcp_sn[0x20];
10063 u8 record_tracker_state[0x2];
10064 u8 auth_state[0x2];
10065 u8 reserved_at_64[0x4];
10066 u8 hw_offset_record_number[0x18];
10069 #endif /* MLX5_IFC_H */