2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include "mlx5_ifc_fpga.h"
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21
67 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
68 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
69 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
70 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
74 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
75 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2,
76 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
80 MLX5_SHARED_RESOURCE_UID = 0xffff,
84 MLX5_OBJ_TYPE_SW_ICM = 0x0008,
88 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
89 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
90 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13),
94 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
95 MLX5_OBJ_TYPE_MKEY = 0xff01,
96 MLX5_OBJ_TYPE_QP = 0xff02,
97 MLX5_OBJ_TYPE_PSV = 0xff03,
98 MLX5_OBJ_TYPE_RMP = 0xff04,
99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
100 MLX5_OBJ_TYPE_RQ = 0xff06,
101 MLX5_OBJ_TYPE_SQ = 0xff07,
102 MLX5_OBJ_TYPE_TIR = 0xff08,
103 MLX5_OBJ_TYPE_TIS = 0xff09,
104 MLX5_OBJ_TYPE_DCT = 0xff0a,
105 MLX5_OBJ_TYPE_XRQ = 0xff0b,
106 MLX5_OBJ_TYPE_RQT = 0xff0e,
107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
108 MLX5_OBJ_TYPE_CQ = 0xff10,
112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
114 MLX5_CMD_OP_INIT_HCA = 0x102,
115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
116 MLX5_CMD_OP_ENABLE_HCA = 0x104,
117 MLX5_CMD_OP_DISABLE_HCA = 0x105,
118 MLX5_CMD_OP_QUERY_PAGES = 0x107,
119 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
120 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
121 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
122 MLX5_CMD_OP_SET_ISSI = 0x10b,
123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111,
125 MLX5_CMD_OP_ALLOC_SF = 0x113,
126 MLX5_CMD_OP_DEALLOC_SF = 0x114,
127 MLX5_CMD_OP_CREATE_MKEY = 0x200,
128 MLX5_CMD_OP_QUERY_MKEY = 0x201,
129 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
130 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
131 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
132 MLX5_CMD_OP_ALLOC_MEMIC = 0x205,
133 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206,
134 MLX5_CMD_OP_CREATE_EQ = 0x301,
135 MLX5_CMD_OP_DESTROY_EQ = 0x302,
136 MLX5_CMD_OP_QUERY_EQ = 0x303,
137 MLX5_CMD_OP_GEN_EQE = 0x304,
138 MLX5_CMD_OP_CREATE_CQ = 0x400,
139 MLX5_CMD_OP_DESTROY_CQ = 0x401,
140 MLX5_CMD_OP_QUERY_CQ = 0x402,
141 MLX5_CMD_OP_MODIFY_CQ = 0x403,
142 MLX5_CMD_OP_CREATE_QP = 0x500,
143 MLX5_CMD_OP_DESTROY_QP = 0x501,
144 MLX5_CMD_OP_RST2INIT_QP = 0x502,
145 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
146 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
147 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
148 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
149 MLX5_CMD_OP_2ERR_QP = 0x507,
150 MLX5_CMD_OP_2RST_QP = 0x50a,
151 MLX5_CMD_OP_QUERY_QP = 0x50b,
152 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
153 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
154 MLX5_CMD_OP_CREATE_PSV = 0x600,
155 MLX5_CMD_OP_DESTROY_PSV = 0x601,
156 MLX5_CMD_OP_CREATE_SRQ = 0x700,
157 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
158 MLX5_CMD_OP_QUERY_SRQ = 0x702,
159 MLX5_CMD_OP_ARM_RQ = 0x703,
160 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
161 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
162 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
163 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
164 MLX5_CMD_OP_CREATE_DCT = 0x710,
165 MLX5_CMD_OP_DESTROY_DCT = 0x711,
166 MLX5_CMD_OP_DRAIN_DCT = 0x712,
167 MLX5_CMD_OP_QUERY_DCT = 0x713,
168 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
169 MLX5_CMD_OP_CREATE_XRQ = 0x717,
170 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
171 MLX5_CMD_OP_QUERY_XRQ = 0x719,
172 MLX5_CMD_OP_ARM_XRQ = 0x71a,
173 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
174 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
175 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
176 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
177 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
178 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740,
179 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
180 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
181 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
182 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
183 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
184 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
185 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
186 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
187 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
188 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
189 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
190 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
191 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
192 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
193 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
194 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
195 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
196 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774,
197 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775,
198 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780,
199 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
200 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
201 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
202 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
203 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
204 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
205 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
206 MLX5_CMD_OP_ALLOC_PD = 0x800,
207 MLX5_CMD_OP_DEALLOC_PD = 0x801,
208 MLX5_CMD_OP_ALLOC_UAR = 0x802,
209 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
210 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
211 MLX5_CMD_OP_ACCESS_REG = 0x805,
212 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
213 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
214 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
215 MLX5_CMD_OP_MAD_IFC = 0x50d,
216 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
217 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
218 MLX5_CMD_OP_NOP = 0x80d,
219 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
220 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
221 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
222 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
223 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
224 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
225 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
226 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
227 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
228 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
229 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
230 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
231 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
232 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
233 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
234 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
235 MLX5_CMD_OP_CREATE_LAG = 0x840,
236 MLX5_CMD_OP_MODIFY_LAG = 0x841,
237 MLX5_CMD_OP_QUERY_LAG = 0x842,
238 MLX5_CMD_OP_DESTROY_LAG = 0x843,
239 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
240 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
241 MLX5_CMD_OP_CREATE_TIR = 0x900,
242 MLX5_CMD_OP_MODIFY_TIR = 0x901,
243 MLX5_CMD_OP_DESTROY_TIR = 0x902,
244 MLX5_CMD_OP_QUERY_TIR = 0x903,
245 MLX5_CMD_OP_CREATE_SQ = 0x904,
246 MLX5_CMD_OP_MODIFY_SQ = 0x905,
247 MLX5_CMD_OP_DESTROY_SQ = 0x906,
248 MLX5_CMD_OP_QUERY_SQ = 0x907,
249 MLX5_CMD_OP_CREATE_RQ = 0x908,
250 MLX5_CMD_OP_MODIFY_RQ = 0x909,
251 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
252 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
253 MLX5_CMD_OP_QUERY_RQ = 0x90b,
254 MLX5_CMD_OP_CREATE_RMP = 0x90c,
255 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
256 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
257 MLX5_CMD_OP_QUERY_RMP = 0x90f,
258 MLX5_CMD_OP_CREATE_TIS = 0x912,
259 MLX5_CMD_OP_MODIFY_TIS = 0x913,
260 MLX5_CMD_OP_DESTROY_TIS = 0x914,
261 MLX5_CMD_OP_QUERY_TIS = 0x915,
262 MLX5_CMD_OP_CREATE_RQT = 0x916,
263 MLX5_CMD_OP_MODIFY_RQT = 0x917,
264 MLX5_CMD_OP_DESTROY_RQT = 0x918,
265 MLX5_CMD_OP_QUERY_RQT = 0x919,
266 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
267 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
268 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
269 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
270 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
271 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
272 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
273 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
274 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
275 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
276 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
277 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
278 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
279 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
280 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
281 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
282 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
283 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
284 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
285 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
286 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
287 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
288 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
289 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
290 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
291 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
292 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
293 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
294 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03,
295 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
296 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
297 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
298 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
299 MLX5_CMD_OP_SYNC_STEERING = 0xb00,
303 /* Valid range for general commands that don't work over an object */
305 MLX5_CMD_OP_GENERAL_START = 0xb00,
306 MLX5_CMD_OP_GENERAL_END = 0xd00,
309 struct mlx5_ifc_flow_table_fields_supported_bits {
312 u8 outer_ether_type[0x1];
313 u8 outer_ip_version[0x1];
314 u8 outer_first_prio[0x1];
315 u8 outer_first_cfi[0x1];
316 u8 outer_first_vid[0x1];
317 u8 outer_ipv4_ttl[0x1];
318 u8 outer_second_prio[0x1];
319 u8 outer_second_cfi[0x1];
320 u8 outer_second_vid[0x1];
321 u8 reserved_at_b[0x1];
325 u8 outer_ip_protocol[0x1];
326 u8 outer_ip_ecn[0x1];
327 u8 outer_ip_dscp[0x1];
328 u8 outer_udp_sport[0x1];
329 u8 outer_udp_dport[0x1];
330 u8 outer_tcp_sport[0x1];
331 u8 outer_tcp_dport[0x1];
332 u8 outer_tcp_flags[0x1];
333 u8 outer_gre_protocol[0x1];
334 u8 outer_gre_key[0x1];
335 u8 outer_vxlan_vni[0x1];
336 u8 outer_geneve_vni[0x1];
337 u8 outer_geneve_oam[0x1];
338 u8 outer_geneve_protocol_type[0x1];
339 u8 outer_geneve_opt_len[0x1];
340 u8 reserved_at_1e[0x1];
341 u8 source_eswitch_port[0x1];
345 u8 inner_ether_type[0x1];
346 u8 inner_ip_version[0x1];
347 u8 inner_first_prio[0x1];
348 u8 inner_first_cfi[0x1];
349 u8 inner_first_vid[0x1];
350 u8 reserved_at_27[0x1];
351 u8 inner_second_prio[0x1];
352 u8 inner_second_cfi[0x1];
353 u8 inner_second_vid[0x1];
354 u8 reserved_at_2b[0x1];
358 u8 inner_ip_protocol[0x1];
359 u8 inner_ip_ecn[0x1];
360 u8 inner_ip_dscp[0x1];
361 u8 inner_udp_sport[0x1];
362 u8 inner_udp_dport[0x1];
363 u8 inner_tcp_sport[0x1];
364 u8 inner_tcp_dport[0x1];
365 u8 inner_tcp_flags[0x1];
366 u8 reserved_at_37[0x9];
368 u8 geneve_tlv_option_0_data[0x1];
369 u8 reserved_at_41[0x4];
370 u8 outer_first_mpls_over_udp[0x4];
371 u8 outer_first_mpls_over_gre[0x4];
372 u8 inner_first_mpls[0x4];
373 u8 outer_first_mpls[0x4];
374 u8 reserved_at_55[0x2];
375 u8 outer_esp_spi[0x1];
376 u8 reserved_at_58[0x2];
378 u8 reserved_at_5b[0x5];
380 u8 reserved_at_60[0x18];
381 u8 metadata_reg_c_7[0x1];
382 u8 metadata_reg_c_6[0x1];
383 u8 metadata_reg_c_5[0x1];
384 u8 metadata_reg_c_4[0x1];
385 u8 metadata_reg_c_3[0x1];
386 u8 metadata_reg_c_2[0x1];
387 u8 metadata_reg_c_1[0x1];
388 u8 metadata_reg_c_0[0x1];
391 struct mlx5_ifc_flow_table_prop_layout_bits {
393 u8 reserved_at_1[0x1];
394 u8 flow_counter[0x1];
395 u8 flow_modify_en[0x1];
397 u8 identified_miss_table_mode[0x1];
398 u8 flow_table_modify[0x1];
401 u8 reserved_at_9[0x1];
404 u8 reserved_at_c[0x1];
407 u8 reformat_and_vlan_action[0x1];
408 u8 reserved_at_10[0x1];
410 u8 reformat_l3_tunnel_to_l2[0x1];
411 u8 reformat_l2_to_l3_tunnel[0x1];
412 u8 reformat_and_modify_action[0x1];
413 u8 ignore_flow_level[0x1];
414 u8 reserved_at_16[0x1];
415 u8 table_miss_action_domain[0x1];
416 u8 termination_table[0x1];
417 u8 reserved_at_19[0x7];
418 u8 reserved_at_20[0x2];
419 u8 log_max_ft_size[0x6];
420 u8 log_max_modify_header_context[0x8];
421 u8 max_modify_header_actions[0x8];
422 u8 max_ft_level[0x8];
424 u8 reserved_at_40[0x20];
426 u8 reserved_at_60[0x18];
427 u8 log_max_ft_num[0x8];
429 u8 reserved_at_80[0x18];
430 u8 log_max_destination[0x8];
432 u8 log_max_flow_counter[0x8];
433 u8 reserved_at_a8[0x10];
434 u8 log_max_flow[0x8];
436 u8 reserved_at_c0[0x40];
438 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
440 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
443 struct mlx5_ifc_odp_per_transport_service_cap_bits {
450 u8 reserved_at_6[0x1a];
453 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
478 u8 reserved_at_c0[0x18];
479 u8 ttl_hoplimit[0x8];
484 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
486 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
489 struct mlx5_ifc_nvgre_key_bits {
494 union mlx5_ifc_gre_key_bits {
495 struct mlx5_ifc_nvgre_key_bits nvgre;
499 struct mlx5_ifc_fte_match_set_misc_bits {
500 u8 gre_c_present[0x1];
501 u8 reserved_at_1[0x1];
502 u8 gre_k_present[0x1];
503 u8 gre_s_present[0x1];
504 u8 source_vhca_port[0x4];
507 u8 source_eswitch_owner_vhca_id[0x10];
508 u8 source_port[0x10];
510 u8 outer_second_prio[0x3];
511 u8 outer_second_cfi[0x1];
512 u8 outer_second_vid[0xc];
513 u8 inner_second_prio[0x3];
514 u8 inner_second_cfi[0x1];
515 u8 inner_second_vid[0xc];
517 u8 outer_second_cvlan_tag[0x1];
518 u8 inner_second_cvlan_tag[0x1];
519 u8 outer_second_svlan_tag[0x1];
520 u8 inner_second_svlan_tag[0x1];
521 u8 reserved_at_64[0xc];
522 u8 gre_protocol[0x10];
524 union mlx5_ifc_gre_key_bits gre_key;
527 u8 reserved_at_b8[0x8];
530 u8 reserved_at_d8[0x7];
533 u8 reserved_at_e0[0xc];
534 u8 outer_ipv6_flow_label[0x14];
536 u8 reserved_at_100[0xc];
537 u8 inner_ipv6_flow_label[0x14];
539 u8 reserved_at_120[0xa];
540 u8 geneve_opt_len[0x6];
541 u8 geneve_protocol_type[0x10];
543 u8 reserved_at_140[0x8];
545 u8 reserved_at_160[0x20];
546 u8 outer_esp_spi[0x20];
547 u8 reserved_at_1a0[0x60];
550 struct mlx5_ifc_fte_match_mpls_bits {
557 struct mlx5_ifc_fte_match_set_misc2_bits {
558 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
560 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
562 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
564 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
566 u8 metadata_reg_c_7[0x20];
568 u8 metadata_reg_c_6[0x20];
570 u8 metadata_reg_c_5[0x20];
572 u8 metadata_reg_c_4[0x20];
574 u8 metadata_reg_c_3[0x20];
576 u8 metadata_reg_c_2[0x20];
578 u8 metadata_reg_c_1[0x20];
580 u8 metadata_reg_c_0[0x20];
582 u8 metadata_reg_a[0x20];
584 u8 metadata_reg_b[0x20];
586 u8 reserved_at_1c0[0x40];
589 struct mlx5_ifc_fte_match_set_misc3_bits {
590 u8 inner_tcp_seq_num[0x20];
592 u8 outer_tcp_seq_num[0x20];
594 u8 inner_tcp_ack_num[0x20];
596 u8 outer_tcp_ack_num[0x20];
598 u8 reserved_at_80[0x8];
599 u8 outer_vxlan_gpe_vni[0x18];
601 u8 outer_vxlan_gpe_next_protocol[0x8];
602 u8 outer_vxlan_gpe_flags[0x8];
603 u8 reserved_at_b0[0x10];
605 u8 icmp_header_data[0x20];
607 u8 icmpv6_header_data[0x20];
614 u8 geneve_tlv_option_0_data[0x20];
616 u8 reserved_at_140[0xc0];
619 struct mlx5_ifc_cmd_pas_bits {
623 u8 reserved_at_34[0xc];
626 struct mlx5_ifc_uint64_bits {
633 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
634 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
635 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
636 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
637 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
638 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
639 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
640 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
641 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
642 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
645 struct mlx5_ifc_ads_bits {
648 u8 reserved_at_2[0xe];
651 u8 reserved_at_20[0x8];
657 u8 reserved_at_45[0x3];
658 u8 src_addr_index[0x8];
659 u8 reserved_at_50[0x4];
663 u8 reserved_at_60[0x4];
667 u8 rgid_rip[16][0x8];
669 u8 reserved_at_100[0x4];
672 u8 reserved_at_106[0x1];
681 u8 vhca_port_num[0x8];
687 struct mlx5_ifc_flow_table_nic_cap_bits {
688 u8 nic_rx_multi_path_tirs[0x1];
689 u8 nic_rx_multi_path_tirs_fts[0x1];
690 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
691 u8 reserved_at_3[0x4];
692 u8 sw_owner_reformat_supported[0x1];
693 u8 reserved_at_8[0x18];
695 u8 encap_general_header[0x1];
696 u8 reserved_at_21[0xa];
697 u8 log_max_packet_reformat_context[0x5];
698 u8 reserved_at_30[0x6];
699 u8 max_encap_header_size[0xa];
700 u8 reserved_at_40[0x1c0];
702 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
704 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
706 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
708 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
710 u8 reserved_at_a00[0x200];
712 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
714 u8 reserved_at_e00[0x1200];
716 u8 sw_steering_nic_rx_action_drop_icm_address[0x40];
718 u8 sw_steering_nic_tx_action_drop_icm_address[0x40];
720 u8 sw_steering_nic_tx_action_allow_icm_address[0x40];
722 u8 reserved_at_20c0[0x5f40];
726 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
727 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
728 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
729 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
730 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
731 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
732 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
733 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
736 struct mlx5_ifc_flow_table_eswitch_cap_bits {
737 u8 fdb_to_vport_reg_c_id[0x8];
738 u8 reserved_at_8[0xd];
739 u8 fdb_modify_header_fwd_to_table[0x1];
740 u8 reserved_at_16[0x1];
742 u8 reserved_at_18[0x2];
743 u8 multi_fdb_encap[0x1];
744 u8 reserved_at_1b[0x1];
745 u8 fdb_multi_path_to_table[0x1];
746 u8 reserved_at_1d[0x3];
748 u8 reserved_at_20[0x1e0];
750 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
752 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
754 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
756 u8 reserved_at_800[0x1000];
758 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40];
760 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40];
762 u8 sw_steering_uplink_icm_address_rx[0x40];
764 u8 sw_steering_uplink_icm_address_tx[0x40];
766 u8 reserved_at_1900[0x6700];
770 MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
771 MLX5_COUNTER_FLOW_ESWITCH = 0x1,
774 struct mlx5_ifc_e_switch_cap_bits {
775 u8 vport_svlan_strip[0x1];
776 u8 vport_cvlan_strip[0x1];
777 u8 vport_svlan_insert[0x1];
778 u8 vport_cvlan_insert_if_not_exist[0x1];
779 u8 vport_cvlan_insert_overwrite[0x1];
780 u8 reserved_at_5[0x3];
781 u8 esw_uplink_ingress_acl[0x1];
782 u8 reserved_at_9[0x10];
783 u8 esw_functions_changed[0x1];
784 u8 reserved_at_1a[0x1];
785 u8 ecpf_vport_exists[0x1];
786 u8 counter_eswitch_affinity[0x1];
787 u8 merged_eswitch[0x1];
788 u8 nic_vport_node_guid_modify[0x1];
789 u8 nic_vport_port_guid_modify[0x1];
791 u8 vxlan_encap_decap[0x1];
792 u8 nvgre_encap_decap[0x1];
793 u8 reserved_at_22[0x1];
794 u8 log_max_fdb_encap_uplink[0x5];
795 u8 reserved_at_21[0x3];
796 u8 log_max_packet_reformat_context[0x5];
798 u8 max_encap_header_size[0xa];
800 u8 reserved_at_40[0xb];
801 u8 log_max_esw_sf[0x5];
802 u8 esw_sf_base_id[0x10];
804 u8 reserved_at_60[0x7a0];
808 struct mlx5_ifc_qos_cap_bits {
809 u8 packet_pacing[0x1];
810 u8 esw_scheduling[0x1];
811 u8 esw_bw_share[0x1];
812 u8 esw_rate_limit[0x1];
813 u8 reserved_at_4[0x1];
814 u8 packet_pacing_burst_bound[0x1];
815 u8 packet_pacing_typical_size[0x1];
816 u8 reserved_at_7[0x19];
818 u8 reserved_at_20[0x20];
820 u8 packet_pacing_max_rate[0x20];
822 u8 packet_pacing_min_rate[0x20];
824 u8 reserved_at_80[0x10];
825 u8 packet_pacing_rate_table_size[0x10];
827 u8 esw_element_type[0x10];
828 u8 esw_tsar_type[0x10];
830 u8 reserved_at_c0[0x10];
831 u8 max_qos_para_vport[0x10];
833 u8 max_tsar_bw_share[0x20];
835 u8 reserved_at_100[0x700];
838 struct mlx5_ifc_debug_cap_bits {
839 u8 core_dump_general[0x1];
840 u8 core_dump_qp[0x1];
841 u8 reserved_at_2[0x7];
842 u8 resource_dump[0x1];
843 u8 reserved_at_a[0x16];
845 u8 reserved_at_20[0x2];
846 u8 stall_detect[0x1];
847 u8 reserved_at_23[0x1d];
849 u8 reserved_at_40[0x7c0];
852 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
856 u8 lro_psh_flag[0x1];
857 u8 lro_time_stamp[0x1];
858 u8 reserved_at_5[0x2];
859 u8 wqe_vlan_insert[0x1];
860 u8 self_lb_en_modifiable[0x1];
861 u8 reserved_at_9[0x2];
863 u8 multi_pkt_send_wqe[0x2];
864 u8 wqe_inline_mode[0x2];
865 u8 rss_ind_tbl_cap[0x4];
868 u8 enhanced_multi_pkt_send_wqe[0x1];
869 u8 tunnel_lso_const_out_ip_id[0x1];
870 u8 reserved_at_1c[0x2];
871 u8 tunnel_stateless_gre[0x1];
872 u8 tunnel_stateless_vxlan[0x1];
877 u8 cqe_checksum_full[0x1];
878 u8 reserved_at_24[0x5];
879 u8 tunnel_stateless_ip_over_ip[0x1];
880 u8 reserved_at_2a[0x6];
881 u8 max_vxlan_udp_ports[0x8];
882 u8 reserved_at_38[0x6];
883 u8 max_geneve_opt_len[0x1];
884 u8 tunnel_stateless_geneve_rx[0x1];
886 u8 reserved_at_40[0x10];
887 u8 lro_min_mss_size[0x10];
889 u8 reserved_at_60[0x120];
891 u8 lro_timer_supported_periods[4][0x20];
893 u8 reserved_at_200[0x600];
896 struct mlx5_ifc_roce_cap_bits {
898 u8 reserved_at_1[0x1f];
900 u8 reserved_at_20[0x60];
902 u8 reserved_at_80[0xc];
904 u8 reserved_at_90[0x8];
905 u8 roce_version[0x8];
907 u8 reserved_at_a0[0x10];
908 u8 r_roce_dest_udp_port[0x10];
910 u8 r_roce_max_src_udp_port[0x10];
911 u8 r_roce_min_src_udp_port[0x10];
913 u8 reserved_at_e0[0x10];
914 u8 roce_address_table_size[0x10];
916 u8 reserved_at_100[0x700];
919 struct mlx5_ifc_sync_steering_in_bits {
923 u8 reserved_at_20[0x10];
926 u8 reserved_at_40[0xc0];
929 struct mlx5_ifc_sync_steering_out_bits {
931 u8 reserved_at_8[0x18];
935 u8 reserved_at_40[0x40];
938 struct mlx5_ifc_device_mem_cap_bits {
940 u8 reserved_at_1[0x1f];
942 u8 reserved_at_20[0xb];
943 u8 log_min_memic_alloc_size[0x5];
944 u8 reserved_at_30[0x8];
945 u8 log_max_memic_addr_alignment[0x8];
947 u8 memic_bar_start_addr[0x40];
949 u8 memic_bar_size[0x20];
951 u8 max_memic_size[0x20];
953 u8 steering_sw_icm_start_address[0x40];
955 u8 reserved_at_100[0x8];
956 u8 log_header_modify_sw_icm_size[0x8];
957 u8 reserved_at_110[0x2];
958 u8 log_sw_icm_alloc_granularity[0x6];
959 u8 log_steering_sw_icm_size[0x8];
961 u8 reserved_at_120[0x20];
963 u8 header_modify_sw_icm_start_address[0x40];
965 u8 reserved_at_180[0x680];
968 struct mlx5_ifc_device_event_cap_bits {
969 u8 user_affiliated_events[4][0x40];
971 u8 user_unaffiliated_events[4][0x40];
974 struct mlx5_ifc_device_virtio_emulation_cap_bits {
975 u8 reserved_at_0[0x20];
977 u8 reserved_at_20[0x13];
978 u8 log_doorbell_stride[0x5];
979 u8 reserved_at_38[0x3];
980 u8 log_doorbell_bar_size[0x5];
982 u8 doorbell_bar_offset[0x40];
984 u8 reserved_at_80[0x780];
988 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
989 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
990 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
991 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
992 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
993 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
994 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
995 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
996 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1000 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1001 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1002 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1003 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1004 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1005 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1006 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1007 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1008 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1011 struct mlx5_ifc_atomic_caps_bits {
1012 u8 reserved_at_0[0x40];
1014 u8 atomic_req_8B_endianness_mode[0x2];
1015 u8 reserved_at_42[0x4];
1016 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
1018 u8 reserved_at_47[0x19];
1020 u8 reserved_at_60[0x20];
1022 u8 reserved_at_80[0x10];
1023 u8 atomic_operations[0x10];
1025 u8 reserved_at_a0[0x10];
1026 u8 atomic_size_qp[0x10];
1028 u8 reserved_at_c0[0x10];
1029 u8 atomic_size_dc[0x10];
1031 u8 reserved_at_e0[0x720];
1034 struct mlx5_ifc_odp_cap_bits {
1035 u8 reserved_at_0[0x40];
1038 u8 reserved_at_41[0x1f];
1040 u8 reserved_at_60[0x20];
1042 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
1044 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
1046 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
1048 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
1050 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps;
1052 u8 reserved_at_120[0x6E0];
1055 struct mlx5_ifc_calc_op {
1056 u8 reserved_at_0[0x10];
1057 u8 reserved_at_10[0x9];
1058 u8 op_swap_endianness[0x1];
1067 struct mlx5_ifc_vector_calc_cap_bits {
1068 u8 calc_matrix[0x1];
1069 u8 reserved_at_1[0x1f];
1070 u8 reserved_at_20[0x8];
1071 u8 max_vec_count[0x8];
1072 u8 reserved_at_30[0xd];
1073 u8 max_chunk_size[0x3];
1074 struct mlx5_ifc_calc_op calc0;
1075 struct mlx5_ifc_calc_op calc1;
1076 struct mlx5_ifc_calc_op calc2;
1077 struct mlx5_ifc_calc_op calc3;
1079 u8 reserved_at_c0[0x720];
1082 struct mlx5_ifc_tls_cap_bits {
1083 u8 tls_1_2_aes_gcm_128[0x1];
1084 u8 tls_1_3_aes_gcm_128[0x1];
1085 u8 tls_1_2_aes_gcm_256[0x1];
1086 u8 tls_1_3_aes_gcm_256[0x1];
1087 u8 reserved_at_4[0x1c];
1089 u8 reserved_at_20[0x7e0];
1093 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1094 MLX5_WQ_TYPE_CYCLIC = 0x1,
1095 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1096 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1100 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1101 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1105 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1106 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1107 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1108 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1109 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1113 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1114 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1115 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1116 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1117 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1118 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1122 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1123 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1127 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1128 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1129 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1133 MLX5_CAP_PORT_TYPE_IB = 0x0,
1134 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1138 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
1139 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
1140 MLX5_CAP_UMR_FENCE_NONE = 0x2,
1144 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3,
1145 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7,
1146 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8,
1147 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9,
1151 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1152 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1155 #define MLX5_FC_BULK_SIZE_FACTOR 128
1157 enum mlx5_fc_bulk_alloc_bitmask {
1158 MLX5_FC_BULK_128 = (1 << 0),
1159 MLX5_FC_BULK_256 = (1 << 1),
1160 MLX5_FC_BULK_512 = (1 << 2),
1161 MLX5_FC_BULK_1024 = (1 << 3),
1162 MLX5_FC_BULK_2048 = (1 << 4),
1163 MLX5_FC_BULK_4096 = (1 << 5),
1164 MLX5_FC_BULK_8192 = (1 << 6),
1165 MLX5_FC_BULK_16384 = (1 << 7),
1168 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1170 struct mlx5_ifc_cmd_hca_cap_bits {
1171 u8 reserved_at_0[0x30];
1174 u8 reserved_at_40[0x40];
1176 u8 log_max_srq_sz[0x8];
1177 u8 log_max_qp_sz[0x8];
1179 u8 reserved_at_91[0x7];
1180 u8 prio_tag_required[0x1];
1181 u8 reserved_at_99[0x2];
1184 u8 reserved_at_a0[0xb];
1185 u8 log_max_srq[0x5];
1186 u8 reserved_at_b0[0x10];
1188 u8 max_sgl_for_optimized_performance[0x8];
1189 u8 log_max_cq_sz[0x8];
1190 u8 reserved_at_d0[0xb];
1193 u8 log_max_eq_sz[0x8];
1194 u8 relaxed_ordering_write[0x1];
1195 u8 relaxed_ordering_read[0x1];
1196 u8 log_max_mkey[0x6];
1197 u8 reserved_at_f0[0x8];
1198 u8 dump_fill_mkey[0x1];
1199 u8 reserved_at_f9[0x2];
1200 u8 fast_teardown[0x1];
1203 u8 max_indirection[0x8];
1204 u8 fixed_buffer_size[0x1];
1205 u8 log_max_mrw_sz[0x7];
1206 u8 force_teardown[0x1];
1207 u8 reserved_at_111[0x1];
1208 u8 log_max_bsf_list_size[0x6];
1209 u8 umr_extended_translation_offset[0x1];
1211 u8 log_max_klm_list_size[0x6];
1213 u8 reserved_at_120[0xa];
1214 u8 log_max_ra_req_dc[0x6];
1215 u8 reserved_at_130[0xa];
1216 u8 log_max_ra_res_dc[0x6];
1218 u8 reserved_at_140[0x9];
1220 u8 log_max_ra_req_qp[0x6];
1221 u8 reserved_at_150[0xa];
1222 u8 log_max_ra_res_qp[0x6];
1225 u8 cc_query_allowed[0x1];
1226 u8 cc_modify_allowed[0x1];
1228 u8 cache_line_128byte[0x1];
1229 u8 reserved_at_165[0x4];
1230 u8 rts2rts_qp_counters_set_id[0x1];
1231 u8 reserved_at_16a[0x2];
1232 u8 vnic_env_int_rq_oob[0x1];
1234 u8 reserved_at_16e[0x1];
1236 u8 gid_table_size[0x10];
1238 u8 out_of_seq_cnt[0x1];
1239 u8 vport_counters[0x1];
1240 u8 retransmission_q_counters[0x1];
1242 u8 modify_rq_counter_set_id[0x1];
1243 u8 rq_delay_drop[0x1];
1245 u8 pkey_table_size[0x10];
1247 u8 vport_group_manager[0x1];
1248 u8 vhca_group_manager[0x1];
1251 u8 vnic_env_queue_counters[0x1];
1253 u8 nic_flow_table[0x1];
1254 u8 eswitch_manager[0x1];
1255 u8 device_memory[0x1];
1258 u8 local_ca_ack_delay[0x5];
1259 u8 port_module_event[0x1];
1260 u8 enhanced_error_q_counters[0x1];
1261 u8 ports_check[0x1];
1262 u8 reserved_at_1b3[0x1];
1263 u8 disable_link_up[0x1];
1268 u8 reserved_at_1c0[0x1];
1271 u8 log_max_msg[0x5];
1272 u8 reserved_at_1c8[0x4];
1274 u8 temp_warn_event[0x1];
1276 u8 general_notification_event[0x1];
1277 u8 reserved_at_1d3[0x2];
1281 u8 reserved_at_1d8[0x1];
1290 u8 stat_rate_support[0x10];
1291 u8 reserved_at_1f0[0xc];
1292 u8 cqe_version[0x4];
1294 u8 compact_address_vector[0x1];
1295 u8 striding_rq[0x1];
1296 u8 reserved_at_202[0x1];
1297 u8 ipoib_enhanced_offloads[0x1];
1298 u8 ipoib_basic_offloads[0x1];
1299 u8 reserved_at_205[0x1];
1300 u8 repeated_block_disabled[0x1];
1301 u8 umr_modify_entity_size_disabled[0x1];
1302 u8 umr_modify_atomic_disabled[0x1];
1303 u8 umr_indirect_mkey_disabled[0x1];
1305 u8 dc_req_scat_data_cqe[0x1];
1306 u8 reserved_at_20d[0x2];
1307 u8 drain_sigerr[0x1];
1308 u8 cmdif_checksum[0x2];
1310 u8 reserved_at_213[0x1];
1311 u8 wq_signature[0x1];
1312 u8 sctr_data_cqe[0x1];
1313 u8 reserved_at_216[0x1];
1319 u8 eth_net_offloads[0x1];
1322 u8 reserved_at_21f[0x1];
1326 u8 cq_moderation[0x1];
1327 u8 reserved_at_223[0x3];
1328 u8 cq_eq_remap[0x1];
1330 u8 block_lb_mc[0x1];
1331 u8 reserved_at_229[0x1];
1332 u8 scqe_break_moderation[0x1];
1333 u8 cq_period_start_from_cqe[0x1];
1335 u8 reserved_at_22d[0x1];
1337 u8 vector_calc[0x1];
1338 u8 umr_ptr_rlky[0x1];
1340 u8 qp_packet_based[0x1];
1341 u8 reserved_at_233[0x3];
1344 u8 set_deth_sqpn[0x1];
1345 u8 reserved_at_239[0x3];
1352 u8 reserved_at_241[0x9];
1354 u8 reserved_at_250[0x8];
1358 u8 driver_version[0x1];
1359 u8 pad_tx_eth_packet[0x1];
1360 u8 reserved_at_263[0x8];
1361 u8 log_bf_reg_size[0x5];
1363 u8 reserved_at_270[0x8];
1364 u8 lag_tx_port_affinity[0x1];
1365 u8 reserved_at_279[0x2];
1367 u8 num_lag_ports[0x4];
1369 u8 reserved_at_280[0x10];
1370 u8 max_wqe_sz_sq[0x10];
1372 u8 reserved_at_2a0[0x10];
1373 u8 max_wqe_sz_rq[0x10];
1375 u8 max_flow_counter_31_16[0x10];
1376 u8 max_wqe_sz_sq_dc[0x10];
1378 u8 reserved_at_2e0[0x7];
1379 u8 max_qp_mcg[0x19];
1381 u8 reserved_at_300[0x10];
1382 u8 flow_counter_bulk_alloc[0x8];
1383 u8 log_max_mcg[0x8];
1385 u8 reserved_at_320[0x3];
1386 u8 log_max_transport_domain[0x5];
1387 u8 reserved_at_328[0x3];
1389 u8 reserved_at_330[0xb];
1390 u8 log_max_xrcd[0x5];
1392 u8 nic_receive_steering_discard[0x1];
1393 u8 receive_discard_vport_down[0x1];
1394 u8 transmit_discard_vport_down[0x1];
1395 u8 reserved_at_343[0x5];
1396 u8 log_max_flow_counter_bulk[0x8];
1397 u8 max_flow_counter_15_0[0x10];
1400 u8 reserved_at_360[0x3];
1402 u8 reserved_at_368[0x3];
1404 u8 reserved_at_370[0x3];
1405 u8 log_max_tir[0x5];
1406 u8 reserved_at_378[0x3];
1407 u8 log_max_tis[0x5];
1409 u8 basic_cyclic_rcv_wqe[0x1];
1410 u8 reserved_at_381[0x2];
1411 u8 log_max_rmp[0x5];
1412 u8 reserved_at_388[0x3];
1413 u8 log_max_rqt[0x5];
1414 u8 reserved_at_390[0x3];
1415 u8 log_max_rqt_size[0x5];
1416 u8 reserved_at_398[0x3];
1417 u8 log_max_tis_per_sq[0x5];
1419 u8 ext_stride_num_range[0x1];
1420 u8 reserved_at_3a1[0x2];
1421 u8 log_max_stride_sz_rq[0x5];
1422 u8 reserved_at_3a8[0x3];
1423 u8 log_min_stride_sz_rq[0x5];
1424 u8 reserved_at_3b0[0x3];
1425 u8 log_max_stride_sz_sq[0x5];
1426 u8 reserved_at_3b8[0x3];
1427 u8 log_min_stride_sz_sq[0x5];
1430 u8 reserved_at_3c1[0x2];
1431 u8 log_max_hairpin_queues[0x5];
1432 u8 reserved_at_3c8[0x3];
1433 u8 log_max_hairpin_wq_data_sz[0x5];
1434 u8 reserved_at_3d0[0x3];
1435 u8 log_max_hairpin_num_packets[0x5];
1436 u8 reserved_at_3d8[0x3];
1437 u8 log_max_wq_sz[0x5];
1439 u8 nic_vport_change_event[0x1];
1440 u8 disable_local_lb_uc[0x1];
1441 u8 disable_local_lb_mc[0x1];
1442 u8 log_min_hairpin_wq_data_sz[0x5];
1443 u8 reserved_at_3e8[0x3];
1444 u8 log_max_vlan_list[0x5];
1445 u8 reserved_at_3f0[0x3];
1446 u8 log_max_current_mc_list[0x5];
1447 u8 reserved_at_3f8[0x3];
1448 u8 log_max_current_uc_list[0x5];
1450 u8 general_obj_types[0x40];
1452 u8 reserved_at_440[0x20];
1454 u8 reserved_at_460[0x3];
1455 u8 log_max_uctx[0x5];
1456 u8 reserved_at_468[0x3];
1457 u8 log_max_umem[0x5];
1458 u8 max_num_eqs[0x10];
1460 u8 reserved_at_480[0x1];
1462 u8 reserved_at_482[0x1];
1463 u8 log_max_l2_table[0x5];
1464 u8 reserved_at_488[0x8];
1465 u8 log_uar_page_sz[0x10];
1467 u8 reserved_at_4a0[0x20];
1468 u8 device_frequency_mhz[0x20];
1469 u8 device_frequency_khz[0x20];
1471 u8 reserved_at_500[0x20];
1472 u8 num_of_uars_per_page[0x20];
1474 u8 flex_parser_protocols[0x20];
1476 u8 max_geneve_tlv_options[0x8];
1477 u8 reserved_at_568[0x3];
1478 u8 max_geneve_tlv_option_data_len[0x5];
1479 u8 reserved_at_570[0x10];
1481 u8 reserved_at_580[0x33];
1482 u8 log_max_dek[0x5];
1483 u8 reserved_at_5b8[0x4];
1484 u8 mini_cqe_resp_stride_index[0x1];
1485 u8 cqe_128_always[0x1];
1486 u8 cqe_compression_128[0x1];
1487 u8 cqe_compression[0x1];
1489 u8 cqe_compression_timeout[0x10];
1490 u8 cqe_compression_max_num[0x10];
1492 u8 reserved_at_5e0[0x10];
1493 u8 tag_matching[0x1];
1494 u8 rndv_offload_rc[0x1];
1495 u8 rndv_offload_dc[0x1];
1496 u8 log_tag_matching_list_sz[0x5];
1497 u8 reserved_at_5f8[0x3];
1498 u8 log_max_xrq[0x5];
1500 u8 affiliate_nic_vport_criteria[0x8];
1501 u8 native_port_num[0x8];
1502 u8 num_vhca_ports[0x8];
1503 u8 reserved_at_618[0x6];
1504 u8 sw_owner_id[0x1];
1505 u8 reserved_at_61f[0x1];
1507 u8 max_num_of_monitor_counters[0x10];
1508 u8 num_ppcnt_monitor_counters[0x10];
1510 u8 reserved_at_640[0x10];
1511 u8 num_q_monitor_counters[0x10];
1513 u8 reserved_at_660[0x20];
1516 u8 sf_set_partition[0x1];
1517 u8 reserved_at_682[0x1];
1519 u8 reserved_at_688[0x8];
1520 u8 log_min_sf_size[0x8];
1521 u8 max_num_sf_partitions[0x8];
1525 u8 reserved_at_6c0[0x4];
1526 u8 flex_parser_id_geneve_tlv_option_0[0x4];
1527 u8 flex_parser_id_icmp_dw1[0x4];
1528 u8 flex_parser_id_icmp_dw0[0x4];
1529 u8 flex_parser_id_icmpv6_dw1[0x4];
1530 u8 flex_parser_id_icmpv6_dw0[0x4];
1531 u8 flex_parser_id_outer_first_mpls_over_gre[0x4];
1532 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4];
1534 u8 reserved_at_6e0[0x10];
1535 u8 sf_base_id[0x10];
1537 u8 reserved_at_700[0x80];
1538 u8 vhca_tunnel_commands[0x40];
1539 u8 reserved_at_7c0[0x40];
1542 enum mlx5_flow_destination_type {
1543 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1544 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1545 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
1547 MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
1548 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
1549 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1552 enum mlx5_flow_table_miss_action {
1553 MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1554 MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1555 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1558 struct mlx5_ifc_dest_format_struct_bits {
1559 u8 destination_type[0x8];
1560 u8 destination_id[0x18];
1562 u8 destination_eswitch_owner_vhca_id_valid[0x1];
1563 u8 packet_reformat[0x1];
1564 u8 reserved_at_22[0xe];
1565 u8 destination_eswitch_owner_vhca_id[0x10];
1568 struct mlx5_ifc_flow_counter_list_bits {
1569 u8 flow_counter_id[0x20];
1571 u8 reserved_at_20[0x20];
1574 struct mlx5_ifc_extended_dest_format_bits {
1575 struct mlx5_ifc_dest_format_struct_bits destination_entry;
1577 u8 packet_reformat_id[0x20];
1579 u8 reserved_at_60[0x20];
1582 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1583 struct mlx5_ifc_extended_dest_format_bits extended_dest_format;
1584 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1587 struct mlx5_ifc_fte_match_param_bits {
1588 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1590 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1592 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1594 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1596 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1598 u8 reserved_at_a00[0x600];
1602 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1603 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1604 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1605 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1606 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1609 struct mlx5_ifc_rx_hash_field_select_bits {
1610 u8 l3_prot_type[0x1];
1611 u8 l4_prot_type[0x1];
1612 u8 selected_fields[0x1e];
1616 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1617 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
1621 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1622 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1625 struct mlx5_ifc_wq_bits {
1627 u8 wq_signature[0x1];
1628 u8 end_padding_mode[0x2];
1630 u8 reserved_at_8[0x18];
1632 u8 hds_skip_first_sge[0x1];
1633 u8 log2_hds_buf_size[0x3];
1634 u8 reserved_at_24[0x7];
1635 u8 page_offset[0x5];
1638 u8 reserved_at_40[0x8];
1641 u8 reserved_at_60[0x8];
1646 u8 hw_counter[0x20];
1648 u8 sw_counter[0x20];
1650 u8 reserved_at_100[0xc];
1651 u8 log_wq_stride[0x4];
1652 u8 reserved_at_110[0x3];
1653 u8 log_wq_pg_sz[0x5];
1654 u8 reserved_at_118[0x3];
1657 u8 dbr_umem_valid[0x1];
1658 u8 wq_umem_valid[0x1];
1659 u8 reserved_at_122[0x1];
1660 u8 log_hairpin_num_packets[0x5];
1661 u8 reserved_at_128[0x3];
1662 u8 log_hairpin_data_sz[0x5];
1664 u8 reserved_at_130[0x4];
1665 u8 log_wqe_num_of_strides[0x4];
1666 u8 two_byte_shift_en[0x1];
1667 u8 reserved_at_139[0x4];
1668 u8 log_wqe_stride_size[0x3];
1670 u8 reserved_at_140[0x4c0];
1672 struct mlx5_ifc_cmd_pas_bits pas[0];
1675 struct mlx5_ifc_rq_num_bits {
1676 u8 reserved_at_0[0x8];
1680 struct mlx5_ifc_mac_address_layout_bits {
1681 u8 reserved_at_0[0x10];
1682 u8 mac_addr_47_32[0x10];
1684 u8 mac_addr_31_0[0x20];
1687 struct mlx5_ifc_vlan_layout_bits {
1688 u8 reserved_at_0[0x14];
1691 u8 reserved_at_20[0x20];
1694 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1695 u8 reserved_at_0[0xa0];
1697 u8 min_time_between_cnps[0x20];
1699 u8 reserved_at_c0[0x12];
1701 u8 reserved_at_d8[0x4];
1702 u8 cnp_prio_mode[0x1];
1703 u8 cnp_802p_prio[0x3];
1705 u8 reserved_at_e0[0x720];
1708 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1709 u8 reserved_at_0[0x60];
1711 u8 reserved_at_60[0x4];
1712 u8 clamp_tgt_rate[0x1];
1713 u8 reserved_at_65[0x3];
1714 u8 clamp_tgt_rate_after_time_inc[0x1];
1715 u8 reserved_at_69[0x17];
1717 u8 reserved_at_80[0x20];
1719 u8 rpg_time_reset[0x20];
1721 u8 rpg_byte_reset[0x20];
1723 u8 rpg_threshold[0x20];
1725 u8 rpg_max_rate[0x20];
1727 u8 rpg_ai_rate[0x20];
1729 u8 rpg_hai_rate[0x20];
1733 u8 rpg_min_dec_fac[0x20];
1735 u8 rpg_min_rate[0x20];
1737 u8 reserved_at_1c0[0xe0];
1739 u8 rate_to_set_on_first_cnp[0x20];
1743 u8 dce_tcp_rtt[0x20];
1745 u8 rate_reduce_monitor_period[0x20];
1747 u8 reserved_at_320[0x20];
1749 u8 initial_alpha_value[0x20];
1751 u8 reserved_at_360[0x4a0];
1754 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1755 u8 reserved_at_0[0x80];
1757 u8 rppp_max_rps[0x20];
1759 u8 rpg_time_reset[0x20];
1761 u8 rpg_byte_reset[0x20];
1763 u8 rpg_threshold[0x20];
1765 u8 rpg_max_rate[0x20];
1767 u8 rpg_ai_rate[0x20];
1769 u8 rpg_hai_rate[0x20];
1773 u8 rpg_min_dec_fac[0x20];
1775 u8 rpg_min_rate[0x20];
1777 u8 reserved_at_1c0[0x640];
1781 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1782 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1783 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1786 struct mlx5_ifc_resize_field_select_bits {
1787 u8 resize_field_select[0x20];
1790 struct mlx5_ifc_resource_dump_bits {
1792 u8 inline_dump[0x1];
1793 u8 reserved_at_2[0xa];
1795 u8 segment_type[0x10];
1797 u8 reserved_at_20[0x10];
1804 u8 num_of_obj1[0x10];
1805 u8 num_of_obj2[0x10];
1807 u8 reserved_at_a0[0x20];
1809 u8 device_opaque[0x40];
1817 u8 inline_data[52][0x20];
1820 struct mlx5_ifc_resource_dump_menu_record_bits {
1821 u8 reserved_at_0[0x4];
1822 u8 num_of_obj2_supports_active[0x1];
1823 u8 num_of_obj2_supports_all[0x1];
1824 u8 must_have_num_of_obj2[0x1];
1825 u8 support_num_of_obj2[0x1];
1826 u8 num_of_obj1_supports_active[0x1];
1827 u8 num_of_obj1_supports_all[0x1];
1828 u8 must_have_num_of_obj1[0x1];
1829 u8 support_num_of_obj1[0x1];
1830 u8 must_have_index2[0x1];
1831 u8 support_index2[0x1];
1832 u8 must_have_index1[0x1];
1833 u8 support_index1[0x1];
1834 u8 segment_type[0x10];
1836 u8 segment_name[4][0x20];
1838 u8 index1_name[4][0x20];
1840 u8 index2_name[4][0x20];
1843 struct mlx5_ifc_resource_dump_segment_header_bits {
1845 u8 segment_type[0x10];
1848 struct mlx5_ifc_resource_dump_command_segment_bits {
1849 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1851 u8 segment_called[0x10];
1858 u8 num_of_obj1[0x10];
1859 u8 num_of_obj2[0x10];
1862 struct mlx5_ifc_resource_dump_error_segment_bits {
1863 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1865 u8 reserved_at_20[0x10];
1866 u8 syndrome_id[0x10];
1868 u8 reserved_at_40[0x40];
1873 struct mlx5_ifc_resource_dump_info_segment_bits {
1874 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1876 u8 reserved_at_20[0x18];
1877 u8 dump_version[0x8];
1879 u8 hw_version[0x20];
1881 u8 fw_version[0x20];
1884 struct mlx5_ifc_resource_dump_menu_segment_bits {
1885 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1887 u8 reserved_at_20[0x10];
1888 u8 num_of_records[0x10];
1890 struct mlx5_ifc_resource_dump_menu_record_bits record[0];
1893 struct mlx5_ifc_resource_dump_resource_segment_bits {
1894 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1896 u8 reserved_at_20[0x20];
1902 u8 payload[0][0x20];
1905 struct mlx5_ifc_resource_dump_terminate_segment_bits {
1906 struct mlx5_ifc_resource_dump_segment_header_bits segment_header;
1909 struct mlx5_ifc_menu_resource_dump_response_bits {
1910 struct mlx5_ifc_resource_dump_info_segment_bits info;
1911 struct mlx5_ifc_resource_dump_command_segment_bits cmd;
1912 struct mlx5_ifc_resource_dump_menu_segment_bits menu;
1913 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate;
1917 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1918 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1919 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1920 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1923 struct mlx5_ifc_modify_field_select_bits {
1924 u8 modify_field_select[0x20];
1927 struct mlx5_ifc_field_select_r_roce_np_bits {
1928 u8 field_select_r_roce_np[0x20];
1931 struct mlx5_ifc_field_select_r_roce_rp_bits {
1932 u8 field_select_r_roce_rp[0x20];
1936 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1937 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1938 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1939 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1940 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1941 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1942 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1943 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1944 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1945 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1948 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1949 u8 field_select_8021qaurp[0x20];
1952 struct mlx5_ifc_phys_layer_cntrs_bits {
1953 u8 time_since_last_clear_high[0x20];
1955 u8 time_since_last_clear_low[0x20];
1957 u8 symbol_errors_high[0x20];
1959 u8 symbol_errors_low[0x20];
1961 u8 sync_headers_errors_high[0x20];
1963 u8 sync_headers_errors_low[0x20];
1965 u8 edpl_bip_errors_lane0_high[0x20];
1967 u8 edpl_bip_errors_lane0_low[0x20];
1969 u8 edpl_bip_errors_lane1_high[0x20];
1971 u8 edpl_bip_errors_lane1_low[0x20];
1973 u8 edpl_bip_errors_lane2_high[0x20];
1975 u8 edpl_bip_errors_lane2_low[0x20];
1977 u8 edpl_bip_errors_lane3_high[0x20];
1979 u8 edpl_bip_errors_lane3_low[0x20];
1981 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1983 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1985 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1987 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1989 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1991 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1993 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1995 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1997 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1999 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
2001 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
2003 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
2005 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
2007 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
2009 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
2011 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
2013 u8 rs_fec_corrected_blocks_high[0x20];
2015 u8 rs_fec_corrected_blocks_low[0x20];
2017 u8 rs_fec_uncorrectable_blocks_high[0x20];
2019 u8 rs_fec_uncorrectable_blocks_low[0x20];
2021 u8 rs_fec_no_errors_blocks_high[0x20];
2023 u8 rs_fec_no_errors_blocks_low[0x20];
2025 u8 rs_fec_single_error_blocks_high[0x20];
2027 u8 rs_fec_single_error_blocks_low[0x20];
2029 u8 rs_fec_corrected_symbols_total_high[0x20];
2031 u8 rs_fec_corrected_symbols_total_low[0x20];
2033 u8 rs_fec_corrected_symbols_lane0_high[0x20];
2035 u8 rs_fec_corrected_symbols_lane0_low[0x20];
2037 u8 rs_fec_corrected_symbols_lane1_high[0x20];
2039 u8 rs_fec_corrected_symbols_lane1_low[0x20];
2041 u8 rs_fec_corrected_symbols_lane2_high[0x20];
2043 u8 rs_fec_corrected_symbols_lane2_low[0x20];
2045 u8 rs_fec_corrected_symbols_lane3_high[0x20];
2047 u8 rs_fec_corrected_symbols_lane3_low[0x20];
2049 u8 link_down_events[0x20];
2051 u8 successful_recovery_events[0x20];
2053 u8 reserved_at_640[0x180];
2056 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
2057 u8 time_since_last_clear_high[0x20];
2059 u8 time_since_last_clear_low[0x20];
2061 u8 phy_received_bits_high[0x20];
2063 u8 phy_received_bits_low[0x20];
2065 u8 phy_symbol_errors_high[0x20];
2067 u8 phy_symbol_errors_low[0x20];
2069 u8 phy_corrected_bits_high[0x20];
2071 u8 phy_corrected_bits_low[0x20];
2073 u8 phy_corrected_bits_lane0_high[0x20];
2075 u8 phy_corrected_bits_lane0_low[0x20];
2077 u8 phy_corrected_bits_lane1_high[0x20];
2079 u8 phy_corrected_bits_lane1_low[0x20];
2081 u8 phy_corrected_bits_lane2_high[0x20];
2083 u8 phy_corrected_bits_lane2_low[0x20];
2085 u8 phy_corrected_bits_lane3_high[0x20];
2087 u8 phy_corrected_bits_lane3_low[0x20];
2089 u8 reserved_at_200[0x5c0];
2092 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
2093 u8 symbol_error_counter[0x10];
2095 u8 link_error_recovery_counter[0x8];
2097 u8 link_downed_counter[0x8];
2099 u8 port_rcv_errors[0x10];
2101 u8 port_rcv_remote_physical_errors[0x10];
2103 u8 port_rcv_switch_relay_errors[0x10];
2105 u8 port_xmit_discards[0x10];
2107 u8 port_xmit_constraint_errors[0x8];
2109 u8 port_rcv_constraint_errors[0x8];
2111 u8 reserved_at_70[0x8];
2113 u8 link_overrun_errors[0x8];
2115 u8 reserved_at_80[0x10];
2117 u8 vl_15_dropped[0x10];
2119 u8 reserved_at_a0[0x80];
2121 u8 port_xmit_wait[0x20];
2124 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits {
2125 u8 transmit_queue_high[0x20];
2127 u8 transmit_queue_low[0x20];
2129 u8 no_buffer_discard_uc_high[0x20];
2131 u8 no_buffer_discard_uc_low[0x20];
2133 u8 reserved_at_80[0x740];
2136 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits {
2137 u8 wred_discard_high[0x20];
2139 u8 wred_discard_low[0x20];
2141 u8 ecn_marked_tc_high[0x20];
2143 u8 ecn_marked_tc_low[0x20];
2145 u8 reserved_at_80[0x740];
2148 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
2149 u8 rx_octets_high[0x20];
2151 u8 rx_octets_low[0x20];
2153 u8 reserved_at_40[0xc0];
2155 u8 rx_frames_high[0x20];
2157 u8 rx_frames_low[0x20];
2159 u8 tx_octets_high[0x20];
2161 u8 tx_octets_low[0x20];
2163 u8 reserved_at_180[0xc0];
2165 u8 tx_frames_high[0x20];
2167 u8 tx_frames_low[0x20];
2169 u8 rx_pause_high[0x20];
2171 u8 rx_pause_low[0x20];
2173 u8 rx_pause_duration_high[0x20];
2175 u8 rx_pause_duration_low[0x20];
2177 u8 tx_pause_high[0x20];
2179 u8 tx_pause_low[0x20];
2181 u8 tx_pause_duration_high[0x20];
2183 u8 tx_pause_duration_low[0x20];
2185 u8 rx_pause_transition_high[0x20];
2187 u8 rx_pause_transition_low[0x20];
2189 u8 rx_discards_high[0x20];
2191 u8 rx_discards_low[0x20];
2193 u8 device_stall_minor_watermark_cnt_high[0x20];
2195 u8 device_stall_minor_watermark_cnt_low[0x20];
2197 u8 device_stall_critical_watermark_cnt_high[0x20];
2199 u8 device_stall_critical_watermark_cnt_low[0x20];
2201 u8 reserved_at_480[0x340];
2204 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
2205 u8 port_transmit_wait_high[0x20];
2207 u8 port_transmit_wait_low[0x20];
2209 u8 reserved_at_40[0x100];
2211 u8 rx_buffer_almost_full_high[0x20];
2213 u8 rx_buffer_almost_full_low[0x20];
2215 u8 rx_buffer_full_high[0x20];
2217 u8 rx_buffer_full_low[0x20];
2219 u8 rx_icrc_encapsulated_high[0x20];
2221 u8 rx_icrc_encapsulated_low[0x20];
2223 u8 reserved_at_200[0x5c0];
2226 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
2227 u8 dot3stats_alignment_errors_high[0x20];
2229 u8 dot3stats_alignment_errors_low[0x20];
2231 u8 dot3stats_fcs_errors_high[0x20];
2233 u8 dot3stats_fcs_errors_low[0x20];
2235 u8 dot3stats_single_collision_frames_high[0x20];
2237 u8 dot3stats_single_collision_frames_low[0x20];
2239 u8 dot3stats_multiple_collision_frames_high[0x20];
2241 u8 dot3stats_multiple_collision_frames_low[0x20];
2243 u8 dot3stats_sqe_test_errors_high[0x20];
2245 u8 dot3stats_sqe_test_errors_low[0x20];
2247 u8 dot3stats_deferred_transmissions_high[0x20];
2249 u8 dot3stats_deferred_transmissions_low[0x20];
2251 u8 dot3stats_late_collisions_high[0x20];
2253 u8 dot3stats_late_collisions_low[0x20];
2255 u8 dot3stats_excessive_collisions_high[0x20];
2257 u8 dot3stats_excessive_collisions_low[0x20];
2259 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
2261 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
2263 u8 dot3stats_carrier_sense_errors_high[0x20];
2265 u8 dot3stats_carrier_sense_errors_low[0x20];
2267 u8 dot3stats_frame_too_longs_high[0x20];
2269 u8 dot3stats_frame_too_longs_low[0x20];
2271 u8 dot3stats_internal_mac_receive_errors_high[0x20];
2273 u8 dot3stats_internal_mac_receive_errors_low[0x20];
2275 u8 dot3stats_symbol_errors_high[0x20];
2277 u8 dot3stats_symbol_errors_low[0x20];
2279 u8 dot3control_in_unknown_opcodes_high[0x20];
2281 u8 dot3control_in_unknown_opcodes_low[0x20];
2283 u8 dot3in_pause_frames_high[0x20];
2285 u8 dot3in_pause_frames_low[0x20];
2287 u8 dot3out_pause_frames_high[0x20];
2289 u8 dot3out_pause_frames_low[0x20];
2291 u8 reserved_at_400[0x3c0];
2294 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2295 u8 ether_stats_drop_events_high[0x20];
2297 u8 ether_stats_drop_events_low[0x20];
2299 u8 ether_stats_octets_high[0x20];
2301 u8 ether_stats_octets_low[0x20];
2303 u8 ether_stats_pkts_high[0x20];
2305 u8 ether_stats_pkts_low[0x20];
2307 u8 ether_stats_broadcast_pkts_high[0x20];
2309 u8 ether_stats_broadcast_pkts_low[0x20];
2311 u8 ether_stats_multicast_pkts_high[0x20];
2313 u8 ether_stats_multicast_pkts_low[0x20];
2315 u8 ether_stats_crc_align_errors_high[0x20];
2317 u8 ether_stats_crc_align_errors_low[0x20];
2319 u8 ether_stats_undersize_pkts_high[0x20];
2321 u8 ether_stats_undersize_pkts_low[0x20];
2323 u8 ether_stats_oversize_pkts_high[0x20];
2325 u8 ether_stats_oversize_pkts_low[0x20];
2327 u8 ether_stats_fragments_high[0x20];
2329 u8 ether_stats_fragments_low[0x20];
2331 u8 ether_stats_jabbers_high[0x20];
2333 u8 ether_stats_jabbers_low[0x20];
2335 u8 ether_stats_collisions_high[0x20];
2337 u8 ether_stats_collisions_low[0x20];
2339 u8 ether_stats_pkts64octets_high[0x20];
2341 u8 ether_stats_pkts64octets_low[0x20];
2343 u8 ether_stats_pkts65to127octets_high[0x20];
2345 u8 ether_stats_pkts65to127octets_low[0x20];
2347 u8 ether_stats_pkts128to255octets_high[0x20];
2349 u8 ether_stats_pkts128to255octets_low[0x20];
2351 u8 ether_stats_pkts256to511octets_high[0x20];
2353 u8 ether_stats_pkts256to511octets_low[0x20];
2355 u8 ether_stats_pkts512to1023octets_high[0x20];
2357 u8 ether_stats_pkts512to1023octets_low[0x20];
2359 u8 ether_stats_pkts1024to1518octets_high[0x20];
2361 u8 ether_stats_pkts1024to1518octets_low[0x20];
2363 u8 ether_stats_pkts1519to2047octets_high[0x20];
2365 u8 ether_stats_pkts1519to2047octets_low[0x20];
2367 u8 ether_stats_pkts2048to4095octets_high[0x20];
2369 u8 ether_stats_pkts2048to4095octets_low[0x20];
2371 u8 ether_stats_pkts4096to8191octets_high[0x20];
2373 u8 ether_stats_pkts4096to8191octets_low[0x20];
2375 u8 ether_stats_pkts8192to10239octets_high[0x20];
2377 u8 ether_stats_pkts8192to10239octets_low[0x20];
2379 u8 reserved_at_540[0x280];
2382 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2383 u8 if_in_octets_high[0x20];
2385 u8 if_in_octets_low[0x20];
2387 u8 if_in_ucast_pkts_high[0x20];
2389 u8 if_in_ucast_pkts_low[0x20];
2391 u8 if_in_discards_high[0x20];
2393 u8 if_in_discards_low[0x20];
2395 u8 if_in_errors_high[0x20];
2397 u8 if_in_errors_low[0x20];
2399 u8 if_in_unknown_protos_high[0x20];
2401 u8 if_in_unknown_protos_low[0x20];
2403 u8 if_out_octets_high[0x20];
2405 u8 if_out_octets_low[0x20];
2407 u8 if_out_ucast_pkts_high[0x20];
2409 u8 if_out_ucast_pkts_low[0x20];
2411 u8 if_out_discards_high[0x20];
2413 u8 if_out_discards_low[0x20];
2415 u8 if_out_errors_high[0x20];
2417 u8 if_out_errors_low[0x20];
2419 u8 if_in_multicast_pkts_high[0x20];
2421 u8 if_in_multicast_pkts_low[0x20];
2423 u8 if_in_broadcast_pkts_high[0x20];
2425 u8 if_in_broadcast_pkts_low[0x20];
2427 u8 if_out_multicast_pkts_high[0x20];
2429 u8 if_out_multicast_pkts_low[0x20];
2431 u8 if_out_broadcast_pkts_high[0x20];
2433 u8 if_out_broadcast_pkts_low[0x20];
2435 u8 reserved_at_340[0x480];
2438 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2439 u8 a_frames_transmitted_ok_high[0x20];
2441 u8 a_frames_transmitted_ok_low[0x20];
2443 u8 a_frames_received_ok_high[0x20];
2445 u8 a_frames_received_ok_low[0x20];
2447 u8 a_frame_check_sequence_errors_high[0x20];
2449 u8 a_frame_check_sequence_errors_low[0x20];
2451 u8 a_alignment_errors_high[0x20];
2453 u8 a_alignment_errors_low[0x20];
2455 u8 a_octets_transmitted_ok_high[0x20];
2457 u8 a_octets_transmitted_ok_low[0x20];
2459 u8 a_octets_received_ok_high[0x20];
2461 u8 a_octets_received_ok_low[0x20];
2463 u8 a_multicast_frames_xmitted_ok_high[0x20];
2465 u8 a_multicast_frames_xmitted_ok_low[0x20];
2467 u8 a_broadcast_frames_xmitted_ok_high[0x20];
2469 u8 a_broadcast_frames_xmitted_ok_low[0x20];
2471 u8 a_multicast_frames_received_ok_high[0x20];
2473 u8 a_multicast_frames_received_ok_low[0x20];
2475 u8 a_broadcast_frames_received_ok_high[0x20];
2477 u8 a_broadcast_frames_received_ok_low[0x20];
2479 u8 a_in_range_length_errors_high[0x20];
2481 u8 a_in_range_length_errors_low[0x20];
2483 u8 a_out_of_range_length_field_high[0x20];
2485 u8 a_out_of_range_length_field_low[0x20];
2487 u8 a_frame_too_long_errors_high[0x20];
2489 u8 a_frame_too_long_errors_low[0x20];
2491 u8 a_symbol_error_during_carrier_high[0x20];
2493 u8 a_symbol_error_during_carrier_low[0x20];
2495 u8 a_mac_control_frames_transmitted_high[0x20];
2497 u8 a_mac_control_frames_transmitted_low[0x20];
2499 u8 a_mac_control_frames_received_high[0x20];
2501 u8 a_mac_control_frames_received_low[0x20];
2503 u8 a_unsupported_opcodes_received_high[0x20];
2505 u8 a_unsupported_opcodes_received_low[0x20];
2507 u8 a_pause_mac_ctrl_frames_received_high[0x20];
2509 u8 a_pause_mac_ctrl_frames_received_low[0x20];
2511 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
2513 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
2515 u8 reserved_at_4c0[0x300];
2518 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2519 u8 life_time_counter_high[0x20];
2521 u8 life_time_counter_low[0x20];
2527 u8 l0_to_recovery_eieos[0x20];
2529 u8 l0_to_recovery_ts[0x20];
2531 u8 l0_to_recovery_framing[0x20];
2533 u8 l0_to_recovery_retrain[0x20];
2535 u8 crc_error_dllp[0x20];
2537 u8 crc_error_tlp[0x20];
2539 u8 tx_overflow_buffer_pkt_high[0x20];
2541 u8 tx_overflow_buffer_pkt_low[0x20];
2543 u8 outbound_stalled_reads[0x20];
2545 u8 outbound_stalled_writes[0x20];
2547 u8 outbound_stalled_reads_events[0x20];
2549 u8 outbound_stalled_writes_events[0x20];
2551 u8 reserved_at_200[0x5c0];
2554 struct mlx5_ifc_cmd_inter_comp_event_bits {
2555 u8 command_completion_vector[0x20];
2557 u8 reserved_at_20[0xc0];
2560 struct mlx5_ifc_stall_vl_event_bits {
2561 u8 reserved_at_0[0x18];
2563 u8 reserved_at_19[0x3];
2566 u8 reserved_at_20[0xa0];
2569 struct mlx5_ifc_db_bf_congestion_event_bits {
2570 u8 event_subtype[0x8];
2571 u8 reserved_at_8[0x8];
2572 u8 congestion_level[0x8];
2573 u8 reserved_at_18[0x8];
2575 u8 reserved_at_20[0xa0];
2578 struct mlx5_ifc_gpio_event_bits {
2579 u8 reserved_at_0[0x60];
2581 u8 gpio_event_hi[0x20];
2583 u8 gpio_event_lo[0x20];
2585 u8 reserved_at_a0[0x40];
2588 struct mlx5_ifc_port_state_change_event_bits {
2589 u8 reserved_at_0[0x40];
2592 u8 reserved_at_44[0x1c];
2594 u8 reserved_at_60[0x80];
2597 struct mlx5_ifc_dropped_packet_logged_bits {
2598 u8 reserved_at_0[0xe0];
2602 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2603 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2606 struct mlx5_ifc_cq_error_bits {
2607 u8 reserved_at_0[0x8];
2610 u8 reserved_at_20[0x20];
2612 u8 reserved_at_40[0x18];
2615 u8 reserved_at_60[0x80];
2618 struct mlx5_ifc_rdma_page_fault_event_bits {
2619 u8 bytes_committed[0x20];
2623 u8 reserved_at_40[0x10];
2624 u8 packet_len[0x10];
2626 u8 rdma_op_len[0x20];
2630 u8 reserved_at_c0[0x5];
2637 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2638 u8 bytes_committed[0x20];
2640 u8 reserved_at_20[0x10];
2643 u8 reserved_at_40[0x10];
2646 u8 reserved_at_60[0x60];
2648 u8 reserved_at_c0[0x5];
2655 struct mlx5_ifc_qp_events_bits {
2656 u8 reserved_at_0[0xa0];
2659 u8 reserved_at_a8[0x18];
2661 u8 reserved_at_c0[0x8];
2662 u8 qpn_rqn_sqn[0x18];
2665 struct mlx5_ifc_dct_events_bits {
2666 u8 reserved_at_0[0xc0];
2668 u8 reserved_at_c0[0x8];
2669 u8 dct_number[0x18];
2672 struct mlx5_ifc_comp_event_bits {
2673 u8 reserved_at_0[0xc0];
2675 u8 reserved_at_c0[0x8];
2680 MLX5_QPC_STATE_RST = 0x0,
2681 MLX5_QPC_STATE_INIT = 0x1,
2682 MLX5_QPC_STATE_RTR = 0x2,
2683 MLX5_QPC_STATE_RTS = 0x3,
2684 MLX5_QPC_STATE_SQER = 0x4,
2685 MLX5_QPC_STATE_ERR = 0x6,
2686 MLX5_QPC_STATE_SQD = 0x7,
2687 MLX5_QPC_STATE_SUSPENDED = 0x9,
2691 MLX5_QPC_ST_RC = 0x0,
2692 MLX5_QPC_ST_UC = 0x1,
2693 MLX5_QPC_ST_UD = 0x2,
2694 MLX5_QPC_ST_XRC = 0x3,
2695 MLX5_QPC_ST_DCI = 0x5,
2696 MLX5_QPC_ST_QP0 = 0x7,
2697 MLX5_QPC_ST_QP1 = 0x8,
2698 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2699 MLX5_QPC_ST_REG_UMR = 0xc,
2703 MLX5_QPC_PM_STATE_ARMED = 0x0,
2704 MLX5_QPC_PM_STATE_REARM = 0x1,
2705 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2706 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2710 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2714 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2715 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2719 MLX5_QPC_MTU_256_BYTES = 0x1,
2720 MLX5_QPC_MTU_512_BYTES = 0x2,
2721 MLX5_QPC_MTU_1K_BYTES = 0x3,
2722 MLX5_QPC_MTU_2K_BYTES = 0x4,
2723 MLX5_QPC_MTU_4K_BYTES = 0x5,
2724 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2728 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2729 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2730 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2731 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2732 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2733 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2734 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2735 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2739 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2740 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2741 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2745 MLX5_QPC_CS_RES_DISABLE = 0x0,
2746 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2747 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2750 struct mlx5_ifc_qpc_bits {
2752 u8 lag_tx_port_affinity[0x4];
2754 u8 reserved_at_10[0x3];
2756 u8 reserved_at_15[0x1];
2757 u8 req_e2e_credit_mode[0x2];
2758 u8 offload_type[0x4];
2759 u8 end_padding_mode[0x2];
2760 u8 reserved_at_1e[0x2];
2762 u8 wq_signature[0x1];
2763 u8 block_lb_mc[0x1];
2764 u8 atomic_like_write_en[0x1];
2765 u8 latency_sensitive[0x1];
2766 u8 reserved_at_24[0x1];
2767 u8 drain_sigerr[0x1];
2768 u8 reserved_at_26[0x2];
2772 u8 log_msg_max[0x5];
2773 u8 reserved_at_48[0x1];
2774 u8 log_rq_size[0x4];
2775 u8 log_rq_stride[0x3];
2777 u8 log_sq_size[0x4];
2778 u8 reserved_at_55[0x6];
2780 u8 ulp_stateless_offload_mode[0x4];
2782 u8 counter_set_id[0x8];
2785 u8 reserved_at_80[0x8];
2786 u8 user_index[0x18];
2788 u8 reserved_at_a0[0x3];
2789 u8 log_page_size[0x5];
2790 u8 remote_qpn[0x18];
2792 struct mlx5_ifc_ads_bits primary_address_path;
2794 struct mlx5_ifc_ads_bits secondary_address_path;
2796 u8 log_ack_req_freq[0x4];
2797 u8 reserved_at_384[0x4];
2798 u8 log_sra_max[0x3];
2799 u8 reserved_at_38b[0x2];
2800 u8 retry_count[0x3];
2802 u8 reserved_at_393[0x1];
2804 u8 cur_rnr_retry[0x3];
2805 u8 cur_retry_count[0x3];
2806 u8 reserved_at_39b[0x5];
2808 u8 reserved_at_3a0[0x20];
2810 u8 reserved_at_3c0[0x8];
2811 u8 next_send_psn[0x18];
2813 u8 reserved_at_3e0[0x8];
2816 u8 reserved_at_400[0x8];
2819 u8 reserved_at_420[0x20];
2821 u8 reserved_at_440[0x8];
2822 u8 last_acked_psn[0x18];
2824 u8 reserved_at_460[0x8];
2827 u8 reserved_at_480[0x8];
2828 u8 log_rra_max[0x3];
2829 u8 reserved_at_48b[0x1];
2830 u8 atomic_mode[0x4];
2834 u8 reserved_at_493[0x1];
2835 u8 page_offset[0x6];
2836 u8 reserved_at_49a[0x3];
2837 u8 cd_slave_receive[0x1];
2838 u8 cd_slave_send[0x1];
2841 u8 reserved_at_4a0[0x3];
2842 u8 min_rnr_nak[0x5];
2843 u8 next_rcv_psn[0x18];
2845 u8 reserved_at_4c0[0x8];
2848 u8 reserved_at_4e0[0x8];
2855 u8 reserved_at_560[0x5];
2857 u8 srqn_rmpn_xrqn[0x18];
2859 u8 reserved_at_580[0x8];
2862 u8 hw_sq_wqebb_counter[0x10];
2863 u8 sw_sq_wqebb_counter[0x10];
2865 u8 hw_rq_counter[0x20];
2867 u8 sw_rq_counter[0x20];
2869 u8 reserved_at_600[0x20];
2871 u8 reserved_at_620[0xf];
2876 u8 dc_access_key[0x40];
2878 u8 reserved_at_680[0x3];
2879 u8 dbr_umem_valid[0x1];
2881 u8 reserved_at_684[0xbc];
2884 struct mlx5_ifc_roce_addr_layout_bits {
2885 u8 source_l3_address[16][0x8];
2887 u8 reserved_at_80[0x3];
2890 u8 source_mac_47_32[0x10];
2892 u8 source_mac_31_0[0x20];
2894 u8 reserved_at_c0[0x14];
2895 u8 roce_l3_type[0x4];
2896 u8 roce_version[0x8];
2898 u8 reserved_at_e0[0x20];
2901 union mlx5_ifc_hca_cap_union_bits {
2902 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2903 struct mlx5_ifc_odp_cap_bits odp_cap;
2904 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2905 struct mlx5_ifc_roce_cap_bits roce_cap;
2906 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2907 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2908 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2909 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2910 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2911 struct mlx5_ifc_qos_cap_bits qos_cap;
2912 struct mlx5_ifc_debug_cap_bits debug_cap;
2913 struct mlx5_ifc_fpga_cap_bits fpga_cap;
2914 struct mlx5_ifc_tls_cap_bits tls_cap;
2915 struct mlx5_ifc_device_mem_cap_bits device_mem_cap;
2916 struct mlx5_ifc_device_virtio_emulation_cap_bits virtio_emulation_cap;
2917 u8 reserved_at_0[0x8000];
2921 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2922 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2923 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2924 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2925 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2926 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2927 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
2928 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
2929 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2930 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
2931 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2935 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0,
2936 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1,
2937 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2,
2940 struct mlx5_ifc_vlan_bits {
2947 struct mlx5_ifc_flow_context_bits {
2948 struct mlx5_ifc_vlan_bits push_vlan;
2952 u8 reserved_at_40[0x8];
2955 u8 reserved_at_60[0x10];
2958 u8 extended_destination[0x1];
2959 u8 reserved_at_81[0x1];
2960 u8 flow_source[0x2];
2961 u8 reserved_at_84[0x4];
2962 u8 destination_list_size[0x18];
2964 u8 reserved_at_a0[0x8];
2965 u8 flow_counter_list_size[0x18];
2967 u8 packet_reformat_id[0x20];
2969 u8 modify_header_id[0x20];
2971 struct mlx5_ifc_vlan_bits push_vlan_2;
2973 u8 reserved_at_120[0xe0];
2975 struct mlx5_ifc_fte_match_param_bits match_value;
2977 u8 reserved_at_1200[0x600];
2979 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2983 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2984 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2987 struct mlx5_ifc_xrc_srqc_bits {
2989 u8 log_xrc_srq_size[0x4];
2990 u8 reserved_at_8[0x18];
2992 u8 wq_signature[0x1];
2994 u8 reserved_at_22[0x1];
2996 u8 basic_cyclic_rcv_wqe[0x1];
2997 u8 log_rq_stride[0x3];
3000 u8 page_offset[0x6];
3001 u8 reserved_at_46[0x1];
3002 u8 dbr_umem_valid[0x1];
3005 u8 reserved_at_60[0x20];
3007 u8 user_index_equal_xrc_srqn[0x1];
3008 u8 reserved_at_81[0x1];
3009 u8 log_page_size[0x6];
3010 u8 user_index[0x18];
3012 u8 reserved_at_a0[0x20];
3014 u8 reserved_at_c0[0x8];
3020 u8 reserved_at_100[0x40];
3022 u8 db_record_addr_h[0x20];
3024 u8 db_record_addr_l[0x1e];
3025 u8 reserved_at_17e[0x2];
3027 u8 reserved_at_180[0x80];
3030 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
3031 u8 counter_error_queues[0x20];
3033 u8 total_error_queues[0x20];
3035 u8 send_queue_priority_update_flow[0x20];
3037 u8 reserved_at_60[0x20];
3039 u8 nic_receive_steering_discard[0x40];
3041 u8 receive_discard_vport_down[0x40];
3043 u8 transmit_discard_vport_down[0x40];
3045 u8 reserved_at_140[0xa0];
3047 u8 internal_rq_out_of_buffer[0x20];
3049 u8 reserved_at_200[0xe00];
3052 struct mlx5_ifc_traffic_counter_bits {
3058 struct mlx5_ifc_tisc_bits {
3059 u8 strict_lag_tx_port_affinity[0x1];
3061 u8 reserved_at_2[0x2];
3062 u8 lag_tx_port_affinity[0x04];
3064 u8 reserved_at_8[0x4];
3066 u8 reserved_at_10[0x10];
3068 u8 reserved_at_20[0x100];
3070 u8 reserved_at_120[0x8];
3071 u8 transport_domain[0x18];
3073 u8 reserved_at_140[0x8];
3074 u8 underlay_qpn[0x18];
3076 u8 reserved_at_160[0x8];
3079 u8 reserved_at_180[0x380];
3083 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
3084 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
3088 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
3089 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
3093 MLX5_RX_HASH_FN_NONE = 0x0,
3094 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
3095 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
3099 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
3100 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
3103 struct mlx5_ifc_tirc_bits {
3104 u8 reserved_at_0[0x20];
3107 u8 reserved_at_24[0x1c];
3109 u8 reserved_at_40[0x40];
3111 u8 reserved_at_80[0x4];
3112 u8 lro_timeout_period_usecs[0x10];
3113 u8 lro_enable_mask[0x4];
3114 u8 lro_max_ip_payload_size[0x8];
3116 u8 reserved_at_a0[0x40];
3118 u8 reserved_at_e0[0x8];
3119 u8 inline_rqn[0x18];
3121 u8 rx_hash_symmetric[0x1];
3122 u8 reserved_at_101[0x1];
3123 u8 tunneled_offload_en[0x1];
3124 u8 reserved_at_103[0x5];
3125 u8 indirect_table[0x18];
3128 u8 reserved_at_124[0x2];
3129 u8 self_lb_block[0x2];
3130 u8 transport_domain[0x18];
3132 u8 rx_hash_toeplitz_key[10][0x20];
3134 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
3136 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
3138 u8 reserved_at_2c0[0x4c0];
3142 MLX5_SRQC_STATE_GOOD = 0x0,
3143 MLX5_SRQC_STATE_ERROR = 0x1,
3146 struct mlx5_ifc_srqc_bits {
3148 u8 log_srq_size[0x4];
3149 u8 reserved_at_8[0x18];
3151 u8 wq_signature[0x1];
3153 u8 reserved_at_22[0x1];
3155 u8 reserved_at_24[0x1];
3156 u8 log_rq_stride[0x3];
3159 u8 page_offset[0x6];
3160 u8 reserved_at_46[0x2];
3163 u8 reserved_at_60[0x20];
3165 u8 reserved_at_80[0x2];
3166 u8 log_page_size[0x6];
3167 u8 reserved_at_88[0x18];
3169 u8 reserved_at_a0[0x20];
3171 u8 reserved_at_c0[0x8];
3177 u8 reserved_at_100[0x40];
3181 u8 reserved_at_180[0x80];
3185 MLX5_SQC_STATE_RST = 0x0,
3186 MLX5_SQC_STATE_RDY = 0x1,
3187 MLX5_SQC_STATE_ERR = 0x3,
3190 struct mlx5_ifc_sqc_bits {
3194 u8 flush_in_error_en[0x1];
3195 u8 allow_multi_pkt_send_wqe[0x1];
3196 u8 min_wqe_inline_mode[0x3];
3201 u8 reserved_at_f[0x11];
3203 u8 reserved_at_20[0x8];
3204 u8 user_index[0x18];
3206 u8 reserved_at_40[0x8];
3209 u8 reserved_at_60[0x8];
3210 u8 hairpin_peer_rq[0x18];
3212 u8 reserved_at_80[0x10];
3213 u8 hairpin_peer_vhca[0x10];
3215 u8 reserved_at_a0[0x50];
3217 u8 packet_pacing_rate_limit_index[0x10];
3218 u8 tis_lst_sz[0x10];
3219 u8 reserved_at_110[0x10];
3221 u8 reserved_at_120[0x40];
3223 u8 reserved_at_160[0x8];
3226 struct mlx5_ifc_wq_bits wq;
3230 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
3231 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
3232 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
3233 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
3237 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0,
3238 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1,
3239 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2,
3240 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3,
3243 struct mlx5_ifc_scheduling_context_bits {
3244 u8 element_type[0x8];
3245 u8 reserved_at_8[0x18];
3247 u8 element_attributes[0x20];
3249 u8 parent_element_id[0x20];
3251 u8 reserved_at_60[0x40];
3255 u8 max_average_bw[0x20];
3257 u8 reserved_at_e0[0x120];
3260 struct mlx5_ifc_rqtc_bits {
3261 u8 reserved_at_0[0xa0];
3263 u8 reserved_at_a0[0x10];
3264 u8 rqt_max_size[0x10];
3266 u8 reserved_at_c0[0x10];
3267 u8 rqt_actual_size[0x10];
3269 u8 reserved_at_e0[0x6a0];
3271 struct mlx5_ifc_rq_num_bits rq_num[0];
3275 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
3276 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
3280 MLX5_RQC_STATE_RST = 0x0,
3281 MLX5_RQC_STATE_RDY = 0x1,
3282 MLX5_RQC_STATE_ERR = 0x3,
3285 struct mlx5_ifc_rqc_bits {
3287 u8 delay_drop_en[0x1];
3288 u8 scatter_fcs[0x1];
3290 u8 mem_rq_type[0x4];
3292 u8 reserved_at_c[0x1];
3293 u8 flush_in_error_en[0x1];
3295 u8 reserved_at_f[0x11];
3297 u8 reserved_at_20[0x8];
3298 u8 user_index[0x18];
3300 u8 reserved_at_40[0x8];
3303 u8 counter_set_id[0x8];
3304 u8 reserved_at_68[0x18];
3306 u8 reserved_at_80[0x8];
3309 u8 reserved_at_a0[0x8];
3310 u8 hairpin_peer_sq[0x18];
3312 u8 reserved_at_c0[0x10];
3313 u8 hairpin_peer_vhca[0x10];
3315 u8 reserved_at_e0[0xa0];
3317 struct mlx5_ifc_wq_bits wq;
3321 MLX5_RMPC_STATE_RDY = 0x1,
3322 MLX5_RMPC_STATE_ERR = 0x3,
3325 struct mlx5_ifc_rmpc_bits {
3326 u8 reserved_at_0[0x8];
3328 u8 reserved_at_c[0x14];
3330 u8 basic_cyclic_rcv_wqe[0x1];
3331 u8 reserved_at_21[0x1f];
3333 u8 reserved_at_40[0x140];
3335 struct mlx5_ifc_wq_bits wq;
3338 struct mlx5_ifc_nic_vport_context_bits {
3339 u8 reserved_at_0[0x5];
3340 u8 min_wqe_inline_mode[0x3];
3341 u8 reserved_at_8[0x15];
3342 u8 disable_mc_local_lb[0x1];
3343 u8 disable_uc_local_lb[0x1];
3346 u8 arm_change_event[0x1];
3347 u8 reserved_at_21[0x1a];
3348 u8 event_on_mtu[0x1];
3349 u8 event_on_promisc_change[0x1];
3350 u8 event_on_vlan_change[0x1];
3351 u8 event_on_mc_address_change[0x1];
3352 u8 event_on_uc_address_change[0x1];
3354 u8 reserved_at_40[0xc];
3356 u8 affiliation_criteria[0x4];
3357 u8 affiliated_vhca_id[0x10];
3359 u8 reserved_at_60[0xd0];
3363 u8 system_image_guid[0x40];
3367 u8 reserved_at_200[0x140];
3368 u8 qkey_violation_counter[0x10];
3369 u8 reserved_at_350[0x430];
3373 u8 promisc_all[0x1];
3374 u8 reserved_at_783[0x2];
3375 u8 allowed_list_type[0x3];
3376 u8 reserved_at_788[0xc];
3377 u8 allowed_list_size[0xc];
3379 struct mlx5_ifc_mac_address_layout_bits permanent_address;
3381 u8 reserved_at_7e0[0x20];
3383 u8 current_uc_mac_address[0][0x40];
3387 MLX5_MKC_ACCESS_MODE_PA = 0x0,
3388 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
3389 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
3390 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
3391 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3392 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3395 struct mlx5_ifc_mkc_bits {
3396 u8 reserved_at_0[0x1];
3398 u8 reserved_at_2[0x1];
3399 u8 access_mode_4_2[0x3];
3400 u8 reserved_at_6[0x7];
3401 u8 relaxed_ordering_write[0x1];
3402 u8 reserved_at_e[0x1];
3403 u8 small_fence_on_rdma_read_response[0x1];
3410 u8 access_mode_1_0[0x2];
3411 u8 reserved_at_18[0x8];
3416 u8 reserved_at_40[0x20];
3421 u8 reserved_at_63[0x2];
3422 u8 expected_sigerr_count[0x1];
3423 u8 reserved_at_66[0x1];
3427 u8 start_addr[0x40];
3431 u8 bsf_octword_size[0x20];
3433 u8 reserved_at_120[0x80];
3435 u8 translations_octword_size[0x20];
3437 u8 reserved_at_1c0[0x19];
3438 u8 relaxed_ordering_read[0x1];
3439 u8 reserved_at_1d9[0x1];
3440 u8 log_page_size[0x5];
3442 u8 reserved_at_1e0[0x20];
3445 struct mlx5_ifc_pkey_bits {
3446 u8 reserved_at_0[0x10];
3450 struct mlx5_ifc_array128_auto_bits {
3451 u8 array128_auto[16][0x8];
3454 struct mlx5_ifc_hca_vport_context_bits {
3455 u8 field_select[0x20];
3457 u8 reserved_at_20[0xe0];
3459 u8 sm_virt_aware[0x1];
3462 u8 grh_required[0x1];
3463 u8 reserved_at_104[0xc];
3464 u8 port_physical_state[0x4];
3465 u8 vport_state_policy[0x4];
3467 u8 vport_state[0x4];
3469 u8 reserved_at_120[0x20];
3471 u8 system_image_guid[0x40];
3479 u8 cap_mask1_field_select[0x20];
3483 u8 cap_mask2_field_select[0x20];
3485 u8 reserved_at_280[0x80];
3488 u8 reserved_at_310[0x4];
3489 u8 init_type_reply[0x4];
3491 u8 subnet_timeout[0x5];
3495 u8 reserved_at_334[0xc];
3497 u8 qkey_violation_counter[0x10];
3498 u8 pkey_violation_counter[0x10];
3500 u8 reserved_at_360[0xca0];
3503 struct mlx5_ifc_esw_vport_context_bits {
3504 u8 fdb_to_vport_reg_c[0x1];
3505 u8 reserved_at_1[0x2];
3506 u8 vport_svlan_strip[0x1];
3507 u8 vport_cvlan_strip[0x1];
3508 u8 vport_svlan_insert[0x1];
3509 u8 vport_cvlan_insert[0x2];
3510 u8 fdb_to_vport_reg_c_id[0x8];
3511 u8 reserved_at_10[0x10];
3513 u8 reserved_at_20[0x20];
3522 u8 reserved_at_60[0x720];
3524 u8 sw_steering_vport_icm_address_rx[0x40];
3526 u8 sw_steering_vport_icm_address_tx[0x40];
3530 MLX5_EQC_STATUS_OK = 0x0,
3531 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3535 MLX5_EQC_ST_ARMED = 0x9,
3536 MLX5_EQC_ST_FIRED = 0xa,
3539 struct mlx5_ifc_eqc_bits {
3541 u8 reserved_at_4[0x9];
3544 u8 reserved_at_f[0x5];
3546 u8 reserved_at_18[0x8];
3548 u8 reserved_at_20[0x20];
3550 u8 reserved_at_40[0x14];
3551 u8 page_offset[0x6];
3552 u8 reserved_at_5a[0x6];
3554 u8 reserved_at_60[0x3];
3555 u8 log_eq_size[0x5];
3558 u8 reserved_at_80[0x20];
3560 u8 reserved_at_a0[0x18];
3563 u8 reserved_at_c0[0x3];
3564 u8 log_page_size[0x5];
3565 u8 reserved_at_c8[0x18];
3567 u8 reserved_at_e0[0x60];
3569 u8 reserved_at_140[0x8];
3570 u8 consumer_counter[0x18];
3572 u8 reserved_at_160[0x8];
3573 u8 producer_counter[0x18];
3575 u8 reserved_at_180[0x80];
3579 MLX5_DCTC_STATE_ACTIVE = 0x0,
3580 MLX5_DCTC_STATE_DRAINING = 0x1,
3581 MLX5_DCTC_STATE_DRAINED = 0x2,
3585 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3586 MLX5_DCTC_CS_RES_NA = 0x1,
3587 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3591 MLX5_DCTC_MTU_256_BYTES = 0x1,
3592 MLX5_DCTC_MTU_512_BYTES = 0x2,
3593 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3594 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3595 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3598 struct mlx5_ifc_dctc_bits {
3599 u8 reserved_at_0[0x4];
3601 u8 reserved_at_8[0x18];
3603 u8 reserved_at_20[0x8];
3604 u8 user_index[0x18];
3606 u8 reserved_at_40[0x8];
3609 u8 counter_set_id[0x8];
3610 u8 atomic_mode[0x4];
3614 u8 atomic_like_write_en[0x1];
3615 u8 latency_sensitive[0x1];
3618 u8 reserved_at_73[0xd];
3620 u8 reserved_at_80[0x8];
3622 u8 reserved_at_90[0x3];
3623 u8 min_rnr_nak[0x5];
3624 u8 reserved_at_98[0x8];
3626 u8 reserved_at_a0[0x8];
3629 u8 reserved_at_c0[0x8];
3633 u8 reserved_at_e8[0x4];
3634 u8 flow_label[0x14];
3636 u8 dc_access_key[0x40];
3638 u8 reserved_at_140[0x5];
3641 u8 pkey_index[0x10];
3643 u8 reserved_at_160[0x8];
3644 u8 my_addr_index[0x8];
3645 u8 reserved_at_170[0x8];
3648 u8 dc_access_key_violation_count[0x20];
3650 u8 reserved_at_1a0[0x14];
3656 u8 reserved_at_1c0[0x40];
3660 MLX5_CQC_STATUS_OK = 0x0,
3661 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3662 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3666 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
3667 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
3671 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
3672 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
3673 MLX5_CQC_ST_FIRED = 0xa,
3677 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3678 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3679 MLX5_CQ_PERIOD_NUM_MODES
3682 struct mlx5_ifc_cqc_bits {
3684 u8 reserved_at_4[0x2];
3685 u8 dbr_umem_valid[0x1];
3686 u8 reserved_at_7[0x1];
3689 u8 reserved_at_c[0x1];
3690 u8 scqe_break_moderation_en[0x1];
3692 u8 cq_period_mode[0x2];
3693 u8 cqe_comp_en[0x1];
3694 u8 mini_cqe_res_format[0x2];
3696 u8 reserved_at_18[0x8];
3698 u8 reserved_at_20[0x20];
3700 u8 reserved_at_40[0x14];
3701 u8 page_offset[0x6];
3702 u8 reserved_at_5a[0x6];
3704 u8 reserved_at_60[0x3];
3705 u8 log_cq_size[0x5];
3708 u8 reserved_at_80[0x4];
3710 u8 cq_max_count[0x10];
3712 u8 reserved_at_a0[0x18];
3715 u8 reserved_at_c0[0x3];
3716 u8 log_page_size[0x5];
3717 u8 reserved_at_c8[0x18];
3719 u8 reserved_at_e0[0x20];
3721 u8 reserved_at_100[0x8];
3722 u8 last_notified_index[0x18];
3724 u8 reserved_at_120[0x8];
3725 u8 last_solicit_index[0x18];
3727 u8 reserved_at_140[0x8];
3728 u8 consumer_counter[0x18];
3730 u8 reserved_at_160[0x8];
3731 u8 producer_counter[0x18];
3733 u8 reserved_at_180[0x40];
3738 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3739 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3740 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3741 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3742 u8 reserved_at_0[0x800];
3745 struct mlx5_ifc_query_adapter_param_block_bits {
3746 u8 reserved_at_0[0xc0];
3748 u8 reserved_at_c0[0x8];
3749 u8 ieee_vendor_id[0x18];
3751 u8 reserved_at_e0[0x10];
3752 u8 vsd_vendor_id[0x10];
3756 u8 vsd_contd_psid[16][0x8];
3760 MLX5_XRQC_STATE_GOOD = 0x0,
3761 MLX5_XRQC_STATE_ERROR = 0x1,
3765 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3766 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3770 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3773 struct mlx5_ifc_tag_matching_topology_context_bits {
3774 u8 log_matching_list_sz[0x4];
3775 u8 reserved_at_4[0xc];
3776 u8 append_next_index[0x10];
3778 u8 sw_phase_cnt[0x10];
3779 u8 hw_phase_cnt[0x10];
3781 u8 reserved_at_40[0x40];
3784 struct mlx5_ifc_xrqc_bits {
3787 u8 reserved_at_5[0xf];
3789 u8 reserved_at_18[0x4];
3792 u8 reserved_at_20[0x8];
3793 u8 user_index[0x18];
3795 u8 reserved_at_40[0x8];
3798 u8 reserved_at_60[0xa0];
3800 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3802 u8 reserved_at_180[0x280];
3804 struct mlx5_ifc_wq_bits wq;
3807 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3808 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3809 struct mlx5_ifc_resize_field_select_bits resize_field_select;
3810 u8 reserved_at_0[0x20];
3813 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3814 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3815 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3816 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3817 u8 reserved_at_0[0x20];
3820 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3821 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3822 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3823 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3824 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3825 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3826 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3827 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
3828 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
3829 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3830 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3831 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3832 u8 reserved_at_0[0x7c0];
3835 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3836 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3837 u8 reserved_at_0[0x7c0];
3840 union mlx5_ifc_event_auto_bits {
3841 struct mlx5_ifc_comp_event_bits comp_event;
3842 struct mlx5_ifc_dct_events_bits dct_events;
3843 struct mlx5_ifc_qp_events_bits qp_events;
3844 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3845 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3846 struct mlx5_ifc_cq_error_bits cq_error;
3847 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3848 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3849 struct mlx5_ifc_gpio_event_bits gpio_event;
3850 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3851 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3852 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3853 u8 reserved_at_0[0xe0];
3856 struct mlx5_ifc_health_buffer_bits {
3857 u8 reserved_at_0[0x100];
3859 u8 assert_existptr[0x20];
3861 u8 assert_callra[0x20];
3863 u8 reserved_at_140[0x40];
3865 u8 fw_version[0x20];
3869 u8 reserved_at_1c0[0x20];
3871 u8 irisc_index[0x8];
3876 struct mlx5_ifc_register_loopback_control_bits {
3878 u8 reserved_at_1[0x7];
3880 u8 reserved_at_10[0x10];
3882 u8 reserved_at_20[0x60];
3885 struct mlx5_ifc_vport_tc_element_bits {
3886 u8 traffic_class[0x4];
3887 u8 reserved_at_4[0xc];
3888 u8 vport_number[0x10];
3891 struct mlx5_ifc_vport_element_bits {
3892 u8 reserved_at_0[0x10];
3893 u8 vport_number[0x10];
3897 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3898 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3899 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3902 struct mlx5_ifc_tsar_element_bits {
3903 u8 reserved_at_0[0x8];
3905 u8 reserved_at_10[0x10];
3909 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3910 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3913 struct mlx5_ifc_teardown_hca_out_bits {
3915 u8 reserved_at_8[0x18];
3919 u8 reserved_at_40[0x3f];
3925 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3926 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3927 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3930 struct mlx5_ifc_teardown_hca_in_bits {
3932 u8 reserved_at_10[0x10];
3934 u8 reserved_at_20[0x10];
3937 u8 reserved_at_40[0x10];
3940 u8 reserved_at_60[0x20];
3943 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3945 u8 reserved_at_8[0x18];
3949 u8 reserved_at_40[0x40];
3952 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3956 u8 reserved_at_20[0x10];
3959 u8 reserved_at_40[0x8];
3962 u8 reserved_at_60[0x20];
3964 u8 opt_param_mask[0x20];
3966 u8 reserved_at_a0[0x20];
3968 struct mlx5_ifc_qpc_bits qpc;
3970 u8 reserved_at_800[0x80];
3973 struct mlx5_ifc_sqd2rts_qp_out_bits {
3975 u8 reserved_at_8[0x18];
3979 u8 reserved_at_40[0x40];
3982 struct mlx5_ifc_sqd2rts_qp_in_bits {
3986 u8 reserved_at_20[0x10];
3989 u8 reserved_at_40[0x8];
3992 u8 reserved_at_60[0x20];
3994 u8 opt_param_mask[0x20];
3996 u8 reserved_at_a0[0x20];
3998 struct mlx5_ifc_qpc_bits qpc;
4000 u8 reserved_at_800[0x80];
4003 struct mlx5_ifc_set_roce_address_out_bits {
4005 u8 reserved_at_8[0x18];
4009 u8 reserved_at_40[0x40];
4012 struct mlx5_ifc_set_roce_address_in_bits {
4014 u8 reserved_at_10[0x10];
4016 u8 reserved_at_20[0x10];
4019 u8 roce_address_index[0x10];
4020 u8 reserved_at_50[0xc];
4021 u8 vhca_port_num[0x4];
4023 u8 reserved_at_60[0x20];
4025 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4028 struct mlx5_ifc_set_mad_demux_out_bits {
4030 u8 reserved_at_8[0x18];
4034 u8 reserved_at_40[0x40];
4038 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4039 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4042 struct mlx5_ifc_set_mad_demux_in_bits {
4044 u8 reserved_at_10[0x10];
4046 u8 reserved_at_20[0x10];
4049 u8 reserved_at_40[0x20];
4051 u8 reserved_at_60[0x6];
4053 u8 reserved_at_68[0x18];
4056 struct mlx5_ifc_set_l2_table_entry_out_bits {
4058 u8 reserved_at_8[0x18];
4062 u8 reserved_at_40[0x40];
4065 struct mlx5_ifc_set_l2_table_entry_in_bits {
4067 u8 reserved_at_10[0x10];
4069 u8 reserved_at_20[0x10];
4072 u8 reserved_at_40[0x60];
4074 u8 reserved_at_a0[0x8];
4075 u8 table_index[0x18];
4077 u8 reserved_at_c0[0x20];
4079 u8 reserved_at_e0[0x13];
4083 struct mlx5_ifc_mac_address_layout_bits mac_address;
4085 u8 reserved_at_140[0xc0];
4088 struct mlx5_ifc_set_issi_out_bits {
4090 u8 reserved_at_8[0x18];
4094 u8 reserved_at_40[0x40];
4097 struct mlx5_ifc_set_issi_in_bits {
4099 u8 reserved_at_10[0x10];
4101 u8 reserved_at_20[0x10];
4104 u8 reserved_at_40[0x10];
4105 u8 current_issi[0x10];
4107 u8 reserved_at_60[0x20];
4110 struct mlx5_ifc_set_hca_cap_out_bits {
4112 u8 reserved_at_8[0x18];
4116 u8 reserved_at_40[0x40];
4119 struct mlx5_ifc_set_hca_cap_in_bits {
4121 u8 reserved_at_10[0x10];
4123 u8 reserved_at_20[0x10];
4126 u8 reserved_at_40[0x40];
4128 union mlx5_ifc_hca_cap_union_bits capability;
4132 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4133 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4134 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4135 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
4138 struct mlx5_ifc_set_fte_out_bits {
4140 u8 reserved_at_8[0x18];
4144 u8 reserved_at_40[0x40];
4147 struct mlx5_ifc_set_fte_in_bits {
4149 u8 reserved_at_10[0x10];
4151 u8 reserved_at_20[0x10];
4154 u8 other_vport[0x1];
4155 u8 reserved_at_41[0xf];
4156 u8 vport_number[0x10];
4158 u8 reserved_at_60[0x20];
4161 u8 reserved_at_88[0x18];
4163 u8 reserved_at_a0[0x8];
4166 u8 ignore_flow_level[0x1];
4167 u8 reserved_at_c1[0x17];
4168 u8 modify_enable_mask[0x8];
4170 u8 reserved_at_e0[0x20];
4172 u8 flow_index[0x20];
4174 u8 reserved_at_120[0xe0];
4176 struct mlx5_ifc_flow_context_bits flow_context;
4179 struct mlx5_ifc_rts2rts_qp_out_bits {
4181 u8 reserved_at_8[0x18];
4185 u8 reserved_at_40[0x40];
4188 struct mlx5_ifc_rts2rts_qp_in_bits {
4192 u8 reserved_at_20[0x10];
4195 u8 reserved_at_40[0x8];
4198 u8 reserved_at_60[0x20];
4200 u8 opt_param_mask[0x20];
4202 u8 reserved_at_a0[0x20];
4204 struct mlx5_ifc_qpc_bits qpc;
4206 u8 reserved_at_800[0x80];
4209 struct mlx5_ifc_rtr2rts_qp_out_bits {
4211 u8 reserved_at_8[0x18];
4215 u8 reserved_at_40[0x40];
4218 struct mlx5_ifc_rtr2rts_qp_in_bits {
4222 u8 reserved_at_20[0x10];
4225 u8 reserved_at_40[0x8];
4228 u8 reserved_at_60[0x20];
4230 u8 opt_param_mask[0x20];
4232 u8 reserved_at_a0[0x20];
4234 struct mlx5_ifc_qpc_bits qpc;
4236 u8 reserved_at_800[0x80];
4239 struct mlx5_ifc_rst2init_qp_out_bits {
4241 u8 reserved_at_8[0x18];
4245 u8 reserved_at_40[0x40];
4248 struct mlx5_ifc_rst2init_qp_in_bits {
4252 u8 reserved_at_20[0x10];
4255 u8 reserved_at_40[0x8];
4258 u8 reserved_at_60[0x20];
4260 u8 opt_param_mask[0x20];
4262 u8 reserved_at_a0[0x20];
4264 struct mlx5_ifc_qpc_bits qpc;
4266 u8 reserved_at_800[0x80];
4269 struct mlx5_ifc_query_xrq_out_bits {
4271 u8 reserved_at_8[0x18];
4275 u8 reserved_at_40[0x40];
4277 struct mlx5_ifc_xrqc_bits xrq_context;
4280 struct mlx5_ifc_query_xrq_in_bits {
4282 u8 reserved_at_10[0x10];
4284 u8 reserved_at_20[0x10];
4287 u8 reserved_at_40[0x8];
4290 u8 reserved_at_60[0x20];
4293 struct mlx5_ifc_query_xrc_srq_out_bits {
4295 u8 reserved_at_8[0x18];
4299 u8 reserved_at_40[0x40];
4301 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4303 u8 reserved_at_280[0x600];
4308 struct mlx5_ifc_query_xrc_srq_in_bits {
4310 u8 reserved_at_10[0x10];
4312 u8 reserved_at_20[0x10];
4315 u8 reserved_at_40[0x8];
4318 u8 reserved_at_60[0x20];
4322 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4323 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4326 struct mlx5_ifc_query_vport_state_out_bits {
4328 u8 reserved_at_8[0x18];
4332 u8 reserved_at_40[0x20];
4334 u8 reserved_at_60[0x18];
4335 u8 admin_state[0x4];
4340 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0,
4341 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1,
4344 struct mlx5_ifc_arm_monitor_counter_in_bits {
4348 u8 reserved_at_20[0x10];
4351 u8 reserved_at_40[0x20];
4353 u8 reserved_at_60[0x20];
4356 struct mlx5_ifc_arm_monitor_counter_out_bits {
4358 u8 reserved_at_8[0x18];
4362 u8 reserved_at_40[0x40];
4366 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0,
4367 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4370 enum mlx5_monitor_counter_ppcnt {
4371 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0,
4372 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1,
4373 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2,
4374 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4375 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4,
4376 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5,
4380 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4,
4383 struct mlx5_ifc_monitor_counter_output_bits {
4384 u8 reserved_at_0[0x4];
4386 u8 reserved_at_8[0x8];
4389 u8 counter_group_id[0x20];
4392 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4393 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1)
4394 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4395 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4397 struct mlx5_ifc_set_monitor_counter_in_bits {
4401 u8 reserved_at_20[0x10];
4404 u8 reserved_at_40[0x10];
4405 u8 num_of_counters[0x10];
4407 u8 reserved_at_60[0x20];
4409 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4412 struct mlx5_ifc_set_monitor_counter_out_bits {
4414 u8 reserved_at_8[0x18];
4418 u8 reserved_at_40[0x40];
4421 struct mlx5_ifc_query_vport_state_in_bits {
4423 u8 reserved_at_10[0x10];
4425 u8 reserved_at_20[0x10];
4428 u8 other_vport[0x1];
4429 u8 reserved_at_41[0xf];
4430 u8 vport_number[0x10];
4432 u8 reserved_at_60[0x20];
4435 struct mlx5_ifc_query_vnic_env_out_bits {
4437 u8 reserved_at_8[0x18];
4441 u8 reserved_at_40[0x40];
4443 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4447 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4450 struct mlx5_ifc_query_vnic_env_in_bits {
4452 u8 reserved_at_10[0x10];
4454 u8 reserved_at_20[0x10];
4457 u8 other_vport[0x1];
4458 u8 reserved_at_41[0xf];
4459 u8 vport_number[0x10];
4461 u8 reserved_at_60[0x20];
4464 struct mlx5_ifc_query_vport_counter_out_bits {
4466 u8 reserved_at_8[0x18];
4470 u8 reserved_at_40[0x40];
4472 struct mlx5_ifc_traffic_counter_bits received_errors;
4474 struct mlx5_ifc_traffic_counter_bits transmit_errors;
4476 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4478 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4480 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4482 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4484 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4486 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4488 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4490 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4492 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4494 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4496 u8 reserved_at_680[0xa00];
4500 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4503 struct mlx5_ifc_query_vport_counter_in_bits {
4505 u8 reserved_at_10[0x10];
4507 u8 reserved_at_20[0x10];
4510 u8 other_vport[0x1];
4511 u8 reserved_at_41[0xb];
4513 u8 vport_number[0x10];
4515 u8 reserved_at_60[0x60];
4518 u8 reserved_at_c1[0x1f];
4520 u8 reserved_at_e0[0x20];
4523 struct mlx5_ifc_query_tis_out_bits {
4525 u8 reserved_at_8[0x18];
4529 u8 reserved_at_40[0x40];
4531 struct mlx5_ifc_tisc_bits tis_context;
4534 struct mlx5_ifc_query_tis_in_bits {
4536 u8 reserved_at_10[0x10];
4538 u8 reserved_at_20[0x10];
4541 u8 reserved_at_40[0x8];
4544 u8 reserved_at_60[0x20];
4547 struct mlx5_ifc_query_tir_out_bits {
4549 u8 reserved_at_8[0x18];
4553 u8 reserved_at_40[0xc0];
4555 struct mlx5_ifc_tirc_bits tir_context;
4558 struct mlx5_ifc_query_tir_in_bits {
4560 u8 reserved_at_10[0x10];
4562 u8 reserved_at_20[0x10];
4565 u8 reserved_at_40[0x8];
4568 u8 reserved_at_60[0x20];
4571 struct mlx5_ifc_query_srq_out_bits {
4573 u8 reserved_at_8[0x18];
4577 u8 reserved_at_40[0x40];
4579 struct mlx5_ifc_srqc_bits srq_context_entry;
4581 u8 reserved_at_280[0x600];
4586 struct mlx5_ifc_query_srq_in_bits {
4588 u8 reserved_at_10[0x10];
4590 u8 reserved_at_20[0x10];
4593 u8 reserved_at_40[0x8];
4596 u8 reserved_at_60[0x20];
4599 struct mlx5_ifc_query_sq_out_bits {
4601 u8 reserved_at_8[0x18];
4605 u8 reserved_at_40[0xc0];
4607 struct mlx5_ifc_sqc_bits sq_context;
4610 struct mlx5_ifc_query_sq_in_bits {
4612 u8 reserved_at_10[0x10];
4614 u8 reserved_at_20[0x10];
4617 u8 reserved_at_40[0x8];
4620 u8 reserved_at_60[0x20];
4623 struct mlx5_ifc_query_special_contexts_out_bits {
4625 u8 reserved_at_8[0x18];
4629 u8 dump_fill_mkey[0x20];
4635 u8 reserved_at_a0[0x60];
4638 struct mlx5_ifc_query_special_contexts_in_bits {
4640 u8 reserved_at_10[0x10];
4642 u8 reserved_at_20[0x10];
4645 u8 reserved_at_40[0x40];
4648 struct mlx5_ifc_query_scheduling_element_out_bits {
4650 u8 reserved_at_10[0x10];
4652 u8 reserved_at_20[0x10];
4655 u8 reserved_at_40[0xc0];
4657 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4659 u8 reserved_at_300[0x100];
4663 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4666 struct mlx5_ifc_query_scheduling_element_in_bits {
4668 u8 reserved_at_10[0x10];
4670 u8 reserved_at_20[0x10];
4673 u8 scheduling_hierarchy[0x8];
4674 u8 reserved_at_48[0x18];
4676 u8 scheduling_element_id[0x20];
4678 u8 reserved_at_80[0x180];
4681 struct mlx5_ifc_query_rqt_out_bits {
4683 u8 reserved_at_8[0x18];
4687 u8 reserved_at_40[0xc0];
4689 struct mlx5_ifc_rqtc_bits rqt_context;
4692 struct mlx5_ifc_query_rqt_in_bits {
4694 u8 reserved_at_10[0x10];
4696 u8 reserved_at_20[0x10];
4699 u8 reserved_at_40[0x8];
4702 u8 reserved_at_60[0x20];
4705 struct mlx5_ifc_query_rq_out_bits {
4707 u8 reserved_at_8[0x18];
4711 u8 reserved_at_40[0xc0];
4713 struct mlx5_ifc_rqc_bits rq_context;
4716 struct mlx5_ifc_query_rq_in_bits {
4718 u8 reserved_at_10[0x10];
4720 u8 reserved_at_20[0x10];
4723 u8 reserved_at_40[0x8];
4726 u8 reserved_at_60[0x20];
4729 struct mlx5_ifc_query_roce_address_out_bits {
4731 u8 reserved_at_8[0x18];
4735 u8 reserved_at_40[0x40];
4737 struct mlx5_ifc_roce_addr_layout_bits roce_address;
4740 struct mlx5_ifc_query_roce_address_in_bits {
4742 u8 reserved_at_10[0x10];
4744 u8 reserved_at_20[0x10];
4747 u8 roce_address_index[0x10];
4748 u8 reserved_at_50[0xc];
4749 u8 vhca_port_num[0x4];
4751 u8 reserved_at_60[0x20];
4754 struct mlx5_ifc_query_rmp_out_bits {
4756 u8 reserved_at_8[0x18];
4760 u8 reserved_at_40[0xc0];
4762 struct mlx5_ifc_rmpc_bits rmp_context;
4765 struct mlx5_ifc_query_rmp_in_bits {
4767 u8 reserved_at_10[0x10];
4769 u8 reserved_at_20[0x10];
4772 u8 reserved_at_40[0x8];
4775 u8 reserved_at_60[0x20];
4778 struct mlx5_ifc_query_qp_out_bits {
4780 u8 reserved_at_8[0x18];
4784 u8 reserved_at_40[0x40];
4786 u8 opt_param_mask[0x20];
4788 u8 reserved_at_a0[0x20];
4790 struct mlx5_ifc_qpc_bits qpc;
4792 u8 reserved_at_800[0x80];
4797 struct mlx5_ifc_query_qp_in_bits {
4799 u8 reserved_at_10[0x10];
4801 u8 reserved_at_20[0x10];
4804 u8 reserved_at_40[0x8];
4807 u8 reserved_at_60[0x20];
4810 struct mlx5_ifc_query_q_counter_out_bits {
4812 u8 reserved_at_8[0x18];
4816 u8 reserved_at_40[0x40];
4818 u8 rx_write_requests[0x20];
4820 u8 reserved_at_a0[0x20];
4822 u8 rx_read_requests[0x20];
4824 u8 reserved_at_e0[0x20];
4826 u8 rx_atomic_requests[0x20];
4828 u8 reserved_at_120[0x20];
4830 u8 rx_dct_connect[0x20];
4832 u8 reserved_at_160[0x20];
4834 u8 out_of_buffer[0x20];
4836 u8 reserved_at_1a0[0x20];
4838 u8 out_of_sequence[0x20];
4840 u8 reserved_at_1e0[0x20];
4842 u8 duplicate_request[0x20];
4844 u8 reserved_at_220[0x20];
4846 u8 rnr_nak_retry_err[0x20];
4848 u8 reserved_at_260[0x20];
4850 u8 packet_seq_err[0x20];
4852 u8 reserved_at_2a0[0x20];
4854 u8 implied_nak_seq_err[0x20];
4856 u8 reserved_at_2e0[0x20];
4858 u8 local_ack_timeout_err[0x20];
4860 u8 reserved_at_320[0xa0];
4862 u8 resp_local_length_error[0x20];
4864 u8 req_local_length_error[0x20];
4866 u8 resp_local_qp_error[0x20];
4868 u8 local_operation_error[0x20];
4870 u8 resp_local_protection[0x20];
4872 u8 req_local_protection[0x20];
4874 u8 resp_cqe_error[0x20];
4876 u8 req_cqe_error[0x20];
4878 u8 req_mw_binding[0x20];
4880 u8 req_bad_response[0x20];
4882 u8 req_remote_invalid_request[0x20];
4884 u8 resp_remote_invalid_request[0x20];
4886 u8 req_remote_access_errors[0x20];
4888 u8 resp_remote_access_errors[0x20];
4890 u8 req_remote_operation_errors[0x20];
4892 u8 req_transport_retries_exceeded[0x20];
4894 u8 cq_overflow[0x20];
4896 u8 resp_cqe_flush_error[0x20];
4898 u8 req_cqe_flush_error[0x20];
4900 u8 reserved_at_620[0x20];
4902 u8 roce_adp_retrans[0x20];
4904 u8 roce_adp_retrans_to[0x20];
4906 u8 roce_slow_restart[0x20];
4908 u8 roce_slow_restart_cnps[0x20];
4910 u8 roce_slow_restart_trans[0x20];
4912 u8 reserved_at_6e0[0x120];
4915 struct mlx5_ifc_query_q_counter_in_bits {
4917 u8 reserved_at_10[0x10];
4919 u8 reserved_at_20[0x10];
4922 u8 reserved_at_40[0x80];
4925 u8 reserved_at_c1[0x1f];
4927 u8 reserved_at_e0[0x18];
4928 u8 counter_set_id[0x8];
4931 struct mlx5_ifc_query_pages_out_bits {
4933 u8 reserved_at_8[0x18];
4937 u8 embedded_cpu_function[0x1];
4938 u8 reserved_at_41[0xf];
4939 u8 function_id[0x10];
4945 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4946 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4947 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4950 struct mlx5_ifc_query_pages_in_bits {
4952 u8 reserved_at_10[0x10];
4954 u8 reserved_at_20[0x10];
4957 u8 embedded_cpu_function[0x1];
4958 u8 reserved_at_41[0xf];
4959 u8 function_id[0x10];
4961 u8 reserved_at_60[0x20];
4964 struct mlx5_ifc_query_nic_vport_context_out_bits {
4966 u8 reserved_at_8[0x18];
4970 u8 reserved_at_40[0x40];
4972 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4975 struct mlx5_ifc_query_nic_vport_context_in_bits {
4977 u8 reserved_at_10[0x10];
4979 u8 reserved_at_20[0x10];
4982 u8 other_vport[0x1];
4983 u8 reserved_at_41[0xf];
4984 u8 vport_number[0x10];
4986 u8 reserved_at_60[0x5];
4987 u8 allowed_list_type[0x3];
4988 u8 reserved_at_68[0x18];
4991 struct mlx5_ifc_query_mkey_out_bits {
4993 u8 reserved_at_8[0x18];
4997 u8 reserved_at_40[0x40];
4999 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5001 u8 reserved_at_280[0x600];
5003 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5005 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5008 struct mlx5_ifc_query_mkey_in_bits {
5010 u8 reserved_at_10[0x10];
5012 u8 reserved_at_20[0x10];
5015 u8 reserved_at_40[0x8];
5016 u8 mkey_index[0x18];
5019 u8 reserved_at_61[0x1f];
5022 struct mlx5_ifc_query_mad_demux_out_bits {
5024 u8 reserved_at_8[0x18];
5028 u8 reserved_at_40[0x40];
5030 u8 mad_dumux_parameters_block[0x20];
5033 struct mlx5_ifc_query_mad_demux_in_bits {
5035 u8 reserved_at_10[0x10];
5037 u8 reserved_at_20[0x10];
5040 u8 reserved_at_40[0x40];
5043 struct mlx5_ifc_query_l2_table_entry_out_bits {
5045 u8 reserved_at_8[0x18];
5049 u8 reserved_at_40[0xa0];
5051 u8 reserved_at_e0[0x13];
5055 struct mlx5_ifc_mac_address_layout_bits mac_address;
5057 u8 reserved_at_140[0xc0];
5060 struct mlx5_ifc_query_l2_table_entry_in_bits {
5062 u8 reserved_at_10[0x10];
5064 u8 reserved_at_20[0x10];
5067 u8 reserved_at_40[0x60];
5069 u8 reserved_at_a0[0x8];
5070 u8 table_index[0x18];
5072 u8 reserved_at_c0[0x140];
5075 struct mlx5_ifc_query_issi_out_bits {
5077 u8 reserved_at_8[0x18];
5081 u8 reserved_at_40[0x10];
5082 u8 current_issi[0x10];
5084 u8 reserved_at_60[0xa0];
5086 u8 reserved_at_100[76][0x8];
5087 u8 supported_issi_dw0[0x20];
5090 struct mlx5_ifc_query_issi_in_bits {
5092 u8 reserved_at_10[0x10];
5094 u8 reserved_at_20[0x10];
5097 u8 reserved_at_40[0x40];
5100 struct mlx5_ifc_set_driver_version_out_bits {
5102 u8 reserved_0[0x18];
5105 u8 reserved_1[0x40];
5108 struct mlx5_ifc_set_driver_version_in_bits {
5110 u8 reserved_0[0x10];
5112 u8 reserved_1[0x10];
5115 u8 reserved_2[0x40];
5116 u8 driver_version[64][0x8];
5119 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
5121 u8 reserved_at_8[0x18];
5125 u8 reserved_at_40[0x40];
5127 struct mlx5_ifc_pkey_bits pkey[0];
5130 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
5132 u8 reserved_at_10[0x10];
5134 u8 reserved_at_20[0x10];
5137 u8 other_vport[0x1];
5138 u8 reserved_at_41[0xb];
5140 u8 vport_number[0x10];
5142 u8 reserved_at_60[0x10];
5143 u8 pkey_index[0x10];
5147 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
5148 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
5149 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
5152 struct mlx5_ifc_query_hca_vport_gid_out_bits {
5154 u8 reserved_at_8[0x18];
5158 u8 reserved_at_40[0x20];
5161 u8 reserved_at_70[0x10];
5163 struct mlx5_ifc_array128_auto_bits gid[0];
5166 struct mlx5_ifc_query_hca_vport_gid_in_bits {
5168 u8 reserved_at_10[0x10];
5170 u8 reserved_at_20[0x10];
5173 u8 other_vport[0x1];
5174 u8 reserved_at_41[0xb];
5176 u8 vport_number[0x10];
5178 u8 reserved_at_60[0x10];
5182 struct mlx5_ifc_query_hca_vport_context_out_bits {
5184 u8 reserved_at_8[0x18];
5188 u8 reserved_at_40[0x40];
5190 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5193 struct mlx5_ifc_query_hca_vport_context_in_bits {
5195 u8 reserved_at_10[0x10];
5197 u8 reserved_at_20[0x10];
5200 u8 other_vport[0x1];
5201 u8 reserved_at_41[0xb];
5203 u8 vport_number[0x10];
5205 u8 reserved_at_60[0x20];
5208 struct mlx5_ifc_query_hca_cap_out_bits {
5210 u8 reserved_at_8[0x18];
5214 u8 reserved_at_40[0x40];
5216 union mlx5_ifc_hca_cap_union_bits capability;
5219 struct mlx5_ifc_query_hca_cap_in_bits {
5221 u8 reserved_at_10[0x10];
5223 u8 reserved_at_20[0x10];
5226 u8 other_function[0x1];
5227 u8 reserved_at_41[0xf];
5228 u8 function_id[0x10];
5230 u8 reserved_at_60[0x20];
5233 struct mlx5_ifc_other_hca_cap_bits {
5235 u8 reserved_at_1[0x27f];
5238 struct mlx5_ifc_query_other_hca_cap_out_bits {
5240 u8 reserved_at_8[0x18];
5244 u8 reserved_at_40[0x40];
5246 struct mlx5_ifc_other_hca_cap_bits other_capability;
5249 struct mlx5_ifc_query_other_hca_cap_in_bits {
5251 u8 reserved_at_10[0x10];
5253 u8 reserved_at_20[0x10];
5256 u8 reserved_at_40[0x10];
5257 u8 function_id[0x10];
5259 u8 reserved_at_60[0x20];
5262 struct mlx5_ifc_modify_other_hca_cap_out_bits {
5264 u8 reserved_at_8[0x18];
5268 u8 reserved_at_40[0x40];
5271 struct mlx5_ifc_modify_other_hca_cap_in_bits {
5273 u8 reserved_at_10[0x10];
5275 u8 reserved_at_20[0x10];
5278 u8 reserved_at_40[0x10];
5279 u8 function_id[0x10];
5280 u8 field_select[0x20];
5282 struct mlx5_ifc_other_hca_cap_bits other_capability;
5285 struct mlx5_ifc_flow_table_context_bits {
5286 u8 reformat_en[0x1];
5289 u8 termination_table[0x1];
5290 u8 table_miss_action[0x4];
5292 u8 reserved_at_10[0x8];
5295 u8 reserved_at_20[0x8];
5296 u8 table_miss_id[0x18];
5298 u8 reserved_at_40[0x8];
5299 u8 lag_master_next_table_id[0x18];
5301 u8 reserved_at_60[0x60];
5303 u8 sw_owner_icm_root_1[0x40];
5305 u8 sw_owner_icm_root_0[0x40];
5309 struct mlx5_ifc_query_flow_table_out_bits {
5311 u8 reserved_at_8[0x18];
5315 u8 reserved_at_40[0x80];
5317 struct mlx5_ifc_flow_table_context_bits flow_table_context;
5320 struct mlx5_ifc_query_flow_table_in_bits {
5322 u8 reserved_at_10[0x10];
5324 u8 reserved_at_20[0x10];
5327 u8 reserved_at_40[0x40];
5330 u8 reserved_at_88[0x18];
5332 u8 reserved_at_a0[0x8];
5335 u8 reserved_at_c0[0x140];
5338 struct mlx5_ifc_query_fte_out_bits {
5340 u8 reserved_at_8[0x18];
5344 u8 reserved_at_40[0x1c0];
5346 struct mlx5_ifc_flow_context_bits flow_context;
5349 struct mlx5_ifc_query_fte_in_bits {
5351 u8 reserved_at_10[0x10];
5353 u8 reserved_at_20[0x10];
5356 u8 reserved_at_40[0x40];
5359 u8 reserved_at_88[0x18];
5361 u8 reserved_at_a0[0x8];
5364 u8 reserved_at_c0[0x40];
5366 u8 flow_index[0x20];
5368 u8 reserved_at_120[0xe0];
5372 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5373 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5374 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5375 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5376 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5379 struct mlx5_ifc_query_flow_group_out_bits {
5381 u8 reserved_at_8[0x18];
5385 u8 reserved_at_40[0xa0];
5387 u8 start_flow_index[0x20];
5389 u8 reserved_at_100[0x20];
5391 u8 end_flow_index[0x20];
5393 u8 reserved_at_140[0xa0];
5395 u8 reserved_at_1e0[0x18];
5396 u8 match_criteria_enable[0x8];
5398 struct mlx5_ifc_fte_match_param_bits match_criteria;
5400 u8 reserved_at_1200[0xe00];
5403 struct mlx5_ifc_query_flow_group_in_bits {
5405 u8 reserved_at_10[0x10];
5407 u8 reserved_at_20[0x10];
5410 u8 reserved_at_40[0x40];
5413 u8 reserved_at_88[0x18];
5415 u8 reserved_at_a0[0x8];
5420 u8 reserved_at_e0[0x120];
5423 struct mlx5_ifc_query_flow_counter_out_bits {
5425 u8 reserved_at_8[0x18];
5429 u8 reserved_at_40[0x40];
5431 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5434 struct mlx5_ifc_query_flow_counter_in_bits {
5436 u8 reserved_at_10[0x10];
5438 u8 reserved_at_20[0x10];
5441 u8 reserved_at_40[0x80];
5444 u8 reserved_at_c1[0xf];
5445 u8 num_of_counters[0x10];
5447 u8 flow_counter_id[0x20];
5450 struct mlx5_ifc_query_esw_vport_context_out_bits {
5452 u8 reserved_at_8[0x18];
5456 u8 reserved_at_40[0x40];
5458 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5461 struct mlx5_ifc_query_esw_vport_context_in_bits {
5463 u8 reserved_at_10[0x10];
5465 u8 reserved_at_20[0x10];
5468 u8 other_vport[0x1];
5469 u8 reserved_at_41[0xf];
5470 u8 vport_number[0x10];
5472 u8 reserved_at_60[0x20];
5475 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5477 u8 reserved_at_8[0x18];
5481 u8 reserved_at_40[0x40];
5484 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5485 u8 reserved_at_0[0x1b];
5486 u8 fdb_to_vport_reg_c_id[0x1];
5487 u8 vport_cvlan_insert[0x1];
5488 u8 vport_svlan_insert[0x1];
5489 u8 vport_cvlan_strip[0x1];
5490 u8 vport_svlan_strip[0x1];
5493 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5495 u8 reserved_at_10[0x10];
5497 u8 reserved_at_20[0x10];
5500 u8 other_vport[0x1];
5501 u8 reserved_at_41[0xf];
5502 u8 vport_number[0x10];
5504 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5506 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5509 struct mlx5_ifc_query_eq_out_bits {
5511 u8 reserved_at_8[0x18];
5515 u8 reserved_at_40[0x40];
5517 struct mlx5_ifc_eqc_bits eq_context_entry;
5519 u8 reserved_at_280[0x40];
5521 u8 event_bitmask[0x40];
5523 u8 reserved_at_300[0x580];
5528 struct mlx5_ifc_query_eq_in_bits {
5530 u8 reserved_at_10[0x10];
5532 u8 reserved_at_20[0x10];
5535 u8 reserved_at_40[0x18];
5538 u8 reserved_at_60[0x20];
5541 struct mlx5_ifc_packet_reformat_context_in_bits {
5542 u8 reserved_at_0[0x5];
5543 u8 reformat_type[0x3];
5544 u8 reserved_at_8[0xe];
5545 u8 reformat_data_size[0xa];
5547 u8 reserved_at_20[0x10];
5548 u8 reformat_data[2][0x8];
5550 u8 more_reformat_data[0][0x8];
5553 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5555 u8 reserved_at_8[0x18];
5559 u8 reserved_at_40[0xa0];
5561 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5564 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5566 u8 reserved_at_10[0x10];
5568 u8 reserved_at_20[0x10];
5571 u8 packet_reformat_id[0x20];
5573 u8 reserved_at_60[0xa0];
5576 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5578 u8 reserved_at_8[0x18];
5582 u8 packet_reformat_id[0x20];
5584 u8 reserved_at_60[0x20];
5587 enum mlx5_reformat_ctx_type {
5588 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5589 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5590 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5591 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5592 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5595 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5597 u8 reserved_at_10[0x10];
5599 u8 reserved_at_20[0x10];
5602 u8 reserved_at_40[0xa0];
5604 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5607 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5609 u8 reserved_at_8[0x18];
5613 u8 reserved_at_40[0x40];
5616 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5618 u8 reserved_at_10[0x10];
5620 u8 reserved_20[0x10];
5623 u8 packet_reformat_id[0x20];
5625 u8 reserved_60[0x20];
5628 struct mlx5_ifc_set_action_in_bits {
5629 u8 action_type[0x4];
5631 u8 reserved_at_10[0x3];
5633 u8 reserved_at_18[0x3];
5639 struct mlx5_ifc_add_action_in_bits {
5640 u8 action_type[0x4];
5642 u8 reserved_at_10[0x10];
5647 struct mlx5_ifc_copy_action_in_bits {
5648 u8 action_type[0x4];
5650 u8 reserved_at_10[0x3];
5652 u8 reserved_at_18[0x3];
5655 u8 reserved_at_20[0x4];
5657 u8 reserved_at_30[0x3];
5659 u8 reserved_at_38[0x8];
5662 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5663 struct mlx5_ifc_set_action_in_bits set_action_in;
5664 struct mlx5_ifc_add_action_in_bits add_action_in;
5665 struct mlx5_ifc_copy_action_in_bits copy_action_in;
5666 u8 reserved_at_0[0x40];
5670 MLX5_ACTION_TYPE_SET = 0x1,
5671 MLX5_ACTION_TYPE_ADD = 0x2,
5672 MLX5_ACTION_TYPE_COPY = 0x3,
5676 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5677 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5678 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5679 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5680 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5681 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5682 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5683 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5684 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5685 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5686 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5687 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5688 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5689 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5690 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5691 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5692 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5693 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5694 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5695 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5696 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5697 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5698 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5699 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5700 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5701 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5702 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5703 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5704 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5705 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5706 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5707 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5708 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5709 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5710 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5711 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5714 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5716 u8 reserved_at_8[0x18];
5720 u8 modify_header_id[0x20];
5722 u8 reserved_at_60[0x20];
5725 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5727 u8 reserved_at_10[0x10];
5729 u8 reserved_at_20[0x10];
5732 u8 reserved_at_40[0x20];
5735 u8 reserved_at_68[0x10];
5736 u8 num_of_actions[0x8];
5738 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5741 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5743 u8 reserved_at_8[0x18];
5747 u8 reserved_at_40[0x40];
5750 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5752 u8 reserved_at_10[0x10];
5754 u8 reserved_at_20[0x10];
5757 u8 modify_header_id[0x20];
5759 u8 reserved_at_60[0x20];
5762 struct mlx5_ifc_query_dct_out_bits {
5764 u8 reserved_at_8[0x18];
5768 u8 reserved_at_40[0x40];
5770 struct mlx5_ifc_dctc_bits dct_context_entry;
5772 u8 reserved_at_280[0x180];
5775 struct mlx5_ifc_query_dct_in_bits {
5777 u8 reserved_at_10[0x10];
5779 u8 reserved_at_20[0x10];
5782 u8 reserved_at_40[0x8];
5785 u8 reserved_at_60[0x20];
5788 struct mlx5_ifc_query_cq_out_bits {
5790 u8 reserved_at_8[0x18];
5794 u8 reserved_at_40[0x40];
5796 struct mlx5_ifc_cqc_bits cq_context;
5798 u8 reserved_at_280[0x600];
5803 struct mlx5_ifc_query_cq_in_bits {
5805 u8 reserved_at_10[0x10];
5807 u8 reserved_at_20[0x10];
5810 u8 reserved_at_40[0x8];
5813 u8 reserved_at_60[0x20];
5816 struct mlx5_ifc_query_cong_status_out_bits {
5818 u8 reserved_at_8[0x18];
5822 u8 reserved_at_40[0x20];
5826 u8 reserved_at_62[0x1e];
5829 struct mlx5_ifc_query_cong_status_in_bits {
5831 u8 reserved_at_10[0x10];
5833 u8 reserved_at_20[0x10];
5836 u8 reserved_at_40[0x18];
5838 u8 cong_protocol[0x4];
5840 u8 reserved_at_60[0x20];
5843 struct mlx5_ifc_query_cong_statistics_out_bits {
5845 u8 reserved_at_8[0x18];
5849 u8 reserved_at_40[0x40];
5851 u8 rp_cur_flows[0x20];
5855 u8 rp_cnp_ignored_high[0x20];
5857 u8 rp_cnp_ignored_low[0x20];
5859 u8 rp_cnp_handled_high[0x20];
5861 u8 rp_cnp_handled_low[0x20];
5863 u8 reserved_at_140[0x100];
5865 u8 time_stamp_high[0x20];
5867 u8 time_stamp_low[0x20];
5869 u8 accumulators_period[0x20];
5871 u8 np_ecn_marked_roce_packets_high[0x20];
5873 u8 np_ecn_marked_roce_packets_low[0x20];
5875 u8 np_cnp_sent_high[0x20];
5877 u8 np_cnp_sent_low[0x20];
5879 u8 reserved_at_320[0x560];
5882 struct mlx5_ifc_query_cong_statistics_in_bits {
5884 u8 reserved_at_10[0x10];
5886 u8 reserved_at_20[0x10];
5890 u8 reserved_at_41[0x1f];
5892 u8 reserved_at_60[0x20];
5895 struct mlx5_ifc_query_cong_params_out_bits {
5897 u8 reserved_at_8[0x18];
5901 u8 reserved_at_40[0x40];
5903 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5906 struct mlx5_ifc_query_cong_params_in_bits {
5908 u8 reserved_at_10[0x10];
5910 u8 reserved_at_20[0x10];
5913 u8 reserved_at_40[0x1c];
5914 u8 cong_protocol[0x4];
5916 u8 reserved_at_60[0x20];
5919 struct mlx5_ifc_query_adapter_out_bits {
5921 u8 reserved_at_8[0x18];
5925 u8 reserved_at_40[0x40];
5927 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5930 struct mlx5_ifc_query_adapter_in_bits {
5932 u8 reserved_at_10[0x10];
5934 u8 reserved_at_20[0x10];
5937 u8 reserved_at_40[0x40];
5940 struct mlx5_ifc_qp_2rst_out_bits {
5942 u8 reserved_at_8[0x18];
5946 u8 reserved_at_40[0x40];
5949 struct mlx5_ifc_qp_2rst_in_bits {
5953 u8 reserved_at_20[0x10];
5956 u8 reserved_at_40[0x8];
5959 u8 reserved_at_60[0x20];
5962 struct mlx5_ifc_qp_2err_out_bits {
5964 u8 reserved_at_8[0x18];
5968 u8 reserved_at_40[0x40];
5971 struct mlx5_ifc_qp_2err_in_bits {
5975 u8 reserved_at_20[0x10];
5978 u8 reserved_at_40[0x8];
5981 u8 reserved_at_60[0x20];
5984 struct mlx5_ifc_page_fault_resume_out_bits {
5986 u8 reserved_at_8[0x18];
5990 u8 reserved_at_40[0x40];
5993 struct mlx5_ifc_page_fault_resume_in_bits {
5995 u8 reserved_at_10[0x10];
5997 u8 reserved_at_20[0x10];
6001 u8 reserved_at_41[0x4];
6002 u8 page_fault_type[0x3];
6005 u8 reserved_at_60[0x8];
6009 struct mlx5_ifc_nop_out_bits {
6011 u8 reserved_at_8[0x18];
6015 u8 reserved_at_40[0x40];
6018 struct mlx5_ifc_nop_in_bits {
6020 u8 reserved_at_10[0x10];
6022 u8 reserved_at_20[0x10];
6025 u8 reserved_at_40[0x40];
6028 struct mlx5_ifc_modify_vport_state_out_bits {
6030 u8 reserved_at_8[0x18];
6034 u8 reserved_at_40[0x40];
6037 struct mlx5_ifc_modify_vport_state_in_bits {
6039 u8 reserved_at_10[0x10];
6041 u8 reserved_at_20[0x10];
6044 u8 other_vport[0x1];
6045 u8 reserved_at_41[0xf];
6046 u8 vport_number[0x10];
6048 u8 reserved_at_60[0x18];
6049 u8 admin_state[0x4];
6050 u8 reserved_at_7c[0x4];
6053 struct mlx5_ifc_modify_tis_out_bits {
6055 u8 reserved_at_8[0x18];
6059 u8 reserved_at_40[0x40];
6062 struct mlx5_ifc_modify_tis_bitmask_bits {
6063 u8 reserved_at_0[0x20];
6065 u8 reserved_at_20[0x1d];
6066 u8 lag_tx_port_affinity[0x1];
6067 u8 strict_lag_tx_port_affinity[0x1];
6071 struct mlx5_ifc_modify_tis_in_bits {
6075 u8 reserved_at_20[0x10];
6078 u8 reserved_at_40[0x8];
6081 u8 reserved_at_60[0x20];
6083 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
6085 u8 reserved_at_c0[0x40];
6087 struct mlx5_ifc_tisc_bits ctx;
6090 struct mlx5_ifc_modify_tir_bitmask_bits {
6091 u8 reserved_at_0[0x20];
6093 u8 reserved_at_20[0x1b];
6095 u8 reserved_at_3c[0x1];
6097 u8 reserved_at_3e[0x1];
6101 struct mlx5_ifc_modify_tir_out_bits {
6103 u8 reserved_at_8[0x18];
6107 u8 reserved_at_40[0x40];
6110 struct mlx5_ifc_modify_tir_in_bits {
6114 u8 reserved_at_20[0x10];
6117 u8 reserved_at_40[0x8];
6120 u8 reserved_at_60[0x20];
6122 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
6124 u8 reserved_at_c0[0x40];
6126 struct mlx5_ifc_tirc_bits ctx;
6129 struct mlx5_ifc_modify_sq_out_bits {
6131 u8 reserved_at_8[0x18];
6135 u8 reserved_at_40[0x40];
6138 struct mlx5_ifc_modify_sq_in_bits {
6142 u8 reserved_at_20[0x10];
6146 u8 reserved_at_44[0x4];
6149 u8 reserved_at_60[0x20];
6151 u8 modify_bitmask[0x40];
6153 u8 reserved_at_c0[0x40];
6155 struct mlx5_ifc_sqc_bits ctx;
6158 struct mlx5_ifc_modify_scheduling_element_out_bits {
6160 u8 reserved_at_8[0x18];
6164 u8 reserved_at_40[0x1c0];
6168 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
6169 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
6172 struct mlx5_ifc_modify_scheduling_element_in_bits {
6174 u8 reserved_at_10[0x10];
6176 u8 reserved_at_20[0x10];
6179 u8 scheduling_hierarchy[0x8];
6180 u8 reserved_at_48[0x18];
6182 u8 scheduling_element_id[0x20];
6184 u8 reserved_at_80[0x20];
6186 u8 modify_bitmask[0x20];
6188 u8 reserved_at_c0[0x40];
6190 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6192 u8 reserved_at_300[0x100];
6195 struct mlx5_ifc_modify_rqt_out_bits {
6197 u8 reserved_at_8[0x18];
6201 u8 reserved_at_40[0x40];
6204 struct mlx5_ifc_rqt_bitmask_bits {
6205 u8 reserved_at_0[0x20];
6207 u8 reserved_at_20[0x1f];
6211 struct mlx5_ifc_modify_rqt_in_bits {
6215 u8 reserved_at_20[0x10];
6218 u8 reserved_at_40[0x8];
6221 u8 reserved_at_60[0x20];
6223 struct mlx5_ifc_rqt_bitmask_bits bitmask;
6225 u8 reserved_at_c0[0x40];
6227 struct mlx5_ifc_rqtc_bits ctx;
6230 struct mlx5_ifc_modify_rq_out_bits {
6232 u8 reserved_at_8[0x18];
6236 u8 reserved_at_40[0x40];
6240 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
6241 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
6242 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
6245 struct mlx5_ifc_modify_rq_in_bits {
6249 u8 reserved_at_20[0x10];
6253 u8 reserved_at_44[0x4];
6256 u8 reserved_at_60[0x20];
6258 u8 modify_bitmask[0x40];
6260 u8 reserved_at_c0[0x40];
6262 struct mlx5_ifc_rqc_bits ctx;
6265 struct mlx5_ifc_modify_rmp_out_bits {
6267 u8 reserved_at_8[0x18];
6271 u8 reserved_at_40[0x40];
6274 struct mlx5_ifc_rmp_bitmask_bits {
6275 u8 reserved_at_0[0x20];
6277 u8 reserved_at_20[0x1f];
6281 struct mlx5_ifc_modify_rmp_in_bits {
6285 u8 reserved_at_20[0x10];
6289 u8 reserved_at_44[0x4];
6292 u8 reserved_at_60[0x20];
6294 struct mlx5_ifc_rmp_bitmask_bits bitmask;
6296 u8 reserved_at_c0[0x40];
6298 struct mlx5_ifc_rmpc_bits ctx;
6301 struct mlx5_ifc_modify_nic_vport_context_out_bits {
6303 u8 reserved_at_8[0x18];
6307 u8 reserved_at_40[0x40];
6310 struct mlx5_ifc_modify_nic_vport_field_select_bits {
6311 u8 reserved_at_0[0x12];
6312 u8 affiliation[0x1];
6313 u8 reserved_at_13[0x1];
6314 u8 disable_uc_local_lb[0x1];
6315 u8 disable_mc_local_lb[0x1];
6320 u8 change_event[0x1];
6322 u8 permanent_address[0x1];
6323 u8 addresses_list[0x1];
6325 u8 reserved_at_1f[0x1];
6328 struct mlx5_ifc_modify_nic_vport_context_in_bits {
6330 u8 reserved_at_10[0x10];
6332 u8 reserved_at_20[0x10];
6335 u8 other_vport[0x1];
6336 u8 reserved_at_41[0xf];
6337 u8 vport_number[0x10];
6339 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
6341 u8 reserved_at_80[0x780];
6343 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
6346 struct mlx5_ifc_modify_hca_vport_context_out_bits {
6348 u8 reserved_at_8[0x18];
6352 u8 reserved_at_40[0x40];
6355 struct mlx5_ifc_modify_hca_vport_context_in_bits {
6357 u8 reserved_at_10[0x10];
6359 u8 reserved_at_20[0x10];
6362 u8 other_vport[0x1];
6363 u8 reserved_at_41[0xb];
6365 u8 vport_number[0x10];
6367 u8 reserved_at_60[0x20];
6369 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
6372 struct mlx5_ifc_modify_cq_out_bits {
6374 u8 reserved_at_8[0x18];
6378 u8 reserved_at_40[0x40];
6382 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6383 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6386 struct mlx5_ifc_modify_cq_in_bits {
6390 u8 reserved_at_20[0x10];
6393 u8 reserved_at_40[0x8];
6396 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
6398 struct mlx5_ifc_cqc_bits cq_context;
6400 u8 reserved_at_280[0x60];
6402 u8 cq_umem_valid[0x1];
6403 u8 reserved_at_2e1[0x1f];
6405 u8 reserved_at_300[0x580];
6410 struct mlx5_ifc_modify_cong_status_out_bits {
6412 u8 reserved_at_8[0x18];
6416 u8 reserved_at_40[0x40];
6419 struct mlx5_ifc_modify_cong_status_in_bits {
6421 u8 reserved_at_10[0x10];
6423 u8 reserved_at_20[0x10];
6426 u8 reserved_at_40[0x18];
6428 u8 cong_protocol[0x4];
6432 u8 reserved_at_62[0x1e];
6435 struct mlx5_ifc_modify_cong_params_out_bits {
6437 u8 reserved_at_8[0x18];
6441 u8 reserved_at_40[0x40];
6444 struct mlx5_ifc_modify_cong_params_in_bits {
6446 u8 reserved_at_10[0x10];
6448 u8 reserved_at_20[0x10];
6451 u8 reserved_at_40[0x1c];
6452 u8 cong_protocol[0x4];
6454 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6456 u8 reserved_at_80[0x80];
6458 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6461 struct mlx5_ifc_manage_pages_out_bits {
6463 u8 reserved_at_8[0x18];
6467 u8 output_num_entries[0x20];
6469 u8 reserved_at_60[0x20];
6475 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
6476 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
6477 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
6480 struct mlx5_ifc_manage_pages_in_bits {
6482 u8 reserved_at_10[0x10];
6484 u8 reserved_at_20[0x10];
6487 u8 embedded_cpu_function[0x1];
6488 u8 reserved_at_41[0xf];
6489 u8 function_id[0x10];
6491 u8 input_num_entries[0x20];
6496 struct mlx5_ifc_mad_ifc_out_bits {
6498 u8 reserved_at_8[0x18];
6502 u8 reserved_at_40[0x40];
6504 u8 response_mad_packet[256][0x8];
6507 struct mlx5_ifc_mad_ifc_in_bits {
6509 u8 reserved_at_10[0x10];
6511 u8 reserved_at_20[0x10];
6514 u8 remote_lid[0x10];
6515 u8 reserved_at_50[0x8];
6518 u8 reserved_at_60[0x20];
6523 struct mlx5_ifc_init_hca_out_bits {
6525 u8 reserved_at_8[0x18];
6529 u8 reserved_at_40[0x40];
6532 struct mlx5_ifc_init_hca_in_bits {
6534 u8 reserved_at_10[0x10];
6536 u8 reserved_at_20[0x10];
6539 u8 reserved_at_40[0x40];
6540 u8 sw_owner_id[4][0x20];
6543 struct mlx5_ifc_init2rtr_qp_out_bits {
6545 u8 reserved_at_8[0x18];
6549 u8 reserved_at_40[0x40];
6552 struct mlx5_ifc_init2rtr_qp_in_bits {
6556 u8 reserved_at_20[0x10];
6559 u8 reserved_at_40[0x8];
6562 u8 reserved_at_60[0x20];
6564 u8 opt_param_mask[0x20];
6566 u8 reserved_at_a0[0x20];
6568 struct mlx5_ifc_qpc_bits qpc;
6570 u8 reserved_at_800[0x80];
6573 struct mlx5_ifc_init2init_qp_out_bits {
6575 u8 reserved_at_8[0x18];
6579 u8 reserved_at_40[0x40];
6582 struct mlx5_ifc_init2init_qp_in_bits {
6586 u8 reserved_at_20[0x10];
6589 u8 reserved_at_40[0x8];
6592 u8 reserved_at_60[0x20];
6594 u8 opt_param_mask[0x20];
6596 u8 reserved_at_a0[0x20];
6598 struct mlx5_ifc_qpc_bits qpc;
6600 u8 reserved_at_800[0x80];
6603 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6605 u8 reserved_at_8[0x18];
6609 u8 reserved_at_40[0x40];
6611 u8 packet_headers_log[128][0x8];
6613 u8 packet_syndrome[64][0x8];
6616 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6618 u8 reserved_at_10[0x10];
6620 u8 reserved_at_20[0x10];
6623 u8 reserved_at_40[0x40];
6626 struct mlx5_ifc_gen_eqe_in_bits {
6628 u8 reserved_at_10[0x10];
6630 u8 reserved_at_20[0x10];
6633 u8 reserved_at_40[0x18];
6636 u8 reserved_at_60[0x20];
6641 struct mlx5_ifc_gen_eq_out_bits {
6643 u8 reserved_at_8[0x18];
6647 u8 reserved_at_40[0x40];
6650 struct mlx5_ifc_enable_hca_out_bits {
6652 u8 reserved_at_8[0x18];
6656 u8 reserved_at_40[0x20];
6659 struct mlx5_ifc_enable_hca_in_bits {
6661 u8 reserved_at_10[0x10];
6663 u8 reserved_at_20[0x10];
6666 u8 embedded_cpu_function[0x1];
6667 u8 reserved_at_41[0xf];
6668 u8 function_id[0x10];
6670 u8 reserved_at_60[0x20];
6673 struct mlx5_ifc_drain_dct_out_bits {
6675 u8 reserved_at_8[0x18];
6679 u8 reserved_at_40[0x40];
6682 struct mlx5_ifc_drain_dct_in_bits {
6686 u8 reserved_at_20[0x10];
6689 u8 reserved_at_40[0x8];
6692 u8 reserved_at_60[0x20];
6695 struct mlx5_ifc_disable_hca_out_bits {
6697 u8 reserved_at_8[0x18];
6701 u8 reserved_at_40[0x20];
6704 struct mlx5_ifc_disable_hca_in_bits {
6706 u8 reserved_at_10[0x10];
6708 u8 reserved_at_20[0x10];
6711 u8 embedded_cpu_function[0x1];
6712 u8 reserved_at_41[0xf];
6713 u8 function_id[0x10];
6715 u8 reserved_at_60[0x20];
6718 struct mlx5_ifc_detach_from_mcg_out_bits {
6720 u8 reserved_at_8[0x18];
6724 u8 reserved_at_40[0x40];
6727 struct mlx5_ifc_detach_from_mcg_in_bits {
6731 u8 reserved_at_20[0x10];
6734 u8 reserved_at_40[0x8];
6737 u8 reserved_at_60[0x20];
6739 u8 multicast_gid[16][0x8];
6742 struct mlx5_ifc_destroy_xrq_out_bits {
6744 u8 reserved_at_8[0x18];
6748 u8 reserved_at_40[0x40];
6751 struct mlx5_ifc_destroy_xrq_in_bits {
6755 u8 reserved_at_20[0x10];
6758 u8 reserved_at_40[0x8];
6761 u8 reserved_at_60[0x20];
6764 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6766 u8 reserved_at_8[0x18];
6770 u8 reserved_at_40[0x40];
6773 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6777 u8 reserved_at_20[0x10];
6780 u8 reserved_at_40[0x8];
6783 u8 reserved_at_60[0x20];
6786 struct mlx5_ifc_destroy_tis_out_bits {
6788 u8 reserved_at_8[0x18];
6792 u8 reserved_at_40[0x40];
6795 struct mlx5_ifc_destroy_tis_in_bits {
6799 u8 reserved_at_20[0x10];
6802 u8 reserved_at_40[0x8];
6805 u8 reserved_at_60[0x20];
6808 struct mlx5_ifc_destroy_tir_out_bits {
6810 u8 reserved_at_8[0x18];
6814 u8 reserved_at_40[0x40];
6817 struct mlx5_ifc_destroy_tir_in_bits {
6821 u8 reserved_at_20[0x10];
6824 u8 reserved_at_40[0x8];
6827 u8 reserved_at_60[0x20];
6830 struct mlx5_ifc_destroy_srq_out_bits {
6832 u8 reserved_at_8[0x18];
6836 u8 reserved_at_40[0x40];
6839 struct mlx5_ifc_destroy_srq_in_bits {
6843 u8 reserved_at_20[0x10];
6846 u8 reserved_at_40[0x8];
6849 u8 reserved_at_60[0x20];
6852 struct mlx5_ifc_destroy_sq_out_bits {
6854 u8 reserved_at_8[0x18];
6858 u8 reserved_at_40[0x40];
6861 struct mlx5_ifc_destroy_sq_in_bits {
6865 u8 reserved_at_20[0x10];
6868 u8 reserved_at_40[0x8];
6871 u8 reserved_at_60[0x20];
6874 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6876 u8 reserved_at_8[0x18];
6880 u8 reserved_at_40[0x1c0];
6883 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6885 u8 reserved_at_10[0x10];
6887 u8 reserved_at_20[0x10];
6890 u8 scheduling_hierarchy[0x8];
6891 u8 reserved_at_48[0x18];
6893 u8 scheduling_element_id[0x20];
6895 u8 reserved_at_80[0x180];
6898 struct mlx5_ifc_destroy_rqt_out_bits {
6900 u8 reserved_at_8[0x18];
6904 u8 reserved_at_40[0x40];
6907 struct mlx5_ifc_destroy_rqt_in_bits {
6911 u8 reserved_at_20[0x10];
6914 u8 reserved_at_40[0x8];
6917 u8 reserved_at_60[0x20];
6920 struct mlx5_ifc_destroy_rq_out_bits {
6922 u8 reserved_at_8[0x18];
6926 u8 reserved_at_40[0x40];
6929 struct mlx5_ifc_destroy_rq_in_bits {
6933 u8 reserved_at_20[0x10];
6936 u8 reserved_at_40[0x8];
6939 u8 reserved_at_60[0x20];
6942 struct mlx5_ifc_set_delay_drop_params_in_bits {
6944 u8 reserved_at_10[0x10];
6946 u8 reserved_at_20[0x10];
6949 u8 reserved_at_40[0x20];
6951 u8 reserved_at_60[0x10];
6952 u8 delay_drop_timeout[0x10];
6955 struct mlx5_ifc_set_delay_drop_params_out_bits {
6957 u8 reserved_at_8[0x18];
6961 u8 reserved_at_40[0x40];
6964 struct mlx5_ifc_destroy_rmp_out_bits {
6966 u8 reserved_at_8[0x18];
6970 u8 reserved_at_40[0x40];
6973 struct mlx5_ifc_destroy_rmp_in_bits {
6977 u8 reserved_at_20[0x10];
6980 u8 reserved_at_40[0x8];
6983 u8 reserved_at_60[0x20];
6986 struct mlx5_ifc_destroy_qp_out_bits {
6988 u8 reserved_at_8[0x18];
6992 u8 reserved_at_40[0x40];
6995 struct mlx5_ifc_destroy_qp_in_bits {
6999 u8 reserved_at_20[0x10];
7002 u8 reserved_at_40[0x8];
7005 u8 reserved_at_60[0x20];
7008 struct mlx5_ifc_destroy_psv_out_bits {
7010 u8 reserved_at_8[0x18];
7014 u8 reserved_at_40[0x40];
7017 struct mlx5_ifc_destroy_psv_in_bits {
7019 u8 reserved_at_10[0x10];
7021 u8 reserved_at_20[0x10];
7024 u8 reserved_at_40[0x8];
7027 u8 reserved_at_60[0x20];
7030 struct mlx5_ifc_destroy_mkey_out_bits {
7032 u8 reserved_at_8[0x18];
7036 u8 reserved_at_40[0x40];
7039 struct mlx5_ifc_destroy_mkey_in_bits {
7041 u8 reserved_at_10[0x10];
7043 u8 reserved_at_20[0x10];
7046 u8 reserved_at_40[0x8];
7047 u8 mkey_index[0x18];
7049 u8 reserved_at_60[0x20];
7052 struct mlx5_ifc_destroy_flow_table_out_bits {
7054 u8 reserved_at_8[0x18];
7058 u8 reserved_at_40[0x40];
7061 struct mlx5_ifc_destroy_flow_table_in_bits {
7063 u8 reserved_at_10[0x10];
7065 u8 reserved_at_20[0x10];
7068 u8 other_vport[0x1];
7069 u8 reserved_at_41[0xf];
7070 u8 vport_number[0x10];
7072 u8 reserved_at_60[0x20];
7075 u8 reserved_at_88[0x18];
7077 u8 reserved_at_a0[0x8];
7080 u8 reserved_at_c0[0x140];
7083 struct mlx5_ifc_destroy_flow_group_out_bits {
7085 u8 reserved_at_8[0x18];
7089 u8 reserved_at_40[0x40];
7092 struct mlx5_ifc_destroy_flow_group_in_bits {
7094 u8 reserved_at_10[0x10];
7096 u8 reserved_at_20[0x10];
7099 u8 other_vport[0x1];
7100 u8 reserved_at_41[0xf];
7101 u8 vport_number[0x10];
7103 u8 reserved_at_60[0x20];
7106 u8 reserved_at_88[0x18];
7108 u8 reserved_at_a0[0x8];
7113 u8 reserved_at_e0[0x120];
7116 struct mlx5_ifc_destroy_eq_out_bits {
7118 u8 reserved_at_8[0x18];
7122 u8 reserved_at_40[0x40];
7125 struct mlx5_ifc_destroy_eq_in_bits {
7127 u8 reserved_at_10[0x10];
7129 u8 reserved_at_20[0x10];
7132 u8 reserved_at_40[0x18];
7135 u8 reserved_at_60[0x20];
7138 struct mlx5_ifc_destroy_dct_out_bits {
7140 u8 reserved_at_8[0x18];
7144 u8 reserved_at_40[0x40];
7147 struct mlx5_ifc_destroy_dct_in_bits {
7151 u8 reserved_at_20[0x10];
7154 u8 reserved_at_40[0x8];
7157 u8 reserved_at_60[0x20];
7160 struct mlx5_ifc_destroy_cq_out_bits {
7162 u8 reserved_at_8[0x18];
7166 u8 reserved_at_40[0x40];
7169 struct mlx5_ifc_destroy_cq_in_bits {
7173 u8 reserved_at_20[0x10];
7176 u8 reserved_at_40[0x8];
7179 u8 reserved_at_60[0x20];
7182 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
7184 u8 reserved_at_8[0x18];
7188 u8 reserved_at_40[0x40];
7191 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
7193 u8 reserved_at_10[0x10];
7195 u8 reserved_at_20[0x10];
7198 u8 reserved_at_40[0x20];
7200 u8 reserved_at_60[0x10];
7201 u8 vxlan_udp_port[0x10];
7204 struct mlx5_ifc_delete_l2_table_entry_out_bits {
7206 u8 reserved_at_8[0x18];
7210 u8 reserved_at_40[0x40];
7213 struct mlx5_ifc_delete_l2_table_entry_in_bits {
7215 u8 reserved_at_10[0x10];
7217 u8 reserved_at_20[0x10];
7220 u8 reserved_at_40[0x60];
7222 u8 reserved_at_a0[0x8];
7223 u8 table_index[0x18];
7225 u8 reserved_at_c0[0x140];
7228 struct mlx5_ifc_delete_fte_out_bits {
7230 u8 reserved_at_8[0x18];
7234 u8 reserved_at_40[0x40];
7237 struct mlx5_ifc_delete_fte_in_bits {
7239 u8 reserved_at_10[0x10];
7241 u8 reserved_at_20[0x10];
7244 u8 other_vport[0x1];
7245 u8 reserved_at_41[0xf];
7246 u8 vport_number[0x10];
7248 u8 reserved_at_60[0x20];
7251 u8 reserved_at_88[0x18];
7253 u8 reserved_at_a0[0x8];
7256 u8 reserved_at_c0[0x40];
7258 u8 flow_index[0x20];
7260 u8 reserved_at_120[0xe0];
7263 struct mlx5_ifc_dealloc_xrcd_out_bits {
7265 u8 reserved_at_8[0x18];
7269 u8 reserved_at_40[0x40];
7272 struct mlx5_ifc_dealloc_xrcd_in_bits {
7276 u8 reserved_at_20[0x10];
7279 u8 reserved_at_40[0x8];
7282 u8 reserved_at_60[0x20];
7285 struct mlx5_ifc_dealloc_uar_out_bits {
7287 u8 reserved_at_8[0x18];
7291 u8 reserved_at_40[0x40];
7294 struct mlx5_ifc_dealloc_uar_in_bits {
7296 u8 reserved_at_10[0x10];
7298 u8 reserved_at_20[0x10];
7301 u8 reserved_at_40[0x8];
7304 u8 reserved_at_60[0x20];
7307 struct mlx5_ifc_dealloc_transport_domain_out_bits {
7309 u8 reserved_at_8[0x18];
7313 u8 reserved_at_40[0x40];
7316 struct mlx5_ifc_dealloc_transport_domain_in_bits {
7320 u8 reserved_at_20[0x10];
7323 u8 reserved_at_40[0x8];
7324 u8 transport_domain[0x18];
7326 u8 reserved_at_60[0x20];
7329 struct mlx5_ifc_dealloc_q_counter_out_bits {
7331 u8 reserved_at_8[0x18];
7335 u8 reserved_at_40[0x40];
7338 struct mlx5_ifc_dealloc_q_counter_in_bits {
7340 u8 reserved_at_10[0x10];
7342 u8 reserved_at_20[0x10];
7345 u8 reserved_at_40[0x18];
7346 u8 counter_set_id[0x8];
7348 u8 reserved_at_60[0x20];
7351 struct mlx5_ifc_dealloc_pd_out_bits {
7353 u8 reserved_at_8[0x18];
7357 u8 reserved_at_40[0x40];
7360 struct mlx5_ifc_dealloc_pd_in_bits {
7364 u8 reserved_at_20[0x10];
7367 u8 reserved_at_40[0x8];
7370 u8 reserved_at_60[0x20];
7373 struct mlx5_ifc_dealloc_flow_counter_out_bits {
7375 u8 reserved_at_8[0x18];
7379 u8 reserved_at_40[0x40];
7382 struct mlx5_ifc_dealloc_flow_counter_in_bits {
7384 u8 reserved_at_10[0x10];
7386 u8 reserved_at_20[0x10];
7389 u8 flow_counter_id[0x20];
7391 u8 reserved_at_60[0x20];
7394 struct mlx5_ifc_create_xrq_out_bits {
7396 u8 reserved_at_8[0x18];
7400 u8 reserved_at_40[0x8];
7403 u8 reserved_at_60[0x20];
7406 struct mlx5_ifc_create_xrq_in_bits {
7410 u8 reserved_at_20[0x10];
7413 u8 reserved_at_40[0x40];
7415 struct mlx5_ifc_xrqc_bits xrq_context;
7418 struct mlx5_ifc_create_xrc_srq_out_bits {
7420 u8 reserved_at_8[0x18];
7424 u8 reserved_at_40[0x8];
7427 u8 reserved_at_60[0x20];
7430 struct mlx5_ifc_create_xrc_srq_in_bits {
7434 u8 reserved_at_20[0x10];
7437 u8 reserved_at_40[0x40];
7439 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7441 u8 reserved_at_280[0x60];
7443 u8 xrc_srq_umem_valid[0x1];
7444 u8 reserved_at_2e1[0x1f];
7446 u8 reserved_at_300[0x580];
7451 struct mlx5_ifc_create_tis_out_bits {
7453 u8 reserved_at_8[0x18];
7457 u8 reserved_at_40[0x8];
7460 u8 reserved_at_60[0x20];
7463 struct mlx5_ifc_create_tis_in_bits {
7467 u8 reserved_at_20[0x10];
7470 u8 reserved_at_40[0xc0];
7472 struct mlx5_ifc_tisc_bits ctx;
7475 struct mlx5_ifc_create_tir_out_bits {
7477 u8 icm_address_63_40[0x18];
7481 u8 icm_address_39_32[0x8];
7484 u8 icm_address_31_0[0x20];
7487 struct mlx5_ifc_create_tir_in_bits {
7491 u8 reserved_at_20[0x10];
7494 u8 reserved_at_40[0xc0];
7496 struct mlx5_ifc_tirc_bits ctx;
7499 struct mlx5_ifc_create_srq_out_bits {
7501 u8 reserved_at_8[0x18];
7505 u8 reserved_at_40[0x8];
7508 u8 reserved_at_60[0x20];
7511 struct mlx5_ifc_create_srq_in_bits {
7515 u8 reserved_at_20[0x10];
7518 u8 reserved_at_40[0x40];
7520 struct mlx5_ifc_srqc_bits srq_context_entry;
7522 u8 reserved_at_280[0x600];
7527 struct mlx5_ifc_create_sq_out_bits {
7529 u8 reserved_at_8[0x18];
7533 u8 reserved_at_40[0x8];
7536 u8 reserved_at_60[0x20];
7539 struct mlx5_ifc_create_sq_in_bits {
7543 u8 reserved_at_20[0x10];
7546 u8 reserved_at_40[0xc0];
7548 struct mlx5_ifc_sqc_bits ctx;
7551 struct mlx5_ifc_create_scheduling_element_out_bits {
7553 u8 reserved_at_8[0x18];
7557 u8 reserved_at_40[0x40];
7559 u8 scheduling_element_id[0x20];
7561 u8 reserved_at_a0[0x160];
7564 struct mlx5_ifc_create_scheduling_element_in_bits {
7566 u8 reserved_at_10[0x10];
7568 u8 reserved_at_20[0x10];
7571 u8 scheduling_hierarchy[0x8];
7572 u8 reserved_at_48[0x18];
7574 u8 reserved_at_60[0xa0];
7576 struct mlx5_ifc_scheduling_context_bits scheduling_context;
7578 u8 reserved_at_300[0x100];
7581 struct mlx5_ifc_create_rqt_out_bits {
7583 u8 reserved_at_8[0x18];
7587 u8 reserved_at_40[0x8];
7590 u8 reserved_at_60[0x20];
7593 struct mlx5_ifc_create_rqt_in_bits {
7597 u8 reserved_at_20[0x10];
7600 u8 reserved_at_40[0xc0];
7602 struct mlx5_ifc_rqtc_bits rqt_context;
7605 struct mlx5_ifc_create_rq_out_bits {
7607 u8 reserved_at_8[0x18];
7611 u8 reserved_at_40[0x8];
7614 u8 reserved_at_60[0x20];
7617 struct mlx5_ifc_create_rq_in_bits {
7621 u8 reserved_at_20[0x10];
7624 u8 reserved_at_40[0xc0];
7626 struct mlx5_ifc_rqc_bits ctx;
7629 struct mlx5_ifc_create_rmp_out_bits {
7631 u8 reserved_at_8[0x18];
7635 u8 reserved_at_40[0x8];
7638 u8 reserved_at_60[0x20];
7641 struct mlx5_ifc_create_rmp_in_bits {
7645 u8 reserved_at_20[0x10];
7648 u8 reserved_at_40[0xc0];
7650 struct mlx5_ifc_rmpc_bits ctx;
7653 struct mlx5_ifc_create_qp_out_bits {
7655 u8 reserved_at_8[0x18];
7659 u8 reserved_at_40[0x8];
7662 u8 reserved_at_60[0x20];
7665 struct mlx5_ifc_create_qp_in_bits {
7669 u8 reserved_at_20[0x10];
7672 u8 reserved_at_40[0x40];
7674 u8 opt_param_mask[0x20];
7676 u8 reserved_at_a0[0x20];
7678 struct mlx5_ifc_qpc_bits qpc;
7680 u8 reserved_at_800[0x60];
7682 u8 wq_umem_valid[0x1];
7683 u8 reserved_at_861[0x1f];
7688 struct mlx5_ifc_create_psv_out_bits {
7690 u8 reserved_at_8[0x18];
7694 u8 reserved_at_40[0x40];
7696 u8 reserved_at_80[0x8];
7697 u8 psv0_index[0x18];
7699 u8 reserved_at_a0[0x8];
7700 u8 psv1_index[0x18];
7702 u8 reserved_at_c0[0x8];
7703 u8 psv2_index[0x18];
7705 u8 reserved_at_e0[0x8];
7706 u8 psv3_index[0x18];
7709 struct mlx5_ifc_create_psv_in_bits {
7711 u8 reserved_at_10[0x10];
7713 u8 reserved_at_20[0x10];
7717 u8 reserved_at_44[0x4];
7720 u8 reserved_at_60[0x20];
7723 struct mlx5_ifc_create_mkey_out_bits {
7725 u8 reserved_at_8[0x18];
7729 u8 reserved_at_40[0x8];
7730 u8 mkey_index[0x18];
7732 u8 reserved_at_60[0x20];
7735 struct mlx5_ifc_create_mkey_in_bits {
7737 u8 reserved_at_10[0x10];
7739 u8 reserved_at_20[0x10];
7742 u8 reserved_at_40[0x20];
7745 u8 mkey_umem_valid[0x1];
7746 u8 reserved_at_62[0x1e];
7748 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7750 u8 reserved_at_280[0x80];
7752 u8 translations_octword_actual_size[0x20];
7754 u8 reserved_at_320[0x560];
7756 u8 klm_pas_mtt[0][0x20];
7760 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0,
7761 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1,
7762 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2,
7763 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3,
7764 MLX5_FLOW_TABLE_TYPE_FDB = 0X4,
7765 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5,
7766 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6,
7769 struct mlx5_ifc_create_flow_table_out_bits {
7771 u8 icm_address_63_40[0x18];
7775 u8 icm_address_39_32[0x8];
7778 u8 icm_address_31_0[0x20];
7781 struct mlx5_ifc_create_flow_table_in_bits {
7783 u8 reserved_at_10[0x10];
7785 u8 reserved_at_20[0x10];
7788 u8 other_vport[0x1];
7789 u8 reserved_at_41[0xf];
7790 u8 vport_number[0x10];
7792 u8 reserved_at_60[0x20];
7795 u8 reserved_at_88[0x18];
7797 u8 reserved_at_a0[0x20];
7799 struct mlx5_ifc_flow_table_context_bits flow_table_context;
7802 struct mlx5_ifc_create_flow_group_out_bits {
7804 u8 reserved_at_8[0x18];
7808 u8 reserved_at_40[0x8];
7811 u8 reserved_at_60[0x20];
7815 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
7816 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
7817 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
7818 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7821 struct mlx5_ifc_create_flow_group_in_bits {
7823 u8 reserved_at_10[0x10];
7825 u8 reserved_at_20[0x10];
7828 u8 other_vport[0x1];
7829 u8 reserved_at_41[0xf];
7830 u8 vport_number[0x10];
7832 u8 reserved_at_60[0x20];
7835 u8 reserved_at_88[0x18];
7837 u8 reserved_at_a0[0x8];
7840 u8 source_eswitch_owner_vhca_id_valid[0x1];
7842 u8 reserved_at_c1[0x1f];
7844 u8 start_flow_index[0x20];
7846 u8 reserved_at_100[0x20];
7848 u8 end_flow_index[0x20];
7850 u8 reserved_at_140[0xa0];
7852 u8 reserved_at_1e0[0x18];
7853 u8 match_criteria_enable[0x8];
7855 struct mlx5_ifc_fte_match_param_bits match_criteria;
7857 u8 reserved_at_1200[0xe00];
7860 struct mlx5_ifc_create_eq_out_bits {
7862 u8 reserved_at_8[0x18];
7866 u8 reserved_at_40[0x18];
7869 u8 reserved_at_60[0x20];
7872 struct mlx5_ifc_create_eq_in_bits {
7876 u8 reserved_at_20[0x10];
7879 u8 reserved_at_40[0x40];
7881 struct mlx5_ifc_eqc_bits eq_context_entry;
7883 u8 reserved_at_280[0x40];
7885 u8 event_bitmask[4][0x40];
7887 u8 reserved_at_3c0[0x4c0];
7892 struct mlx5_ifc_create_dct_out_bits {
7894 u8 reserved_at_8[0x18];
7898 u8 reserved_at_40[0x8];
7901 u8 reserved_at_60[0x20];
7904 struct mlx5_ifc_create_dct_in_bits {
7908 u8 reserved_at_20[0x10];
7911 u8 reserved_at_40[0x40];
7913 struct mlx5_ifc_dctc_bits dct_context_entry;
7915 u8 reserved_at_280[0x180];
7918 struct mlx5_ifc_create_cq_out_bits {
7920 u8 reserved_at_8[0x18];
7924 u8 reserved_at_40[0x8];
7927 u8 reserved_at_60[0x20];
7930 struct mlx5_ifc_create_cq_in_bits {
7934 u8 reserved_at_20[0x10];
7937 u8 reserved_at_40[0x40];
7939 struct mlx5_ifc_cqc_bits cq_context;
7941 u8 reserved_at_280[0x60];
7943 u8 cq_umem_valid[0x1];
7944 u8 reserved_at_2e1[0x59f];
7949 struct mlx5_ifc_config_int_moderation_out_bits {
7951 u8 reserved_at_8[0x18];
7955 u8 reserved_at_40[0x4];
7957 u8 int_vector[0x10];
7959 u8 reserved_at_60[0x20];
7963 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
7964 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
7967 struct mlx5_ifc_config_int_moderation_in_bits {
7969 u8 reserved_at_10[0x10];
7971 u8 reserved_at_20[0x10];
7974 u8 reserved_at_40[0x4];
7976 u8 int_vector[0x10];
7978 u8 reserved_at_60[0x20];
7981 struct mlx5_ifc_attach_to_mcg_out_bits {
7983 u8 reserved_at_8[0x18];
7987 u8 reserved_at_40[0x40];
7990 struct mlx5_ifc_attach_to_mcg_in_bits {
7994 u8 reserved_at_20[0x10];
7997 u8 reserved_at_40[0x8];
8000 u8 reserved_at_60[0x20];
8002 u8 multicast_gid[16][0x8];
8005 struct mlx5_ifc_arm_xrq_out_bits {
8007 u8 reserved_at_8[0x18];
8011 u8 reserved_at_40[0x40];
8014 struct mlx5_ifc_arm_xrq_in_bits {
8016 u8 reserved_at_10[0x10];
8018 u8 reserved_at_20[0x10];
8021 u8 reserved_at_40[0x8];
8024 u8 reserved_at_60[0x10];
8028 struct mlx5_ifc_arm_xrc_srq_out_bits {
8030 u8 reserved_at_8[0x18];
8034 u8 reserved_at_40[0x40];
8038 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8041 struct mlx5_ifc_arm_xrc_srq_in_bits {
8045 u8 reserved_at_20[0x10];
8048 u8 reserved_at_40[0x8];
8051 u8 reserved_at_60[0x10];
8055 struct mlx5_ifc_arm_rq_out_bits {
8057 u8 reserved_at_8[0x18];
8061 u8 reserved_at_40[0x40];
8065 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8066 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
8069 struct mlx5_ifc_arm_rq_in_bits {
8073 u8 reserved_at_20[0x10];
8076 u8 reserved_at_40[0x8];
8077 u8 srq_number[0x18];
8079 u8 reserved_at_60[0x10];
8083 struct mlx5_ifc_arm_dct_out_bits {
8085 u8 reserved_at_8[0x18];
8089 u8 reserved_at_40[0x40];
8092 struct mlx5_ifc_arm_dct_in_bits {
8094 u8 reserved_at_10[0x10];
8096 u8 reserved_at_20[0x10];
8099 u8 reserved_at_40[0x8];
8100 u8 dct_number[0x18];
8102 u8 reserved_at_60[0x20];
8105 struct mlx5_ifc_alloc_xrcd_out_bits {
8107 u8 reserved_at_8[0x18];
8111 u8 reserved_at_40[0x8];
8114 u8 reserved_at_60[0x20];
8117 struct mlx5_ifc_alloc_xrcd_in_bits {
8121 u8 reserved_at_20[0x10];
8124 u8 reserved_at_40[0x40];
8127 struct mlx5_ifc_alloc_uar_out_bits {
8129 u8 reserved_at_8[0x18];
8133 u8 reserved_at_40[0x8];
8136 u8 reserved_at_60[0x20];
8139 struct mlx5_ifc_alloc_uar_in_bits {
8141 u8 reserved_at_10[0x10];
8143 u8 reserved_at_20[0x10];
8146 u8 reserved_at_40[0x40];
8149 struct mlx5_ifc_alloc_transport_domain_out_bits {
8151 u8 reserved_at_8[0x18];
8155 u8 reserved_at_40[0x8];
8156 u8 transport_domain[0x18];
8158 u8 reserved_at_60[0x20];
8161 struct mlx5_ifc_alloc_transport_domain_in_bits {
8165 u8 reserved_at_20[0x10];
8168 u8 reserved_at_40[0x40];
8171 struct mlx5_ifc_alloc_q_counter_out_bits {
8173 u8 reserved_at_8[0x18];
8177 u8 reserved_at_40[0x18];
8178 u8 counter_set_id[0x8];
8180 u8 reserved_at_60[0x20];
8183 struct mlx5_ifc_alloc_q_counter_in_bits {
8187 u8 reserved_at_20[0x10];
8190 u8 reserved_at_40[0x40];
8193 struct mlx5_ifc_alloc_pd_out_bits {
8195 u8 reserved_at_8[0x18];
8199 u8 reserved_at_40[0x8];
8202 u8 reserved_at_60[0x20];
8205 struct mlx5_ifc_alloc_pd_in_bits {
8209 u8 reserved_at_20[0x10];
8212 u8 reserved_at_40[0x40];
8215 struct mlx5_ifc_alloc_flow_counter_out_bits {
8217 u8 reserved_at_8[0x18];
8221 u8 flow_counter_id[0x20];
8223 u8 reserved_at_60[0x20];
8226 struct mlx5_ifc_alloc_flow_counter_in_bits {
8228 u8 reserved_at_10[0x10];
8230 u8 reserved_at_20[0x10];
8233 u8 reserved_at_40[0x38];
8234 u8 flow_counter_bulk[0x8];
8237 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
8239 u8 reserved_at_8[0x18];
8243 u8 reserved_at_40[0x40];
8246 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
8248 u8 reserved_at_10[0x10];
8250 u8 reserved_at_20[0x10];
8253 u8 reserved_at_40[0x20];
8255 u8 reserved_at_60[0x10];
8256 u8 vxlan_udp_port[0x10];
8259 struct mlx5_ifc_set_pp_rate_limit_out_bits {
8261 u8 reserved_at_8[0x18];
8265 u8 reserved_at_40[0x40];
8268 struct mlx5_ifc_set_pp_rate_limit_in_bits {
8270 u8 reserved_at_10[0x10];
8272 u8 reserved_at_20[0x10];
8275 u8 reserved_at_40[0x10];
8276 u8 rate_limit_index[0x10];
8278 u8 reserved_at_60[0x20];
8280 u8 rate_limit[0x20];
8282 u8 burst_upper_bound[0x20];
8284 u8 reserved_at_c0[0x10];
8285 u8 typical_packet_size[0x10];
8287 u8 reserved_at_e0[0x120];
8290 struct mlx5_ifc_access_register_out_bits {
8292 u8 reserved_at_8[0x18];
8296 u8 reserved_at_40[0x40];
8298 u8 register_data[0][0x20];
8302 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8303 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8306 struct mlx5_ifc_access_register_in_bits {
8308 u8 reserved_at_10[0x10];
8310 u8 reserved_at_20[0x10];
8313 u8 reserved_at_40[0x10];
8314 u8 register_id[0x10];
8318 u8 register_data[0][0x20];
8321 struct mlx5_ifc_sltp_reg_bits {
8326 u8 reserved_at_12[0x2];
8328 u8 reserved_at_18[0x8];
8330 u8 reserved_at_20[0x20];
8332 u8 reserved_at_40[0x7];
8338 u8 reserved_at_60[0xc];
8339 u8 ob_preemp_mode[0x4];
8343 u8 reserved_at_80[0x20];
8346 struct mlx5_ifc_slrg_reg_bits {
8351 u8 reserved_at_12[0x2];
8353 u8 reserved_at_18[0x8];
8355 u8 time_to_link_up[0x10];
8356 u8 reserved_at_30[0xc];
8357 u8 grade_lane_speed[0x4];
8359 u8 grade_version[0x8];
8362 u8 reserved_at_60[0x4];
8363 u8 height_grade_type[0x4];
8364 u8 height_grade[0x18];
8369 u8 reserved_at_a0[0x10];
8370 u8 height_sigma[0x10];
8372 u8 reserved_at_c0[0x20];
8374 u8 reserved_at_e0[0x4];
8375 u8 phase_grade_type[0x4];
8376 u8 phase_grade[0x18];
8378 u8 reserved_at_100[0x8];
8379 u8 phase_eo_pos[0x8];
8380 u8 reserved_at_110[0x8];
8381 u8 phase_eo_neg[0x8];
8383 u8 ffe_set_tested[0x10];
8384 u8 test_errors_per_lane[0x10];
8387 struct mlx5_ifc_pvlc_reg_bits {
8388 u8 reserved_at_0[0x8];
8390 u8 reserved_at_10[0x10];
8392 u8 reserved_at_20[0x1c];
8395 u8 reserved_at_40[0x1c];
8398 u8 reserved_at_60[0x1c];
8399 u8 vl_operational[0x4];
8402 struct mlx5_ifc_pude_reg_bits {
8405 u8 reserved_at_10[0x4];
8406 u8 admin_status[0x4];
8407 u8 reserved_at_18[0x4];
8408 u8 oper_status[0x4];
8410 u8 reserved_at_20[0x60];
8413 struct mlx5_ifc_ptys_reg_bits {
8414 u8 reserved_at_0[0x1];
8415 u8 an_disable_admin[0x1];
8416 u8 an_disable_cap[0x1];
8417 u8 reserved_at_3[0x5];
8419 u8 reserved_at_10[0xd];
8423 u8 reserved_at_24[0x1c];
8425 u8 ext_eth_proto_capability[0x20];
8427 u8 eth_proto_capability[0x20];
8429 u8 ib_link_width_capability[0x10];
8430 u8 ib_proto_capability[0x10];
8432 u8 ext_eth_proto_admin[0x20];
8434 u8 eth_proto_admin[0x20];
8436 u8 ib_link_width_admin[0x10];
8437 u8 ib_proto_admin[0x10];
8439 u8 ext_eth_proto_oper[0x20];
8441 u8 eth_proto_oper[0x20];
8443 u8 ib_link_width_oper[0x10];
8444 u8 ib_proto_oper[0x10];
8446 u8 reserved_at_160[0x1c];
8447 u8 connector_type[0x4];
8449 u8 eth_proto_lp_advertise[0x20];
8451 u8 reserved_at_1a0[0x60];
8454 struct mlx5_ifc_mlcr_reg_bits {
8455 u8 reserved_at_0[0x8];
8457 u8 reserved_at_10[0x20];
8459 u8 beacon_duration[0x10];
8460 u8 reserved_at_40[0x10];
8462 u8 beacon_remain[0x10];
8465 struct mlx5_ifc_ptas_reg_bits {
8466 u8 reserved_at_0[0x20];
8468 u8 algorithm_options[0x10];
8469 u8 reserved_at_30[0x4];
8470 u8 repetitions_mode[0x4];
8471 u8 num_of_repetitions[0x8];
8473 u8 grade_version[0x8];
8474 u8 height_grade_type[0x4];
8475 u8 phase_grade_type[0x4];
8476 u8 height_grade_weight[0x8];
8477 u8 phase_grade_weight[0x8];
8479 u8 gisim_measure_bits[0x10];
8480 u8 adaptive_tap_measure_bits[0x10];
8482 u8 ber_bath_high_error_threshold[0x10];
8483 u8 ber_bath_mid_error_threshold[0x10];
8485 u8 ber_bath_low_error_threshold[0x10];
8486 u8 one_ratio_high_threshold[0x10];
8488 u8 one_ratio_high_mid_threshold[0x10];
8489 u8 one_ratio_low_mid_threshold[0x10];
8491 u8 one_ratio_low_threshold[0x10];
8492 u8 ndeo_error_threshold[0x10];
8494 u8 mixer_offset_step_size[0x10];
8495 u8 reserved_at_110[0x8];
8496 u8 mix90_phase_for_voltage_bath[0x8];
8498 u8 mixer_offset_start[0x10];
8499 u8 mixer_offset_end[0x10];
8501 u8 reserved_at_140[0x15];
8502 u8 ber_test_time[0xb];
8505 struct mlx5_ifc_pspa_reg_bits {
8509 u8 reserved_at_18[0x8];
8511 u8 reserved_at_20[0x20];
8514 struct mlx5_ifc_pqdr_reg_bits {
8515 u8 reserved_at_0[0x8];
8517 u8 reserved_at_10[0x5];
8519 u8 reserved_at_18[0x6];
8522 u8 reserved_at_20[0x20];
8524 u8 reserved_at_40[0x10];
8525 u8 min_threshold[0x10];
8527 u8 reserved_at_60[0x10];
8528 u8 max_threshold[0x10];
8530 u8 reserved_at_80[0x10];
8531 u8 mark_probability_denominator[0x10];
8533 u8 reserved_at_a0[0x60];
8536 struct mlx5_ifc_ppsc_reg_bits {
8537 u8 reserved_at_0[0x8];
8539 u8 reserved_at_10[0x10];
8541 u8 reserved_at_20[0x60];
8543 u8 reserved_at_80[0x1c];
8546 u8 reserved_at_a0[0x1c];
8547 u8 wrps_status[0x4];
8549 u8 reserved_at_c0[0x8];
8550 u8 up_threshold[0x8];
8551 u8 reserved_at_d0[0x8];
8552 u8 down_threshold[0x8];
8554 u8 reserved_at_e0[0x20];
8556 u8 reserved_at_100[0x1c];
8559 u8 reserved_at_120[0x1c];
8560 u8 srps_status[0x4];
8562 u8 reserved_at_140[0x40];
8565 struct mlx5_ifc_pplr_reg_bits {
8566 u8 reserved_at_0[0x8];
8568 u8 reserved_at_10[0x10];
8570 u8 reserved_at_20[0x8];
8572 u8 reserved_at_30[0x8];
8576 struct mlx5_ifc_pplm_reg_bits {
8577 u8 reserved_at_0[0x8];
8579 u8 reserved_at_10[0x10];
8581 u8 reserved_at_20[0x20];
8583 u8 port_profile_mode[0x8];
8584 u8 static_port_profile[0x8];
8585 u8 active_port_profile[0x8];
8586 u8 reserved_at_58[0x8];
8588 u8 retransmission_active[0x8];
8589 u8 fec_mode_active[0x18];
8591 u8 rs_fec_correction_bypass_cap[0x4];
8592 u8 reserved_at_84[0x8];
8593 u8 fec_override_cap_56g[0x4];
8594 u8 fec_override_cap_100g[0x4];
8595 u8 fec_override_cap_50g[0x4];
8596 u8 fec_override_cap_25g[0x4];
8597 u8 fec_override_cap_10g_40g[0x4];
8599 u8 rs_fec_correction_bypass_admin[0x4];
8600 u8 reserved_at_a4[0x8];
8601 u8 fec_override_admin_56g[0x4];
8602 u8 fec_override_admin_100g[0x4];
8603 u8 fec_override_admin_50g[0x4];
8604 u8 fec_override_admin_25g[0x4];
8605 u8 fec_override_admin_10g_40g[0x4];
8607 u8 fec_override_cap_400g_8x[0x10];
8608 u8 fec_override_cap_200g_4x[0x10];
8610 u8 fec_override_cap_100g_2x[0x10];
8611 u8 fec_override_cap_50g_1x[0x10];
8613 u8 fec_override_admin_400g_8x[0x10];
8614 u8 fec_override_admin_200g_4x[0x10];
8616 u8 fec_override_admin_100g_2x[0x10];
8617 u8 fec_override_admin_50g_1x[0x10];
8620 struct mlx5_ifc_ppcnt_reg_bits {
8624 u8 reserved_at_12[0x8];
8628 u8 reserved_at_21[0x1c];
8631 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8634 struct mlx5_ifc_mpein_reg_bits {
8635 u8 reserved_at_0[0x2];
8639 u8 reserved_at_18[0x8];
8641 u8 capability_mask[0x20];
8643 u8 reserved_at_40[0x8];
8644 u8 link_width_enabled[0x8];
8645 u8 link_speed_enabled[0x10];
8647 u8 lane0_physical_position[0x8];
8648 u8 link_width_active[0x8];
8649 u8 link_speed_active[0x10];
8651 u8 num_of_pfs[0x10];
8652 u8 num_of_vfs[0x10];
8655 u8 reserved_at_b0[0x10];
8657 u8 max_read_request_size[0x4];
8658 u8 max_payload_size[0x4];
8659 u8 reserved_at_c8[0x5];
8662 u8 reserved_at_d4[0xb];
8663 u8 lane_reversal[0x1];
8665 u8 reserved_at_e0[0x14];
8668 u8 reserved_at_100[0x20];
8670 u8 device_status[0x10];
8672 u8 reserved_at_138[0x8];
8674 u8 reserved_at_140[0x10];
8675 u8 receiver_detect_result[0x10];
8677 u8 reserved_at_160[0x20];
8680 struct mlx5_ifc_mpcnt_reg_bits {
8681 u8 reserved_at_0[0x8];
8683 u8 reserved_at_10[0xa];
8687 u8 reserved_at_21[0x1f];
8689 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8692 struct mlx5_ifc_ppad_reg_bits {
8693 u8 reserved_at_0[0x3];
8695 u8 reserved_at_4[0x4];
8701 u8 reserved_at_40[0x40];
8704 struct mlx5_ifc_pmtu_reg_bits {
8705 u8 reserved_at_0[0x8];
8707 u8 reserved_at_10[0x10];
8710 u8 reserved_at_30[0x10];
8713 u8 reserved_at_50[0x10];
8716 u8 reserved_at_70[0x10];
8719 struct mlx5_ifc_pmpr_reg_bits {
8720 u8 reserved_at_0[0x8];
8722 u8 reserved_at_10[0x10];
8724 u8 reserved_at_20[0x18];
8725 u8 attenuation_5g[0x8];
8727 u8 reserved_at_40[0x18];
8728 u8 attenuation_7g[0x8];
8730 u8 reserved_at_60[0x18];
8731 u8 attenuation_12g[0x8];
8734 struct mlx5_ifc_pmpe_reg_bits {
8735 u8 reserved_at_0[0x8];
8737 u8 reserved_at_10[0xc];
8738 u8 module_status[0x4];
8740 u8 reserved_at_20[0x60];
8743 struct mlx5_ifc_pmpc_reg_bits {
8744 u8 module_state_updated[32][0x8];
8747 struct mlx5_ifc_pmlpn_reg_bits {
8748 u8 reserved_at_0[0x4];
8749 u8 mlpn_status[0x4];
8751 u8 reserved_at_10[0x10];
8754 u8 reserved_at_21[0x1f];
8757 struct mlx5_ifc_pmlp_reg_bits {
8759 u8 reserved_at_1[0x7];
8761 u8 reserved_at_10[0x8];
8764 u8 lane0_module_mapping[0x20];
8766 u8 lane1_module_mapping[0x20];
8768 u8 lane2_module_mapping[0x20];
8770 u8 lane3_module_mapping[0x20];
8772 u8 reserved_at_a0[0x160];
8775 struct mlx5_ifc_pmaos_reg_bits {
8776 u8 reserved_at_0[0x8];
8778 u8 reserved_at_10[0x4];
8779 u8 admin_status[0x4];
8780 u8 reserved_at_18[0x4];
8781 u8 oper_status[0x4];
8785 u8 reserved_at_22[0x1c];
8788 u8 reserved_at_40[0x40];
8791 struct mlx5_ifc_plpc_reg_bits {
8792 u8 reserved_at_0[0x4];
8794 u8 reserved_at_10[0x4];
8796 u8 reserved_at_18[0x8];
8798 u8 reserved_at_20[0x10];
8799 u8 lane_speed[0x10];
8801 u8 reserved_at_40[0x17];
8803 u8 fec_mode_policy[0x8];
8805 u8 retransmission_capability[0x8];
8806 u8 fec_mode_capability[0x18];
8808 u8 retransmission_support_admin[0x8];
8809 u8 fec_mode_support_admin[0x18];
8811 u8 retransmission_request_admin[0x8];
8812 u8 fec_mode_request_admin[0x18];
8814 u8 reserved_at_c0[0x80];
8817 struct mlx5_ifc_plib_reg_bits {
8818 u8 reserved_at_0[0x8];
8820 u8 reserved_at_10[0x8];
8823 u8 reserved_at_20[0x60];
8826 struct mlx5_ifc_plbf_reg_bits {
8827 u8 reserved_at_0[0x8];
8829 u8 reserved_at_10[0xd];
8832 u8 reserved_at_20[0x20];
8835 struct mlx5_ifc_pipg_reg_bits {
8836 u8 reserved_at_0[0x8];
8838 u8 reserved_at_10[0x10];
8841 u8 reserved_at_21[0x19];
8843 u8 reserved_at_3e[0x2];
8846 struct mlx5_ifc_pifr_reg_bits {
8847 u8 reserved_at_0[0x8];
8849 u8 reserved_at_10[0x10];
8851 u8 reserved_at_20[0xe0];
8853 u8 port_filter[8][0x20];
8855 u8 port_filter_update_en[8][0x20];
8858 struct mlx5_ifc_pfcc_reg_bits {
8859 u8 reserved_at_0[0x8];
8861 u8 reserved_at_10[0xb];
8862 u8 ppan_mask_n[0x1];
8863 u8 minor_stall_mask[0x1];
8864 u8 critical_stall_mask[0x1];
8865 u8 reserved_at_1e[0x2];
8868 u8 reserved_at_24[0x4];
8869 u8 prio_mask_tx[0x8];
8870 u8 reserved_at_30[0x8];
8871 u8 prio_mask_rx[0x8];
8875 u8 pptx_mask_n[0x1];
8876 u8 reserved_at_43[0x5];
8878 u8 reserved_at_50[0x10];
8882 u8 pprx_mask_n[0x1];
8883 u8 reserved_at_63[0x5];
8885 u8 reserved_at_70[0x10];
8887 u8 device_stall_minor_watermark[0x10];
8888 u8 device_stall_critical_watermark[0x10];
8890 u8 reserved_at_a0[0x60];
8893 struct mlx5_ifc_pelc_reg_bits {
8895 u8 reserved_at_4[0x4];
8897 u8 reserved_at_10[0x10];
8900 u8 op_capability[0x8];
8906 u8 capability[0x40];
8912 u8 reserved_at_140[0x80];
8915 struct mlx5_ifc_peir_reg_bits {
8916 u8 reserved_at_0[0x8];
8918 u8 reserved_at_10[0x10];
8920 u8 reserved_at_20[0xc];
8921 u8 error_count[0x4];
8922 u8 reserved_at_30[0x10];
8924 u8 reserved_at_40[0xc];
8926 u8 reserved_at_50[0x8];
8930 struct mlx5_ifc_mpegc_reg_bits {
8931 u8 reserved_at_0[0x30];
8932 u8 field_select[0x10];
8934 u8 tx_overflow_sense[0x1];
8937 u8 reserved_at_43[0x1b];
8938 u8 tx_lossy_overflow_oper[0x2];
8940 u8 reserved_at_60[0x100];
8943 struct mlx5_ifc_pcam_enhanced_features_bits {
8944 u8 reserved_at_0[0x68];
8945 u8 fec_50G_per_lane_in_pplm[0x1];
8946 u8 reserved_at_69[0x4];
8947 u8 rx_icrc_encapsulated_counter[0x1];
8948 u8 reserved_at_6e[0x4];
8949 u8 ptys_extended_ethernet[0x1];
8950 u8 reserved_at_73[0x3];
8952 u8 reserved_at_77[0x3];
8953 u8 per_lane_error_counters[0x1];
8954 u8 rx_buffer_fullness_counters[0x1];
8955 u8 ptys_connector_type[0x1];
8956 u8 reserved_at_7d[0x1];
8957 u8 ppcnt_discard_group[0x1];
8958 u8 ppcnt_statistical_group[0x1];
8961 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8962 u8 port_access_reg_cap_mask_127_to_96[0x20];
8963 u8 port_access_reg_cap_mask_95_to_64[0x20];
8965 u8 port_access_reg_cap_mask_63_to_36[0x1c];
8967 u8 port_access_reg_cap_mask_34_to_32[0x3];
8969 u8 port_access_reg_cap_mask_31_to_13[0x13];
8972 u8 port_access_reg_cap_mask_10_to_09[0x2];
8974 u8 port_access_reg_cap_mask_07_to_00[0x8];
8977 struct mlx5_ifc_pcam_reg_bits {
8978 u8 reserved_at_0[0x8];
8979 u8 feature_group[0x8];
8980 u8 reserved_at_10[0x8];
8981 u8 access_reg_group[0x8];
8983 u8 reserved_at_20[0x20];
8986 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8987 u8 reserved_at_0[0x80];
8988 } port_access_reg_cap_mask;
8990 u8 reserved_at_c0[0x80];
8993 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8994 u8 reserved_at_0[0x80];
8997 u8 reserved_at_1c0[0xc0];
9000 struct mlx5_ifc_mcam_enhanced_features_bits {
9001 u8 reserved_at_0[0x6e];
9002 u8 pci_status_and_power[0x1];
9003 u8 reserved_at_6f[0x5];
9004 u8 mark_tx_action_cnp[0x1];
9005 u8 mark_tx_action_cqe[0x1];
9006 u8 dynamic_tx_overflow[0x1];
9007 u8 reserved_at_77[0x4];
9008 u8 pcie_outbound_stalled[0x1];
9009 u8 tx_overflow_buffer_pkt[0x1];
9010 u8 mtpps_enh_out_per_adj[0x1];
9012 u8 pcie_performance_group[0x1];
9015 struct mlx5_ifc_mcam_access_reg_bits {
9016 u8 reserved_at_0[0x1c];
9022 u8 regs_95_to_87[0x9];
9024 u8 regs_85_to_68[0x12];
9025 u8 tracer_registers[0x4];
9027 u8 regs_63_to_32[0x20];
9028 u8 regs_31_to_0[0x20];
9031 struct mlx5_ifc_mcam_access_reg_bits1 {
9032 u8 regs_127_to_96[0x20];
9034 u8 regs_95_to_64[0x20];
9036 u8 regs_63_to_32[0x20];
9038 u8 regs_31_to_0[0x20];
9041 struct mlx5_ifc_mcam_access_reg_bits2 {
9042 u8 regs_127_to_99[0x1d];
9044 u8 regs_97_to_96[0x2];
9046 u8 regs_95_to_64[0x20];
9048 u8 regs_63_to_32[0x20];
9050 u8 regs_31_to_0[0x20];
9053 struct mlx5_ifc_mcam_reg_bits {
9054 u8 reserved_at_0[0x8];
9055 u8 feature_group[0x8];
9056 u8 reserved_at_10[0x8];
9057 u8 access_reg_group[0x8];
9059 u8 reserved_at_20[0x20];
9062 struct mlx5_ifc_mcam_access_reg_bits access_regs;
9063 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1;
9064 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2;
9065 u8 reserved_at_0[0x80];
9066 } mng_access_reg_cap_mask;
9068 u8 reserved_at_c0[0x80];
9071 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
9072 u8 reserved_at_0[0x80];
9073 } mng_feature_cap_mask;
9075 u8 reserved_at_1c0[0x80];
9078 struct mlx5_ifc_qcam_access_reg_cap_mask {
9079 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9081 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9085 u8 qcam_access_reg_cap_mask_0[0x1];
9088 struct mlx5_ifc_qcam_qos_feature_cap_mask {
9089 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9090 u8 qpts_trust_both[0x1];
9093 struct mlx5_ifc_qcam_reg_bits {
9094 u8 reserved_at_0[0x8];
9095 u8 feature_group[0x8];
9096 u8 reserved_at_10[0x8];
9097 u8 access_reg_group[0x8];
9098 u8 reserved_at_20[0x20];
9101 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
9102 u8 reserved_at_0[0x80];
9103 } qos_access_reg_cap_mask;
9105 u8 reserved_at_c0[0x80];
9108 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
9109 u8 reserved_at_0[0x80];
9110 } qos_feature_cap_mask;
9112 u8 reserved_at_1c0[0x80];
9115 struct mlx5_ifc_core_dump_reg_bits {
9116 u8 reserved_at_0[0x18];
9117 u8 core_dump_type[0x8];
9119 u8 reserved_at_20[0x30];
9122 u8 reserved_at_60[0x8];
9124 u8 reserved_at_80[0x180];
9127 struct mlx5_ifc_pcap_reg_bits {
9128 u8 reserved_at_0[0x8];
9130 u8 reserved_at_10[0x10];
9132 u8 port_capability_mask[4][0x20];
9135 struct mlx5_ifc_paos_reg_bits {
9138 u8 reserved_at_10[0x4];
9139 u8 admin_status[0x4];
9140 u8 reserved_at_18[0x4];
9141 u8 oper_status[0x4];
9145 u8 reserved_at_22[0x1c];
9148 u8 reserved_at_40[0x40];
9151 struct mlx5_ifc_pamp_reg_bits {
9152 u8 reserved_at_0[0x8];
9153 u8 opamp_group[0x8];
9154 u8 reserved_at_10[0xc];
9155 u8 opamp_group_type[0x4];
9157 u8 start_index[0x10];
9158 u8 reserved_at_30[0x4];
9159 u8 num_of_indices[0xc];
9161 u8 index_data[18][0x10];
9164 struct mlx5_ifc_pcmr_reg_bits {
9165 u8 reserved_at_0[0x8];
9167 u8 reserved_at_10[0x10];
9168 u8 entropy_force_cap[0x1];
9169 u8 entropy_calc_cap[0x1];
9170 u8 entropy_gre_calc_cap[0x1];
9171 u8 reserved_at_23[0x1b];
9173 u8 reserved_at_3f[0x1];
9174 u8 entropy_force[0x1];
9175 u8 entropy_calc[0x1];
9176 u8 entropy_gre_calc[0x1];
9177 u8 reserved_at_43[0x1b];
9179 u8 reserved_at_5f[0x1];
9182 struct mlx5_ifc_lane_2_module_mapping_bits {
9183 u8 reserved_at_0[0x6];
9185 u8 reserved_at_8[0x6];
9187 u8 reserved_at_10[0x8];
9191 struct mlx5_ifc_bufferx_reg_bits {
9192 u8 reserved_at_0[0x6];
9195 u8 reserved_at_8[0xc];
9198 u8 xoff_threshold[0x10];
9199 u8 xon_threshold[0x10];
9202 struct mlx5_ifc_set_node_in_bits {
9203 u8 node_description[64][0x8];
9206 struct mlx5_ifc_register_power_settings_bits {
9207 u8 reserved_at_0[0x18];
9208 u8 power_settings_level[0x8];
9210 u8 reserved_at_20[0x60];
9213 struct mlx5_ifc_register_host_endianness_bits {
9215 u8 reserved_at_1[0x1f];
9217 u8 reserved_at_20[0x60];
9220 struct mlx5_ifc_umr_pointer_desc_argument_bits {
9221 u8 reserved_at_0[0x20];
9225 u8 addressh_63_32[0x20];
9227 u8 addressl_31_0[0x20];
9230 struct mlx5_ifc_ud_adrs_vector_bits {
9234 u8 reserved_at_41[0x7];
9235 u8 destination_qp_dct[0x18];
9237 u8 static_rate[0x4];
9238 u8 sl_eth_prio[0x4];
9241 u8 rlid_udp_sport[0x10];
9243 u8 reserved_at_80[0x20];
9245 u8 rmac_47_16[0x20];
9251 u8 reserved_at_e0[0x1];
9253 u8 reserved_at_e2[0x2];
9254 u8 src_addr_index[0x8];
9255 u8 flow_label[0x14];
9257 u8 rgid_rip[16][0x8];
9260 struct mlx5_ifc_pages_req_event_bits {
9261 u8 reserved_at_0[0x10];
9262 u8 function_id[0x10];
9266 u8 reserved_at_40[0xa0];
9269 struct mlx5_ifc_eqe_bits {
9270 u8 reserved_at_0[0x8];
9272 u8 reserved_at_10[0x8];
9273 u8 event_sub_type[0x8];
9275 u8 reserved_at_20[0xe0];
9277 union mlx5_ifc_event_auto_bits event_data;
9279 u8 reserved_at_1e0[0x10];
9281 u8 reserved_at_1f8[0x7];
9286 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
9289 struct mlx5_ifc_cmd_queue_entry_bits {
9291 u8 reserved_at_8[0x18];
9293 u8 input_length[0x20];
9295 u8 input_mailbox_pointer_63_32[0x20];
9297 u8 input_mailbox_pointer_31_9[0x17];
9298 u8 reserved_at_77[0x9];
9300 u8 command_input_inline_data[16][0x8];
9302 u8 command_output_inline_data[16][0x8];
9304 u8 output_mailbox_pointer_63_32[0x20];
9306 u8 output_mailbox_pointer_31_9[0x17];
9307 u8 reserved_at_1b7[0x9];
9309 u8 output_length[0x20];
9313 u8 reserved_at_1f0[0x8];
9318 struct mlx5_ifc_cmd_out_bits {
9320 u8 reserved_at_8[0x18];
9324 u8 command_output[0x20];
9327 struct mlx5_ifc_cmd_in_bits {
9329 u8 reserved_at_10[0x10];
9331 u8 reserved_at_20[0x10];
9334 u8 command[0][0x20];
9337 struct mlx5_ifc_cmd_if_box_bits {
9338 u8 mailbox_data[512][0x8];
9340 u8 reserved_at_1000[0x180];
9342 u8 next_pointer_63_32[0x20];
9344 u8 next_pointer_31_10[0x16];
9345 u8 reserved_at_11b6[0xa];
9347 u8 block_number[0x20];
9349 u8 reserved_at_11e0[0x8];
9351 u8 ctrl_signature[0x8];
9355 struct mlx5_ifc_mtt_bits {
9356 u8 ptag_63_32[0x20];
9359 u8 reserved_at_38[0x6];
9364 struct mlx5_ifc_query_wol_rol_out_bits {
9366 u8 reserved_at_8[0x18];
9370 u8 reserved_at_40[0x10];
9374 u8 reserved_at_60[0x20];
9377 struct mlx5_ifc_query_wol_rol_in_bits {
9379 u8 reserved_at_10[0x10];
9381 u8 reserved_at_20[0x10];
9384 u8 reserved_at_40[0x40];
9387 struct mlx5_ifc_set_wol_rol_out_bits {
9389 u8 reserved_at_8[0x18];
9393 u8 reserved_at_40[0x40];
9396 struct mlx5_ifc_set_wol_rol_in_bits {
9398 u8 reserved_at_10[0x10];
9400 u8 reserved_at_20[0x10];
9403 u8 rol_mode_valid[0x1];
9404 u8 wol_mode_valid[0x1];
9405 u8 reserved_at_42[0xe];
9409 u8 reserved_at_60[0x20];
9413 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
9414 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
9415 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
9419 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
9420 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
9421 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
9425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
9426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
9427 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
9428 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
9429 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
9430 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
9431 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
9432 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
9433 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
9434 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
9435 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
9438 struct mlx5_ifc_initial_seg_bits {
9439 u8 fw_rev_minor[0x10];
9440 u8 fw_rev_major[0x10];
9442 u8 cmd_interface_rev[0x10];
9443 u8 fw_rev_subminor[0x10];
9445 u8 reserved_at_40[0x40];
9447 u8 cmdq_phy_addr_63_32[0x20];
9449 u8 cmdq_phy_addr_31_12[0x14];
9450 u8 reserved_at_b4[0x2];
9451 u8 nic_interface[0x2];
9452 u8 log_cmdq_size[0x4];
9453 u8 log_cmdq_stride[0x4];
9455 u8 command_doorbell_vector[0x20];
9457 u8 reserved_at_e0[0xf00];
9459 u8 initializing[0x1];
9460 u8 reserved_at_fe1[0x4];
9461 u8 nic_interface_supported[0x3];
9462 u8 embedded_cpu[0x1];
9463 u8 reserved_at_fe9[0x17];
9465 struct mlx5_ifc_health_buffer_bits health_buffer;
9467 u8 no_dram_nic_offset[0x20];
9469 u8 reserved_at_1220[0x6e40];
9471 u8 reserved_at_8060[0x1f];
9474 u8 health_syndrome[0x8];
9475 u8 health_counter[0x18];
9477 u8 reserved_at_80a0[0x17fc0];
9480 struct mlx5_ifc_mtpps_reg_bits {
9481 u8 reserved_at_0[0xc];
9482 u8 cap_number_of_pps_pins[0x4];
9483 u8 reserved_at_10[0x4];
9484 u8 cap_max_num_of_pps_in_pins[0x4];
9485 u8 reserved_at_18[0x4];
9486 u8 cap_max_num_of_pps_out_pins[0x4];
9488 u8 reserved_at_20[0x24];
9489 u8 cap_pin_3_mode[0x4];
9490 u8 reserved_at_48[0x4];
9491 u8 cap_pin_2_mode[0x4];
9492 u8 reserved_at_50[0x4];
9493 u8 cap_pin_1_mode[0x4];
9494 u8 reserved_at_58[0x4];
9495 u8 cap_pin_0_mode[0x4];
9497 u8 reserved_at_60[0x4];
9498 u8 cap_pin_7_mode[0x4];
9499 u8 reserved_at_68[0x4];
9500 u8 cap_pin_6_mode[0x4];
9501 u8 reserved_at_70[0x4];
9502 u8 cap_pin_5_mode[0x4];
9503 u8 reserved_at_78[0x4];
9504 u8 cap_pin_4_mode[0x4];
9506 u8 field_select[0x20];
9507 u8 reserved_at_a0[0x60];
9510 u8 reserved_at_101[0xb];
9512 u8 reserved_at_110[0x4];
9516 u8 reserved_at_120[0x20];
9518 u8 time_stamp[0x40];
9520 u8 out_pulse_duration[0x10];
9521 u8 out_periodic_adjustment[0x10];
9522 u8 enhanced_out_periodic_adjustment[0x20];
9524 u8 reserved_at_1c0[0x20];
9527 struct mlx5_ifc_mtppse_reg_bits {
9528 u8 reserved_at_0[0x18];
9531 u8 reserved_at_21[0x1b];
9532 u8 event_generation_mode[0x4];
9533 u8 reserved_at_40[0x40];
9536 struct mlx5_ifc_mcqs_reg_bits {
9537 u8 last_index_flag[0x1];
9538 u8 reserved_at_1[0x7];
9540 u8 component_index[0x10];
9542 u8 reserved_at_20[0x10];
9543 u8 identifier[0x10];
9545 u8 reserved_at_40[0x17];
9546 u8 component_status[0x5];
9547 u8 component_update_state[0x4];
9549 u8 last_update_state_changer_type[0x4];
9550 u8 last_update_state_changer_host_id[0x4];
9551 u8 reserved_at_68[0x18];
9554 struct mlx5_ifc_mcqi_cap_bits {
9555 u8 supported_info_bitmask[0x20];
9557 u8 component_size[0x20];
9559 u8 max_component_size[0x20];
9561 u8 log_mcda_word_size[0x4];
9562 u8 reserved_at_64[0xc];
9563 u8 mcda_max_write_size[0x10];
9566 u8 reserved_at_81[0x1];
9567 u8 match_chip_id[0x1];
9569 u8 check_user_timestamp[0x1];
9570 u8 match_base_guid_mac[0x1];
9571 u8 reserved_at_86[0x1a];
9574 struct mlx5_ifc_mcqi_version_bits {
9575 u8 reserved_at_0[0x2];
9576 u8 build_time_valid[0x1];
9577 u8 user_defined_time_valid[0x1];
9578 u8 reserved_at_4[0x14];
9579 u8 version_string_length[0x8];
9583 u8 build_time[0x40];
9585 u8 user_defined_time[0x40];
9587 u8 build_tool_version[0x20];
9589 u8 reserved_at_e0[0x20];
9591 u8 version_string[92][0x8];
9594 struct mlx5_ifc_mcqi_activation_method_bits {
9595 u8 pending_server_ac_power_cycle[0x1];
9596 u8 pending_server_dc_power_cycle[0x1];
9597 u8 pending_server_reboot[0x1];
9598 u8 pending_fw_reset[0x1];
9599 u8 auto_activate[0x1];
9600 u8 all_hosts_sync[0x1];
9601 u8 device_hw_reset[0x1];
9602 u8 reserved_at_7[0x19];
9605 union mlx5_ifc_mcqi_reg_data_bits {
9606 struct mlx5_ifc_mcqi_cap_bits mcqi_caps;
9607 struct mlx5_ifc_mcqi_version_bits mcqi_version;
9608 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9611 struct mlx5_ifc_mcqi_reg_bits {
9612 u8 read_pending_component[0x1];
9613 u8 reserved_at_1[0xf];
9614 u8 component_index[0x10];
9616 u8 reserved_at_20[0x20];
9618 u8 reserved_at_40[0x1b];
9625 u8 reserved_at_a0[0x10];
9628 union mlx5_ifc_mcqi_reg_data_bits data[0];
9631 struct mlx5_ifc_mcc_reg_bits {
9632 u8 reserved_at_0[0x4];
9633 u8 time_elapsed_since_last_cmd[0xc];
9634 u8 reserved_at_10[0x8];
9635 u8 instruction[0x8];
9637 u8 reserved_at_20[0x10];
9638 u8 component_index[0x10];
9640 u8 reserved_at_40[0x8];
9641 u8 update_handle[0x18];
9643 u8 handle_owner_type[0x4];
9644 u8 handle_owner_host_id[0x4];
9645 u8 reserved_at_68[0x1];
9646 u8 control_progress[0x7];
9648 u8 reserved_at_78[0x4];
9649 u8 control_state[0x4];
9651 u8 component_size[0x20];
9653 u8 reserved_at_a0[0x60];
9656 struct mlx5_ifc_mcda_reg_bits {
9657 u8 reserved_at_0[0x8];
9658 u8 update_handle[0x18];
9662 u8 reserved_at_40[0x10];
9665 u8 reserved_at_60[0x20];
9670 struct mlx5_ifc_mirc_reg_bits {
9671 u8 reserved_at_0[0x18];
9672 u8 status_code[0x8];
9674 u8 reserved_at_20[0x20];
9677 union mlx5_ifc_ports_control_registers_document_bits {
9678 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9679 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9680 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9681 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9682 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9683 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9684 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9685 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout;
9686 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout;
9687 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9688 struct mlx5_ifc_pamp_reg_bits pamp_reg;
9689 struct mlx5_ifc_paos_reg_bits paos_reg;
9690 struct mlx5_ifc_pcap_reg_bits pcap_reg;
9691 struct mlx5_ifc_peir_reg_bits peir_reg;
9692 struct mlx5_ifc_pelc_reg_bits pelc_reg;
9693 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9694 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9695 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9696 struct mlx5_ifc_pifr_reg_bits pifr_reg;
9697 struct mlx5_ifc_pipg_reg_bits pipg_reg;
9698 struct mlx5_ifc_plbf_reg_bits plbf_reg;
9699 struct mlx5_ifc_plib_reg_bits plib_reg;
9700 struct mlx5_ifc_plpc_reg_bits plpc_reg;
9701 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9702 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9703 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9704 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9705 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9706 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9707 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9708 struct mlx5_ifc_ppad_reg_bits ppad_reg;
9709 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9710 struct mlx5_ifc_mpein_reg_bits mpein_reg;
9711 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9712 struct mlx5_ifc_pplm_reg_bits pplm_reg;
9713 struct mlx5_ifc_pplr_reg_bits pplr_reg;
9714 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9715 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9716 struct mlx5_ifc_pspa_reg_bits pspa_reg;
9717 struct mlx5_ifc_ptas_reg_bits ptas_reg;
9718 struct mlx5_ifc_ptys_reg_bits ptys_reg;
9719 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9720 struct mlx5_ifc_pude_reg_bits pude_reg;
9721 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9722 struct mlx5_ifc_slrg_reg_bits slrg_reg;
9723 struct mlx5_ifc_sltp_reg_bits sltp_reg;
9724 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9725 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9726 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9727 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9728 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9729 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9730 struct mlx5_ifc_mcc_reg_bits mcc_reg;
9731 struct mlx5_ifc_mcda_reg_bits mcda_reg;
9732 struct mlx5_ifc_mirc_reg_bits mirc_reg;
9733 u8 reserved_at_0[0x60e0];
9736 union mlx5_ifc_debug_enhancements_document_bits {
9737 struct mlx5_ifc_health_buffer_bits health_buffer;
9738 u8 reserved_at_0[0x200];
9741 union mlx5_ifc_uplink_pci_interface_document_bits {
9742 struct mlx5_ifc_initial_seg_bits initial_seg;
9743 u8 reserved_at_0[0x20060];
9746 struct mlx5_ifc_set_flow_table_root_out_bits {
9748 u8 reserved_at_8[0x18];
9752 u8 reserved_at_40[0x40];
9755 struct mlx5_ifc_set_flow_table_root_in_bits {
9757 u8 reserved_at_10[0x10];
9759 u8 reserved_at_20[0x10];
9762 u8 other_vport[0x1];
9763 u8 reserved_at_41[0xf];
9764 u8 vport_number[0x10];
9766 u8 reserved_at_60[0x20];
9769 u8 reserved_at_88[0x18];
9771 u8 reserved_at_a0[0x8];
9774 u8 reserved_at_c0[0x8];
9775 u8 underlay_qpn[0x18];
9776 u8 reserved_at_e0[0x120];
9780 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
9781 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9784 struct mlx5_ifc_modify_flow_table_out_bits {
9786 u8 reserved_at_8[0x18];
9790 u8 reserved_at_40[0x40];
9793 struct mlx5_ifc_modify_flow_table_in_bits {
9795 u8 reserved_at_10[0x10];
9797 u8 reserved_at_20[0x10];
9800 u8 other_vport[0x1];
9801 u8 reserved_at_41[0xf];
9802 u8 vport_number[0x10];
9804 u8 reserved_at_60[0x10];
9805 u8 modify_field_select[0x10];
9808 u8 reserved_at_88[0x18];
9810 u8 reserved_at_a0[0x8];
9813 struct mlx5_ifc_flow_table_context_bits flow_table_context;
9816 struct mlx5_ifc_ets_tcn_config_reg_bits {
9820 u8 reserved_at_3[0x9];
9822 u8 reserved_at_10[0x9];
9823 u8 bw_allocation[0x7];
9825 u8 reserved_at_20[0xc];
9826 u8 max_bw_units[0x4];
9827 u8 reserved_at_30[0x8];
9828 u8 max_bw_value[0x8];
9831 struct mlx5_ifc_ets_global_config_reg_bits {
9832 u8 reserved_at_0[0x2];
9834 u8 reserved_at_3[0x1d];
9836 u8 reserved_at_20[0xc];
9837 u8 max_bw_units[0x4];
9838 u8 reserved_at_30[0x8];
9839 u8 max_bw_value[0x8];
9842 struct mlx5_ifc_qetc_reg_bits {
9843 u8 reserved_at_0[0x8];
9844 u8 port_number[0x8];
9845 u8 reserved_at_10[0x30];
9847 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
9848 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9851 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9853 u8 reserved_at_01[0x0b];
9857 struct mlx5_ifc_qpdpm_reg_bits {
9858 u8 reserved_at_0[0x8];
9860 u8 reserved_at_10[0x10];
9861 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64];
9864 struct mlx5_ifc_qpts_reg_bits {
9865 u8 reserved_at_0[0x8];
9867 u8 reserved_at_10[0x2d];
9868 u8 trust_state[0x3];
9871 struct mlx5_ifc_pptb_reg_bits {
9872 u8 reserved_at_0[0x2];
9874 u8 reserved_at_4[0x4];
9876 u8 reserved_at_10[0x6];
9881 u8 prio_x_buff[0x20];
9884 u8 reserved_at_48[0x10];
9886 u8 untagged_buff[0x4];
9889 struct mlx5_ifc_pbmc_reg_bits {
9890 u8 reserved_at_0[0x8];
9892 u8 reserved_at_10[0x10];
9894 u8 xoff_timer_value[0x10];
9895 u8 xoff_refresh[0x10];
9897 u8 reserved_at_40[0x9];
9898 u8 fullness_threshold[0x7];
9899 u8 port_buffer_size[0x10];
9901 struct mlx5_ifc_bufferx_reg_bits buffer[10];
9903 u8 reserved_at_2e0[0x40];
9906 struct mlx5_ifc_qtct_reg_bits {
9907 u8 reserved_at_0[0x8];
9908 u8 port_number[0x8];
9909 u8 reserved_at_10[0xd];
9912 u8 reserved_at_20[0x1d];
9916 struct mlx5_ifc_mcia_reg_bits {
9918 u8 reserved_at_1[0x7];
9920 u8 reserved_at_10[0x8];
9923 u8 i2c_device_address[0x8];
9924 u8 page_number[0x8];
9925 u8 device_address[0x10];
9927 u8 reserved_at_40[0x10];
9930 u8 reserved_at_60[0x20];
9946 struct mlx5_ifc_dcbx_param_bits {
9947 u8 dcbx_cee_cap[0x1];
9948 u8 dcbx_ieee_cap[0x1];
9949 u8 dcbx_standby_cap[0x1];
9950 u8 reserved_at_3[0x5];
9951 u8 port_number[0x8];
9952 u8 reserved_at_10[0xa];
9953 u8 max_application_table_size[6];
9954 u8 reserved_at_20[0x15];
9955 u8 version_oper[0x3];
9956 u8 reserved_at_38[5];
9957 u8 version_admin[0x3];
9958 u8 willing_admin[0x1];
9959 u8 reserved_at_41[0x3];
9960 u8 pfc_cap_oper[0x4];
9961 u8 reserved_at_48[0x4];
9962 u8 pfc_cap_admin[0x4];
9963 u8 reserved_at_50[0x4];
9964 u8 num_of_tc_oper[0x4];
9965 u8 reserved_at_58[0x4];
9966 u8 num_of_tc_admin[0x4];
9967 u8 remote_willing[0x1];
9968 u8 reserved_at_61[3];
9969 u8 remote_pfc_cap[4];
9970 u8 reserved_at_68[0x14];
9971 u8 remote_num_of_tc[0x4];
9972 u8 reserved_at_80[0x18];
9974 u8 reserved_at_a0[0x160];
9977 struct mlx5_ifc_lagc_bits {
9978 u8 reserved_at_0[0x1d];
9981 u8 reserved_at_20[0x14];
9982 u8 tx_remap_affinity_2[0x4];
9983 u8 reserved_at_38[0x4];
9984 u8 tx_remap_affinity_1[0x4];
9987 struct mlx5_ifc_create_lag_out_bits {
9989 u8 reserved_at_8[0x18];
9993 u8 reserved_at_40[0x40];
9996 struct mlx5_ifc_create_lag_in_bits {
9998 u8 reserved_at_10[0x10];
10000 u8 reserved_at_20[0x10];
10003 struct mlx5_ifc_lagc_bits ctx;
10006 struct mlx5_ifc_modify_lag_out_bits {
10008 u8 reserved_at_8[0x18];
10012 u8 reserved_at_40[0x40];
10015 struct mlx5_ifc_modify_lag_in_bits {
10017 u8 reserved_at_10[0x10];
10019 u8 reserved_at_20[0x10];
10022 u8 reserved_at_40[0x20];
10023 u8 field_select[0x20];
10025 struct mlx5_ifc_lagc_bits ctx;
10028 struct mlx5_ifc_query_lag_out_bits {
10030 u8 reserved_at_8[0x18];
10034 struct mlx5_ifc_lagc_bits ctx;
10037 struct mlx5_ifc_query_lag_in_bits {
10039 u8 reserved_at_10[0x10];
10041 u8 reserved_at_20[0x10];
10044 u8 reserved_at_40[0x40];
10047 struct mlx5_ifc_destroy_lag_out_bits {
10049 u8 reserved_at_8[0x18];
10053 u8 reserved_at_40[0x40];
10056 struct mlx5_ifc_destroy_lag_in_bits {
10058 u8 reserved_at_10[0x10];
10060 u8 reserved_at_20[0x10];
10063 u8 reserved_at_40[0x40];
10066 struct mlx5_ifc_create_vport_lag_out_bits {
10068 u8 reserved_at_8[0x18];
10072 u8 reserved_at_40[0x40];
10075 struct mlx5_ifc_create_vport_lag_in_bits {
10077 u8 reserved_at_10[0x10];
10079 u8 reserved_at_20[0x10];
10082 u8 reserved_at_40[0x40];
10085 struct mlx5_ifc_destroy_vport_lag_out_bits {
10087 u8 reserved_at_8[0x18];
10091 u8 reserved_at_40[0x40];
10094 struct mlx5_ifc_destroy_vport_lag_in_bits {
10096 u8 reserved_at_10[0x10];
10098 u8 reserved_at_20[0x10];
10101 u8 reserved_at_40[0x40];
10104 struct mlx5_ifc_alloc_memic_in_bits {
10106 u8 reserved_at_10[0x10];
10108 u8 reserved_at_20[0x10];
10111 u8 reserved_at_30[0x20];
10113 u8 reserved_at_40[0x18];
10114 u8 log_memic_addr_alignment[0x8];
10116 u8 range_start_addr[0x40];
10118 u8 range_size[0x20];
10120 u8 memic_size[0x20];
10123 struct mlx5_ifc_alloc_memic_out_bits {
10125 u8 reserved_at_8[0x18];
10129 u8 memic_start_addr[0x40];
10132 struct mlx5_ifc_dealloc_memic_in_bits {
10134 u8 reserved_at_10[0x10];
10136 u8 reserved_at_20[0x10];
10139 u8 reserved_at_40[0x40];
10141 u8 memic_start_addr[0x40];
10143 u8 memic_size[0x20];
10145 u8 reserved_at_e0[0x20];
10148 struct mlx5_ifc_dealloc_memic_out_bits {
10150 u8 reserved_at_8[0x18];
10154 u8 reserved_at_40[0x40];
10157 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
10161 u8 vhca_tunnel_id[0x10];
10166 u8 reserved_at_60[0x20];
10169 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
10171 u8 reserved_at_8[0x18];
10177 u8 reserved_at_60[0x20];
10180 struct mlx5_ifc_umem_bits {
10181 u8 reserved_at_0[0x80];
10183 u8 reserved_at_80[0x1b];
10184 u8 log_page_size[0x5];
10186 u8 page_offset[0x20];
10188 u8 num_of_mtt[0x40];
10190 struct mlx5_ifc_mtt_bits mtt[0];
10193 struct mlx5_ifc_uctx_bits {
10196 u8 reserved_at_20[0x160];
10199 struct mlx5_ifc_sw_icm_bits {
10200 u8 modify_field_select[0x40];
10202 u8 reserved_at_40[0x18];
10203 u8 log_sw_icm_size[0x8];
10205 u8 reserved_at_60[0x20];
10207 u8 sw_icm_start_addr[0x40];
10209 u8 reserved_at_c0[0x140];
10212 struct mlx5_ifc_geneve_tlv_option_bits {
10213 u8 modify_field_select[0x40];
10215 u8 reserved_at_40[0x18];
10216 u8 geneve_option_fte_index[0x8];
10218 u8 option_class[0x10];
10219 u8 option_type[0x8];
10220 u8 reserved_at_78[0x3];
10221 u8 option_data_length[0x5];
10223 u8 reserved_at_80[0x180];
10226 struct mlx5_ifc_create_umem_in_bits {
10230 u8 reserved_at_20[0x10];
10233 u8 reserved_at_40[0x40];
10235 struct mlx5_ifc_umem_bits umem;
10238 struct mlx5_ifc_create_uctx_in_bits {
10240 u8 reserved_at_10[0x10];
10242 u8 reserved_at_20[0x10];
10245 u8 reserved_at_40[0x40];
10247 struct mlx5_ifc_uctx_bits uctx;
10250 struct mlx5_ifc_destroy_uctx_in_bits {
10252 u8 reserved_at_10[0x10];
10254 u8 reserved_at_20[0x10];
10257 u8 reserved_at_40[0x10];
10260 u8 reserved_at_60[0x20];
10263 struct mlx5_ifc_create_sw_icm_in_bits {
10264 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10265 struct mlx5_ifc_sw_icm_bits sw_icm;
10268 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
10269 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
10270 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
10273 struct mlx5_ifc_mtrc_string_db_param_bits {
10274 u8 string_db_base_address[0x20];
10276 u8 reserved_at_20[0x8];
10277 u8 string_db_size[0x18];
10280 struct mlx5_ifc_mtrc_cap_bits {
10281 u8 trace_owner[0x1];
10282 u8 trace_to_memory[0x1];
10283 u8 reserved_at_2[0x4];
10285 u8 reserved_at_8[0x14];
10286 u8 num_string_db[0x4];
10288 u8 first_string_trace[0x8];
10289 u8 num_string_trace[0x8];
10290 u8 reserved_at_30[0x28];
10292 u8 log_max_trace_buffer_size[0x8];
10294 u8 reserved_at_60[0x20];
10296 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
10298 u8 reserved_at_280[0x180];
10301 struct mlx5_ifc_mtrc_conf_bits {
10302 u8 reserved_at_0[0x1c];
10303 u8 trace_mode[0x4];
10304 u8 reserved_at_20[0x18];
10305 u8 log_trace_buffer_size[0x8];
10306 u8 trace_mkey[0x20];
10307 u8 reserved_at_60[0x3a0];
10310 struct mlx5_ifc_mtrc_stdb_bits {
10311 u8 string_db_index[0x4];
10312 u8 reserved_at_4[0x4];
10313 u8 read_size[0x18];
10314 u8 start_offset[0x20];
10315 u8 string_db_data[0];
10318 struct mlx5_ifc_mtrc_ctrl_bits {
10319 u8 trace_status[0x2];
10320 u8 reserved_at_2[0x2];
10322 u8 reserved_at_5[0xb];
10323 u8 modify_field_select[0x10];
10324 u8 reserved_at_20[0x2b];
10325 u8 current_timestamp52_32[0x15];
10326 u8 current_timestamp31_0[0x20];
10327 u8 reserved_at_80[0x180];
10330 struct mlx5_ifc_host_params_context_bits {
10331 u8 host_number[0x8];
10332 u8 reserved_at_8[0x7];
10333 u8 host_pf_disabled[0x1];
10334 u8 host_num_of_vfs[0x10];
10336 u8 host_total_vfs[0x10];
10337 u8 host_pci_bus[0x10];
10339 u8 reserved_at_40[0x10];
10340 u8 host_pci_device[0x10];
10342 u8 reserved_at_60[0x10];
10343 u8 host_pci_function[0x10];
10345 u8 reserved_at_80[0x180];
10348 struct mlx5_ifc_query_esw_functions_in_bits {
10350 u8 reserved_at_10[0x10];
10352 u8 reserved_at_20[0x10];
10355 u8 reserved_at_40[0x40];
10358 struct mlx5_ifc_query_esw_functions_out_bits {
10360 u8 reserved_at_8[0x18];
10364 u8 reserved_at_40[0x40];
10366 struct mlx5_ifc_host_params_context_bits host_params_context;
10368 u8 reserved_at_280[0x180];
10369 u8 host_sf_enable[0][0x40];
10372 struct mlx5_ifc_sf_partition_bits {
10373 u8 reserved_at_0[0x10];
10374 u8 log_num_sf[0x8];
10375 u8 log_sf_bar_size[0x8];
10378 struct mlx5_ifc_query_sf_partitions_out_bits {
10380 u8 reserved_at_8[0x18];
10384 u8 reserved_at_40[0x18];
10385 u8 num_sf_partitions[0x8];
10387 u8 reserved_at_60[0x20];
10389 struct mlx5_ifc_sf_partition_bits sf_partition[0];
10392 struct mlx5_ifc_query_sf_partitions_in_bits {
10394 u8 reserved_at_10[0x10];
10396 u8 reserved_at_20[0x10];
10399 u8 reserved_at_40[0x40];
10402 struct mlx5_ifc_dealloc_sf_out_bits {
10404 u8 reserved_at_8[0x18];
10408 u8 reserved_at_40[0x40];
10411 struct mlx5_ifc_dealloc_sf_in_bits {
10413 u8 reserved_at_10[0x10];
10415 u8 reserved_at_20[0x10];
10418 u8 reserved_at_40[0x10];
10419 u8 function_id[0x10];
10421 u8 reserved_at_60[0x20];
10424 struct mlx5_ifc_alloc_sf_out_bits {
10426 u8 reserved_at_8[0x18];
10430 u8 reserved_at_40[0x40];
10433 struct mlx5_ifc_alloc_sf_in_bits {
10435 u8 reserved_at_10[0x10];
10437 u8 reserved_at_20[0x10];
10440 u8 reserved_at_40[0x10];
10441 u8 function_id[0x10];
10443 u8 reserved_at_60[0x20];
10446 struct mlx5_ifc_affiliated_event_header_bits {
10447 u8 reserved_at_0[0x10];
10454 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10458 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10461 struct mlx5_ifc_encryption_key_obj_bits {
10462 u8 modify_field_select[0x40];
10464 u8 reserved_at_40[0x14];
10466 u8 reserved_at_58[0x4];
10469 u8 reserved_at_60[0x8];
10472 u8 reserved_at_80[0x180];
10475 u8 reserved_at_300[0x500];
10478 struct mlx5_ifc_create_encryption_key_in_bits {
10479 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10480 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10484 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10485 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10489 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10492 struct mlx5_ifc_tls_static_params_bits {
10494 u8 tls_version[0x4];
10496 u8 reserved_at_8[0x14];
10497 u8 encryption_standard[0x4];
10499 u8 reserved_at_20[0x20];
10501 u8 initial_record_number[0x40];
10503 u8 resync_tcp_sn[0x20];
10507 u8 implicit_iv[0x40];
10509 u8 reserved_at_100[0x8];
10510 u8 dek_index[0x18];
10512 u8 reserved_at_120[0xe0];
10515 struct mlx5_ifc_tls_progress_params_bits {
10516 u8 reserved_at_0[0x8];
10519 u8 next_record_tcp_sn[0x20];
10521 u8 hw_resync_tcp_sn[0x20];
10523 u8 record_tracker_state[0x2];
10524 u8 auth_state[0x2];
10525 u8 reserved_at_64[0x4];
10526 u8 hw_offset_record_number[0x18];
10529 #endif /* MLX5_IFC_H */