include/linux/mlx5/mlx5_ifc.h

   1 /*
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31 */
  32 #ifndef MLX5_IFC_H
  33 #define MLX5_IFC_H
  34
  35 #include "mlx5_ifc_fpga.h"
  36
  37 enum {
  38         MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS                   = 0x0,
  39         MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED             = 0x1,
  40         MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED           = 0x2,
  41         MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED                  = 0x3,
  42         MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED                    = 0x13,
  43         MLX5_EVENT_TYPE_CODING_SRQ_LIMIT                           = 0x14,
  44         MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED          = 0x1c,
  45         MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION            = 0x1d,
  46         MLX5_EVENT_TYPE_CODING_CQ_ERROR                            = 0x4,
  47         MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR         = 0x5,
  48         MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED               = 0x7,
  49         MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT                    = 0xc,
  50         MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR      = 0x10,
  51         MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR     = 0x11,
  52         MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR        = 0x12,
  53         MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR                      = 0x8,
  54         MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE                   = 0x9,
  55         MLX5_EVENT_TYPE_CODING_GPIO_EVENT                          = 0x15,
  56         MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
  57         MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
  58         MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT                      = 0x1b,
  59         MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT         = 0x1f,
  60         MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION        = 0xa,
  61         MLX5_EVENT_TYPE_CODING_PAGE_REQUEST                        = 0xb,
  62         MLX5_EVENT_TYPE_CODING_FPGA_ERROR                          = 0x20,
  63         MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR                       = 0x21
  64 };
  65
  66 enum {
  67         MLX5_MODIFY_TIR_BITMASK_LRO                   = 0x0,
  68         MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE        = 0x1,
  69         MLX5_MODIFY_TIR_BITMASK_HASH                  = 0x2,
  70         MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN   = 0x3
  71 };
  72
  73 enum {
  74         MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE        = 0x0,
  75         MLX5_SET_HCA_CAP_OP_MOD_ODP                   = 0x2,
  76         MLX5_SET_HCA_CAP_OP_MOD_ATOMIC                = 0x3,
  77 };
  78
  79 enum {
  80         MLX5_SHARED_RESOURCE_UID = 0xffff,
  81 };
  82
  83 enum {
  84         MLX5_OBJ_TYPE_SW_ICM = 0x0008,
  85 };
  86
  87 enum {
  88         MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM),
  89         MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11),
  90 };
  91
  92 enum {
  93         MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
  94         MLX5_OBJ_TYPE_MKEY = 0xff01,
  95         MLX5_OBJ_TYPE_QP = 0xff02,
  96         MLX5_OBJ_TYPE_PSV = 0xff03,
  97         MLX5_OBJ_TYPE_RMP = 0xff04,
  98         MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
  99         MLX5_OBJ_TYPE_RQ = 0xff06,
 100         MLX5_OBJ_TYPE_SQ = 0xff07,
 101         MLX5_OBJ_TYPE_TIR = 0xff08,
 102         MLX5_OBJ_TYPE_TIS = 0xff09,
 103         MLX5_OBJ_TYPE_DCT = 0xff0a,
 104         MLX5_OBJ_TYPE_XRQ = 0xff0b,
 105         MLX5_OBJ_TYPE_RQT = 0xff0e,
 106         MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
 107         MLX5_OBJ_TYPE_CQ = 0xff10,
 108 };
 109
 110 enum {
 111         MLX5_CMD_OP_QUERY_HCA_CAP                 = 0x100,
 112         MLX5_CMD_OP_QUERY_ADAPTER                 = 0x101,
 113         MLX5_CMD_OP_INIT_HCA                      = 0x102,
 114         MLX5_CMD_OP_TEARDOWN_HCA                  = 0x103,
 115         MLX5_CMD_OP_ENABLE_HCA                    = 0x104,
 116         MLX5_CMD_OP_DISABLE_HCA                   = 0x105,
 117         MLX5_CMD_OP_QUERY_PAGES                   = 0x107,
 118         MLX5_CMD_OP_MANAGE_PAGES                  = 0x108,
 119         MLX5_CMD_OP_SET_HCA_CAP                   = 0x109,
 120         MLX5_CMD_OP_QUERY_ISSI                    = 0x10a,
 121         MLX5_CMD_OP_SET_ISSI                      = 0x10b,
 122         MLX5_CMD_OP_SET_DRIVER_VERSION            = 0x10d,
 123         MLX5_CMD_OP_QUERY_SF_PARTITION            = 0x111,
 124         MLX5_CMD_OP_ALLOC_SF                      = 0x113,
 125         MLX5_CMD_OP_DEALLOC_SF                    = 0x114,
 126         MLX5_CMD_OP_CREATE_MKEY                   = 0x200,
 127         MLX5_CMD_OP_QUERY_MKEY                    = 0x201,
 128         MLX5_CMD_OP_DESTROY_MKEY                  = 0x202,
 129         MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS        = 0x203,
 130         MLX5_CMD_OP_PAGE_FAULT_RESUME             = 0x204,
 131         MLX5_CMD_OP_ALLOC_MEMIC                   = 0x205,
 132         MLX5_CMD_OP_DEALLOC_MEMIC                 = 0x206,
 133         MLX5_CMD_OP_CREATE_EQ                     = 0x301,
 134         MLX5_CMD_OP_DESTROY_EQ                    = 0x302,
 135         MLX5_CMD_OP_QUERY_EQ                      = 0x303,
 136         MLX5_CMD_OP_GEN_EQE                       = 0x304,
 137         MLX5_CMD_OP_CREATE_CQ                     = 0x400,
 138         MLX5_CMD_OP_DESTROY_CQ                    = 0x401,
 139         MLX5_CMD_OP_QUERY_CQ                      = 0x402,
 140         MLX5_CMD_OP_MODIFY_CQ                     = 0x403,
 141         MLX5_CMD_OP_CREATE_QP                     = 0x500,
 142         MLX5_CMD_OP_DESTROY_QP                    = 0x501,
 143         MLX5_CMD_OP_RST2INIT_QP                   = 0x502,
 144         MLX5_CMD_OP_INIT2RTR_QP                   = 0x503,
 145         MLX5_CMD_OP_RTR2RTS_QP                    = 0x504,
 146         MLX5_CMD_OP_RTS2RTS_QP                    = 0x505,
 147         MLX5_CMD_OP_SQERR2RTS_QP                  = 0x506,
 148         MLX5_CMD_OP_2ERR_QP                       = 0x507,
 149         MLX5_CMD_OP_2RST_QP                       = 0x50a,
 150         MLX5_CMD_OP_QUERY_QP                      = 0x50b,
 151         MLX5_CMD_OP_SQD_RTS_QP                    = 0x50c,
 152         MLX5_CMD_OP_INIT2INIT_QP                  = 0x50e,
 153         MLX5_CMD_OP_CREATE_PSV                    = 0x600,
 154         MLX5_CMD_OP_DESTROY_PSV                   = 0x601,
 155         MLX5_CMD_OP_CREATE_SRQ                    = 0x700,
 156         MLX5_CMD_OP_DESTROY_SRQ                   = 0x701,
 157         MLX5_CMD_OP_QUERY_SRQ                     = 0x702,
 158         MLX5_CMD_OP_ARM_RQ                        = 0x703,
 159         MLX5_CMD_OP_CREATE_XRC_SRQ                = 0x705,
 160         MLX5_CMD_OP_DESTROY_XRC_SRQ               = 0x706,
 161         MLX5_CMD_OP_QUERY_XRC_SRQ                 = 0x707,
 162         MLX5_CMD_OP_ARM_XRC_SRQ                   = 0x708,
 163         MLX5_CMD_OP_CREATE_DCT                    = 0x710,
 164         MLX5_CMD_OP_DESTROY_DCT                   = 0x711,
 165         MLX5_CMD_OP_DRAIN_DCT                     = 0x712,
 166         MLX5_CMD_OP_QUERY_DCT                     = 0x713,
 167         MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION     = 0x714,
 168         MLX5_CMD_OP_CREATE_XRQ                    = 0x717,
 169         MLX5_CMD_OP_DESTROY_XRQ                   = 0x718,
 170         MLX5_CMD_OP_QUERY_XRQ                     = 0x719,
 171         MLX5_CMD_OP_ARM_XRQ                       = 0x71a,
 172         MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
 173         MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
 174         MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
 175         MLX5_CMD_OP_QUERY_ESW_FUNCTIONS           = 0x740,
 176         MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
 177         MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
 178         MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
 179         MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT      = 0x753,
 180         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT       = 0x754,
 181         MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT      = 0x755,
 182         MLX5_CMD_OP_QUERY_ROCE_ADDRESS            = 0x760,
 183         MLX5_CMD_OP_SET_ROCE_ADDRESS              = 0x761,
 184         MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT       = 0x762,
 185         MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT      = 0x763,
 186         MLX5_CMD_OP_QUERY_HCA_VPORT_GID           = 0x764,
 187         MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY          = 0x765,
 188         MLX5_CMD_OP_QUERY_VNIC_ENV                = 0x76f,
 189         MLX5_CMD_OP_QUERY_VPORT_COUNTER           = 0x770,
 190         MLX5_CMD_OP_ALLOC_Q_COUNTER               = 0x771,
 191         MLX5_CMD_OP_DEALLOC_Q_COUNTER             = 0x772,
 192         MLX5_CMD_OP_QUERY_Q_COUNTER               = 0x773,
 193         MLX5_CMD_OP_SET_MONITOR_COUNTER           = 0x774,
 194         MLX5_CMD_OP_ARM_MONITOR_COUNTER           = 0x775,
 195         MLX5_CMD_OP_SET_PP_RATE_LIMIT             = 0x780,
 196         MLX5_CMD_OP_QUERY_RATE_LIMIT              = 0x781,
 197         MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT      = 0x782,
 198         MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT     = 0x783,
 199         MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT       = 0x784,
 200         MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT      = 0x785,
 201         MLX5_CMD_OP_CREATE_QOS_PARA_VPORT         = 0x786,
 202         MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT        = 0x787,
 203         MLX5_CMD_OP_ALLOC_PD                      = 0x800,
 204         MLX5_CMD_OP_DEALLOC_PD                    = 0x801,
 205         MLX5_CMD_OP_ALLOC_UAR                     = 0x802,
 206         MLX5_CMD_OP_DEALLOC_UAR                   = 0x803,
 207         MLX5_CMD_OP_CONFIG_INT_MODERATION         = 0x804,
 208         MLX5_CMD_OP_ACCESS_REG                    = 0x805,
 209         MLX5_CMD_OP_ATTACH_TO_MCG                 = 0x806,
 210         MLX5_CMD_OP_DETACH_FROM_MCG               = 0x807,
 211         MLX5_CMD_OP_GET_DROPPED_PACKET_LOG        = 0x80a,
 212         MLX5_CMD_OP_MAD_IFC                       = 0x50d,
 213         MLX5_CMD_OP_QUERY_MAD_DEMUX               = 0x80b,
 214         MLX5_CMD_OP_SET_MAD_DEMUX                 = 0x80c,
 215         MLX5_CMD_OP_NOP                           = 0x80d,
 216         MLX5_CMD_OP_ALLOC_XRCD                    = 0x80e,
 217         MLX5_CMD_OP_DEALLOC_XRCD                  = 0x80f,
 218         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN        = 0x816,
 219         MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN      = 0x817,
 220         MLX5_CMD_OP_QUERY_CONG_STATUS             = 0x822,
 221         MLX5_CMD_OP_MODIFY_CONG_STATUS            = 0x823,
 222         MLX5_CMD_OP_QUERY_CONG_PARAMS             = 0x824,
 223         MLX5_CMD_OP_MODIFY_CONG_PARAMS            = 0x825,
 224         MLX5_CMD_OP_QUERY_CONG_STATISTICS         = 0x826,
 225         MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT           = 0x827,
 226         MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT        = 0x828,
 227         MLX5_CMD_OP_SET_L2_TABLE_ENTRY            = 0x829,
 228         MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY          = 0x82a,
 229         MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY         = 0x82b,
 230         MLX5_CMD_OP_SET_WOL_ROL                   = 0x830,
 231         MLX5_CMD_OP_QUERY_WOL_ROL                 = 0x831,
 232         MLX5_CMD_OP_CREATE_LAG                    = 0x840,
 233         MLX5_CMD_OP_MODIFY_LAG                    = 0x841,
 234         MLX5_CMD_OP_QUERY_LAG                     = 0x842,
 235         MLX5_CMD_OP_DESTROY_LAG                   = 0x843,
 236         MLX5_CMD_OP_CREATE_VPORT_LAG              = 0x844,
 237         MLX5_CMD_OP_DESTROY_VPORT_LAG             = 0x845,
 238         MLX5_CMD_OP_CREATE_TIR                    = 0x900,
 239         MLX5_CMD_OP_MODIFY_TIR                    = 0x901,
 240         MLX5_CMD_OP_DESTROY_TIR                   = 0x902,
 241         MLX5_CMD_OP_QUERY_TIR                     = 0x903,
 242         MLX5_CMD_OP_CREATE_SQ                     = 0x904,
 243         MLX5_CMD_OP_MODIFY_SQ                     = 0x905,
 244         MLX5_CMD_OP_DESTROY_SQ                    = 0x906,
 245         MLX5_CMD_OP_QUERY_SQ                      = 0x907,
 246         MLX5_CMD_OP_CREATE_RQ                     = 0x908,
 247         MLX5_CMD_OP_MODIFY_RQ                     = 0x909,
 248         MLX5_CMD_OP_SET_DELAY_DROP_PARAMS         = 0x910,
 249         MLX5_CMD_OP_DESTROY_RQ                    = 0x90a,
 250         MLX5_CMD_OP_QUERY_RQ                      = 0x90b,
 251         MLX5_CMD_OP_CREATE_RMP                    = 0x90c,
 252         MLX5_CMD_OP_MODIFY_RMP                    = 0x90d,
 253         MLX5_CMD_OP_DESTROY_RMP                   = 0x90e,
 254         MLX5_CMD_OP_QUERY_RMP                     = 0x90f,
 255         MLX5_CMD_OP_CREATE_TIS                    = 0x912,
 256         MLX5_CMD_OP_MODIFY_TIS                    = 0x913,
 257         MLX5_CMD_OP_DESTROY_TIS                   = 0x914,
 258         MLX5_CMD_OP_QUERY_TIS                     = 0x915,
 259         MLX5_CMD_OP_CREATE_RQT                    = 0x916,
 260         MLX5_CMD_OP_MODIFY_RQT                    = 0x917,
 261         MLX5_CMD_OP_DESTROY_RQT                   = 0x918,
 262         MLX5_CMD_OP_QUERY_RQT                     = 0x919,
 263         MLX5_CMD_OP_SET_FLOW_TABLE_ROOT           = 0x92f,
 264         MLX5_CMD_OP_CREATE_FLOW_TABLE             = 0x930,
 265         MLX5_CMD_OP_DESTROY_FLOW_TABLE            = 0x931,
 266         MLX5_CMD_OP_QUERY_FLOW_TABLE              = 0x932,
 267         MLX5_CMD_OP_CREATE_FLOW_GROUP             = 0x933,
 268         MLX5_CMD_OP_DESTROY_FLOW_GROUP            = 0x934,
 269         MLX5_CMD_OP_QUERY_FLOW_GROUP              = 0x935,
 270         MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY          = 0x936,
 271         MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY        = 0x937,
 272         MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY       = 0x938,
 273         MLX5_CMD_OP_ALLOC_FLOW_COUNTER            = 0x939,
 274         MLX5_CMD_OP_DEALLOC_FLOW_COUNTER          = 0x93a,
 275         MLX5_CMD_OP_QUERY_FLOW_COUNTER            = 0x93b,
 276         MLX5_CMD_OP_MODIFY_FLOW_TABLE             = 0x93c,
 277         MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
 278         MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
 279         MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
 280         MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT   = 0x940,
 281         MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
 282         MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT   = 0x942,
 283         MLX5_CMD_OP_FPGA_CREATE_QP                = 0x960,
 284         MLX5_CMD_OP_FPGA_MODIFY_QP                = 0x961,
 285         MLX5_CMD_OP_FPGA_QUERY_QP                 = 0x962,
 286         MLX5_CMD_OP_FPGA_DESTROY_QP               = 0x963,
 287         MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS        = 0x964,
 288         MLX5_CMD_OP_CREATE_GENERAL_OBJECT         = 0xa00,
 289         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT         = 0xa01,
 290         MLX5_CMD_OP_QUERY_GENERAL_OBJECT          = 0xa02,
 291         MLX5_CMD_OP_DESTROY_GENERAL_OBJECT        = 0xa03,
 292         MLX5_CMD_OP_CREATE_UCTX                   = 0xa04,
 293         MLX5_CMD_OP_DESTROY_UCTX                  = 0xa06,
 294         MLX5_CMD_OP_CREATE_UMEM                   = 0xa08,
 295         MLX5_CMD_OP_DESTROY_UMEM                  = 0xa0a,
 296         MLX5_CMD_OP_MAX
 297 };
 298
 299 /* Valid range for general commands that don't work over an object */
 300 enum {
 301         MLX5_CMD_OP_GENERAL_START = 0xb00,
 302         MLX5_CMD_OP_GENERAL_END = 0xd00,
 303 };
 304
 305 struct mlx5_ifc_flow_table_fields_supported_bits {
 306         u8         outer_dmac[0x1];
 307         u8         outer_smac[0x1];
 308         u8         outer_ether_type[0x1];
 309         u8         outer_ip_version[0x1];
 310         u8         outer_first_prio[0x1];
 311         u8         outer_first_cfi[0x1];
 312         u8         outer_first_vid[0x1];
 313         u8         outer_ipv4_ttl[0x1];
 314         u8         outer_second_prio[0x1];
 315         u8         outer_second_cfi[0x1];
 316         u8         outer_second_vid[0x1];
 317         u8         reserved_at_b[0x1];
 318         u8         outer_sip[0x1];
 319         u8         outer_dip[0x1];
 320         u8         outer_frag[0x1];
 321         u8         outer_ip_protocol[0x1];
 322         u8         outer_ip_ecn[0x1];
 323         u8         outer_ip_dscp[0x1];
 324         u8         outer_udp_sport[0x1];
 325         u8         outer_udp_dport[0x1];
 326         u8         outer_tcp_sport[0x1];
 327         u8         outer_tcp_dport[0x1];
 328         u8         outer_tcp_flags[0x1];
 329         u8         outer_gre_protocol[0x1];
 330         u8         outer_gre_key[0x1];
 331         u8         outer_vxlan_vni[0x1];
 332         u8         outer_geneve_vni[0x1];
 333         u8         outer_geneve_oam[0x1];
 334         u8         outer_geneve_protocol_type[0x1];
 335         u8         outer_geneve_opt_len[0x1];
 336         u8         reserved_at_1e[0x1];
 337         u8         source_eswitch_port[0x1];
 338
 339         u8         inner_dmac[0x1];
 340         u8         inner_smac[0x1];
 341         u8         inner_ether_type[0x1];
 342         u8         inner_ip_version[0x1];
 343         u8         inner_first_prio[0x1];
 344         u8         inner_first_cfi[0x1];
 345         u8         inner_first_vid[0x1];
 346         u8         reserved_at_27[0x1];
 347         u8         inner_second_prio[0x1];
 348         u8         inner_second_cfi[0x1];
 349         u8         inner_second_vid[0x1];
 350         u8         reserved_at_2b[0x1];
 351         u8         inner_sip[0x1];
 352         u8         inner_dip[0x1];
 353         u8         inner_frag[0x1];
 354         u8         inner_ip_protocol[0x1];
 355         u8         inner_ip_ecn[0x1];
 356         u8         inner_ip_dscp[0x1];
 357         u8         inner_udp_sport[0x1];
 358         u8         inner_udp_dport[0x1];
 359         u8         inner_tcp_sport[0x1];
 360         u8         inner_tcp_dport[0x1];
 361         u8         inner_tcp_flags[0x1];
 362         u8         reserved_at_37[0x9];
 363
 364         u8         geneve_tlv_option_0_data[0x1];
 365         u8         reserved_at_41[0x4];
 366         u8         outer_first_mpls_over_udp[0x4];
 367         u8         outer_first_mpls_over_gre[0x4];
 368         u8         inner_first_mpls[0x4];
 369         u8         outer_first_mpls[0x4];
 370         u8         reserved_at_55[0x2];
 371         u8         outer_esp_spi[0x1];
 372         u8         reserved_at_58[0x2];
 373         u8         bth_dst_qp[0x1];
 374
 375         u8         reserved_at_5b[0x25];
 376 };
 377
 378 struct mlx5_ifc_flow_table_prop_layout_bits {
 379         u8         ft_support[0x1];
 380         u8         reserved_at_1[0x1];
 381         u8         flow_counter[0x1];
 382         u8         flow_modify_en[0x1];
 383         u8         modify_root[0x1];
 384         u8         identified_miss_table_mode[0x1];
 385         u8         flow_table_modify[0x1];
 386         u8         reformat[0x1];
 387         u8         decap[0x1];
 388         u8         reserved_at_9[0x1];
 389         u8         pop_vlan[0x1];
 390         u8         push_vlan[0x1];
 391         u8         reserved_at_c[0x1];
 392         u8         pop_vlan_2[0x1];
 393         u8         push_vlan_2[0x1];
 394         u8         reformat_and_vlan_action[0x1];
 395         u8         reserved_at_10[0x1];
 396         u8         sw_owner[0x1];
 397         u8         reformat_l3_tunnel_to_l2[0x1];
 398         u8         reformat_l2_to_l3_tunnel[0x1];
 399         u8         reformat_and_modify_action[0x1];
 400         u8         reserved_at_15[0x2];
 401         u8         table_miss_action_domain[0x1];
 402         u8         termination_table[0x1];
 403         u8         reserved_at_19[0x7];
 404         u8         reserved_at_20[0x2];
 405         u8         log_max_ft_size[0x6];
 406         u8         log_max_modify_header_context[0x8];
 407         u8         max_modify_header_actions[0x8];
 408         u8         max_ft_level[0x8];
 409
 410         u8         reserved_at_40[0x20];
 411
 412         u8         reserved_at_60[0x18];
 413         u8         log_max_ft_num[0x8];
 414
 415         u8         reserved_at_80[0x18];
 416         u8         log_max_destination[0x8];
 417
 418         u8         log_max_flow_counter[0x8];
 419         u8         reserved_at_a8[0x10];
 420         u8         log_max_flow[0x8];
 421
 422         u8         reserved_at_c0[0x40];
 423
 424         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
 425
 426         struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
 427 };
 428
 429 struct mlx5_ifc_odp_per_transport_service_cap_bits {
 430         u8         send[0x1];
 431         u8         receive[0x1];
 432         u8         write[0x1];
 433         u8         read[0x1];
 434         u8         atomic[0x1];
 435         u8         srq_receive[0x1];
 436         u8         reserved_at_6[0x1a];
 437 };
 438
 439 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 440         u8         smac_47_16[0x20];
 441
 442         u8         smac_15_0[0x10];
 443         u8         ethertype[0x10];
 444
 445         u8         dmac_47_16[0x20];
 446
 447         u8         dmac_15_0[0x10];
 448         u8         first_prio[0x3];
 449         u8         first_cfi[0x1];
 450         u8         first_vid[0xc];
 451
 452         u8         ip_protocol[0x8];
 453         u8         ip_dscp[0x6];
 454         u8         ip_ecn[0x2];
 455         u8         cvlan_tag[0x1];
 456         u8         svlan_tag[0x1];
 457         u8         frag[0x1];
 458         u8         ip_version[0x4];
 459         u8         tcp_flags[0x9];
 460
 461         u8         tcp_sport[0x10];
 462         u8         tcp_dport[0x10];
 463
 464         u8         reserved_at_c0[0x18];
 465         u8         ttl_hoplimit[0x8];
 466
 467         u8         udp_sport[0x10];
 468         u8         udp_dport[0x10];
 469
 470         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 471
 472         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 473 };
 474
 475 struct mlx5_ifc_nvgre_key_bits {
 476         u8 hi[0x18];
 477         u8 lo[0x8];
 478 };
 479
 480 union mlx5_ifc_gre_key_bits {
 481         struct mlx5_ifc_nvgre_key_bits nvgre;
 482         u8 key[0x20];
 483 };
 484
 485 struct mlx5_ifc_fte_match_set_misc_bits {
 486         u8         reserved_at_0[0x8];
 487         u8         source_sqn[0x18];
 488
 489         u8         source_eswitch_owner_vhca_id[0x10];
 490         u8         source_port[0x10];
 491
 492         u8         outer_second_prio[0x3];
 493         u8         outer_second_cfi[0x1];
 494         u8         outer_second_vid[0xc];
 495         u8         inner_second_prio[0x3];
 496         u8         inner_second_cfi[0x1];
 497         u8         inner_second_vid[0xc];
 498
 499         u8         outer_second_cvlan_tag[0x1];
 500         u8         inner_second_cvlan_tag[0x1];
 501         u8         outer_second_svlan_tag[0x1];
 502         u8         inner_second_svlan_tag[0x1];
 503         u8         reserved_at_64[0xc];
 504         u8         gre_protocol[0x10];
 505
 506         union mlx5_ifc_gre_key_bits gre_key;
 507
 508         u8         vxlan_vni[0x18];
 509         u8         reserved_at_b8[0x8];
 510
 511         u8         geneve_vni[0x18];
 512         u8         reserved_at_d8[0x7];
 513         u8         geneve_oam[0x1];
 514
 515         u8         reserved_at_e0[0xc];
 516         u8         outer_ipv6_flow_label[0x14];
 517
 518         u8         reserved_at_100[0xc];
 519         u8         inner_ipv6_flow_label[0x14];
 520
 521         u8         reserved_at_120[0xa];
 522         u8         geneve_opt_len[0x6];
 523         u8         geneve_protocol_type[0x10];
 524
 525         u8         reserved_at_140[0x8];
 526         u8         bth_dst_qp[0x18];
 527         u8         reserved_at_160[0x20];
 528         u8         outer_esp_spi[0x20];
 529         u8         reserved_at_1a0[0x60];
 530 };
 531
 532 struct mlx5_ifc_fte_match_mpls_bits {
 533         u8         mpls_label[0x14];
 534         u8         mpls_exp[0x3];
 535         u8         mpls_s_bos[0x1];
 536         u8         mpls_ttl[0x8];
 537 };
 538
 539 struct mlx5_ifc_fte_match_set_misc2_bits {
 540         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 541
 542         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 543
 544         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 545
 546         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 547
 548         u8         metadata_reg_c_7[0x20];
 549
 550         u8         metadata_reg_c_6[0x20];
 551
 552         u8         metadata_reg_c_5[0x20];
 553
 554         u8         metadata_reg_c_4[0x20];
 555
 556         u8         metadata_reg_c_3[0x20];
 557
 558         u8         metadata_reg_c_2[0x20];
 559
 560         u8         metadata_reg_c_1[0x20];
 561
 562         u8         metadata_reg_c_0[0x20];
 563
 564         u8         metadata_reg_a[0x20];
 565
 566         u8         reserved_at_1a0[0x60];
 567 };
 568
 569 struct mlx5_ifc_fte_match_set_misc3_bits {
 570         u8         reserved_at_0[0x120];
 571         u8         geneve_tlv_option_0_data[0x20];
 572         u8         reserved_at_140[0xc0];
 573 };
 574
 575 struct mlx5_ifc_cmd_pas_bits {
 576         u8         pa_h[0x20];
 577
 578         u8         pa_l[0x14];
 579         u8         reserved_at_34[0xc];
 580 };
 581
 582 struct mlx5_ifc_uint64_bits {
 583         u8         hi[0x20];
 584
 585         u8         lo[0x20];
 586 };
 587
 588 enum {
 589         MLX5_ADS_STAT_RATE_NO_LIMIT  = 0x0,
 590         MLX5_ADS_STAT_RATE_2_5GBPS   = 0x7,
 591         MLX5_ADS_STAT_RATE_10GBPS    = 0x8,
 592         MLX5_ADS_STAT_RATE_30GBPS    = 0x9,
 593         MLX5_ADS_STAT_RATE_5GBPS     = 0xa,
 594         MLX5_ADS_STAT_RATE_20GBPS    = 0xb,
 595         MLX5_ADS_STAT_RATE_40GBPS    = 0xc,
 596         MLX5_ADS_STAT_RATE_60GBPS    = 0xd,
 597         MLX5_ADS_STAT_RATE_80GBPS    = 0xe,
 598         MLX5_ADS_STAT_RATE_120GBPS   = 0xf,
 599 };
 600
 601 struct mlx5_ifc_ads_bits {
 602         u8         fl[0x1];
 603         u8         free_ar[0x1];
 604         u8         reserved_at_2[0xe];
 605         u8         pkey_index[0x10];
 606
 607         u8         reserved_at_20[0x8];
 608         u8         grh[0x1];
 609         u8         mlid[0x7];
 610         u8         rlid[0x10];
 611
 612         u8         ack_timeout[0x5];
 613         u8         reserved_at_45[0x3];
 614         u8         src_addr_index[0x8];
 615         u8         reserved_at_50[0x4];
 616         u8         stat_rate[0x4];
 617         u8         hop_limit[0x8];
 618
 619         u8         reserved_at_60[0x4];
 620         u8         tclass[0x8];
 621         u8         flow_label[0x14];
 622
 623         u8         rgid_rip[16][0x8];
 624
 625         u8         reserved_at_100[0x4];
 626         u8         f_dscp[0x1];
 627         u8         f_ecn[0x1];
 628         u8         reserved_at_106[0x1];
 629         u8         f_eth_prio[0x1];
 630         u8         ecn[0x2];
 631         u8         dscp[0x6];
 632         u8         udp_sport[0x10];
 633
 634         u8         dei_cfi[0x1];
 635         u8         eth_prio[0x3];
 636         u8         sl[0x4];
 637         u8         vhca_port_num[0x8];
 638         u8         rmac_47_32[0x10];
 639
 640         u8         rmac_31_0[0x20];
 641 };
 642
 643 struct mlx5_ifc_flow_table_nic_cap_bits {
 644         u8         nic_rx_multi_path_tirs[0x1];
 645         u8         nic_rx_multi_path_tirs_fts[0x1];
 646         u8         allow_sniffer_and_nic_rx_shared_tir[0x1];
 647         u8         reserved_at_3[0x1d];
 648         u8         encap_general_header[0x1];
 649         u8         reserved_at_21[0xa];
 650         u8         log_max_packet_reformat_context[0x5];
 651         u8         reserved_at_30[0x6];
 652         u8         max_encap_header_size[0xa];
 653         u8         reserved_at_40[0x1c0];
 654
 655         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
 656
 657         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma;
 658
 659         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
 660
 661         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
 662
 663         u8         reserved_at_a00[0x200];
 664
 665         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
 666
 667         u8         reserved_at_e00[0x7200];
 668 };
 669
 670 enum {
 671         MLX5_FDB_TO_VPORT_REG_C_0 = 0x01,
 672         MLX5_FDB_TO_VPORT_REG_C_1 = 0x02,
 673         MLX5_FDB_TO_VPORT_REG_C_2 = 0x04,
 674         MLX5_FDB_TO_VPORT_REG_C_3 = 0x08,
 675         MLX5_FDB_TO_VPORT_REG_C_4 = 0x10,
 676         MLX5_FDB_TO_VPORT_REG_C_5 = 0x20,
 677         MLX5_FDB_TO_VPORT_REG_C_6 = 0x40,
 678         MLX5_FDB_TO_VPORT_REG_C_7 = 0x80,
 679 };
 680
 681 struct mlx5_ifc_flow_table_eswitch_cap_bits {
 682         u8      fdb_to_vport_reg_c_id[0x8];
 683         u8      reserved_at_8[0xf];
 684         u8      flow_source[0x1];
 685         u8      reserved_at_18[0x2];
 686         u8      multi_fdb_encap[0x1];
 687         u8      reserved_at_1b[0x1];
 688         u8      fdb_multi_path_to_table[0x1];
 689         u8      reserved_at_1d[0x3];
 690
 691         u8      reserved_at_20[0x1e0];
 692
 693         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
 694
 695         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
 696
 697         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
 698
 699         u8      reserved_at_800[0x7800];
 700 };
 701
 702 enum {
 703         MLX5_COUNTER_SOURCE_ESWITCH = 0x0,
 704         MLX5_COUNTER_FLOW_ESWITCH   = 0x1,
 705 };
 706
 707 struct mlx5_ifc_e_switch_cap_bits {
 708         u8         vport_svlan_strip[0x1];
 709         u8         vport_cvlan_strip[0x1];
 710         u8         vport_svlan_insert[0x1];
 711         u8         vport_cvlan_insert_if_not_exist[0x1];
 712         u8         vport_cvlan_insert_overwrite[0x1];
 713         u8         reserved_at_5[0x3];
 714         u8         esw_uplink_ingress_acl[0x1];
 715         u8         reserved_at_9[0x10];
 716         u8         esw_functions_changed[0x1];
 717         u8         reserved_at_1a[0x1];
 718         u8         ecpf_vport_exists[0x1];
 719         u8         counter_eswitch_affinity[0x1];
 720         u8         merged_eswitch[0x1];
 721         u8         nic_vport_node_guid_modify[0x1];
 722         u8         nic_vport_port_guid_modify[0x1];
 723
 724         u8         vxlan_encap_decap[0x1];
 725         u8         nvgre_encap_decap[0x1];
 726         u8         reserved_at_22[0x1];
 727         u8         log_max_fdb_encap_uplink[0x5];
 728         u8         reserved_at_21[0x3];
 729         u8         log_max_packet_reformat_context[0x5];
 730         u8         reserved_2b[0x6];
 731         u8         max_encap_header_size[0xa];
 732
 733         u8         reserved_at_40[0xb];
 734         u8         log_max_esw_sf[0x5];
 735         u8         esw_sf_base_id[0x10];
 736
 737         u8         reserved_at_60[0x7a0];
 738
 739 };
 740
 741 struct mlx5_ifc_qos_cap_bits {
 742         u8         packet_pacing[0x1];
 743         u8         esw_scheduling[0x1];
 744         u8         esw_bw_share[0x1];
 745         u8         esw_rate_limit[0x1];
 746         u8         reserved_at_4[0x1];
 747         u8         packet_pacing_burst_bound[0x1];
 748         u8         packet_pacing_typical_size[0x1];
 749         u8         reserved_at_7[0x19];
 750
 751         u8         reserved_at_20[0x20];
 752
 753         u8         packet_pacing_max_rate[0x20];
 754
 755         u8         packet_pacing_min_rate[0x20];
 756
 757         u8         reserved_at_80[0x10];
 758         u8         packet_pacing_rate_table_size[0x10];
 759
 760         u8         esw_element_type[0x10];
 761         u8         esw_tsar_type[0x10];
 762
 763         u8         reserved_at_c0[0x10];
 764         u8         max_qos_para_vport[0x10];
 765
 766         u8         max_tsar_bw_share[0x20];
 767
 768         u8         reserved_at_100[0x700];
 769 };
 770
 771 struct mlx5_ifc_debug_cap_bits {
 772         u8         core_dump_general[0x1];
 773         u8         core_dump_qp[0x1];
 774         u8         reserved_at_2[0x1e];
 775
 776         u8         reserved_at_20[0x2];
 777         u8         stall_detect[0x1];
 778         u8         reserved_at_23[0x1d];
 779
 780         u8         reserved_at_40[0x7c0];
 781 };
 782
 783 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
 784         u8         csum_cap[0x1];
 785         u8         vlan_cap[0x1];
 786         u8         lro_cap[0x1];
 787         u8         lro_psh_flag[0x1];
 788         u8         lro_time_stamp[0x1];
 789         u8         reserved_at_5[0x2];
 790         u8         wqe_vlan_insert[0x1];
 791         u8         self_lb_en_modifiable[0x1];
 792         u8         reserved_at_9[0x2];
 793         u8         max_lso_cap[0x5];
 794         u8         multi_pkt_send_wqe[0x2];
 795         u8         wqe_inline_mode[0x2];
 796         u8         rss_ind_tbl_cap[0x4];
 797         u8         reg_umr_sq[0x1];
 798         u8         scatter_fcs[0x1];
 799         u8         enhanced_multi_pkt_send_wqe[0x1];
 800         u8         tunnel_lso_const_out_ip_id[0x1];
 801         u8         reserved_at_1c[0x2];
 802         u8         tunnel_stateless_gre[0x1];
 803         u8         tunnel_stateless_vxlan[0x1];
 804
 805         u8         swp[0x1];
 806         u8         swp_csum[0x1];
 807         u8         swp_lso[0x1];
 808         u8         cqe_checksum_full[0x1];
 809         u8         reserved_at_24[0xc];
 810         u8         max_vxlan_udp_ports[0x8];
 811         u8         reserved_at_38[0x6];
 812         u8         max_geneve_opt_len[0x1];
 813         u8         tunnel_stateless_geneve_rx[0x1];
 814
 815         u8         reserved_at_40[0x10];
 816         u8         lro_min_mss_size[0x10];
 817
 818         u8         reserved_at_60[0x120];
 819
 820         u8         lro_timer_supported_periods[4][0x20];
 821
 822         u8         reserved_at_200[0x600];
 823 };
 824
 825 struct mlx5_ifc_roce_cap_bits {
 826         u8         roce_apm[0x1];
 827         u8         reserved_at_1[0x1f];
 828
 829         u8         reserved_at_20[0x60];
 830
 831         u8         reserved_at_80[0xc];
 832         u8         l3_type[0x4];
 833         u8         reserved_at_90[0x8];
 834         u8         roce_version[0x8];
 835
 836         u8         reserved_at_a0[0x10];
 837         u8         r_roce_dest_udp_port[0x10];
 838
 839         u8         r_roce_max_src_udp_port[0x10];
 840         u8         r_roce_min_src_udp_port[0x10];
 841
 842         u8         reserved_at_e0[0x10];
 843         u8         roce_address_table_size[0x10];
 844
 845         u8         reserved_at_100[0x700];
 846 };
 847
 848 struct mlx5_ifc_device_mem_cap_bits {
 849         u8         memic[0x1];
 850         u8         reserved_at_1[0x1f];
 851
 852         u8         reserved_at_20[0xb];
 853         u8         log_min_memic_alloc_size[0x5];
 854         u8         reserved_at_30[0x8];
 855         u8         log_max_memic_addr_alignment[0x8];
 856
 857         u8         memic_bar_start_addr[0x40];
 858
 859         u8         memic_bar_size[0x20];
 860
 861         u8         max_memic_size[0x20];
 862
 863         u8         steering_sw_icm_start_address[0x40];
 864
 865         u8         reserved_at_100[0x8];
 866         u8         log_header_modify_sw_icm_size[0x8];
 867         u8         reserved_at_110[0x2];
 868         u8         log_sw_icm_alloc_granularity[0x6];
 869         u8         log_steering_sw_icm_size[0x8];
 870
 871         u8         reserved_at_120[0x20];
 872
 873         u8         header_modify_sw_icm_start_address[0x40];
 874
 875         u8         reserved_at_180[0x680];
 876 };
 877
 878 struct mlx5_ifc_device_event_cap_bits {
 879         u8         user_affiliated_events[4][0x40];
 880
 881         u8         user_unaffiliated_events[4][0x40];
 882 };
 883
 884 enum {
 885         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE     = 0x0,
 886         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES    = 0x2,
 887         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES    = 0x4,
 888         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES    = 0x8,
 889         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES   = 0x10,
 890         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES   = 0x20,
 891         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES   = 0x40,
 892         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES  = 0x80,
 893         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES  = 0x100,
 894 };
 895
 896 enum {
 897         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE     = 0x1,
 898         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES    = 0x2,
 899         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES    = 0x4,
 900         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES    = 0x8,
 901         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES   = 0x10,
 902         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES   = 0x20,
 903         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES   = 0x40,
 904         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES  = 0x80,
 905         MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES  = 0x100,
 906 };
 907
 908 struct mlx5_ifc_atomic_caps_bits {
 909         u8         reserved_at_0[0x40];
 910
 911         u8         atomic_req_8B_endianness_mode[0x2];
 912         u8         reserved_at_42[0x4];
 913         u8         supported_atomic_req_8B_endianness_mode_1[0x1];
 914
 915         u8         reserved_at_47[0x19];
 916
 917         u8         reserved_at_60[0x20];
 918
 919         u8         reserved_at_80[0x10];
 920         u8         atomic_operations[0x10];
 921
 922         u8         reserved_at_a0[0x10];
 923         u8         atomic_size_qp[0x10];
 924
 925         u8         reserved_at_c0[0x10];
 926         u8         atomic_size_dc[0x10];
 927
 928         u8         reserved_at_e0[0x720];
 929 };
 930
 931 struct mlx5_ifc_odp_cap_bits {
 932         u8         reserved_at_0[0x40];
 933
 934         u8         sig[0x1];
 935         u8         reserved_at_41[0x1f];
 936
 937         u8         reserved_at_60[0x20];
 938
 939         struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
 940
 941         struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
 942
 943         struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
 944
 945         struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps;
 946
 947         u8         reserved_at_100[0x700];
 948 };
 949
 950 struct mlx5_ifc_calc_op {
 951         u8        reserved_at_0[0x10];
 952         u8        reserved_at_10[0x9];
 953         u8        op_swap_endianness[0x1];
 954         u8        op_min[0x1];
 955         u8        op_xor[0x1];
 956         u8        op_or[0x1];
 957         u8        op_and[0x1];
 958         u8        op_max[0x1];
 959         u8        op_add[0x1];
 960 };
 961
 962 struct mlx5_ifc_vector_calc_cap_bits {
 963         u8         calc_matrix[0x1];
 964         u8         reserved_at_1[0x1f];
 965         u8         reserved_at_20[0x8];
 966         u8         max_vec_count[0x8];
 967         u8         reserved_at_30[0xd];
 968         u8         max_chunk_size[0x3];
 969         struct mlx5_ifc_calc_op calc0;
 970         struct mlx5_ifc_calc_op calc1;
 971         struct mlx5_ifc_calc_op calc2;
 972         struct mlx5_ifc_calc_op calc3;
 973
 974         u8         reserved_at_c0[0x720];
 975 };
 976
 977 struct mlx5_ifc_tls_cap_bits {
 978         u8         tls_1_2_aes_gcm_128[0x1];
 979         u8         tls_1_3_aes_gcm_128[0x1];
 980         u8         tls_1_2_aes_gcm_256[0x1];
 981         u8         tls_1_3_aes_gcm_256[0x1];
 982         u8         reserved_at_4[0x1c];
 983
 984         u8         reserved_at_20[0x7e0];
 985 };
 986
 987 enum {
 988         MLX5_WQ_TYPE_LINKED_LIST  = 0x0,
 989         MLX5_WQ_TYPE_CYCLIC       = 0x1,
 990         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
 991         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
 992 };
 993
 994 enum {
 995         MLX5_WQ_END_PAD_MODE_NONE   = 0x0,
 996         MLX5_WQ_END_PAD_MODE_ALIGN  = 0x1,
 997 };
 998
 999 enum {
1000         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES    = 0x0,
1001         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES   = 0x1,
1002         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES   = 0x2,
1003         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES   = 0x3,
1004         MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES  = 0x4,
1005 };
1006
1007 enum {
1008         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES  = 0x0,
1009         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES  = 0x1,
1010         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES  = 0x2,
1011         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES   = 0x3,
1012         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES   = 0x4,
1013         MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES   = 0x5,
1014 };
1015
1016 enum {
1017         MLX5_CMD_HCA_CAP_PORT_TYPE_IB        = 0x0,
1018         MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET  = 0x1,
1019 };
1020
1021 enum {
1022         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED       = 0x0,
1023         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE  = 0x1,
1024         MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED        = 0x3,
1025 };
1026
1027 enum {
1028         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1029         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1030 };
1031
1032 enum {
1033         MLX5_CAP_UMR_FENCE_STRONG       = 0x0,
1034         MLX5_CAP_UMR_FENCE_SMALL        = 0x1,
1035         MLX5_CAP_UMR_FENCE_NONE         = 0x2,
1036 };
1037
1038 enum {
1039         MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1040         MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1,
1041 };
1042
1043 #define MLX5_FC_BULK_SIZE_FACTOR 128
1044
1045 enum mlx5_fc_bulk_alloc_bitmask {
1046         MLX5_FC_BULK_128   = (1 << 0),
1047         MLX5_FC_BULK_256   = (1 << 1),
1048         MLX5_FC_BULK_512   = (1 << 2),
1049         MLX5_FC_BULK_1024  = (1 << 3),
1050         MLX5_FC_BULK_2048  = (1 << 4),
1051         MLX5_FC_BULK_4096  = (1 << 5),
1052         MLX5_FC_BULK_8192  = (1 << 6),
1053         MLX5_FC_BULK_16384 = (1 << 7),
1054 };
1055
1056 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum))
1057
1058 struct mlx5_ifc_cmd_hca_cap_bits {
1059         u8         reserved_at_0[0x30];
1060         u8         vhca_id[0x10];
1061
1062         u8         reserved_at_40[0x40];
1063
1064         u8         log_max_srq_sz[0x8];
1065         u8         log_max_qp_sz[0x8];
1066         u8         event_cap[0x1];
1067         u8         reserved_at_91[0x7];
1068         u8         prio_tag_required[0x1];
1069         u8         reserved_at_99[0x2];
1070         u8         log_max_qp[0x5];
1071
1072         u8         reserved_at_a0[0xb];
1073         u8         log_max_srq[0x5];
1074         u8         reserved_at_b0[0x10];
1075
1076         u8         reserved_at_c0[0x8];
1077         u8         log_max_cq_sz[0x8];
1078         u8         reserved_at_d0[0xb];
1079         u8         log_max_cq[0x5];
1080
1081         u8         log_max_eq_sz[0x8];
1082         u8         reserved_at_e8[0x2];
1083         u8         log_max_mkey[0x6];
1084         u8         reserved_at_f0[0x8];
1085         u8         dump_fill_mkey[0x1];
1086         u8         reserved_at_f9[0x2];
1087         u8         fast_teardown[0x1];
1088         u8         log_max_eq[0x4];
1089
1090         u8         max_indirection[0x8];
1091         u8         fixed_buffer_size[0x1];
1092         u8         log_max_mrw_sz[0x7];
1093         u8         force_teardown[0x1];
1094         u8         reserved_at_111[0x1];
1095         u8         log_max_bsf_list_size[0x6];
1096         u8         umr_extended_translation_offset[0x1];
1097         u8         null_mkey[0x1];
1098         u8         log_max_klm_list_size[0x6];
1099
1100         u8         reserved_at_120[0xa];
1101         u8         log_max_ra_req_dc[0x6];
1102         u8         reserved_at_130[0xa];
1103         u8         log_max_ra_res_dc[0x6];
1104
1105         u8         reserved_at_140[0xa];
1106         u8         log_max_ra_req_qp[0x6];
1107         u8         reserved_at_150[0xa];
1108         u8         log_max_ra_res_qp[0x6];
1109
1110         u8         end_pad[0x1];
1111         u8         cc_query_allowed[0x1];
1112         u8         cc_modify_allowed[0x1];
1113         u8         start_pad[0x1];
1114         u8         cache_line_128byte[0x1];
1115         u8         reserved_at_165[0x4];
1116         u8         rts2rts_qp_counters_set_id[0x1];
1117         u8         reserved_at_16a[0x5];
1118         u8         qcam_reg[0x1];
1119         u8         gid_table_size[0x10];
1120
1121         u8         out_of_seq_cnt[0x1];
1122         u8         vport_counters[0x1];
1123         u8         retransmission_q_counters[0x1];
1124         u8         debug[0x1];
1125         u8         modify_rq_counter_set_id[0x1];
1126         u8         rq_delay_drop[0x1];
1127         u8         max_qp_cnt[0xa];
1128         u8         pkey_table_size[0x10];
1129
1130         u8         vport_group_manager[0x1];
1131         u8         vhca_group_manager[0x1];
1132         u8         ib_virt[0x1];
1133         u8         eth_virt[0x1];
1134         u8         vnic_env_queue_counters[0x1];
1135         u8         ets[0x1];
1136         u8         nic_flow_table[0x1];
1137         u8         eswitch_manager[0x1];
1138         u8         device_memory[0x1];
1139         u8         mcam_reg[0x1];
1140         u8         pcam_reg[0x1];
1141         u8         local_ca_ack_delay[0x5];
1142         u8         port_module_event[0x1];
1143         u8         enhanced_error_q_counters[0x1];
1144         u8         ports_check[0x1];
1145         u8         reserved_at_1b3[0x1];
1146         u8         disable_link_up[0x1];
1147         u8         beacon_led[0x1];
1148         u8         port_type[0x2];
1149         u8         num_ports[0x8];
1150
1151         u8         reserved_at_1c0[0x1];
1152         u8         pps[0x1];
1153         u8         pps_modify[0x1];
1154         u8         log_max_msg[0x5];
1155         u8         reserved_at_1c8[0x4];
1156         u8         max_tc[0x4];
1157         u8         temp_warn_event[0x1];
1158         u8         dcbx[0x1];
1159         u8         general_notification_event[0x1];
1160         u8         reserved_at_1d3[0x2];
1161         u8         fpga[0x1];
1162         u8         rol_s[0x1];
1163         u8         rol_g[0x1];
1164         u8         reserved_at_1d8[0x1];
1165         u8         wol_s[0x1];
1166         u8         wol_g[0x1];
1167         u8         wol_a[0x1];
1168         u8         wol_b[0x1];
1169         u8         wol_m[0x1];
1170         u8         wol_u[0x1];
1171         u8         wol_p[0x1];
1172
1173         u8         stat_rate_support[0x10];
1174         u8         reserved_at_1f0[0xc];
1175         u8         cqe_version[0x4];
1176
1177         u8         compact_address_vector[0x1];
1178         u8         striding_rq[0x1];
1179         u8         reserved_at_202[0x1];
1180         u8         ipoib_enhanced_offloads[0x1];
1181         u8         ipoib_basic_offloads[0x1];
1182         u8         reserved_at_205[0x1];
1183         u8         repeated_block_disabled[0x1];
1184         u8         umr_modify_entity_size_disabled[0x1];
1185         u8         umr_modify_atomic_disabled[0x1];
1186         u8         umr_indirect_mkey_disabled[0x1];
1187         u8         umr_fence[0x2];
1188         u8         dc_req_scat_data_cqe[0x1];
1189         u8         reserved_at_20d[0x2];
1190         u8         drain_sigerr[0x1];
1191         u8         cmdif_checksum[0x2];
1192         u8         sigerr_cqe[0x1];
1193         u8         reserved_at_213[0x1];
1194         u8         wq_signature[0x1];
1195         u8         sctr_data_cqe[0x1];
1196         u8         reserved_at_216[0x1];
1197         u8         sho[0x1];
1198         u8         tph[0x1];
1199         u8         rf[0x1];
1200         u8         dct[0x1];
1201         u8         qos[0x1];
1202         u8         eth_net_offloads[0x1];
1203         u8         roce[0x1];
1204         u8         atomic[0x1];
1205         u8         reserved_at_21f[0x1];
1206
1207         u8         cq_oi[0x1];
1208         u8         cq_resize[0x1];
1209         u8         cq_moderation[0x1];
1210         u8         reserved_at_223[0x3];
1211         u8         cq_eq_remap[0x1];
1212         u8         pg[0x1];
1213         u8         block_lb_mc[0x1];
1214         u8         reserved_at_229[0x1];
1215         u8         scqe_break_moderation[0x1];
1216         u8         cq_period_start_from_cqe[0x1];
1217         u8         cd[0x1];
1218         u8         reserved_at_22d[0x1];
1219         u8         apm[0x1];
1220         u8         vector_calc[0x1];
1221         u8         umr_ptr_rlky[0x1];
1222         u8         imaicl[0x1];
1223         u8         qp_packet_based[0x1];
1224         u8         reserved_at_233[0x3];
1225         u8         qkv[0x1];
1226         u8         pkv[0x1];
1227         u8         set_deth_sqpn[0x1];
1228         u8         reserved_at_239[0x3];
1229         u8         xrc[0x1];
1230         u8         ud[0x1];
1231         u8         uc[0x1];
1232         u8         rc[0x1];
1233
1234         u8         uar_4k[0x1];
1235         u8         reserved_at_241[0x9];
1236         u8         uar_sz[0x6];
1237         u8         reserved_at_250[0x8];
1238         u8         log_pg_sz[0x8];
1239
1240         u8         bf[0x1];
1241         u8         driver_version[0x1];
1242         u8         pad_tx_eth_packet[0x1];
1243         u8         reserved_at_263[0x8];
1244         u8         log_bf_reg_size[0x5];
1245
1246         u8         reserved_at_270[0xb];
1247         u8         lag_master[0x1];
1248         u8         num_lag_ports[0x4];
1249
1250         u8         reserved_at_280[0x10];
1251         u8         max_wqe_sz_sq[0x10];
1252
1253         u8         reserved_at_2a0[0x10];
1254         u8         max_wqe_sz_rq[0x10];
1255
1256         u8         max_flow_counter_31_16[0x10];
1257         u8         max_wqe_sz_sq_dc[0x10];
1258
1259         u8         reserved_at_2e0[0x7];
1260         u8         max_qp_mcg[0x19];
1261
1262         u8         reserved_at_300[0x10];
1263         u8         flow_counter_bulk_alloc[0x8];
1264         u8         log_max_mcg[0x8];
1265
1266         u8         reserved_at_320[0x3];
1267         u8         log_max_transport_domain[0x5];
1268         u8         reserved_at_328[0x3];
1269         u8         log_max_pd[0x5];
1270         u8         reserved_at_330[0xb];
1271         u8         log_max_xrcd[0x5];
1272
1273         u8         nic_receive_steering_discard[0x1];
1274         u8         receive_discard_vport_down[0x1];
1275         u8         transmit_discard_vport_down[0x1];
1276         u8         reserved_at_343[0x5];
1277         u8         log_max_flow_counter_bulk[0x8];
1278         u8         max_flow_counter_15_0[0x10];
1279
1280
1281         u8         reserved_at_360[0x3];
1282         u8         log_max_rq[0x5];
1283         u8         reserved_at_368[0x3];
1284         u8         log_max_sq[0x5];
1285         u8         reserved_at_370[0x3];
1286         u8         log_max_tir[0x5];
1287         u8         reserved_at_378[0x3];
1288         u8         log_max_tis[0x5];
1289
1290         u8         basic_cyclic_rcv_wqe[0x1];
1291         u8         reserved_at_381[0x2];
1292         u8         log_max_rmp[0x5];
1293         u8         reserved_at_388[0x3];
1294         u8         log_max_rqt[0x5];
1295         u8         reserved_at_390[0x3];
1296         u8         log_max_rqt_size[0x5];
1297         u8         reserved_at_398[0x3];
1298         u8         log_max_tis_per_sq[0x5];
1299
1300         u8         ext_stride_num_range[0x1];
1301         u8         reserved_at_3a1[0x2];
1302         u8         log_max_stride_sz_rq[0x5];
1303         u8         reserved_at_3a8[0x3];
1304         u8         log_min_stride_sz_rq[0x5];
1305         u8         reserved_at_3b0[0x3];
1306         u8         log_max_stride_sz_sq[0x5];
1307         u8         reserved_at_3b8[0x3];
1308         u8         log_min_stride_sz_sq[0x5];
1309
1310         u8         hairpin[0x1];
1311         u8         reserved_at_3c1[0x2];
1312         u8         log_max_hairpin_queues[0x5];
1313         u8         reserved_at_3c8[0x3];
1314         u8         log_max_hairpin_wq_data_sz[0x5];
1315         u8         reserved_at_3d0[0x3];
1316         u8         log_max_hairpin_num_packets[0x5];
1317         u8         reserved_at_3d8[0x3];
1318         u8         log_max_wq_sz[0x5];
1319
1320         u8         nic_vport_change_event[0x1];
1321         u8         disable_local_lb_uc[0x1];
1322         u8         disable_local_lb_mc[0x1];
1323         u8         log_min_hairpin_wq_data_sz[0x5];
1324         u8         reserved_at_3e8[0x3];
1325         u8         log_max_vlan_list[0x5];
1326         u8         reserved_at_3f0[0x3];
1327         u8         log_max_current_mc_list[0x5];
1328         u8         reserved_at_3f8[0x3];
1329         u8         log_max_current_uc_list[0x5];
1330
1331         u8         general_obj_types[0x40];
1332
1333         u8         reserved_at_440[0x20];
1334
1335         u8         tls[0x1];
1336         u8         reserved_at_461[0x2];
1337         u8         log_max_uctx[0x5];
1338         u8         reserved_at_468[0x3];
1339         u8         log_max_umem[0x5];
1340         u8         max_num_eqs[0x10];
1341
1342         u8         reserved_at_480[0x3];
1343         u8         log_max_l2_table[0x5];
1344         u8         reserved_at_488[0x8];
1345         u8         log_uar_page_sz[0x10];
1346
1347         u8         reserved_at_4a0[0x20];
1348         u8         device_frequency_mhz[0x20];
1349         u8         device_frequency_khz[0x20];
1350
1351         u8         reserved_at_500[0x20];
1352         u8         num_of_uars_per_page[0x20];
1353
1354         u8         flex_parser_protocols[0x20];
1355
1356         u8         max_geneve_tlv_options[0x8];
1357         u8         reserved_at_568[0x3];
1358         u8         max_geneve_tlv_option_data_len[0x5];
1359         u8         reserved_at_570[0x10];
1360
1361         u8         reserved_at_580[0x33];
1362         u8         log_max_dek[0x5];
1363         u8         reserved_at_5b8[0x4];
1364         u8         mini_cqe_resp_stride_index[0x1];
1365         u8         cqe_128_always[0x1];
1366         u8         cqe_compression_128[0x1];
1367         u8         cqe_compression[0x1];
1368
1369         u8         cqe_compression_timeout[0x10];
1370         u8         cqe_compression_max_num[0x10];
1371
1372         u8         reserved_at_5e0[0x10];
1373         u8         tag_matching[0x1];
1374         u8         rndv_offload_rc[0x1];
1375         u8         rndv_offload_dc[0x1];
1376         u8         log_tag_matching_list_sz[0x5];
1377         u8         reserved_at_5f8[0x3];
1378         u8         log_max_xrq[0x5];
1379
1380         u8         affiliate_nic_vport_criteria[0x8];
1381         u8         native_port_num[0x8];
1382         u8         num_vhca_ports[0x8];
1383         u8         reserved_at_618[0x6];
1384         u8         sw_owner_id[0x1];
1385         u8         reserved_at_61f[0x1];
1386
1387         u8         max_num_of_monitor_counters[0x10];
1388         u8         num_ppcnt_monitor_counters[0x10];
1389
1390         u8         reserved_at_640[0x10];
1391         u8         num_q_monitor_counters[0x10];
1392
1393         u8         reserved_at_660[0x20];
1394
1395         u8         sf[0x1];
1396         u8         sf_set_partition[0x1];
1397         u8         reserved_at_682[0x1];
1398         u8         log_max_sf[0x5];
1399         u8         reserved_at_688[0x8];
1400         u8         log_min_sf_size[0x8];
1401         u8         max_num_sf_partitions[0x8];
1402
1403         u8         uctx_cap[0x20];
1404
1405         u8         reserved_at_6c0[0x4];
1406         u8         flex_parser_id_geneve_tlv_option_0[0x4];
1407         u8         reserved_at_6c8[0x28];
1408         u8         sf_base_id[0x10];
1409
1410         u8         reserved_at_700[0x80];
1411         u8         vhca_tunnel_commands[0x40];
1412         u8         reserved_at_7c0[0x40];
1413 };
1414
1415 enum mlx5_flow_destination_type {
1416         MLX5_FLOW_DESTINATION_TYPE_VPORT        = 0x0,
1417         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE   = 0x1,
1418         MLX5_FLOW_DESTINATION_TYPE_TIR          = 0x2,
1419
1420         MLX5_FLOW_DESTINATION_TYPE_PORT         = 0x99,
1421         MLX5_FLOW_DESTINATION_TYPE_COUNTER      = 0x100,
1422         MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
1423 };
1424
1425 enum mlx5_flow_table_miss_action {
1426         MLX5_FLOW_TABLE_MISS_ACTION_DEF,
1427         MLX5_FLOW_TABLE_MISS_ACTION_FWD,
1428         MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN,
1429 };
1430
1431 struct mlx5_ifc_dest_format_struct_bits {
1432         u8         destination_type[0x8];
1433         u8         destination_id[0x18];
1434
1435         u8         destination_eswitch_owner_vhca_id_valid[0x1];
1436         u8         packet_reformat[0x1];
1437         u8         reserved_at_22[0xe];
1438         u8         destination_eswitch_owner_vhca_id[0x10];
1439 };
1440
1441 struct mlx5_ifc_flow_counter_list_bits {
1442         u8         flow_counter_id[0x20];
1443
1444         u8         reserved_at_20[0x20];
1445 };
1446
1447 struct mlx5_ifc_extended_dest_format_bits {
1448         struct mlx5_ifc_dest_format_struct_bits destination_entry;
1449
1450         u8         packet_reformat_id[0x20];
1451
1452         u8         reserved_at_60[0x20];
1453 };
1454
1455 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1456         struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1457         struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1458         u8         reserved_at_0[0x40];
1459 };
1460
1461 struct mlx5_ifc_fte_match_param_bits {
1462         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1463
1464         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1465
1466         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
1467
1468         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
1469
1470         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
1471
1472         u8         reserved_at_a00[0x600];
1473 };
1474
1475 enum {
1476         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1477         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1478         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1479         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1480         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1481 };
1482
1483 struct mlx5_ifc_rx_hash_field_select_bits {
1484         u8         l3_prot_type[0x1];
1485         u8         l4_prot_type[0x1];
1486         u8         selected_fields[0x1e];
1487 };
1488
1489 enum {
1490         MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST  = 0x0,
1491         MLX5_WQ_WQ_TYPE_WQ_CYCLIC       = 0x1,
1492 };
1493
1494 enum {
1495         MLX5_WQ_END_PADDING_MODE_END_PAD_NONE   = 0x0,
1496         MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN  = 0x1,
1497 };
1498
1499 struct mlx5_ifc_wq_bits {
1500         u8         wq_type[0x4];
1501         u8         wq_signature[0x1];
1502         u8         end_padding_mode[0x2];
1503         u8         cd_slave[0x1];
1504         u8         reserved_at_8[0x18];
1505
1506         u8         hds_skip_first_sge[0x1];
1507         u8         log2_hds_buf_size[0x3];
1508         u8         reserved_at_24[0x7];
1509         u8         page_offset[0x5];
1510         u8         lwm[0x10];
1511
1512         u8         reserved_at_40[0x8];
1513         u8         pd[0x18];
1514
1515         u8         reserved_at_60[0x8];
1516         u8         uar_page[0x18];
1517
1518         u8         dbr_addr[0x40];
1519
1520         u8         hw_counter[0x20];
1521
1522         u8         sw_counter[0x20];
1523
1524         u8         reserved_at_100[0xc];
1525         u8         log_wq_stride[0x4];
1526         u8         reserved_at_110[0x3];
1527         u8         log_wq_pg_sz[0x5];
1528         u8         reserved_at_118[0x3];
1529         u8         log_wq_sz[0x5];
1530
1531         u8         dbr_umem_valid[0x1];
1532         u8         wq_umem_valid[0x1];
1533         u8         reserved_at_122[0x1];
1534         u8         log_hairpin_num_packets[0x5];
1535         u8         reserved_at_128[0x3];
1536         u8         log_hairpin_data_sz[0x5];
1537
1538         u8         reserved_at_130[0x4];
1539         u8         log_wqe_num_of_strides[0x4];
1540         u8         two_byte_shift_en[0x1];
1541         u8         reserved_at_139[0x4];
1542         u8         log_wqe_stride_size[0x3];
1543
1544         u8         reserved_at_140[0x4c0];
1545
1546         struct mlx5_ifc_cmd_pas_bits pas[0];
1547 };
1548
1549 struct mlx5_ifc_rq_num_bits {
1550         u8         reserved_at_0[0x8];
1551         u8         rq_num[0x18];
1552 };
1553
1554 struct mlx5_ifc_mac_address_layout_bits {
1555         u8         reserved_at_0[0x10];
1556         u8         mac_addr_47_32[0x10];
1557
1558         u8         mac_addr_31_0[0x20];
1559 };
1560
1561 struct mlx5_ifc_vlan_layout_bits {
1562         u8         reserved_at_0[0x14];
1563         u8         vlan[0x0c];
1564
1565         u8         reserved_at_20[0x20];
1566 };
1567
1568 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
1569         u8         reserved_at_0[0xa0];
1570
1571         u8         min_time_between_cnps[0x20];
1572
1573         u8         reserved_at_c0[0x12];
1574         u8         cnp_dscp[0x6];
1575         u8         reserved_at_d8[0x4];
1576         u8         cnp_prio_mode[0x1];
1577         u8         cnp_802p_prio[0x3];
1578
1579         u8         reserved_at_e0[0x720];
1580 };
1581
1582 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
1583         u8         reserved_at_0[0x60];
1584
1585         u8         reserved_at_60[0x4];
1586         u8         clamp_tgt_rate[0x1];
1587         u8         reserved_at_65[0x3];
1588         u8         clamp_tgt_rate_after_time_inc[0x1];
1589         u8         reserved_at_69[0x17];
1590
1591         u8         reserved_at_80[0x20];
1592
1593         u8         rpg_time_reset[0x20];
1594
1595         u8         rpg_byte_reset[0x20];
1596
1597         u8         rpg_threshold[0x20];
1598
1599         u8         rpg_max_rate[0x20];
1600
1601         u8         rpg_ai_rate[0x20];
1602
1603         u8         rpg_hai_rate[0x20];
1604
1605         u8         rpg_gd[0x20];
1606
1607         u8         rpg_min_dec_fac[0x20];
1608
1609         u8         rpg_min_rate[0x20];
1610
1611         u8         reserved_at_1c0[0xe0];
1612
1613         u8         rate_to_set_on_first_cnp[0x20];
1614
1615         u8         dce_tcp_g[0x20];
1616
1617         u8         dce_tcp_rtt[0x20];
1618
1619         u8         rate_reduce_monitor_period[0x20];
1620
1621         u8         reserved_at_320[0x20];
1622
1623         u8         initial_alpha_value[0x20];
1624
1625         u8         reserved_at_360[0x4a0];
1626 };
1627
1628 struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1629         u8         reserved_at_0[0x80];
1630
1631         u8         rppp_max_rps[0x20];
1632
1633         u8         rpg_time_reset[0x20];
1634
1635         u8         rpg_byte_reset[0x20];
1636
1637         u8         rpg_threshold[0x20];
1638
1639         u8         rpg_max_rate[0x20];
1640
1641         u8         rpg_ai_rate[0x20];
1642
1643         u8         rpg_hai_rate[0x20];
1644
1645         u8         rpg_gd[0x20];
1646
1647         u8         rpg_min_dec_fac[0x20];
1648
1649         u8         rpg_min_rate[0x20];
1650
1651         u8         reserved_at_1c0[0x640];
1652 };
1653
1654 enum {
1655         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE    = 0x1,
1656         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET    = 0x2,
1657         MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE  = 0x4,
1658 };
1659
1660 struct mlx5_ifc_resize_field_select_bits {
1661         u8         resize_field_select[0x20];
1662 };
1663
1664 enum {
1665         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD     = 0x1,
1666         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT  = 0x2,
1667         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI            = 0x4,
1668         MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN         = 0x8,
1669 };
1670
1671 struct mlx5_ifc_modify_field_select_bits {
1672         u8         modify_field_select[0x20];
1673 };
1674
1675 struct mlx5_ifc_field_select_r_roce_np_bits {
1676         u8         field_select_r_roce_np[0x20];
1677 };
1678
1679 struct mlx5_ifc_field_select_r_roce_rp_bits {
1680         u8         field_select_r_roce_rp[0x20];
1681 };
1682
1683 enum {
1684         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS     = 0x4,
1685         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET   = 0x8,
1686         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET   = 0x10,
1687         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD    = 0x20,
1688         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE     = 0x40,
1689         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE      = 0x80,
1690         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE     = 0x100,
1691         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD           = 0x200,
1692         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC  = 0x400,
1693         MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE     = 0x800,
1694 };
1695
1696 struct mlx5_ifc_field_select_802_1qau_rp_bits {
1697         u8         field_select_8021qaurp[0x20];
1698 };
1699
1700 struct mlx5_ifc_phys_layer_cntrs_bits {
1701         u8         time_since_last_clear_high[0x20];
1702
1703         u8         time_since_last_clear_low[0x20];
1704
1705         u8         symbol_errors_high[0x20];
1706
1707         u8         symbol_errors_low[0x20];
1708
1709         u8         sync_headers_errors_high[0x20];
1710
1711         u8         sync_headers_errors_low[0x20];
1712
1713         u8         edpl_bip_errors_lane0_high[0x20];
1714
1715         u8         edpl_bip_errors_lane0_low[0x20];
1716
1717         u8         edpl_bip_errors_lane1_high[0x20];
1718
1719         u8         edpl_bip_errors_lane1_low[0x20];
1720
1721         u8         edpl_bip_errors_lane2_high[0x20];
1722
1723         u8         edpl_bip_errors_lane2_low[0x20];
1724
1725         u8         edpl_bip_errors_lane3_high[0x20];
1726
1727         u8         edpl_bip_errors_lane3_low[0x20];
1728
1729         u8         fc_fec_corrected_blocks_lane0_high[0x20];
1730
1731         u8         fc_fec_corrected_blocks_lane0_low[0x20];
1732
1733         u8         fc_fec_corrected_blocks_lane1_high[0x20];
1734
1735         u8         fc_fec_corrected_blocks_lane1_low[0x20];
1736
1737         u8         fc_fec_corrected_blocks_lane2_high[0x20];
1738
1739         u8         fc_fec_corrected_blocks_lane2_low[0x20];
1740
1741         u8         fc_fec_corrected_blocks_lane3_high[0x20];
1742
1743         u8         fc_fec_corrected_blocks_lane3_low[0x20];
1744
1745         u8         fc_fec_uncorrectable_blocks_lane0_high[0x20];
1746
1747         u8         fc_fec_uncorrectable_blocks_lane0_low[0x20];
1748
1749         u8         fc_fec_uncorrectable_blocks_lane1_high[0x20];
1750
1751         u8         fc_fec_uncorrectable_blocks_lane1_low[0x20];
1752
1753         u8         fc_fec_uncorrectable_blocks_lane2_high[0x20];
1754
1755         u8         fc_fec_uncorrectable_blocks_lane2_low[0x20];
1756
1757         u8         fc_fec_uncorrectable_blocks_lane3_high[0x20];
1758
1759         u8         fc_fec_uncorrectable_blocks_lane3_low[0x20];
1760
1761         u8         rs_fec_corrected_blocks_high[0x20];
1762
1763         u8         rs_fec_corrected_blocks_low[0x20];
1764
1765         u8         rs_fec_uncorrectable_blocks_high[0x20];
1766
1767         u8         rs_fec_uncorrectable_blocks_low[0x20];
1768
1769         u8         rs_fec_no_errors_blocks_high[0x20];
1770
1771         u8         rs_fec_no_errors_blocks_low[0x20];
1772
1773         u8         rs_fec_single_error_blocks_high[0x20];
1774
1775         u8         rs_fec_single_error_blocks_low[0x20];
1776
1777         u8         rs_fec_corrected_symbols_total_high[0x20];
1778
1779         u8         rs_fec_corrected_symbols_total_low[0x20];
1780
1781         u8         rs_fec_corrected_symbols_lane0_high[0x20];
1782
1783         u8         rs_fec_corrected_symbols_lane0_low[0x20];
1784
1785         u8         rs_fec_corrected_symbols_lane1_high[0x20];
1786
1787         u8         rs_fec_corrected_symbols_lane1_low[0x20];
1788
1789         u8         rs_fec_corrected_symbols_lane2_high[0x20];
1790
1791         u8         rs_fec_corrected_symbols_lane2_low[0x20];
1792
1793         u8         rs_fec_corrected_symbols_lane3_high[0x20];
1794
1795         u8         rs_fec_corrected_symbols_lane3_low[0x20];
1796
1797         u8         link_down_events[0x20];
1798
1799         u8         successful_recovery_events[0x20];
1800
1801         u8         reserved_at_640[0x180];
1802 };
1803
1804 struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1805         u8         time_since_last_clear_high[0x20];
1806
1807         u8         time_since_last_clear_low[0x20];
1808
1809         u8         phy_received_bits_high[0x20];
1810
1811         u8         phy_received_bits_low[0x20];
1812
1813         u8         phy_symbol_errors_high[0x20];
1814
1815         u8         phy_symbol_errors_low[0x20];
1816
1817         u8         phy_corrected_bits_high[0x20];
1818
1819         u8         phy_corrected_bits_low[0x20];
1820
1821         u8         phy_corrected_bits_lane0_high[0x20];
1822
1823         u8         phy_corrected_bits_lane0_low[0x20];
1824
1825         u8         phy_corrected_bits_lane1_high[0x20];
1826
1827         u8         phy_corrected_bits_lane1_low[0x20];
1828
1829         u8         phy_corrected_bits_lane2_high[0x20];
1830
1831         u8         phy_corrected_bits_lane2_low[0x20];
1832
1833         u8         phy_corrected_bits_lane3_high[0x20];
1834
1835         u8         phy_corrected_bits_lane3_low[0x20];
1836
1837         u8         reserved_at_200[0x5c0];
1838 };
1839
1840 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1841         u8         symbol_error_counter[0x10];
1842
1843         u8         link_error_recovery_counter[0x8];
1844
1845         u8         link_downed_counter[0x8];
1846
1847         u8         port_rcv_errors[0x10];
1848
1849         u8         port_rcv_remote_physical_errors[0x10];
1850
1851         u8         port_rcv_switch_relay_errors[0x10];
1852
1853         u8         port_xmit_discards[0x10];
1854
1855         u8         port_xmit_constraint_errors[0x8];
1856
1857         u8         port_rcv_constraint_errors[0x8];
1858
1859         u8         reserved_at_70[0x8];
1860
1861         u8         link_overrun_errors[0x8];
1862
1863         u8         reserved_at_80[0x10];
1864
1865         u8         vl_15_dropped[0x10];
1866
1867         u8         reserved_at_a0[0x80];
1868
1869         u8         port_xmit_wait[0x20];
1870 };
1871
1872 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1873         u8         transmit_queue_high[0x20];
1874
1875         u8         transmit_queue_low[0x20];
1876
1877         u8         reserved_at_40[0x780];
1878 };
1879
1880 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1881         u8         rx_octets_high[0x20];
1882
1883         u8         rx_octets_low[0x20];
1884
1885         u8         reserved_at_40[0xc0];
1886
1887         u8         rx_frames_high[0x20];
1888
1889         u8         rx_frames_low[0x20];
1890
1891         u8         tx_octets_high[0x20];
1892
1893         u8         tx_octets_low[0x20];
1894
1895         u8         reserved_at_180[0xc0];
1896
1897         u8         tx_frames_high[0x20];
1898
1899         u8         tx_frames_low[0x20];
1900
1901         u8         rx_pause_high[0x20];
1902
1903         u8         rx_pause_low[0x20];
1904
1905         u8         rx_pause_duration_high[0x20];
1906
1907         u8         rx_pause_duration_low[0x20];
1908
1909         u8         tx_pause_high[0x20];
1910
1911         u8         tx_pause_low[0x20];
1912
1913         u8         tx_pause_duration_high[0x20];
1914
1915         u8         tx_pause_duration_low[0x20];
1916
1917         u8         rx_pause_transition_high[0x20];
1918
1919         u8         rx_pause_transition_low[0x20];
1920
1921         u8         reserved_at_3c0[0x40];
1922
1923         u8         device_stall_minor_watermark_cnt_high[0x20];
1924
1925         u8         device_stall_minor_watermark_cnt_low[0x20];
1926
1927         u8         device_stall_critical_watermark_cnt_high[0x20];
1928
1929         u8         device_stall_critical_watermark_cnt_low[0x20];
1930
1931         u8         reserved_at_480[0x340];
1932 };
1933
1934 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1935         u8         port_transmit_wait_high[0x20];
1936
1937         u8         port_transmit_wait_low[0x20];
1938
1939         u8         reserved_at_40[0x100];
1940
1941         u8         rx_buffer_almost_full_high[0x20];
1942
1943         u8         rx_buffer_almost_full_low[0x20];
1944
1945         u8         rx_buffer_full_high[0x20];
1946
1947         u8         rx_buffer_full_low[0x20];
1948
1949         u8         rx_icrc_encapsulated_high[0x20];
1950
1951         u8         rx_icrc_encapsulated_low[0x20];
1952
1953         u8         reserved_at_200[0x5c0];
1954 };
1955
1956 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1957         u8         dot3stats_alignment_errors_high[0x20];
1958
1959         u8         dot3stats_alignment_errors_low[0x20];
1960
1961         u8         dot3stats_fcs_errors_high[0x20];
1962
1963         u8         dot3stats_fcs_errors_low[0x20];
1964
1965         u8         dot3stats_single_collision_frames_high[0x20];
1966
1967         u8         dot3stats_single_collision_frames_low[0x20];
1968
1969         u8         dot3stats_multiple_collision_frames_high[0x20];
1970
1971         u8         dot3stats_multiple_collision_frames_low[0x20];
1972
1973         u8         dot3stats_sqe_test_errors_high[0x20];
1974
1975         u8         dot3stats_sqe_test_errors_low[0x20];
1976
1977         u8         dot3stats_deferred_transmissions_high[0x20];
1978
1979         u8         dot3stats_deferred_transmissions_low[0x20];
1980
1981         u8         dot3stats_late_collisions_high[0x20];
1982
1983         u8         dot3stats_late_collisions_low[0x20];
1984
1985         u8         dot3stats_excessive_collisions_high[0x20];
1986
1987         u8         dot3stats_excessive_collisions_low[0x20];
1988
1989         u8         dot3stats_internal_mac_transmit_errors_high[0x20];
1990
1991         u8         dot3stats_internal_mac_transmit_errors_low[0x20];
1992
1993         u8         dot3stats_carrier_sense_errors_high[0x20];
1994
1995         u8         dot3stats_carrier_sense_errors_low[0x20];
1996
1997         u8         dot3stats_frame_too_longs_high[0x20];
1998
1999         u8         dot3stats_frame_too_longs_low[0x20];
2000
2001         u8         dot3stats_internal_mac_receive_errors_high[0x20];
2002
2003         u8         dot3stats_internal_mac_receive_errors_low[0x20];
2004
2005         u8         dot3stats_symbol_errors_high[0x20];
2006
2007         u8         dot3stats_symbol_errors_low[0x20];
2008
2009         u8         dot3control_in_unknown_opcodes_high[0x20];
2010
2011         u8         dot3control_in_unknown_opcodes_low[0x20];
2012
2013         u8         dot3in_pause_frames_high[0x20];
2014
2015         u8         dot3in_pause_frames_low[0x20];
2016
2017         u8         dot3out_pause_frames_high[0x20];
2018
2019         u8         dot3out_pause_frames_low[0x20];
2020
2021         u8         reserved_at_400[0x3c0];
2022 };
2023
2024 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
2025         u8         ether_stats_drop_events_high[0x20];
2026
2027         u8         ether_stats_drop_events_low[0x20];
2028
2029         u8         ether_stats_octets_high[0x20];
2030
2031         u8         ether_stats_octets_low[0x20];
2032
2033         u8         ether_stats_pkts_high[0x20];
2034
2035         u8         ether_stats_pkts_low[0x20];
2036
2037         u8         ether_stats_broadcast_pkts_high[0x20];
2038
2039         u8         ether_stats_broadcast_pkts_low[0x20];
2040
2041         u8         ether_stats_multicast_pkts_high[0x20];
2042
2043         u8         ether_stats_multicast_pkts_low[0x20];
2044
2045         u8         ether_stats_crc_align_errors_high[0x20];
2046
2047         u8         ether_stats_crc_align_errors_low[0x20];
2048
2049         u8         ether_stats_undersize_pkts_high[0x20];
2050
2051         u8         ether_stats_undersize_pkts_low[0x20];
2052
2053         u8         ether_stats_oversize_pkts_high[0x20];
2054
2055         u8         ether_stats_oversize_pkts_low[0x20];
2056
2057         u8         ether_stats_fragments_high[0x20];
2058
2059         u8         ether_stats_fragments_low[0x20];
2060
2061         u8         ether_stats_jabbers_high[0x20];
2062
2063         u8         ether_stats_jabbers_low[0x20];
2064
2065         u8         ether_stats_collisions_high[0x20];
2066
2067         u8         ether_stats_collisions_low[0x20];
2068
2069         u8         ether_stats_pkts64octets_high[0x20];
2070
2071         u8         ether_stats_pkts64octets_low[0x20];
2072
2073         u8         ether_stats_pkts65to127octets_high[0x20];
2074
2075         u8         ether_stats_pkts65to127octets_low[0x20];
2076
2077         u8         ether_stats_pkts128to255octets_high[0x20];
2078
2079         u8         ether_stats_pkts128to255octets_low[0x20];
2080
2081         u8         ether_stats_pkts256to511octets_high[0x20];
2082
2083         u8         ether_stats_pkts256to511octets_low[0x20];
2084
2085         u8         ether_stats_pkts512to1023octets_high[0x20];
2086
2087         u8         ether_stats_pkts512to1023octets_low[0x20];
2088
2089         u8         ether_stats_pkts1024to1518octets_high[0x20];
2090
2091         u8         ether_stats_pkts1024to1518octets_low[0x20];
2092
2093         u8         ether_stats_pkts1519to2047octets_high[0x20];
2094
2095         u8         ether_stats_pkts1519to2047octets_low[0x20];
2096
2097         u8         ether_stats_pkts2048to4095octets_high[0x20];
2098
2099         u8         ether_stats_pkts2048to4095octets_low[0x20];
2100
2101         u8         ether_stats_pkts4096to8191octets_high[0x20];
2102
2103         u8         ether_stats_pkts4096to8191octets_low[0x20];
2104
2105         u8         ether_stats_pkts8192to10239octets_high[0x20];
2106
2107         u8         ether_stats_pkts8192to10239octets_low[0x20];
2108
2109         u8         reserved_at_540[0x280];
2110 };
2111
2112 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
2113         u8         if_in_octets_high[0x20];
2114
2115         u8         if_in_octets_low[0x20];
2116
2117         u8         if_in_ucast_pkts_high[0x20];
2118
2119         u8         if_in_ucast_pkts_low[0x20];
2120
2121         u8         if_in_discards_high[0x20];
2122
2123         u8         if_in_discards_low[0x20];
2124
2125         u8         if_in_errors_high[0x20];
2126
2127         u8         if_in_errors_low[0x20];
2128
2129         u8         if_in_unknown_protos_high[0x20];
2130
2131         u8         if_in_unknown_protos_low[0x20];
2132
2133         u8         if_out_octets_high[0x20];
2134
2135         u8         if_out_octets_low[0x20];
2136
2137         u8         if_out_ucast_pkts_high[0x20];
2138
2139         u8         if_out_ucast_pkts_low[0x20];
2140
2141         u8         if_out_discards_high[0x20];
2142
2143         u8         if_out_discards_low[0x20];
2144
2145         u8         if_out_errors_high[0x20];
2146
2147         u8         if_out_errors_low[0x20];
2148
2149         u8         if_in_multicast_pkts_high[0x20];
2150
2151         u8         if_in_multicast_pkts_low[0x20];
2152
2153         u8         if_in_broadcast_pkts_high[0x20];
2154
2155         u8         if_in_broadcast_pkts_low[0x20];
2156
2157         u8         if_out_multicast_pkts_high[0x20];
2158
2159         u8         if_out_multicast_pkts_low[0x20];
2160
2161         u8         if_out_broadcast_pkts_high[0x20];
2162
2163         u8         if_out_broadcast_pkts_low[0x20];
2164
2165         u8         reserved_at_340[0x480];
2166 };
2167
2168 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
2169         u8         a_frames_transmitted_ok_high[0x20];
2170
2171         u8         a_frames_transmitted_ok_low[0x20];
2172
2173         u8         a_frames_received_ok_high[0x20];
2174
2175         u8         a_frames_received_ok_low[0x20];
2176
2177         u8         a_frame_check_sequence_errors_high[0x20];
2178
2179         u8         a_frame_check_sequence_errors_low[0x20];
2180
2181         u8         a_alignment_errors_high[0x20];
2182
2183         u8         a_alignment_errors_low[0x20];
2184
2185         u8         a_octets_transmitted_ok_high[0x20];
2186
2187         u8         a_octets_transmitted_ok_low[0x20];
2188
2189         u8         a_octets_received_ok_high[0x20];
2190
2191         u8         a_octets_received_ok_low[0x20];
2192
2193         u8         a_multicast_frames_xmitted_ok_high[0x20];
2194
2195         u8         a_multicast_frames_xmitted_ok_low[0x20];
2196
2197         u8         a_broadcast_frames_xmitted_ok_high[0x20];
2198
2199         u8         a_broadcast_frames_xmitted_ok_low[0x20];
2200
2201         u8         a_multicast_frames_received_ok_high[0x20];
2202
2203         u8         a_multicast_frames_received_ok_low[0x20];
2204
2205         u8         a_broadcast_frames_received_ok_high[0x20];
2206
2207         u8         a_broadcast_frames_received_ok_low[0x20];
2208
2209         u8         a_in_range_length_errors_high[0x20];
2210
2211         u8         a_in_range_length_errors_low[0x20];
2212
2213         u8         a_out_of_range_length_field_high[0x20];
2214
2215         u8         a_out_of_range_length_field_low[0x20];
2216
2217         u8         a_frame_too_long_errors_high[0x20];
2218
2219         u8         a_frame_too_long_errors_low[0x20];
2220
2221         u8         a_symbol_error_during_carrier_high[0x20];
2222
2223         u8         a_symbol_error_during_carrier_low[0x20];
2224
2225         u8         a_mac_control_frames_transmitted_high[0x20];
2226
2227         u8         a_mac_control_frames_transmitted_low[0x20];
2228
2229         u8         a_mac_control_frames_received_high[0x20];
2230
2231         u8         a_mac_control_frames_received_low[0x20];
2232
2233         u8         a_unsupported_opcodes_received_high[0x20];
2234
2235         u8         a_unsupported_opcodes_received_low[0x20];
2236
2237         u8         a_pause_mac_ctrl_frames_received_high[0x20];
2238
2239         u8         a_pause_mac_ctrl_frames_received_low[0x20];
2240
2241         u8         a_pause_mac_ctrl_frames_transmitted_high[0x20];
2242
2243         u8         a_pause_mac_ctrl_frames_transmitted_low[0x20];
2244
2245         u8         reserved_at_4c0[0x300];
2246 };
2247
2248 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
2249         u8         life_time_counter_high[0x20];
2250
2251         u8         life_time_counter_low[0x20];
2252
2253         u8         rx_errors[0x20];
2254
2255         u8         tx_errors[0x20];
2256
2257         u8         l0_to_recovery_eieos[0x20];
2258
2259         u8         l0_to_recovery_ts[0x20];
2260
2261         u8         l0_to_recovery_framing[0x20];
2262
2263         u8         l0_to_recovery_retrain[0x20];
2264
2265         u8         crc_error_dllp[0x20];
2266
2267         u8         crc_error_tlp[0x20];
2268
2269         u8         tx_overflow_buffer_pkt_high[0x20];
2270
2271         u8         tx_overflow_buffer_pkt_low[0x20];
2272
2273         u8         outbound_stalled_reads[0x20];
2274
2275         u8         outbound_stalled_writes[0x20];
2276
2277         u8         outbound_stalled_reads_events[0x20];
2278
2279         u8         outbound_stalled_writes_events[0x20];
2280
2281         u8         reserved_at_200[0x5c0];
2282 };
2283
2284 struct mlx5_ifc_cmd_inter_comp_event_bits {
2285         u8         command_completion_vector[0x20];
2286
2287         u8         reserved_at_20[0xc0];
2288 };
2289
2290 struct mlx5_ifc_stall_vl_event_bits {
2291         u8         reserved_at_0[0x18];
2292         u8         port_num[0x1];
2293         u8         reserved_at_19[0x3];
2294         u8         vl[0x4];
2295
2296         u8         reserved_at_20[0xa0];
2297 };
2298
2299 struct mlx5_ifc_db_bf_congestion_event_bits {
2300         u8         event_subtype[0x8];
2301         u8         reserved_at_8[0x8];
2302         u8         congestion_level[0x8];
2303         u8         reserved_at_18[0x8];
2304
2305         u8         reserved_at_20[0xa0];
2306 };
2307
2308 struct mlx5_ifc_gpio_event_bits {
2309         u8         reserved_at_0[0x60];
2310
2311         u8         gpio_event_hi[0x20];
2312
2313         u8         gpio_event_lo[0x20];
2314
2315         u8         reserved_at_a0[0x40];
2316 };
2317
2318 struct mlx5_ifc_port_state_change_event_bits {
2319         u8         reserved_at_0[0x40];
2320
2321         u8         port_num[0x4];
2322         u8         reserved_at_44[0x1c];
2323
2324         u8         reserved_at_60[0x80];
2325 };
2326
2327 struct mlx5_ifc_dropped_packet_logged_bits {
2328         u8         reserved_at_0[0xe0];
2329 };
2330
2331 enum {
2332         MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,
2333         MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,
2334 };
2335
2336 struct mlx5_ifc_cq_error_bits {
2337         u8         reserved_at_0[0x8];
2338         u8         cqn[0x18];
2339
2340         u8         reserved_at_20[0x20];
2341
2342         u8         reserved_at_40[0x18];
2343         u8         syndrome[0x8];
2344
2345         u8         reserved_at_60[0x80];
2346 };
2347
2348 struct mlx5_ifc_rdma_page_fault_event_bits {
2349         u8         bytes_committed[0x20];
2350
2351         u8         r_key[0x20];
2352
2353         u8         reserved_at_40[0x10];
2354         u8         packet_len[0x10];
2355
2356         u8         rdma_op_len[0x20];
2357
2358         u8         rdma_va[0x40];
2359
2360         u8         reserved_at_c0[0x5];
2361         u8         rdma[0x1];
2362         u8         write[0x1];
2363         u8         requestor[0x1];
2364         u8         qp_number[0x18];
2365 };
2366
2367 struct mlx5_ifc_wqe_associated_page_fault_event_bits {
2368         u8         bytes_committed[0x20];
2369
2370         u8         reserved_at_20[0x10];
2371         u8         wqe_index[0x10];
2372
2373         u8         reserved_at_40[0x10];
2374         u8         len[0x10];
2375
2376         u8         reserved_at_60[0x60];
2377
2378         u8         reserved_at_c0[0x5];
2379         u8         rdma[0x1];
2380         u8         write_read[0x1];
2381         u8         requestor[0x1];
2382         u8         qpn[0x18];
2383 };
2384
2385 struct mlx5_ifc_qp_events_bits {
2386         u8         reserved_at_0[0xa0];
2387
2388         u8         type[0x8];
2389         u8         reserved_at_a8[0x18];
2390
2391         u8         reserved_at_c0[0x8];
2392         u8         qpn_rqn_sqn[0x18];
2393 };
2394
2395 struct mlx5_ifc_dct_events_bits {
2396         u8         reserved_at_0[0xc0];
2397
2398         u8         reserved_at_c0[0x8];
2399         u8         dct_number[0x18];
2400 };
2401
2402 struct mlx5_ifc_comp_event_bits {
2403         u8         reserved_at_0[0xc0];
2404
2405         u8         reserved_at_c0[0x8];
2406         u8         cq_number[0x18];
2407 };
2408
2409 enum {
2410         MLX5_QPC_STATE_RST        = 0x0,
2411         MLX5_QPC_STATE_INIT       = 0x1,
2412         MLX5_QPC_STATE_RTR        = 0x2,
2413         MLX5_QPC_STATE_RTS        = 0x3,
2414         MLX5_QPC_STATE_SQER       = 0x4,
2415         MLX5_QPC_STATE_ERR        = 0x6,
2416         MLX5_QPC_STATE_SQD        = 0x7,
2417         MLX5_QPC_STATE_SUSPENDED  = 0x9,
2418 };
2419
2420 enum {
2421         MLX5_QPC_ST_RC            = 0x0,
2422         MLX5_QPC_ST_UC            = 0x1,
2423         MLX5_QPC_ST_UD            = 0x2,
2424         MLX5_QPC_ST_XRC           = 0x3,
2425         MLX5_QPC_ST_DCI           = 0x5,
2426         MLX5_QPC_ST_QP0           = 0x7,
2427         MLX5_QPC_ST_QP1           = 0x8,
2428         MLX5_QPC_ST_RAW_DATAGRAM  = 0x9,
2429         MLX5_QPC_ST_REG_UMR       = 0xc,
2430 };
2431
2432 enum {
2433         MLX5_QPC_PM_STATE_ARMED     = 0x0,
2434         MLX5_QPC_PM_STATE_REARM     = 0x1,
2435         MLX5_QPC_PM_STATE_RESERVED  = 0x2,
2436         MLX5_QPC_PM_STATE_MIGRATED  = 0x3,
2437 };
2438
2439 enum {
2440         MLX5_QPC_OFFLOAD_TYPE_RNDV  = 0x1,
2441 };
2442
2443 enum {
2444         MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS                = 0x0,
2445         MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT  = 0x1,
2446 };
2447
2448 enum {
2449         MLX5_QPC_MTU_256_BYTES        = 0x1,
2450         MLX5_QPC_MTU_512_BYTES        = 0x2,
2451         MLX5_QPC_MTU_1K_BYTES         = 0x3,
2452         MLX5_QPC_MTU_2K_BYTES         = 0x4,
2453         MLX5_QPC_MTU_4K_BYTES         = 0x5,
2454         MLX5_QPC_MTU_RAW_ETHERNET_QP  = 0x7,
2455 };
2456
2457 enum {
2458         MLX5_QPC_ATOMIC_MODE_IB_SPEC     = 0x1,
2459         MLX5_QPC_ATOMIC_MODE_ONLY_8B     = 0x2,
2460         MLX5_QPC_ATOMIC_MODE_UP_TO_8B    = 0x3,
2461         MLX5_QPC_ATOMIC_MODE_UP_TO_16B   = 0x4,
2462         MLX5_QPC_ATOMIC_MODE_UP_TO_32B   = 0x5,
2463         MLX5_QPC_ATOMIC_MODE_UP_TO_64B   = 0x6,
2464         MLX5_QPC_ATOMIC_MODE_UP_TO_128B  = 0x7,
2465         MLX5_QPC_ATOMIC_MODE_UP_TO_256B  = 0x8,
2466 };
2467
2468 enum {
2469         MLX5_QPC_CS_REQ_DISABLE    = 0x0,
2470         MLX5_QPC_CS_REQ_UP_TO_32B  = 0x11,
2471         MLX5_QPC_CS_REQ_UP_TO_64B  = 0x22,
2472 };
2473
2474 enum {
2475         MLX5_QPC_CS_RES_DISABLE    = 0x0,
2476         MLX5_QPC_CS_RES_UP_TO_32B  = 0x1,
2477         MLX5_QPC_CS_RES_UP_TO_64B  = 0x2,
2478 };
2479
2480 struct mlx5_ifc_qpc_bits {
2481         u8         state[0x4];
2482         u8         lag_tx_port_affinity[0x4];
2483         u8         st[0x8];
2484         u8         reserved_at_10[0x3];
2485         u8         pm_state[0x2];
2486         u8         reserved_at_15[0x1];
2487         u8         req_e2e_credit_mode[0x2];
2488         u8         offload_type[0x4];
2489         u8         end_padding_mode[0x2];
2490         u8         reserved_at_1e[0x2];
2491
2492         u8         wq_signature[0x1];
2493         u8         block_lb_mc[0x1];
2494         u8         atomic_like_write_en[0x1];
2495         u8         latency_sensitive[0x1];
2496         u8         reserved_at_24[0x1];
2497         u8         drain_sigerr[0x1];
2498         u8         reserved_at_26[0x2];
2499         u8         pd[0x18];
2500
2501         u8         mtu[0x3];
2502         u8         log_msg_max[0x5];
2503         u8         reserved_at_48[0x1];
2504         u8         log_rq_size[0x4];
2505         u8         log_rq_stride[0x3];
2506         u8         no_sq[0x1];
2507         u8         log_sq_size[0x4];
2508         u8         reserved_at_55[0x6];
2509         u8         rlky[0x1];
2510         u8         ulp_stateless_offload_mode[0x4];
2511
2512         u8         counter_set_id[0x8];
2513         u8         uar_page[0x18];
2514
2515         u8         reserved_at_80[0x8];
2516         u8         user_index[0x18];
2517
2518         u8         reserved_at_a0[0x3];
2519         u8         log_page_size[0x5];
2520         u8         remote_qpn[0x18];
2521
2522         struct mlx5_ifc_ads_bits primary_address_path;
2523
2524         struct mlx5_ifc_ads_bits secondary_address_path;
2525
2526         u8         log_ack_req_freq[0x4];
2527         u8         reserved_at_384[0x4];
2528         u8         log_sra_max[0x3];
2529         u8         reserved_at_38b[0x2];
2530         u8         retry_count[0x3];
2531         u8         rnr_retry[0x3];
2532         u8         reserved_at_393[0x1];
2533         u8         fre[0x1];
2534         u8         cur_rnr_retry[0x3];
2535         u8         cur_retry_count[0x3];
2536         u8         reserved_at_39b[0x5];
2537
2538         u8         reserved_at_3a0[0x20];
2539
2540         u8         reserved_at_3c0[0x8];
2541         u8         next_send_psn[0x18];
2542
2543         u8         reserved_at_3e0[0x8];
2544         u8         cqn_snd[0x18];
2545
2546         u8         reserved_at_400[0x8];
2547         u8         deth_sqpn[0x18];
2548
2549         u8         reserved_at_420[0x20];
2550
2551         u8         reserved_at_440[0x8];
2552         u8         last_acked_psn[0x18];
2553
2554         u8         reserved_at_460[0x8];
2555         u8         ssn[0x18];
2556
2557         u8         reserved_at_480[0x8];
2558         u8         log_rra_max[0x3];
2559         u8         reserved_at_48b[0x1];
2560         u8         atomic_mode[0x4];
2561         u8         rre[0x1];
2562         u8         rwe[0x1];
2563         u8         rae[0x1];
2564         u8         reserved_at_493[0x1];
2565         u8         page_offset[0x6];
2566         u8         reserved_at_49a[0x3];
2567         u8         cd_slave_receive[0x1];
2568         u8         cd_slave_send[0x1];
2569         u8         cd_master[0x1];
2570
2571         u8         reserved_at_4a0[0x3];
2572         u8         min_rnr_nak[0x5];
2573         u8         next_rcv_psn[0x18];
2574
2575         u8         reserved_at_4c0[0x8];
2576         u8         xrcd[0x18];
2577
2578         u8         reserved_at_4e0[0x8];
2579         u8         cqn_rcv[0x18];
2580
2581         u8         dbr_addr[0x40];
2582
2583         u8         q_key[0x20];
2584
2585         u8         reserved_at_560[0x5];
2586         u8         rq_type[0x3];
2587         u8         srqn_rmpn_xrqn[0x18];
2588
2589         u8         reserved_at_580[0x8];
2590         u8         rmsn[0x18];
2591
2592         u8         hw_sq_wqebb_counter[0x10];
2593         u8         sw_sq_wqebb_counter[0x10];
2594
2595         u8         hw_rq_counter[0x20];
2596
2597         u8         sw_rq_counter[0x20];
2598
2599         u8         reserved_at_600[0x20];
2600
2601         u8         reserved_at_620[0xf];
2602         u8         cgs[0x1];
2603         u8         cs_req[0x8];
2604         u8         cs_res[0x8];
2605
2606         u8         dc_access_key[0x40];
2607
2608         u8         reserved_at_680[0x3];
2609         u8         dbr_umem_valid[0x1];
2610
2611         u8         reserved_at_684[0xbc];
2612 };
2613
2614 struct mlx5_ifc_roce_addr_layout_bits {
2615         u8         source_l3_address[16][0x8];
2616
2617         u8         reserved_at_80[0x3];
2618         u8         vlan_valid[0x1];
2619         u8         vlan_id[0xc];
2620         u8         source_mac_47_32[0x10];
2621
2622         u8         source_mac_31_0[0x20];
2623
2624         u8         reserved_at_c0[0x14];
2625         u8         roce_l3_type[0x4];
2626         u8         roce_version[0x8];
2627
2628         u8         reserved_at_e0[0x20];
2629 };
2630
2631 union mlx5_ifc_hca_cap_union_bits {
2632         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2633         struct mlx5_ifc_odp_cap_bits odp_cap;
2634         struct mlx5_ifc_atomic_caps_bits atomic_caps;
2635         struct mlx5_ifc_roce_cap_bits roce_cap;
2636         struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2637         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
2638         struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
2639         struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
2640         struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
2641         struct mlx5_ifc_qos_cap_bits qos_cap;
2642         struct mlx5_ifc_debug_cap_bits debug_cap;
2643         struct mlx5_ifc_fpga_cap_bits fpga_cap;
2644         struct mlx5_ifc_tls_cap_bits tls_cap;
2645         u8         reserved_at_0[0x8000];
2646 };
2647
2648 enum {
2649         MLX5_FLOW_CONTEXT_ACTION_ALLOW     = 0x1,
2650         MLX5_FLOW_CONTEXT_ACTION_DROP      = 0x2,
2651         MLX5_FLOW_CONTEXT_ACTION_FWD_DEST  = 0x4,
2652         MLX5_FLOW_CONTEXT_ACTION_COUNT     = 0x8,
2653         MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
2654         MLX5_FLOW_CONTEXT_ACTION_DECAP     = 0x20,
2655         MLX5_FLOW_CONTEXT_ACTION_MOD_HDR   = 0x40,
2656         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP  = 0x80,
2657         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
2658         MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2  = 0x400,
2659         MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
2660 };
2661
2662 enum {
2663         MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT         = 0x0,
2664         MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK            = 0x1,
2665         MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT       = 0x2,
2666 };
2667
2668 struct mlx5_ifc_vlan_bits {
2669         u8         ethtype[0x10];
2670         u8         prio[0x3];
2671         u8         cfi[0x1];
2672         u8         vid[0xc];
2673 };
2674
2675 struct mlx5_ifc_flow_context_bits {
2676         struct mlx5_ifc_vlan_bits push_vlan;
2677
2678         u8         group_id[0x20];
2679
2680         u8         reserved_at_40[0x8];
2681         u8         flow_tag[0x18];
2682
2683         u8         reserved_at_60[0x10];
2684         u8         action[0x10];
2685
2686         u8         extended_destination[0x1];
2687         u8         reserved_at_81[0x1];
2688         u8         flow_source[0x2];
2689         u8         reserved_at_84[0x4];
2690         u8         destination_list_size[0x18];
2691
2692         u8         reserved_at_a0[0x8];
2693         u8         flow_counter_list_size[0x18];
2694
2695         u8         packet_reformat_id[0x20];
2696
2697         u8         modify_header_id[0x20];
2698
2699         struct mlx5_ifc_vlan_bits push_vlan_2;
2700
2701         u8         reserved_at_120[0xe0];
2702
2703         struct mlx5_ifc_fte_match_param_bits match_value;
2704
2705         u8         reserved_at_1200[0x600];
2706
2707         union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
2708 };
2709
2710 enum {
2711         MLX5_XRC_SRQC_STATE_GOOD   = 0x0,
2712         MLX5_XRC_SRQC_STATE_ERROR  = 0x1,
2713 };
2714
2715 struct mlx5_ifc_xrc_srqc_bits {
2716         u8         state[0x4];
2717         u8         log_xrc_srq_size[0x4];
2718         u8         reserved_at_8[0x18];
2719
2720         u8         wq_signature[0x1];
2721         u8         cont_srq[0x1];
2722         u8         reserved_at_22[0x1];
2723         u8         rlky[0x1];
2724         u8         basic_cyclic_rcv_wqe[0x1];
2725         u8         log_rq_stride[0x3];
2726         u8         xrcd[0x18];
2727
2728         u8         page_offset[0x6];
2729         u8         reserved_at_46[0x1];
2730         u8         dbr_umem_valid[0x1];
2731         u8         cqn[0x18];
2732
2733         u8         reserved_at_60[0x20];
2734
2735         u8         user_index_equal_xrc_srqn[0x1];
2736         u8         reserved_at_81[0x1];
2737         u8         log_page_size[0x6];
2738         u8         user_index[0x18];
2739
2740         u8         reserved_at_a0[0x20];
2741
2742         u8         reserved_at_c0[0x8];
2743         u8         pd[0x18];
2744
2745         u8         lwm[0x10];
2746         u8         wqe_cnt[0x10];
2747
2748         u8         reserved_at_100[0x40];
2749
2750         u8         db_record_addr_h[0x20];
2751
2752         u8         db_record_addr_l[0x1e];
2753         u8         reserved_at_17e[0x2];
2754
2755         u8         reserved_at_180[0x80];
2756 };
2757
2758 struct mlx5_ifc_vnic_diagnostic_statistics_bits {
2759         u8         counter_error_queues[0x20];
2760
2761         u8         total_error_queues[0x20];
2762
2763         u8         send_queue_priority_update_flow[0x20];
2764
2765         u8         reserved_at_60[0x20];
2766
2767         u8         nic_receive_steering_discard[0x40];
2768
2769         u8         receive_discard_vport_down[0x40];
2770
2771         u8         transmit_discard_vport_down[0x40];
2772
2773         u8         reserved_at_140[0xec0];
2774 };
2775
2776 struct mlx5_ifc_traffic_counter_bits {
2777         u8         packets[0x40];
2778
2779         u8         octets[0x40];
2780 };
2781
2782 struct mlx5_ifc_tisc_bits {
2783         u8         strict_lag_tx_port_affinity[0x1];
2784         u8         tls_en[0x1];
2785         u8         reserved_at_2[0x2];
2786         u8         lag_tx_port_affinity[0x04];
2787
2788         u8         reserved_at_8[0x4];
2789         u8         prio[0x4];
2790         u8         reserved_at_10[0x10];
2791
2792         u8         reserved_at_20[0x100];
2793
2794         u8         reserved_at_120[0x8];
2795         u8         transport_domain[0x18];
2796
2797         u8         reserved_at_140[0x8];
2798         u8         underlay_qpn[0x18];
2799
2800         u8         reserved_at_160[0x8];
2801         u8         pd[0x18];
2802
2803         u8         reserved_at_180[0x380];
2804 };
2805
2806 enum {
2807         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2808         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2809 };
2810
2811 enum {
2812         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2813         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2814 };
2815
2816 enum {
2817         MLX5_RX_HASH_FN_NONE           = 0x0,
2818         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2819         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2820 };
2821
2822 enum {
2823         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2824         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2825 };
2826
2827 struct mlx5_ifc_tirc_bits {
2828         u8         reserved_at_0[0x20];
2829
2830         u8         disp_type[0x4];
2831         u8         reserved_at_24[0x1c];
2832
2833         u8         reserved_at_40[0x40];
2834
2835         u8         reserved_at_80[0x4];
2836         u8         lro_timeout_period_usecs[0x10];
2837         u8         lro_enable_mask[0x4];
2838         u8         lro_max_ip_payload_size[0x8];
2839
2840         u8         reserved_at_a0[0x40];
2841
2842         u8         reserved_at_e0[0x8];
2843         u8         inline_rqn[0x18];
2844
2845         u8         rx_hash_symmetric[0x1];
2846         u8         reserved_at_101[0x1];
2847         u8         tunneled_offload_en[0x1];
2848         u8         reserved_at_103[0x5];
2849         u8         indirect_table[0x18];
2850
2851         u8         rx_hash_fn[0x4];
2852         u8         reserved_at_124[0x2];
2853         u8         self_lb_block[0x2];
2854         u8         transport_domain[0x18];
2855
2856         u8         rx_hash_toeplitz_key[10][0x20];
2857
2858         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2859
2860         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2861
2862         u8         reserved_at_2c0[0x4c0];
2863 };
2864
2865 enum {
2866         MLX5_SRQC_STATE_GOOD   = 0x0,
2867         MLX5_SRQC_STATE_ERROR  = 0x1,
2868 };
2869
2870 struct mlx5_ifc_srqc_bits {
2871         u8         state[0x4];
2872         u8         log_srq_size[0x4];
2873         u8         reserved_at_8[0x18];
2874
2875         u8         wq_signature[0x1];
2876         u8         cont_srq[0x1];
2877         u8         reserved_at_22[0x1];
2878         u8         rlky[0x1];
2879         u8         reserved_at_24[0x1];
2880         u8         log_rq_stride[0x3];
2881         u8         xrcd[0x18];
2882
2883         u8         page_offset[0x6];
2884         u8         reserved_at_46[0x2];
2885         u8         cqn[0x18];
2886
2887         u8         reserved_at_60[0x20];
2888
2889         u8         reserved_at_80[0x2];
2890         u8         log_page_size[0x6];
2891         u8         reserved_at_88[0x18];
2892
2893         u8         reserved_at_a0[0x20];
2894
2895         u8         reserved_at_c0[0x8];
2896         u8         pd[0x18];
2897
2898         u8         lwm[0x10];
2899         u8         wqe_cnt[0x10];
2900
2901         u8         reserved_at_100[0x40];
2902
2903         u8         dbr_addr[0x40];
2904
2905         u8         reserved_at_180[0x80];
2906 };
2907
2908 enum {
2909         MLX5_SQC_STATE_RST  = 0x0,
2910         MLX5_SQC_STATE_RDY  = 0x1,
2911         MLX5_SQC_STATE_ERR  = 0x3,
2912 };
2913
2914 struct mlx5_ifc_sqc_bits {
2915         u8         rlky[0x1];
2916         u8         cd_master[0x1];
2917         u8         fre[0x1];
2918         u8         flush_in_error_en[0x1];
2919         u8         allow_multi_pkt_send_wqe[0x1];
2920         u8         min_wqe_inline_mode[0x3];
2921         u8         state[0x4];
2922         u8         reg_umr[0x1];
2923         u8         allow_swp[0x1];
2924         u8         hairpin[0x1];
2925         u8         reserved_at_f[0x11];
2926
2927         u8         reserved_at_20[0x8];
2928         u8         user_index[0x18];
2929
2930         u8         reserved_at_40[0x8];
2931         u8         cqn[0x18];
2932
2933         u8         reserved_at_60[0x8];
2934         u8         hairpin_peer_rq[0x18];
2935
2936         u8         reserved_at_80[0x10];
2937         u8         hairpin_peer_vhca[0x10];
2938
2939         u8         reserved_at_a0[0x50];
2940
2941         u8         packet_pacing_rate_limit_index[0x10];
2942         u8         tis_lst_sz[0x10];
2943         u8         reserved_at_110[0x10];
2944
2945         u8         reserved_at_120[0x40];
2946
2947         u8         reserved_at_160[0x8];
2948         u8         tis_num_0[0x18];
2949
2950         struct mlx5_ifc_wq_bits wq;
2951 };
2952
2953 enum {
2954         SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2955         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2956         SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2957         SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2958 };
2959
2960 enum {
2961         ELEMENT_TYPE_CAP_MASK_TASR              = 1 << 0,
2962         ELEMENT_TYPE_CAP_MASK_VPORT             = 1 << 1,
2963         ELEMENT_TYPE_CAP_MASK_VPORT_TC          = 1 << 2,
2964         ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC     = 1 << 3,
2965 };
2966
2967 struct mlx5_ifc_scheduling_context_bits {
2968         u8         element_type[0x8];
2969         u8         reserved_at_8[0x18];
2970
2971         u8         element_attributes[0x20];
2972
2973         u8         parent_element_id[0x20];
2974
2975         u8         reserved_at_60[0x40];
2976
2977         u8         bw_share[0x20];
2978
2979         u8         max_average_bw[0x20];
2980
2981         u8         reserved_at_e0[0x120];
2982 };
2983
2984 struct mlx5_ifc_rqtc_bits {
2985         u8         reserved_at_0[0xa0];
2986
2987         u8         reserved_at_a0[0x10];
2988         u8         rqt_max_size[0x10];
2989
2990         u8         reserved_at_c0[0x10];
2991         u8         rqt_actual_size[0x10];
2992
2993         u8         reserved_at_e0[0x6a0];
2994
2995         struct mlx5_ifc_rq_num_bits rq_num[0];
2996 };
2997
2998 enum {
2999         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
3000         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
3001 };
3002
3003 enum {
3004         MLX5_RQC_STATE_RST  = 0x0,
3005         MLX5_RQC_STATE_RDY  = 0x1,
3006         MLX5_RQC_STATE_ERR  = 0x3,
3007 };
3008
3009 struct mlx5_ifc_rqc_bits {
3010         u8         rlky[0x1];
3011         u8         delay_drop_en[0x1];
3012         u8         scatter_fcs[0x1];
3013         u8         vsd[0x1];
3014         u8         mem_rq_type[0x4];
3015         u8         state[0x4];
3016         u8         reserved_at_c[0x1];
3017         u8         flush_in_error_en[0x1];
3018         u8         hairpin[0x1];
3019         u8         reserved_at_f[0x11];
3020
3021         u8         reserved_at_20[0x8];
3022         u8         user_index[0x18];
3023
3024         u8         reserved_at_40[0x8];
3025         u8         cqn[0x18];
3026
3027         u8         counter_set_id[0x8];
3028         u8         reserved_at_68[0x18];
3029
3030         u8         reserved_at_80[0x8];
3031         u8         rmpn[0x18];
3032
3033         u8         reserved_at_a0[0x8];
3034         u8         hairpin_peer_sq[0x18];
3035
3036         u8         reserved_at_c0[0x10];
3037         u8         hairpin_peer_vhca[0x10];
3038
3039         u8         reserved_at_e0[0xa0];
3040
3041         struct mlx5_ifc_wq_bits wq;
3042 };
3043
3044 enum {
3045         MLX5_RMPC_STATE_RDY  = 0x1,
3046         MLX5_RMPC_STATE_ERR  = 0x3,
3047 };
3048
3049 struct mlx5_ifc_rmpc_bits {
3050         u8         reserved_at_0[0x8];
3051         u8         state[0x4];
3052         u8         reserved_at_c[0x14];
3053
3054         u8         basic_cyclic_rcv_wqe[0x1];
3055         u8         reserved_at_21[0x1f];
3056
3057         u8         reserved_at_40[0x140];
3058
3059         struct mlx5_ifc_wq_bits wq;
3060 };
3061
3062 struct mlx5_ifc_nic_vport_context_bits {
3063         u8         reserved_at_0[0x5];
3064         u8         min_wqe_inline_mode[0x3];
3065         u8         reserved_at_8[0x15];
3066         u8         disable_mc_local_lb[0x1];
3067         u8         disable_uc_local_lb[0x1];
3068         u8         roce_en[0x1];
3069
3070         u8         arm_change_event[0x1];
3071         u8         reserved_at_21[0x1a];
3072         u8         event_on_mtu[0x1];
3073         u8         event_on_promisc_change[0x1];
3074         u8         event_on_vlan_change[0x1];
3075         u8         event_on_mc_address_change[0x1];
3076         u8         event_on_uc_address_change[0x1];
3077
3078         u8         reserved_at_40[0xc];
3079
3080         u8         affiliation_criteria[0x4];
3081         u8         affiliated_vhca_id[0x10];
3082
3083         u8         reserved_at_60[0xd0];
3084
3085         u8         mtu[0x10];
3086
3087         u8         system_image_guid[0x40];
3088         u8         port_guid[0x40];
3089         u8         node_guid[0x40];
3090
3091         u8         reserved_at_200[0x140];
3092         u8         qkey_violation_counter[0x10];
3093         u8         reserved_at_350[0x430];
3094
3095         u8         promisc_uc[0x1];
3096         u8         promisc_mc[0x1];
3097         u8         promisc_all[0x1];
3098         u8         reserved_at_783[0x2];
3099         u8         allowed_list_type[0x3];
3100         u8         reserved_at_788[0xc];
3101         u8         allowed_list_size[0xc];
3102
3103         struct mlx5_ifc_mac_address_layout_bits permanent_address;
3104
3105         u8         reserved_at_7e0[0x20];
3106
3107         u8         current_uc_mac_address[0][0x40];
3108 };
3109
3110 enum {
3111         MLX5_MKC_ACCESS_MODE_PA    = 0x0,
3112         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
3113         MLX5_MKC_ACCESS_MODE_KLMS  = 0x2,
3114         MLX5_MKC_ACCESS_MODE_KSM   = 0x3,
3115         MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4,
3116         MLX5_MKC_ACCESS_MODE_MEMIC = 0x5,
3117 };
3118
3119 struct mlx5_ifc_mkc_bits {
3120         u8         reserved_at_0[0x1];
3121         u8         free[0x1];
3122         u8         reserved_at_2[0x1];
3123         u8         access_mode_4_2[0x3];
3124         u8         reserved_at_6[0x7];
3125         u8         relaxed_ordering_write[0x1];
3126         u8         reserved_at_e[0x1];
3127         u8         small_fence_on_rdma_read_response[0x1];
3128         u8         umr_en[0x1];
3129         u8         a[0x1];
3130         u8         rw[0x1];
3131         u8         rr[0x1];
3132         u8         lw[0x1];
3133         u8         lr[0x1];
3134         u8         access_mode_1_0[0x2];
3135         u8         reserved_at_18[0x8];
3136
3137         u8         qpn[0x18];
3138         u8         mkey_7_0[0x8];
3139
3140         u8         reserved_at_40[0x20];
3141
3142         u8         length64[0x1];
3143         u8         bsf_en[0x1];
3144         u8         sync_umr[0x1];
3145         u8         reserved_at_63[0x2];
3146         u8         expected_sigerr_count[0x1];
3147         u8         reserved_at_66[0x1];
3148         u8         en_rinval[0x1];
3149         u8         pd[0x18];
3150
3151         u8         start_addr[0x40];
3152
3153         u8         len[0x40];
3154
3155         u8         bsf_octword_size[0x20];
3156
3157         u8         reserved_at_120[0x80];
3158
3159         u8         translations_octword_size[0x20];
3160
3161         u8         reserved_at_1c0[0x1b];
3162         u8         log_page_size[0x5];
3163
3164         u8         reserved_at_1e0[0x20];
3165 };
3166
3167 struct mlx5_ifc_pkey_bits {
3168         u8         reserved_at_0[0x10];
3169         u8         pkey[0x10];
3170 };
3171
3172 struct mlx5_ifc_array128_auto_bits {
3173         u8         array128_auto[16][0x8];
3174 };
3175
3176 struct mlx5_ifc_hca_vport_context_bits {
3177         u8         field_select[0x20];
3178
3179         u8         reserved_at_20[0xe0];
3180
3181         u8         sm_virt_aware[0x1];
3182         u8         has_smi[0x1];
3183         u8         has_raw[0x1];
3184         u8         grh_required[0x1];
3185         u8         reserved_at_104[0xc];
3186         u8         port_physical_state[0x4];
3187         u8         vport_state_policy[0x4];
3188         u8         port_state[0x4];
3189         u8         vport_state[0x4];
3190
3191         u8         reserved_at_120[0x20];
3192
3193         u8         system_image_guid[0x40];
3194
3195         u8         port_guid[0x40];
3196
3197         u8         node_guid[0x40];
3198
3199         u8         cap_mask1[0x20];
3200
3201         u8         cap_mask1_field_select[0x20];
3202
3203         u8         cap_mask2[0x20];
3204
3205         u8         cap_mask2_field_select[0x20];
3206
3207         u8         reserved_at_280[0x80];
3208
3209         u8         lid[0x10];
3210         u8         reserved_at_310[0x4];
3211         u8         init_type_reply[0x4];
3212         u8         lmc[0x3];
3213         u8         subnet_timeout[0x5];
3214
3215         u8         sm_lid[0x10];
3216         u8         sm_sl[0x4];
3217         u8         reserved_at_334[0xc];
3218
3219         u8         qkey_violation_counter[0x10];
3220         u8         pkey_violation_counter[0x10];
3221
3222         u8         reserved_at_360[0xca0];
3223 };
3224
3225 struct mlx5_ifc_esw_vport_context_bits {
3226         u8         fdb_to_vport_reg_c[0x1];
3227         u8         reserved_at_1[0x2];
3228         u8         vport_svlan_strip[0x1];
3229         u8         vport_cvlan_strip[0x1];
3230         u8         vport_svlan_insert[0x1];
3231         u8         vport_cvlan_insert[0x2];
3232         u8         fdb_to_vport_reg_c_id[0x8];
3233         u8         reserved_at_10[0x10];
3234
3235         u8         reserved_at_20[0x20];
3236
3237         u8         svlan_cfi[0x1];
3238         u8         svlan_pcp[0x3];
3239         u8         svlan_id[0xc];
3240         u8         cvlan_cfi[0x1];
3241         u8         cvlan_pcp[0x3];
3242         u8         cvlan_id[0xc];
3243
3244         u8         reserved_at_60[0x7a0];
3245 };
3246
3247 enum {
3248         MLX5_EQC_STATUS_OK                = 0x0,
3249         MLX5_EQC_STATUS_EQ_WRITE_FAILURE  = 0xa,
3250 };
3251
3252 enum {
3253         MLX5_EQC_ST_ARMED  = 0x9,
3254         MLX5_EQC_ST_FIRED  = 0xa,
3255 };
3256
3257 struct mlx5_ifc_eqc_bits {
3258         u8         status[0x4];
3259         u8         reserved_at_4[0x9];
3260         u8         ec[0x1];
3261         u8         oi[0x1];
3262         u8         reserved_at_f[0x5];
3263         u8         st[0x4];
3264         u8         reserved_at_18[0x8];
3265
3266         u8         reserved_at_20[0x20];
3267
3268         u8         reserved_at_40[0x14];
3269         u8         page_offset[0x6];
3270         u8         reserved_at_5a[0x6];
3271
3272         u8         reserved_at_60[0x3];
3273         u8         log_eq_size[0x5];
3274         u8         uar_page[0x18];
3275
3276         u8         reserved_at_80[0x20];
3277
3278         u8         reserved_at_a0[0x18];
3279         u8         intr[0x8];
3280
3281         u8         reserved_at_c0[0x3];
3282         u8         log_page_size[0x5];
3283         u8         reserved_at_c8[0x18];
3284
3285         u8         reserved_at_e0[0x60];
3286
3287         u8         reserved_at_140[0x8];
3288         u8         consumer_counter[0x18];
3289
3290         u8         reserved_at_160[0x8];
3291         u8         producer_counter[0x18];
3292
3293         u8         reserved_at_180[0x80];
3294 };
3295
3296 enum {
3297         MLX5_DCTC_STATE_ACTIVE    = 0x0,
3298         MLX5_DCTC_STATE_DRAINING  = 0x1,
3299         MLX5_DCTC_STATE_DRAINED   = 0x2,
3300 };
3301
3302 enum {
3303         MLX5_DCTC_CS_RES_DISABLE    = 0x0,
3304         MLX5_DCTC_CS_RES_NA         = 0x1,
3305         MLX5_DCTC_CS_RES_UP_TO_64B  = 0x2,
3306 };
3307
3308 enum {
3309         MLX5_DCTC_MTU_256_BYTES  = 0x1,
3310         MLX5_DCTC_MTU_512_BYTES  = 0x2,
3311         MLX5_DCTC_MTU_1K_BYTES   = 0x3,
3312         MLX5_DCTC_MTU_2K_BYTES   = 0x4,
3313         MLX5_DCTC_MTU_4K_BYTES   = 0x5,
3314 };
3315
3316 struct mlx5_ifc_dctc_bits {
3317         u8         reserved_at_0[0x4];
3318         u8         state[0x4];
3319         u8         reserved_at_8[0x18];
3320
3321         u8         reserved_at_20[0x8];
3322         u8         user_index[0x18];
3323
3324         u8         reserved_at_40[0x8];
3325         u8         cqn[0x18];
3326
3327         u8         counter_set_id[0x8];
3328         u8         atomic_mode[0x4];
3329         u8         rre[0x1];
3330         u8         rwe[0x1];
3331         u8         rae[0x1];
3332         u8         atomic_like_write_en[0x1];
3333         u8         latency_sensitive[0x1];
3334         u8         rlky[0x1];
3335         u8         free_ar[0x1];
3336         u8         reserved_at_73[0xd];
3337
3338         u8         reserved_at_80[0x8];
3339         u8         cs_res[0x8];
3340         u8         reserved_at_90[0x3];
3341         u8         min_rnr_nak[0x5];
3342         u8         reserved_at_98[0x8];
3343
3344         u8         reserved_at_a0[0x8];
3345         u8         srqn_xrqn[0x18];
3346
3347         u8         reserved_at_c0[0x8];
3348         u8         pd[0x18];
3349
3350         u8         tclass[0x8];
3351         u8         reserved_at_e8[0x4];
3352         u8         flow_label[0x14];
3353
3354         u8         dc_access_key[0x40];
3355
3356         u8         reserved_at_140[0x5];
3357         u8         mtu[0x3];
3358         u8         port[0x8];
3359         u8         pkey_index[0x10];
3360
3361         u8         reserved_at_160[0x8];
3362         u8         my_addr_index[0x8];
3363         u8         reserved_at_170[0x8];
3364         u8         hop_limit[0x8];
3365
3366         u8         dc_access_key_violation_count[0x20];
3367
3368         u8         reserved_at_1a0[0x14];
3369         u8         dei_cfi[0x1];
3370         u8         eth_prio[0x3];
3371         u8         ecn[0x2];
3372         u8         dscp[0x6];
3373
3374         u8         reserved_at_1c0[0x40];
3375 };
3376
3377 enum {
3378         MLX5_CQC_STATUS_OK             = 0x0,
3379         MLX5_CQC_STATUS_CQ_OVERFLOW    = 0x9,
3380         MLX5_CQC_STATUS_CQ_WRITE_FAIL  = 0xa,
3381 };
3382
3383 enum {
3384         MLX5_CQC_CQE_SZ_64_BYTES   = 0x0,
3385         MLX5_CQC_CQE_SZ_128_BYTES  = 0x1,
3386 };
3387
3388 enum {
3389         MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED  = 0x6,
3390         MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED            = 0x9,
3391         MLX5_CQC_ST_FIRED                                 = 0xa,
3392 };
3393
3394 enum {
3395         MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3396         MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3397         MLX5_CQ_PERIOD_NUM_MODES
3398 };
3399
3400 struct mlx5_ifc_cqc_bits {
3401         u8         status[0x4];
3402         u8         reserved_at_4[0x2];
3403         u8         dbr_umem_valid[0x1];
3404         u8         reserved_at_7[0x1];
3405         u8         cqe_sz[0x3];
3406         u8         cc[0x1];
3407         u8         reserved_at_c[0x1];
3408         u8         scqe_break_moderation_en[0x1];
3409         u8         oi[0x1];
3410         u8         cq_period_mode[0x2];
3411         u8         cqe_comp_en[0x1];
3412         u8         mini_cqe_res_format[0x2];
3413         u8         st[0x4];
3414         u8         reserved_at_18[0x8];
3415
3416         u8         reserved_at_20[0x20];
3417
3418         u8         reserved_at_40[0x14];
3419         u8         page_offset[0x6];
3420         u8         reserved_at_5a[0x6];
3421
3422         u8         reserved_at_60[0x3];
3423         u8         log_cq_size[0x5];
3424         u8         uar_page[0x18];
3425
3426         u8         reserved_at_80[0x4];
3427         u8         cq_period[0xc];
3428         u8         cq_max_count[0x10];
3429
3430         u8         reserved_at_a0[0x18];
3431         u8         c_eqn[0x8];
3432
3433         u8         reserved_at_c0[0x3];
3434         u8         log_page_size[0x5];
3435         u8         reserved_at_c8[0x18];
3436
3437         u8         reserved_at_e0[0x20];
3438
3439         u8         reserved_at_100[0x8];
3440         u8         last_notified_index[0x18];
3441
3442         u8         reserved_at_120[0x8];
3443         u8         last_solicit_index[0x18];
3444
3445         u8         reserved_at_140[0x8];
3446         u8         consumer_counter[0x18];
3447
3448         u8         reserved_at_160[0x8];
3449         u8         producer_counter[0x18];
3450
3451         u8         reserved_at_180[0x40];
3452
3453         u8         dbr_addr[0x40];
3454 };
3455
3456 union mlx5_ifc_cong_control_roce_ecn_auto_bits {
3457         struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
3458         struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
3459         struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
3460         u8         reserved_at_0[0x800];
3461 };
3462
3463 struct mlx5_ifc_query_adapter_param_block_bits {
3464         u8         reserved_at_0[0xc0];
3465
3466         u8         reserved_at_c0[0x8];
3467         u8         ieee_vendor_id[0x18];
3468
3469         u8         reserved_at_e0[0x10];
3470         u8         vsd_vendor_id[0x10];
3471
3472         u8         vsd[208][0x8];
3473
3474         u8         vsd_contd_psid[16][0x8];
3475 };
3476
3477 enum {
3478         MLX5_XRQC_STATE_GOOD   = 0x0,
3479         MLX5_XRQC_STATE_ERROR  = 0x1,
3480 };
3481
3482 enum {
3483         MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3484         MLX5_XRQC_TOPOLOGY_TAG_MATCHING        = 0x1,
3485 };
3486
3487 enum {
3488         MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3489 };
3490
3491 struct mlx5_ifc_tag_matching_topology_context_bits {
3492         u8         log_matching_list_sz[0x4];
3493         u8         reserved_at_4[0xc];
3494         u8         append_next_index[0x10];
3495
3496         u8         sw_phase_cnt[0x10];
3497         u8         hw_phase_cnt[0x10];
3498
3499         u8         reserved_at_40[0x40];
3500 };
3501
3502 struct mlx5_ifc_xrqc_bits {
3503         u8         state[0x4];
3504         u8         rlkey[0x1];
3505         u8         reserved_at_5[0xf];
3506         u8         topology[0x4];
3507         u8         reserved_at_18[0x4];
3508         u8         offload[0x4];
3509
3510         u8         reserved_at_20[0x8];
3511         u8         user_index[0x18];
3512
3513         u8         reserved_at_40[0x8];
3514         u8         cqn[0x18];
3515
3516         u8         reserved_at_60[0xa0];
3517
3518         struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3519
3520         u8         reserved_at_180[0x280];
3521
3522         struct mlx5_ifc_wq_bits wq;
3523 };
3524
3525 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3526         struct mlx5_ifc_modify_field_select_bits modify_field_select;
3527         struct mlx5_ifc_resize_field_select_bits resize_field_select;
3528         u8         reserved_at_0[0x20];
3529 };
3530
3531 union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3532         struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3533         struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3534         struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
3535         u8         reserved_at_0[0x20];
3536 };
3537
3538 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3539         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3540         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3541         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3542         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3543         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3544         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3545         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
3546         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
3547         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
3548         struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
3549         u8         reserved_at_0[0x7c0];
3550 };
3551
3552 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3553         struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3554         u8         reserved_at_0[0x7c0];
3555 };
3556
3557 union mlx5_ifc_event_auto_bits {
3558         struct mlx5_ifc_comp_event_bits comp_event;
3559         struct mlx5_ifc_dct_events_bits dct_events;
3560         struct mlx5_ifc_qp_events_bits qp_events;
3561         struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3562         struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3563         struct mlx5_ifc_cq_error_bits cq_error;
3564         struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3565         struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3566         struct mlx5_ifc_gpio_event_bits gpio_event;
3567         struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3568         struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3569         struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
3570         u8         reserved_at_0[0xe0];
3571 };
3572
3573 struct mlx5_ifc_health_buffer_bits {
3574         u8         reserved_at_0[0x100];
3575
3576         u8         assert_existptr[0x20];
3577
3578         u8         assert_callra[0x20];
3579
3580         u8         reserved_at_140[0x40];
3581
3582         u8         fw_version[0x20];
3583
3584         u8         hw_id[0x20];
3585
3586         u8         reserved_at_1c0[0x20];
3587
3588         u8         irisc_index[0x8];
3589         u8         synd[0x8];
3590         u8         ext_synd[0x10];
3591 };
3592
3593 struct mlx5_ifc_register_loopback_control_bits {
3594         u8         no_lb[0x1];
3595         u8         reserved_at_1[0x7];
3596         u8         port[0x8];
3597         u8         reserved_at_10[0x10];
3598
3599         u8         reserved_at_20[0x60];
3600 };
3601
3602 struct mlx5_ifc_vport_tc_element_bits {
3603         u8         traffic_class[0x4];
3604         u8         reserved_at_4[0xc];
3605         u8         vport_number[0x10];
3606 };
3607
3608 struct mlx5_ifc_vport_element_bits {
3609         u8         reserved_at_0[0x10];
3610         u8         vport_number[0x10];
3611 };
3612
3613 enum {
3614         TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3615         TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3616         TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3617 };
3618
3619 struct mlx5_ifc_tsar_element_bits {
3620         u8         reserved_at_0[0x8];
3621         u8         tsar_type[0x8];
3622         u8         reserved_at_10[0x10];
3623 };
3624
3625 enum {
3626         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3627         MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3628 };
3629
3630 struct mlx5_ifc_teardown_hca_out_bits {
3631         u8         status[0x8];
3632         u8         reserved_at_8[0x18];
3633
3634         u8         syndrome[0x20];
3635
3636         u8         reserved_at_40[0x3f];
3637
3638         u8         state[0x1];
3639 };
3640
3641 enum {
3642         MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE  = 0x0,
3643         MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE     = 0x1,
3644         MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3645 };
3646
3647 struct mlx5_ifc_teardown_hca_in_bits {
3648         u8         opcode[0x10];
3649         u8         reserved_at_10[0x10];
3650
3651         u8         reserved_at_20[0x10];
3652         u8         op_mod[0x10];
3653
3654         u8         reserved_at_40[0x10];
3655         u8         profile[0x10];
3656
3657         u8         reserved_at_60[0x20];
3658 };
3659
3660 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3661         u8         status[0x8];
3662         u8         reserved_at_8[0x18];
3663
3664         u8         syndrome[0x20];
3665
3666         u8         reserved_at_40[0x40];
3667 };
3668
3669 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3670         u8         opcode[0x10];
3671         u8         uid[0x10];
3672
3673         u8         reserved_at_20[0x10];
3674         u8         op_mod[0x10];
3675
3676         u8         reserved_at_40[0x8];
3677         u8         qpn[0x18];
3678
3679         u8         reserved_at_60[0x20];
3680
3681         u8         opt_param_mask[0x20];
3682
3683         u8         reserved_at_a0[0x20];
3684
3685         struct mlx5_ifc_qpc_bits qpc;
3686
3687         u8         reserved_at_800[0x80];
3688 };
3689
3690 struct mlx5_ifc_sqd2rts_qp_out_bits {
3691         u8         status[0x8];
3692         u8         reserved_at_8[0x18];
3693
3694         u8         syndrome[0x20];
3695
3696         u8         reserved_at_40[0x40];
3697 };
3698
3699 struct mlx5_ifc_sqd2rts_qp_in_bits {
3700         u8         opcode[0x10];
3701         u8         uid[0x10];
3702
3703         u8         reserved_at_20[0x10];
3704         u8         op_mod[0x10];
3705
3706         u8         reserved_at_40[0x8];
3707         u8         qpn[0x18];
3708
3709         u8         reserved_at_60[0x20];
3710
3711         u8         opt_param_mask[0x20];
3712
3713         u8         reserved_at_a0[0x20];
3714
3715         struct mlx5_ifc_qpc_bits qpc;
3716
3717         u8         reserved_at_800[0x80];
3718 };
3719
3720 struct mlx5_ifc_set_roce_address_out_bits {
3721         u8         status[0x8];
3722         u8         reserved_at_8[0x18];
3723
3724         u8         syndrome[0x20];
3725
3726         u8         reserved_at_40[0x40];
3727 };
3728
3729 struct mlx5_ifc_set_roce_address_in_bits {
3730         u8         opcode[0x10];
3731         u8         reserved_at_10[0x10];
3732
3733         u8         reserved_at_20[0x10];
3734         u8         op_mod[0x10];
3735
3736         u8         roce_address_index[0x10];
3737         u8         reserved_at_50[0xc];
3738         u8         vhca_port_num[0x4];
3739
3740         u8         reserved_at_60[0x20];
3741
3742         struct mlx5_ifc_roce_addr_layout_bits roce_address;
3743 };
3744
3745 struct mlx5_ifc_set_mad_demux_out_bits {
3746         u8         status[0x8];
3747         u8         reserved_at_8[0x18];
3748
3749         u8         syndrome[0x20];
3750
3751         u8         reserved_at_40[0x40];
3752 };
3753
3754 enum {
3755         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL   = 0x0,
3756         MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE  = 0x2,
3757 };
3758
3759 struct mlx5_ifc_set_mad_demux_in_bits {
3760         u8         opcode[0x10];
3761         u8         reserved_at_10[0x10];
3762
3763         u8         reserved_at_20[0x10];
3764         u8         op_mod[0x10];
3765
3766         u8         reserved_at_40[0x20];
3767
3768         u8         reserved_at_60[0x6];
3769         u8         demux_mode[0x2];
3770         u8         reserved_at_68[0x18];
3771 };
3772
3773 struct mlx5_ifc_set_l2_table_entry_out_bits {
3774         u8         status[0x8];
3775         u8         reserved_at_8[0x18];
3776
3777         u8         syndrome[0x20];
3778
3779         u8         reserved_at_40[0x40];
3780 };
3781
3782 struct mlx5_ifc_set_l2_table_entry_in_bits {
3783         u8         opcode[0x10];
3784         u8         reserved_at_10[0x10];
3785
3786         u8         reserved_at_20[0x10];
3787         u8         op_mod[0x10];
3788
3789         u8         reserved_at_40[0x60];
3790
3791         u8         reserved_at_a0[0x8];
3792         u8         table_index[0x18];
3793
3794         u8         reserved_at_c0[0x20];
3795
3796         u8         reserved_at_e0[0x13];
3797         u8         vlan_valid[0x1];
3798         u8         vlan[0xc];
3799
3800         struct mlx5_ifc_mac_address_layout_bits mac_address;
3801
3802         u8         reserved_at_140[0xc0];
3803 };
3804
3805 struct mlx5_ifc_set_issi_out_bits {
3806         u8         status[0x8];
3807         u8         reserved_at_8[0x18];
3808
3809         u8         syndrome[0x20];
3810
3811         u8         reserved_at_40[0x40];
3812 };
3813
3814 struct mlx5_ifc_set_issi_in_bits {
3815         u8         opcode[0x10];
3816         u8         reserved_at_10[0x10];
3817
3818         u8         reserved_at_20[0x10];
3819         u8         op_mod[0x10];
3820
3821         u8         reserved_at_40[0x10];
3822         u8         current_issi[0x10];
3823
3824         u8         reserved_at_60[0x20];
3825 };
3826
3827 struct mlx5_ifc_set_hca_cap_out_bits {
3828         u8         status[0x8];
3829         u8         reserved_at_8[0x18];
3830
3831         u8         syndrome[0x20];
3832
3833         u8         reserved_at_40[0x40];
3834 };
3835
3836 struct mlx5_ifc_set_hca_cap_in_bits {
3837         u8         opcode[0x10];
3838         u8         reserved_at_10[0x10];
3839
3840         u8         reserved_at_20[0x10];
3841         u8         op_mod[0x10];
3842
3843         u8         reserved_at_40[0x40];
3844
3845         union mlx5_ifc_hca_cap_union_bits capability;
3846 };
3847
3848 enum {
3849         MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION    = 0x0,
3850         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG  = 0x1,
3851         MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST    = 0x2,
3852         MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS    = 0x3
3853 };
3854
3855 struct mlx5_ifc_set_fte_out_bits {
3856         u8         status[0x8];
3857         u8         reserved_at_8[0x18];
3858
3859         u8         syndrome[0x20];
3860
3861         u8         reserved_at_40[0x40];
3862 };
3863
3864 struct mlx5_ifc_set_fte_in_bits {
3865         u8         opcode[0x10];
3866         u8         reserved_at_10[0x10];
3867
3868         u8         reserved_at_20[0x10];
3869         u8         op_mod[0x10];
3870
3871         u8         other_vport[0x1];
3872         u8         reserved_at_41[0xf];
3873         u8         vport_number[0x10];
3874
3875         u8         reserved_at_60[0x20];
3876
3877         u8         table_type[0x8];
3878         u8         reserved_at_88[0x18];
3879
3880         u8         reserved_at_a0[0x8];
3881         u8         table_id[0x18];
3882
3883         u8         reserved_at_c0[0x18];
3884         u8         modify_enable_mask[0x8];
3885
3886         u8         reserved_at_e0[0x20];
3887
3888         u8         flow_index[0x20];
3889
3890         u8         reserved_at_120[0xe0];
3891
3892         struct mlx5_ifc_flow_context_bits flow_context;
3893 };
3894
3895 struct mlx5_ifc_rts2rts_qp_out_bits {
3896         u8         status[0x8];
3897         u8         reserved_at_8[0x18];
3898
3899         u8         syndrome[0x20];
3900
3901         u8         reserved_at_40[0x40];
3902 };
3903
3904 struct mlx5_ifc_rts2rts_qp_in_bits {
3905         u8         opcode[0x10];
3906         u8         uid[0x10];
3907
3908         u8         reserved_at_20[0x10];
3909         u8         op_mod[0x10];
3910
3911         u8         reserved_at_40[0x8];
3912         u8         qpn[0x18];
3913
3914         u8         reserved_at_60[0x20];
3915
3916         u8         opt_param_mask[0x20];
3917
3918         u8         reserved_at_a0[0x20];
3919
3920         struct mlx5_ifc_qpc_bits qpc;
3921
3922         u8         reserved_at_800[0x80];
3923 };
3924
3925 struct mlx5_ifc_rtr2rts_qp_out_bits {
3926         u8         status[0x8];
3927         u8         reserved_at_8[0x18];
3928
3929         u8         syndrome[0x20];
3930
3931         u8         reserved_at_40[0x40];
3932 };
3933
3934 struct mlx5_ifc_rtr2rts_qp_in_bits {
3935         u8         opcode[0x10];
3936         u8         uid[0x10];
3937
3938         u8         reserved_at_20[0x10];
3939         u8         op_mod[0x10];
3940
3941         u8         reserved_at_40[0x8];
3942         u8         qpn[0x18];
3943
3944         u8         reserved_at_60[0x20];
3945
3946         u8         opt_param_mask[0x20];
3947
3948         u8         reserved_at_a0[0x20];
3949
3950         struct mlx5_ifc_qpc_bits qpc;
3951
3952         u8         reserved_at_800[0x80];
3953 };
3954
3955 struct mlx5_ifc_rst2init_qp_out_bits {
3956         u8         status[0x8];
3957         u8         reserved_at_8[0x18];
3958
3959         u8         syndrome[0x20];
3960
3961         u8         reserved_at_40[0x40];
3962 };
3963
3964 struct mlx5_ifc_rst2init_qp_in_bits {
3965         u8         opcode[0x10];
3966         u8         uid[0x10];
3967
3968         u8         reserved_at_20[0x10];
3969         u8         op_mod[0x10];
3970
3971         u8         reserved_at_40[0x8];
3972         u8         qpn[0x18];
3973
3974         u8         reserved_at_60[0x20];
3975
3976         u8         opt_param_mask[0x20];
3977
3978         u8         reserved_at_a0[0x20];
3979
3980         struct mlx5_ifc_qpc_bits qpc;
3981
3982         u8         reserved_at_800[0x80];
3983 };
3984
3985 struct mlx5_ifc_query_xrq_out_bits {
3986         u8         status[0x8];
3987         u8         reserved_at_8[0x18];
3988
3989         u8         syndrome[0x20];
3990
3991         u8         reserved_at_40[0x40];
3992
3993         struct mlx5_ifc_xrqc_bits xrq_context;
3994 };
3995
3996 struct mlx5_ifc_query_xrq_in_bits {
3997         u8         opcode[0x10];
3998         u8         reserved_at_10[0x10];
3999
4000         u8         reserved_at_20[0x10];
4001         u8         op_mod[0x10];
4002
4003         u8         reserved_at_40[0x8];
4004         u8         xrqn[0x18];
4005
4006         u8         reserved_at_60[0x20];
4007 };
4008
4009 struct mlx5_ifc_query_xrc_srq_out_bits {
4010         u8         status[0x8];
4011         u8         reserved_at_8[0x18];
4012
4013         u8         syndrome[0x20];
4014
4015         u8         reserved_at_40[0x40];
4016
4017         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
4018
4019         u8         reserved_at_280[0x600];
4020
4021         u8         pas[0][0x40];
4022 };
4023
4024 struct mlx5_ifc_query_xrc_srq_in_bits {
4025         u8         opcode[0x10];
4026         u8         reserved_at_10[0x10];
4027
4028         u8         reserved_at_20[0x10];
4029         u8         op_mod[0x10];
4030
4031         u8         reserved_at_40[0x8];
4032         u8         xrc_srqn[0x18];
4033
4034         u8         reserved_at_60[0x20];
4035 };
4036
4037 enum {
4038         MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN  = 0x0,
4039         MLX5_QUERY_VPORT_STATE_OUT_STATE_UP    = 0x1,
4040 };
4041
4042 struct mlx5_ifc_query_vport_state_out_bits {
4043         u8         status[0x8];
4044         u8         reserved_at_8[0x18];
4045
4046         u8         syndrome[0x20];
4047
4048         u8         reserved_at_40[0x20];
4049
4050         u8         reserved_at_60[0x18];
4051         u8         admin_state[0x4];
4052         u8         state[0x4];
4053 };
4054
4055 enum {
4056         MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT  = 0x0,
4057         MLX5_VPORT_STATE_OP_MOD_ESW_VPORT   = 0x1,
4058 };
4059
4060 struct mlx5_ifc_arm_monitor_counter_in_bits {
4061         u8         opcode[0x10];
4062         u8         uid[0x10];
4063
4064         u8         reserved_at_20[0x10];
4065         u8         op_mod[0x10];
4066
4067         u8         reserved_at_40[0x20];
4068
4069         u8         reserved_at_60[0x20];
4070 };
4071
4072 struct mlx5_ifc_arm_monitor_counter_out_bits {
4073         u8         status[0x8];
4074         u8         reserved_at_8[0x18];
4075
4076         u8         syndrome[0x20];
4077
4078         u8         reserved_at_40[0x40];
4079 };
4080
4081 enum {
4082         MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT     = 0x0,
4083         MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1,
4084 };
4085
4086 enum mlx5_monitor_counter_ppcnt {
4087         MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS      = 0x0,
4088         MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD   = 0x1,
4089         MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS       = 0x2,
4090         MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3,
4091         MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS            = 0x4,
4092         MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS             = 0x5,
4093 };
4094
4095 enum {
4096         MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER     = 0x4,
4097 };
4098
4099 struct mlx5_ifc_monitor_counter_output_bits {
4100         u8         reserved_at_0[0x4];
4101         u8         type[0x4];
4102         u8         reserved_at_8[0x8];
4103         u8         counter[0x10];
4104
4105         u8         counter_group_id[0x20];
4106 };
4107
4108 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6)
4109 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1    (1)
4110 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\
4111                                           MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1)
4112
4113 struct mlx5_ifc_set_monitor_counter_in_bits {
4114         u8         opcode[0x10];
4115         u8         uid[0x10];
4116
4117         u8         reserved_at_20[0x10];
4118         u8         op_mod[0x10];
4119
4120         u8         reserved_at_40[0x10];
4121         u8         num_of_counters[0x10];
4122
4123         u8         reserved_at_60[0x20];
4124
4125         struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER];
4126 };
4127
4128 struct mlx5_ifc_set_monitor_counter_out_bits {
4129         u8         status[0x8];
4130         u8         reserved_at_8[0x18];
4131
4132         u8         syndrome[0x20];
4133
4134         u8         reserved_at_40[0x40];
4135 };
4136
4137 struct mlx5_ifc_query_vport_state_in_bits {
4138         u8         opcode[0x10];
4139         u8         reserved_at_10[0x10];
4140
4141         u8         reserved_at_20[0x10];
4142         u8         op_mod[0x10];
4143
4144         u8         other_vport[0x1];
4145         u8         reserved_at_41[0xf];
4146         u8         vport_number[0x10];
4147
4148         u8         reserved_at_60[0x20];
4149 };
4150
4151 struct mlx5_ifc_query_vnic_env_out_bits {
4152         u8         status[0x8];
4153         u8         reserved_at_8[0x18];
4154
4155         u8         syndrome[0x20];
4156
4157         u8         reserved_at_40[0x40];
4158
4159         struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env;
4160 };
4161
4162 enum {
4163         MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS  = 0x0,
4164 };
4165
4166 struct mlx5_ifc_query_vnic_env_in_bits {
4167         u8         opcode[0x10];
4168         u8         reserved_at_10[0x10];
4169
4170         u8         reserved_at_20[0x10];
4171         u8         op_mod[0x10];
4172
4173         u8         other_vport[0x1];
4174         u8         reserved_at_41[0xf];
4175         u8         vport_number[0x10];
4176
4177         u8         reserved_at_60[0x20];
4178 };
4179
4180 struct mlx5_ifc_query_vport_counter_out_bits {
4181         u8         status[0x8];
4182         u8         reserved_at_8[0x18];
4183
4184         u8         syndrome[0x20];
4185
4186         u8         reserved_at_40[0x40];
4187
4188         struct mlx5_ifc_traffic_counter_bits received_errors;
4189
4190         struct mlx5_ifc_traffic_counter_bits transmit_errors;
4191
4192         struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
4193
4194         struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
4195
4196         struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
4197
4198         struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
4199
4200         struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
4201
4202         struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
4203
4204         struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
4205
4206         struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
4207
4208         struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
4209
4210         struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
4211
4212         u8         reserved_at_680[0xa00];
4213 };
4214
4215 enum {
4216         MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS  = 0x0,
4217 };
4218
4219 struct mlx5_ifc_query_vport_counter_in_bits {
4220         u8         opcode[0x10];
4221         u8         reserved_at_10[0x10];
4222
4223         u8         reserved_at_20[0x10];
4224         u8         op_mod[0x10];
4225
4226         u8         other_vport[0x1];
4227         u8         reserved_at_41[0xb];
4228         u8         port_num[0x4];
4229         u8         vport_number[0x10];
4230
4231         u8         reserved_at_60[0x60];
4232
4233         u8         clear[0x1];
4234         u8         reserved_at_c1[0x1f];
4235
4236         u8         reserved_at_e0[0x20];
4237 };
4238
4239 struct mlx5_ifc_query_tis_out_bits {
4240         u8         status[0x8];
4241         u8         reserved_at_8[0x18];
4242
4243         u8         syndrome[0x20];
4244
4245         u8         reserved_at_40[0x40];
4246
4247         struct mlx5_ifc_tisc_bits tis_context;
4248 };
4249
4250 struct mlx5_ifc_query_tis_in_bits {
4251         u8         opcode[0x10];
4252         u8         reserved_at_10[0x10];
4253
4254         u8         reserved_at_20[0x10];
4255         u8         op_mod[0x10];
4256
4257         u8         reserved_at_40[0x8];
4258         u8         tisn[0x18];
4259
4260         u8         reserved_at_60[0x20];
4261 };
4262
4263 struct mlx5_ifc_query_tir_out_bits {
4264         u8         status[0x8];
4265         u8         reserved_at_8[0x18];
4266
4267         u8         syndrome[0x20];
4268
4269         u8         reserved_at_40[0xc0];
4270
4271         struct mlx5_ifc_tirc_bits tir_context;
4272 };
4273
4274 struct mlx5_ifc_query_tir_in_bits {
4275         u8         opcode[0x10];
4276         u8         reserved_at_10[0x10];
4277
4278         u8         reserved_at_20[0x10];
4279         u8         op_mod[0x10];
4280
4281         u8         reserved_at_40[0x8];
4282         u8         tirn[0x18];
4283
4284         u8         reserved_at_60[0x20];
4285 };
4286
4287 struct mlx5_ifc_query_srq_out_bits {
4288         u8         status[0x8];
4289         u8         reserved_at_8[0x18];
4290
4291         u8         syndrome[0x20];
4292
4293         u8         reserved_at_40[0x40];
4294
4295         struct mlx5_ifc_srqc_bits srq_context_entry;
4296
4297         u8         reserved_at_280[0x600];
4298
4299         u8         pas[0][0x40];
4300 };
4301
4302 struct mlx5_ifc_query_srq_in_bits {
4303         u8         opcode[0x10];
4304         u8         reserved_at_10[0x10];
4305
4306         u8         reserved_at_20[0x10];
4307         u8         op_mod[0x10];
4308
4309         u8         reserved_at_40[0x8];
4310         u8         srqn[0x18];
4311
4312         u8         reserved_at_60[0x20];
4313 };
4314
4315 struct mlx5_ifc_query_sq_out_bits {
4316         u8         status[0x8];
4317         u8         reserved_at_8[0x18];
4318
4319         u8         syndrome[0x20];
4320
4321         u8         reserved_at_40[0xc0];
4322
4323         struct mlx5_ifc_sqc_bits sq_context;
4324 };
4325
4326 struct mlx5_ifc_query_sq_in_bits {
4327         u8         opcode[0x10];
4328         u8         reserved_at_10[0x10];
4329
4330         u8         reserved_at_20[0x10];
4331         u8         op_mod[0x10];
4332
4333         u8         reserved_at_40[0x8];
4334         u8         sqn[0x18];
4335
4336         u8         reserved_at_60[0x20];
4337 };
4338
4339 struct mlx5_ifc_query_special_contexts_out_bits {
4340         u8         status[0x8];
4341         u8         reserved_at_8[0x18];
4342
4343         u8         syndrome[0x20];
4344
4345         u8         dump_fill_mkey[0x20];
4346
4347         u8         resd_lkey[0x20];
4348
4349         u8         null_mkey[0x20];
4350
4351         u8         reserved_at_a0[0x60];
4352 };
4353
4354 struct mlx5_ifc_query_special_contexts_in_bits {
4355         u8         opcode[0x10];
4356         u8         reserved_at_10[0x10];
4357
4358         u8         reserved_at_20[0x10];
4359         u8         op_mod[0x10];
4360
4361         u8         reserved_at_40[0x40];
4362 };
4363
4364 struct mlx5_ifc_query_scheduling_element_out_bits {
4365         u8         opcode[0x10];
4366         u8         reserved_at_10[0x10];
4367
4368         u8         reserved_at_20[0x10];
4369         u8         op_mod[0x10];
4370
4371         u8         reserved_at_40[0xc0];
4372
4373         struct mlx5_ifc_scheduling_context_bits scheduling_context;
4374
4375         u8         reserved_at_300[0x100];
4376 };
4377
4378 enum {
4379         SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
4380 };
4381
4382 struct mlx5_ifc_query_scheduling_element_in_bits {
4383         u8         opcode[0x10];
4384         u8         reserved_at_10[0x10];
4385
4386         u8         reserved_at_20[0x10];
4387         u8         op_mod[0x10];
4388
4389         u8         scheduling_hierarchy[0x8];
4390         u8         reserved_at_48[0x18];
4391
4392         u8         scheduling_element_id[0x20];
4393
4394         u8         reserved_at_80[0x180];
4395 };
4396
4397 struct mlx5_ifc_query_rqt_out_bits {
4398         u8         status[0x8];
4399         u8         reserved_at_8[0x18];
4400
4401         u8         syndrome[0x20];
4402
4403         u8         reserved_at_40[0xc0];
4404
4405         struct mlx5_ifc_rqtc_bits rqt_context;
4406 };
4407
4408 struct mlx5_ifc_query_rqt_in_bits {
4409         u8         opcode[0x10];
4410         u8         reserved_at_10[0x10];
4411
4412         u8         reserved_at_20[0x10];
4413         u8         op_mod[0x10];
4414
4415         u8         reserved_at_40[0x8];
4416         u8         rqtn[0x18];
4417
4418         u8         reserved_at_60[0x20];
4419 };
4420
4421 struct mlx5_ifc_query_rq_out_bits {
4422         u8         status[0x8];
4423         u8         reserved_at_8[0x18];
4424
4425         u8         syndrome[0x20];
4426
4427         u8         reserved_at_40[0xc0];
4428
4429         struct mlx5_ifc_rqc_bits rq_context;
4430 };
4431
4432 struct mlx5_ifc_query_rq_in_bits {
4433         u8         opcode[0x10];
4434         u8         reserved_at_10[0x10];
4435
4436         u8         reserved_at_20[0x10];
4437         u8         op_mod[0x10];
4438
4439         u8         reserved_at_40[0x8];
4440         u8         rqn[0x18];
4441
4442         u8         reserved_at_60[0x20];
4443 };
4444
4445 struct mlx5_ifc_query_roce_address_out_bits {
4446         u8         status[0x8];
4447         u8         reserved_at_8[0x18];
4448
4449         u8         syndrome[0x20];
4450
4451         u8         reserved_at_40[0x40];
4452
4453         struct mlx5_ifc_roce_addr_layout_bits roce_address;
4454 };
4455
4456 struct mlx5_ifc_query_roce_address_in_bits {
4457         u8         opcode[0x10];
4458         u8         reserved_at_10[0x10];
4459
4460         u8         reserved_at_20[0x10];
4461         u8         op_mod[0x10];
4462
4463         u8         roce_address_index[0x10];
4464         u8         reserved_at_50[0xc];
4465         u8         vhca_port_num[0x4];
4466
4467         u8         reserved_at_60[0x20];
4468 };
4469
4470 struct mlx5_ifc_query_rmp_out_bits {
4471         u8         status[0x8];
4472         u8         reserved_at_8[0x18];
4473
4474         u8         syndrome[0x20];
4475
4476         u8         reserved_at_40[0xc0];
4477
4478         struct mlx5_ifc_rmpc_bits rmp_context;
4479 };
4480
4481 struct mlx5_ifc_query_rmp_in_bits {
4482         u8         opcode[0x10];
4483         u8         reserved_at_10[0x10];
4484
4485         u8         reserved_at_20[0x10];
4486         u8         op_mod[0x10];
4487
4488         u8         reserved_at_40[0x8];
4489         u8         rmpn[0x18];
4490
4491         u8         reserved_at_60[0x20];
4492 };
4493
4494 struct mlx5_ifc_query_qp_out_bits {
4495         u8         status[0x8];
4496         u8         reserved_at_8[0x18];
4497
4498         u8         syndrome[0x20];
4499
4500         u8         reserved_at_40[0x40];
4501
4502         u8         opt_param_mask[0x20];
4503
4504         u8         reserved_at_a0[0x20];
4505
4506         struct mlx5_ifc_qpc_bits qpc;
4507
4508         u8         reserved_at_800[0x80];
4509
4510         u8         pas[0][0x40];
4511 };
4512
4513 struct mlx5_ifc_query_qp_in_bits {
4514         u8         opcode[0x10];
4515         u8         reserved_at_10[0x10];
4516
4517         u8         reserved_at_20[0x10];
4518         u8         op_mod[0x10];
4519
4520         u8         reserved_at_40[0x8];
4521         u8         qpn[0x18];
4522
4523         u8         reserved_at_60[0x20];
4524 };
4525
4526 struct mlx5_ifc_query_q_counter_out_bits {
4527         u8         status[0x8];
4528         u8         reserved_at_8[0x18];
4529
4530         u8         syndrome[0x20];
4531
4532         u8         reserved_at_40[0x40];
4533
4534         u8         rx_write_requests[0x20];
4535
4536         u8         reserved_at_a0[0x20];
4537
4538         u8         rx_read_requests[0x20];
4539
4540         u8         reserved_at_e0[0x20];
4541
4542         u8         rx_atomic_requests[0x20];
4543
4544         u8         reserved_at_120[0x20];
4545
4546         u8         rx_dct_connect[0x20];
4547
4548         u8         reserved_at_160[0x20];
4549
4550         u8         out_of_buffer[0x20];
4551
4552         u8         reserved_at_1a0[0x20];
4553
4554         u8         out_of_sequence[0x20];
4555
4556         u8         reserved_at_1e0[0x20];
4557
4558         u8         duplicate_request[0x20];
4559
4560         u8         reserved_at_220[0x20];
4561
4562         u8         rnr_nak_retry_err[0x20];
4563
4564         u8         reserved_at_260[0x20];
4565
4566         u8         packet_seq_err[0x20];
4567
4568         u8         reserved_at_2a0[0x20];
4569
4570         u8         implied_nak_seq_err[0x20];
4571
4572         u8         reserved_at_2e0[0x20];
4573
4574         u8         local_ack_timeout_err[0x20];
4575
4576         u8         reserved_at_320[0xa0];
4577
4578         u8         resp_local_length_error[0x20];
4579
4580         u8         req_local_length_error[0x20];
4581
4582         u8         resp_local_qp_error[0x20];
4583
4584         u8         local_operation_error[0x20];
4585
4586         u8         resp_local_protection[0x20];
4587
4588         u8         req_local_protection[0x20];
4589
4590         u8         resp_cqe_error[0x20];
4591
4592         u8         req_cqe_error[0x20];
4593
4594         u8         req_mw_binding[0x20];
4595
4596         u8         req_bad_response[0x20];
4597
4598         u8         req_remote_invalid_request[0x20];
4599
4600         u8         resp_remote_invalid_request[0x20];
4601
4602         u8         req_remote_access_errors[0x20];
4603
4604         u8         resp_remote_access_errors[0x20];
4605
4606         u8         req_remote_operation_errors[0x20];
4607
4608         u8         req_transport_retries_exceeded[0x20];
4609
4610         u8         cq_overflow[0x20];
4611
4612         u8         resp_cqe_flush_error[0x20];
4613
4614         u8         req_cqe_flush_error[0x20];
4615
4616         u8         reserved_at_620[0x1e0];
4617 };
4618
4619 struct mlx5_ifc_query_q_counter_in_bits {
4620         u8         opcode[0x10];
4621         u8         reserved_at_10[0x10];
4622
4623         u8         reserved_at_20[0x10];
4624         u8         op_mod[0x10];
4625
4626         u8         reserved_at_40[0x80];
4627
4628         u8         clear[0x1];
4629         u8         reserved_at_c1[0x1f];
4630
4631         u8         reserved_at_e0[0x18];
4632         u8         counter_set_id[0x8];
4633 };
4634
4635 struct mlx5_ifc_query_pages_out_bits {
4636         u8         status[0x8];
4637         u8         reserved_at_8[0x18];
4638
4639         u8         syndrome[0x20];
4640
4641         u8         embedded_cpu_function[0x1];
4642         u8         reserved_at_41[0xf];
4643         u8         function_id[0x10];
4644
4645         u8         num_pages[0x20];
4646 };
4647
4648 enum {
4649         MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES     = 0x1,
4650         MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES     = 0x2,
4651         MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES  = 0x3,
4652 };
4653
4654 struct mlx5_ifc_query_pages_in_bits {
4655         u8         opcode[0x10];
4656         u8         reserved_at_10[0x10];
4657
4658         u8         reserved_at_20[0x10];
4659         u8         op_mod[0x10];
4660
4661         u8         embedded_cpu_function[0x1];
4662         u8         reserved_at_41[0xf];
4663         u8         function_id[0x10];
4664
4665         u8         reserved_at_60[0x20];
4666 };
4667
4668 struct mlx5_ifc_query_nic_vport_context_out_bits {
4669         u8         status[0x8];
4670         u8         reserved_at_8[0x18];
4671
4672         u8         syndrome[0x20];
4673
4674         u8         reserved_at_40[0x40];
4675
4676         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4677 };
4678
4679 struct mlx5_ifc_query_nic_vport_context_in_bits {
4680         u8         opcode[0x10];
4681         u8         reserved_at_10[0x10];
4682
4683         u8         reserved_at_20[0x10];
4684         u8         op_mod[0x10];
4685
4686         u8         other_vport[0x1];
4687         u8         reserved_at_41[0xf];
4688         u8         vport_number[0x10];
4689
4690         u8         reserved_at_60[0x5];
4691         u8         allowed_list_type[0x3];
4692         u8         reserved_at_68[0x18];
4693 };
4694
4695 struct mlx5_ifc_query_mkey_out_bits {
4696         u8         status[0x8];
4697         u8         reserved_at_8[0x18];
4698
4699         u8         syndrome[0x20];
4700
4701         u8         reserved_at_40[0x40];
4702
4703         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4704
4705         u8         reserved_at_280[0x600];
4706
4707         u8         bsf0_klm0_pas_mtt0_1[16][0x8];
4708
4709         u8         bsf1_klm1_pas_mtt2_3[16][0x8];
4710 };
4711
4712 struct mlx5_ifc_query_mkey_in_bits {
4713         u8         opcode[0x10];
4714         u8         reserved_at_10[0x10];
4715
4716         u8         reserved_at_20[0x10];
4717         u8         op_mod[0x10];
4718
4719         u8         reserved_at_40[0x8];
4720         u8         mkey_index[0x18];
4721
4722         u8         pg_access[0x1];
4723         u8         reserved_at_61[0x1f];
4724 };
4725
4726 struct mlx5_ifc_query_mad_demux_out_bits {
4727         u8         status[0x8];
4728         u8         reserved_at_8[0x18];
4729
4730         u8         syndrome[0x20];
4731
4732         u8         reserved_at_40[0x40];
4733
4734         u8         mad_dumux_parameters_block[0x20];
4735 };
4736
4737 struct mlx5_ifc_query_mad_demux_in_bits {
4738         u8         opcode[0x10];
4739         u8         reserved_at_10[0x10];
4740
4741         u8         reserved_at_20[0x10];
4742         u8         op_mod[0x10];
4743
4744         u8         reserved_at_40[0x40];
4745 };
4746
4747 struct mlx5_ifc_query_l2_table_entry_out_bits {
4748         u8         status[0x8];
4749         u8         reserved_at_8[0x18];
4750
4751         u8         syndrome[0x20];
4752
4753         u8         reserved_at_40[0xa0];
4754
4755         u8         reserved_at_e0[0x13];
4756         u8         vlan_valid[0x1];
4757         u8         vlan[0xc];
4758
4759         struct mlx5_ifc_mac_address_layout_bits mac_address;
4760
4761         u8         reserved_at_140[0xc0];
4762 };
4763
4764 struct mlx5_ifc_query_l2_table_entry_in_bits {
4765         u8         opcode[0x10];
4766         u8         reserved_at_10[0x10];
4767
4768         u8         reserved_at_20[0x10];
4769         u8         op_mod[0x10];
4770
4771         u8         reserved_at_40[0x60];
4772
4773         u8         reserved_at_a0[0x8];
4774         u8         table_index[0x18];
4775
4776         u8         reserved_at_c0[0x140];
4777 };
4778
4779 struct mlx5_ifc_query_issi_out_bits {
4780         u8         status[0x8];
4781         u8         reserved_at_8[0x18];
4782
4783         u8         syndrome[0x20];
4784
4785         u8         reserved_at_40[0x10];
4786         u8         current_issi[0x10];
4787
4788         u8         reserved_at_60[0xa0];
4789
4790         u8         reserved_at_100[76][0x8];
4791         u8         supported_issi_dw0[0x20];
4792 };
4793
4794 struct mlx5_ifc_query_issi_in_bits {
4795         u8         opcode[0x10];
4796         u8         reserved_at_10[0x10];
4797
4798         u8         reserved_at_20[0x10];
4799         u8         op_mod[0x10];
4800
4801         u8         reserved_at_40[0x40];
4802 };
4803
4804 struct mlx5_ifc_set_driver_version_out_bits {
4805         u8         status[0x8];
4806         u8         reserved_0[0x18];
4807
4808         u8         syndrome[0x20];
4809         u8         reserved_1[0x40];
4810 };
4811
4812 struct mlx5_ifc_set_driver_version_in_bits {
4813         u8         opcode[0x10];
4814         u8         reserved_0[0x10];
4815
4816         u8         reserved_1[0x10];
4817         u8         op_mod[0x10];
4818
4819         u8         reserved_2[0x40];
4820         u8         driver_version[64][0x8];
4821 };
4822
4823 struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4824         u8         status[0x8];
4825         u8         reserved_at_8[0x18];
4826
4827         u8         syndrome[0x20];
4828
4829         u8         reserved_at_40[0x40];
4830
4831         struct mlx5_ifc_pkey_bits pkey[0];
4832 };
4833
4834 struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4835         u8         opcode[0x10];
4836         u8         reserved_at_10[0x10];
4837
4838         u8         reserved_at_20[0x10];
4839         u8         op_mod[0x10];
4840
4841         u8         other_vport[0x1];
4842         u8         reserved_at_41[0xb];
4843         u8         port_num[0x4];
4844         u8         vport_number[0x10];
4845
4846         u8         reserved_at_60[0x10];
4847         u8         pkey_index[0x10];
4848 };
4849
4850 enum {
4851         MLX5_HCA_VPORT_SEL_PORT_GUID    = 1 << 0,
4852         MLX5_HCA_VPORT_SEL_NODE_GUID    = 1 << 1,
4853         MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4854 };
4855
4856 struct mlx5_ifc_query_hca_vport_gid_out_bits {
4857         u8         status[0x8];
4858         u8         reserved_at_8[0x18];
4859
4860         u8         syndrome[0x20];
4861
4862         u8         reserved_at_40[0x20];
4863
4864         u8         gids_num[0x10];
4865         u8         reserved_at_70[0x10];
4866
4867         struct mlx5_ifc_array128_auto_bits gid[0];
4868 };
4869
4870 struct mlx5_ifc_query_hca_vport_gid_in_bits {
4871         u8         opcode[0x10];
4872         u8         reserved_at_10[0x10];
4873
4874         u8         reserved_at_20[0x10];
4875         u8         op_mod[0x10];
4876
4877         u8         other_vport[0x1];
4878         u8         reserved_at_41[0xb];
4879         u8         port_num[0x4];
4880         u8         vport_number[0x10];
4881
4882         u8         reserved_at_60[0x10];
4883         u8         gid_index[0x10];
4884 };
4885
4886 struct mlx5_ifc_query_hca_vport_context_out_bits {
4887         u8         status[0x8];
4888         u8         reserved_at_8[0x18];
4889
4890         u8         syndrome[0x20];
4891
4892         u8         reserved_at_40[0x40];
4893
4894         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4895 };
4896
4897 struct mlx5_ifc_query_hca_vport_context_in_bits {
4898         u8         opcode[0x10];
4899         u8         reserved_at_10[0x10];
4900
4901         u8         reserved_at_20[0x10];
4902         u8         op_mod[0x10];
4903
4904         u8         other_vport[0x1];
4905         u8         reserved_at_41[0xb];
4906         u8         port_num[0x4];
4907         u8         vport_number[0x10];
4908
4909         u8         reserved_at_60[0x20];
4910 };
4911
4912 struct mlx5_ifc_query_hca_cap_out_bits {
4913         u8         status[0x8];
4914         u8         reserved_at_8[0x18];
4915
4916         u8         syndrome[0x20];
4917
4918         u8         reserved_at_40[0x40];
4919
4920         union mlx5_ifc_hca_cap_union_bits capability;
4921 };
4922
4923 struct mlx5_ifc_query_hca_cap_in_bits {
4924         u8         opcode[0x10];
4925         u8         reserved_at_10[0x10];
4926
4927         u8         reserved_at_20[0x10];
4928         u8         op_mod[0x10];
4929
4930         u8         reserved_at_40[0x40];
4931 };
4932
4933 struct mlx5_ifc_query_flow_table_out_bits {
4934         u8         status[0x8];
4935         u8         reserved_at_8[0x18];
4936
4937         u8         syndrome[0x20];
4938
4939         u8         reserved_at_40[0x80];
4940
4941         u8         reserved_at_c0[0x8];
4942         u8         level[0x8];
4943         u8         reserved_at_d0[0x8];
4944         u8         log_size[0x8];
4945
4946         u8         reserved_at_e0[0x120];
4947 };
4948
4949 struct mlx5_ifc_query_flow_table_in_bits {
4950         u8         opcode[0x10];
4951         u8         reserved_at_10[0x10];
4952
4953         u8         reserved_at_20[0x10];
4954         u8         op_mod[0x10];
4955
4956         u8         reserved_at_40[0x40];
4957
4958         u8         table_type[0x8];
4959         u8         reserved_at_88[0x18];
4960
4961         u8         reserved_at_a0[0x8];
4962         u8         table_id[0x18];
4963
4964         u8         reserved_at_c0[0x140];
4965 };
4966
4967 struct mlx5_ifc_query_fte_out_bits {
4968         u8         status[0x8];
4969         u8         reserved_at_8[0x18];
4970
4971         u8         syndrome[0x20];
4972
4973         u8         reserved_at_40[0x1c0];
4974
4975         struct mlx5_ifc_flow_context_bits flow_context;
4976 };
4977
4978 struct mlx5_ifc_query_fte_in_bits {
4979         u8         opcode[0x10];
4980         u8         reserved_at_10[0x10];
4981
4982         u8         reserved_at_20[0x10];
4983         u8         op_mod[0x10];
4984
4985         u8         reserved_at_40[0x40];
4986
4987         u8         table_type[0x8];
4988         u8         reserved_at_88[0x18];
4989
4990         u8         reserved_at_a0[0x8];
4991         u8         table_id[0x18];
4992
4993         u8         reserved_at_c0[0x40];
4994
4995         u8         flow_index[0x20];
4996
4997         u8         reserved_at_120[0xe0];
4998 };
4999
5000 enum {
5001         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS    = 0x0,
5002         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS  = 0x1,
5003         MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS    = 0x2,
5004         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
5005         MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4,
5006 };
5007
5008 struct mlx5_ifc_query_flow_group_out_bits {
5009         u8         status[0x8];
5010         u8         reserved_at_8[0x18];
5011
5012         u8         syndrome[0x20];
5013
5014         u8         reserved_at_40[0xa0];
5015
5016         u8         start_flow_index[0x20];
5017
5018         u8         reserved_at_100[0x20];
5019
5020         u8         end_flow_index[0x20];
5021
5022         u8         reserved_at_140[0xa0];
5023
5024         u8         reserved_at_1e0[0x18];
5025         u8         match_criteria_enable[0x8];
5026
5027         struct mlx5_ifc_fte_match_param_bits match_criteria;
5028
5029         u8         reserved_at_1200[0xe00];
5030 };
5031
5032 struct mlx5_ifc_query_flow_group_in_bits {
5033         u8         opcode[0x10];
5034         u8         reserved_at_10[0x10];
5035
5036         u8         reserved_at_20[0x10];
5037         u8         op_mod[0x10];
5038
5039         u8         reserved_at_40[0x40];
5040
5041         u8         table_type[0x8];
5042         u8         reserved_at_88[0x18];
5043
5044         u8         reserved_at_a0[0x8];
5045         u8         table_id[0x18];
5046
5047         u8         group_id[0x20];
5048
5049         u8         reserved_at_e0[0x120];
5050 };
5051
5052 struct mlx5_ifc_query_flow_counter_out_bits {
5053         u8         status[0x8];
5054         u8         reserved_at_8[0x18];
5055
5056         u8         syndrome[0x20];
5057
5058         u8         reserved_at_40[0x40];
5059
5060         struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5061 };
5062
5063 struct mlx5_ifc_query_flow_counter_in_bits {
5064         u8         opcode[0x10];
5065         u8         reserved_at_10[0x10];
5066
5067         u8         reserved_at_20[0x10];
5068         u8         op_mod[0x10];
5069
5070         u8         reserved_at_40[0x80];
5071
5072         u8         clear[0x1];
5073         u8         reserved_at_c1[0xf];
5074         u8         num_of_counters[0x10];
5075
5076         u8         flow_counter_id[0x20];
5077 };
5078
5079 struct mlx5_ifc_query_esw_vport_context_out_bits {
5080         u8         status[0x8];
5081         u8         reserved_at_8[0x18];
5082
5083         u8         syndrome[0x20];
5084
5085         u8         reserved_at_40[0x40];
5086
5087         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5088 };
5089
5090 struct mlx5_ifc_query_esw_vport_context_in_bits {
5091         u8         opcode[0x10];
5092         u8         reserved_at_10[0x10];
5093
5094         u8         reserved_at_20[0x10];
5095         u8         op_mod[0x10];
5096
5097         u8         other_vport[0x1];
5098         u8         reserved_at_41[0xf];
5099         u8         vport_number[0x10];
5100
5101         u8         reserved_at_60[0x20];
5102 };
5103
5104 struct mlx5_ifc_modify_esw_vport_context_out_bits {
5105         u8         status[0x8];
5106         u8         reserved_at_8[0x18];
5107
5108         u8         syndrome[0x20];
5109
5110         u8         reserved_at_40[0x40];
5111 };
5112
5113 struct mlx5_ifc_esw_vport_context_fields_select_bits {
5114         u8         reserved_at_0[0x1b];
5115         u8         fdb_to_vport_reg_c_id[0x1];
5116         u8         vport_cvlan_insert[0x1];
5117         u8         vport_svlan_insert[0x1];
5118         u8         vport_cvlan_strip[0x1];
5119         u8         vport_svlan_strip[0x1];
5120 };
5121
5122 struct mlx5_ifc_modify_esw_vport_context_in_bits {
5123         u8         opcode[0x10];
5124         u8         reserved_at_10[0x10];
5125
5126         u8         reserved_at_20[0x10];
5127         u8         op_mod[0x10];
5128
5129         u8         other_vport[0x1];
5130         u8         reserved_at_41[0xf];
5131         u8         vport_number[0x10];
5132
5133         struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
5134
5135         struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
5136 };
5137
5138 struct mlx5_ifc_query_eq_out_bits {
5139         u8         status[0x8];
5140         u8         reserved_at_8[0x18];
5141
5142         u8         syndrome[0x20];
5143
5144         u8         reserved_at_40[0x40];
5145
5146         struct mlx5_ifc_eqc_bits eq_context_entry;
5147
5148         u8         reserved_at_280[0x40];
5149
5150         u8         event_bitmask[0x40];
5151
5152         u8         reserved_at_300[0x580];
5153
5154         u8         pas[0][0x40];
5155 };
5156
5157 struct mlx5_ifc_query_eq_in_bits {
5158         u8         opcode[0x10];
5159         u8         reserved_at_10[0x10];
5160
5161         u8         reserved_at_20[0x10];
5162         u8         op_mod[0x10];
5163
5164         u8         reserved_at_40[0x18];
5165         u8         eq_number[0x8];
5166
5167         u8         reserved_at_60[0x20];
5168 };
5169
5170 struct mlx5_ifc_packet_reformat_context_in_bits {
5171         u8         reserved_at_0[0x5];
5172         u8         reformat_type[0x3];
5173         u8         reserved_at_8[0xe];
5174         u8         reformat_data_size[0xa];
5175
5176         u8         reserved_at_20[0x10];
5177         u8         reformat_data[2][0x8];
5178
5179         u8         more_reformat_data[0][0x8];
5180 };
5181
5182 struct mlx5_ifc_query_packet_reformat_context_out_bits {
5183         u8         status[0x8];
5184         u8         reserved_at_8[0x18];
5185
5186         u8         syndrome[0x20];
5187
5188         u8         reserved_at_40[0xa0];
5189
5190         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5191 };
5192
5193 struct mlx5_ifc_query_packet_reformat_context_in_bits {
5194         u8         opcode[0x10];
5195         u8         reserved_at_10[0x10];
5196
5197         u8         reserved_at_20[0x10];
5198         u8         op_mod[0x10];
5199
5200         u8         packet_reformat_id[0x20];
5201
5202         u8         reserved_at_60[0xa0];
5203 };
5204
5205 struct mlx5_ifc_alloc_packet_reformat_context_out_bits {
5206         u8         status[0x8];
5207         u8         reserved_at_8[0x18];
5208
5209         u8         syndrome[0x20];
5210
5211         u8         packet_reformat_id[0x20];
5212
5213         u8         reserved_at_60[0x20];
5214 };
5215
5216 enum {
5217         MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5218         MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5219         MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5220         MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5221         MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5222 };
5223
5224 struct mlx5_ifc_alloc_packet_reformat_context_in_bits {
5225         u8         opcode[0x10];
5226         u8         reserved_at_10[0x10];
5227
5228         u8         reserved_at_20[0x10];
5229         u8         op_mod[0x10];
5230
5231         u8         reserved_at_40[0xa0];
5232
5233         struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context;
5234 };
5235
5236 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits {
5237         u8         status[0x8];
5238         u8         reserved_at_8[0x18];
5239
5240         u8         syndrome[0x20];
5241
5242         u8         reserved_at_40[0x40];
5243 };
5244
5245 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits {
5246         u8         opcode[0x10];
5247         u8         reserved_at_10[0x10];
5248
5249         u8         reserved_20[0x10];
5250         u8         op_mod[0x10];
5251
5252         u8         packet_reformat_id[0x20];
5253
5254         u8         reserved_60[0x20];
5255 };
5256
5257 struct mlx5_ifc_set_action_in_bits {
5258         u8         action_type[0x4];
5259         u8         field[0xc];
5260         u8         reserved_at_10[0x3];
5261         u8         offset[0x5];
5262         u8         reserved_at_18[0x3];
5263         u8         length[0x5];
5264
5265         u8         data[0x20];
5266 };
5267
5268 struct mlx5_ifc_add_action_in_bits {
5269         u8         action_type[0x4];
5270         u8         field[0xc];
5271         u8         reserved_at_10[0x10];
5272
5273         u8         data[0x20];
5274 };
5275
5276 union mlx5_ifc_set_action_in_add_action_in_auto_bits {
5277         struct mlx5_ifc_set_action_in_bits set_action_in;
5278         struct mlx5_ifc_add_action_in_bits add_action_in;
5279         u8         reserved_at_0[0x40];
5280 };
5281
5282 enum {
5283         MLX5_ACTION_TYPE_SET   = 0x1,
5284         MLX5_ACTION_TYPE_ADD   = 0x2,
5285 };
5286
5287 enum {
5288         MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16    = 0x1,
5289         MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0     = 0x2,
5290         MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE     = 0x3,
5291         MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16    = 0x4,
5292         MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0     = 0x5,
5293         MLX5_ACTION_IN_FIELD_OUT_IP_DSCP       = 0x6,
5294         MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS     = 0x7,
5295         MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT     = 0x8,
5296         MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT     = 0x9,
5297         MLX5_ACTION_IN_FIELD_OUT_IP_TTL        = 0xa,
5298         MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT     = 0xb,
5299         MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT     = 0xc,
5300         MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96  = 0xd,
5301         MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64   = 0xe,
5302         MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32   = 0xf,
5303         MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0    = 0x10,
5304         MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96  = 0x11,
5305         MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64   = 0x12,
5306         MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32   = 0x13,
5307         MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0    = 0x14,
5308         MLX5_ACTION_IN_FIELD_OUT_SIPV4         = 0x15,
5309         MLX5_ACTION_IN_FIELD_OUT_DIPV4         = 0x16,
5310         MLX5_ACTION_IN_FIELD_OUT_FIRST_VID     = 0x17,
5311         MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5312         MLX5_ACTION_IN_FIELD_METADATA_REG_C_0  = 0x51,
5313 };
5314
5315 struct mlx5_ifc_alloc_modify_header_context_out_bits {
5316         u8         status[0x8];
5317         u8         reserved_at_8[0x18];
5318
5319         u8         syndrome[0x20];
5320
5321         u8         modify_header_id[0x20];
5322
5323         u8         reserved_at_60[0x20];
5324 };
5325
5326 struct mlx5_ifc_alloc_modify_header_context_in_bits {
5327         u8         opcode[0x10];
5328         u8         reserved_at_10[0x10];
5329
5330         u8         reserved_at_20[0x10];
5331         u8         op_mod[0x10];
5332
5333         u8         reserved_at_40[0x20];
5334
5335         u8         table_type[0x8];
5336         u8         reserved_at_68[0x10];
5337         u8         num_of_actions[0x8];
5338
5339         union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
5340 };
5341
5342 struct mlx5_ifc_dealloc_modify_header_context_out_bits {
5343         u8         status[0x8];
5344         u8         reserved_at_8[0x18];
5345
5346         u8         syndrome[0x20];
5347
5348         u8         reserved_at_40[0x40];
5349 };
5350
5351 struct mlx5_ifc_dealloc_modify_header_context_in_bits {
5352         u8         opcode[0x10];
5353         u8         reserved_at_10[0x10];
5354
5355         u8         reserved_at_20[0x10];
5356         u8         op_mod[0x10];
5357
5358         u8         modify_header_id[0x20];
5359
5360         u8         reserved_at_60[0x20];
5361 };
5362
5363 struct mlx5_ifc_query_dct_out_bits {
5364         u8         status[0x8];
5365         u8         reserved_at_8[0x18];
5366
5367         u8         syndrome[0x20];
5368
5369         u8         reserved_at_40[0x40];
5370
5371         struct mlx5_ifc_dctc_bits dct_context_entry;
5372
5373         u8         reserved_at_280[0x180];
5374 };
5375
5376 struct mlx5_ifc_query_dct_in_bits {
5377         u8         opcode[0x10];
5378         u8         reserved_at_10[0x10];
5379
5380         u8         reserved_at_20[0x10];
5381         u8         op_mod[0x10];
5382
5383         u8         reserved_at_40[0x8];
5384         u8         dctn[0x18];
5385
5386         u8         reserved_at_60[0x20];
5387 };
5388
5389 struct mlx5_ifc_query_cq_out_bits {
5390         u8         status[0x8];
5391         u8         reserved_at_8[0x18];
5392
5393         u8         syndrome[0x20];
5394
5395         u8         reserved_at_40[0x40];
5396
5397         struct mlx5_ifc_cqc_bits cq_context;
5398
5399         u8         reserved_at_280[0x600];
5400
5401         u8         pas[0][0x40];
5402 };
5403
5404 struct mlx5_ifc_query_cq_in_bits {
5405         u8         opcode[0x10];
5406         u8         reserved_at_10[0x10];
5407
5408         u8         reserved_at_20[0x10];
5409         u8         op_mod[0x10];
5410
5411         u8         reserved_at_40[0x8];
5412         u8         cqn[0x18];
5413
5414         u8         reserved_at_60[0x20];
5415 };
5416
5417 struct mlx5_ifc_query_cong_status_out_bits {
5418         u8         status[0x8];
5419         u8         reserved_at_8[0x18];
5420
5421         u8         syndrome[0x20];
5422
5423         u8         reserved_at_40[0x20];
5424
5425         u8         enable[0x1];
5426         u8         tag_enable[0x1];
5427         u8         reserved_at_62[0x1e];
5428 };
5429
5430 struct mlx5_ifc_query_cong_status_in_bits {
5431         u8         opcode[0x10];
5432         u8         reserved_at_10[0x10];
5433
5434         u8         reserved_at_20[0x10];
5435         u8         op_mod[0x10];
5436
5437         u8         reserved_at_40[0x18];
5438         u8         priority[0x4];
5439         u8         cong_protocol[0x4];
5440
5441         u8         reserved_at_60[0x20];
5442 };
5443
5444 struct mlx5_ifc_query_cong_statistics_out_bits {
5445         u8         status[0x8];
5446         u8         reserved_at_8[0x18];
5447
5448         u8         syndrome[0x20];
5449
5450         u8         reserved_at_40[0x40];
5451
5452         u8         rp_cur_flows[0x20];
5453
5454         u8         sum_flows[0x20];
5455
5456         u8         rp_cnp_ignored_high[0x20];
5457
5458         u8         rp_cnp_ignored_low[0x20];
5459
5460         u8         rp_cnp_handled_high[0x20];
5461
5462         u8         rp_cnp_handled_low[0x20];
5463
5464         u8         reserved_at_140[0x100];
5465
5466         u8         time_stamp_high[0x20];
5467
5468         u8         time_stamp_low[0x20];
5469
5470         u8         accumulators_period[0x20];
5471
5472         u8         np_ecn_marked_roce_packets_high[0x20];
5473
5474         u8         np_ecn_marked_roce_packets_low[0x20];
5475
5476         u8         np_cnp_sent_high[0x20];
5477
5478         u8         np_cnp_sent_low[0x20];
5479
5480         u8         reserved_at_320[0x560];
5481 };
5482
5483 struct mlx5_ifc_query_cong_statistics_in_bits {
5484         u8         opcode[0x10];
5485         u8         reserved_at_10[0x10];
5486
5487         u8         reserved_at_20[0x10];
5488         u8         op_mod[0x10];
5489
5490         u8         clear[0x1];
5491         u8         reserved_at_41[0x1f];
5492
5493         u8         reserved_at_60[0x20];
5494 };
5495
5496 struct mlx5_ifc_query_cong_params_out_bits {
5497         u8         status[0x8];
5498         u8         reserved_at_8[0x18];
5499
5500         u8         syndrome[0x20];
5501
5502         u8         reserved_at_40[0x40];
5503
5504         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5505 };
5506
5507 struct mlx5_ifc_query_cong_params_in_bits {
5508         u8         opcode[0x10];
5509         u8         reserved_at_10[0x10];
5510
5511         u8         reserved_at_20[0x10];
5512         u8         op_mod[0x10];
5513
5514         u8         reserved_at_40[0x1c];
5515         u8         cong_protocol[0x4];
5516
5517         u8         reserved_at_60[0x20];
5518 };
5519
5520 struct mlx5_ifc_query_adapter_out_bits {
5521         u8         status[0x8];
5522         u8         reserved_at_8[0x18];
5523
5524         u8         syndrome[0x20];
5525
5526         u8         reserved_at_40[0x40];
5527
5528         struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
5529 };
5530
5531 struct mlx5_ifc_query_adapter_in_bits {
5532         u8         opcode[0x10];
5533         u8         reserved_at_10[0x10];
5534
5535         u8         reserved_at_20[0x10];
5536         u8         op_mod[0x10];
5537
5538         u8         reserved_at_40[0x40];
5539 };
5540
5541 struct mlx5_ifc_qp_2rst_out_bits {
5542         u8         status[0x8];
5543         u8         reserved_at_8[0x18];
5544
5545         u8         syndrome[0x20];
5546
5547         u8         reserved_at_40[0x40];
5548 };
5549
5550 struct mlx5_ifc_qp_2rst_in_bits {
5551         u8         opcode[0x10];
5552         u8         uid[0x10];
5553
5554         u8         reserved_at_20[0x10];
5555         u8         op_mod[0x10];
5556
5557         u8         reserved_at_40[0x8];
5558         u8         qpn[0x18];
5559
5560         u8         reserved_at_60[0x20];
5561 };
5562
5563 struct mlx5_ifc_qp_2err_out_bits {
5564         u8         status[0x8];
5565         u8         reserved_at_8[0x18];
5566
5567         u8         syndrome[0x20];
5568
5569         u8         reserved_at_40[0x40];
5570 };
5571
5572 struct mlx5_ifc_qp_2err_in_bits {
5573         u8         opcode[0x10];
5574         u8         uid[0x10];
5575
5576         u8         reserved_at_20[0x10];
5577         u8         op_mod[0x10];
5578
5579         u8         reserved_at_40[0x8];
5580         u8         qpn[0x18];
5581
5582         u8         reserved_at_60[0x20];
5583 };
5584
5585 struct mlx5_ifc_page_fault_resume_out_bits {
5586         u8         status[0x8];
5587         u8         reserved_at_8[0x18];
5588
5589         u8         syndrome[0x20];
5590
5591         u8         reserved_at_40[0x40];
5592 };
5593
5594 struct mlx5_ifc_page_fault_resume_in_bits {
5595         u8         opcode[0x10];
5596         u8         reserved_at_10[0x10];
5597
5598         u8         reserved_at_20[0x10];
5599         u8         op_mod[0x10];
5600
5601         u8         error[0x1];
5602         u8         reserved_at_41[0x4];
5603         u8         page_fault_type[0x3];
5604         u8         wq_number[0x18];
5605
5606         u8         reserved_at_60[0x8];
5607         u8         token[0x18];
5608 };
5609
5610 struct mlx5_ifc_nop_out_bits {
5611         u8         status[0x8];
5612         u8         reserved_at_8[0x18];
5613
5614         u8         syndrome[0x20];
5615
5616         u8         reserved_at_40[0x40];
5617 };
5618
5619 struct mlx5_ifc_nop_in_bits {
5620         u8         opcode[0x10];
5621         u8         reserved_at_10[0x10];
5622
5623         u8         reserved_at_20[0x10];
5624         u8         op_mod[0x10];
5625
5626         u8         reserved_at_40[0x40];
5627 };
5628
5629 struct mlx5_ifc_modify_vport_state_out_bits {
5630         u8         status[0x8];
5631         u8         reserved_at_8[0x18];
5632
5633         u8         syndrome[0x20];
5634
5635         u8         reserved_at_40[0x40];
5636 };
5637
5638 struct mlx5_ifc_modify_vport_state_in_bits {
5639         u8         opcode[0x10];
5640         u8         reserved_at_10[0x10];
5641
5642         u8         reserved_at_20[0x10];
5643         u8         op_mod[0x10];
5644
5645         u8         other_vport[0x1];
5646         u8         reserved_at_41[0xf];
5647         u8         vport_number[0x10];
5648
5649         u8         reserved_at_60[0x18];
5650         u8         admin_state[0x4];
5651         u8         reserved_at_7c[0x4];
5652 };
5653
5654 struct mlx5_ifc_modify_tis_out_bits {
5655         u8         status[0x8];
5656         u8         reserved_at_8[0x18];
5657
5658         u8         syndrome[0x20];
5659
5660         u8         reserved_at_40[0x40];
5661 };
5662
5663 struct mlx5_ifc_modify_tis_bitmask_bits {
5664         u8         reserved_at_0[0x20];
5665
5666         u8         reserved_at_20[0x1d];
5667         u8         lag_tx_port_affinity[0x1];
5668         u8         strict_lag_tx_port_affinity[0x1];
5669         u8         prio[0x1];
5670 };
5671
5672 struct mlx5_ifc_modify_tis_in_bits {
5673         u8         opcode[0x10];
5674         u8         uid[0x10];
5675
5676         u8         reserved_at_20[0x10];
5677         u8         op_mod[0x10];
5678
5679         u8         reserved_at_40[0x8];
5680         u8         tisn[0x18];
5681
5682         u8         reserved_at_60[0x20];
5683
5684         struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
5685
5686         u8         reserved_at_c0[0x40];
5687
5688         struct mlx5_ifc_tisc_bits ctx;
5689 };
5690
5691 struct mlx5_ifc_modify_tir_bitmask_bits {
5692         u8         reserved_at_0[0x20];
5693
5694         u8         reserved_at_20[0x1b];
5695         u8         self_lb_en[0x1];
5696         u8         reserved_at_3c[0x1];
5697         u8         hash[0x1];
5698         u8         reserved_at_3e[0x1];
5699         u8         lro[0x1];
5700 };
5701
5702 struct mlx5_ifc_modify_tir_out_bits {
5703         u8         status[0x8];
5704         u8         reserved_at_8[0x18];
5705
5706         u8         syndrome[0x20];
5707
5708         u8         reserved_at_40[0x40];
5709 };
5710
5711 struct mlx5_ifc_modify_tir_in_bits {
5712         u8         opcode[0x10];
5713         u8         uid[0x10];
5714
5715         u8         reserved_at_20[0x10];
5716         u8         op_mod[0x10];
5717
5718         u8         reserved_at_40[0x8];
5719         u8         tirn[0x18];
5720
5721         u8         reserved_at_60[0x20];
5722
5723         struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
5724
5725         u8         reserved_at_c0[0x40];
5726
5727         struct mlx5_ifc_tirc_bits ctx;
5728 };
5729
5730 struct mlx5_ifc_modify_sq_out_bits {
5731         u8         status[0x8];
5732         u8         reserved_at_8[0x18];
5733
5734         u8         syndrome[0x20];
5735
5736         u8         reserved_at_40[0x40];
5737 };
5738
5739 struct mlx5_ifc_modify_sq_in_bits {
5740         u8         opcode[0x10];
5741         u8         uid[0x10];
5742
5743         u8         reserved_at_20[0x10];
5744         u8         op_mod[0x10];
5745
5746         u8         sq_state[0x4];
5747         u8         reserved_at_44[0x4];
5748         u8         sqn[0x18];
5749
5750         u8         reserved_at_60[0x20];
5751
5752         u8         modify_bitmask[0x40];
5753
5754         u8         reserved_at_c0[0x40];
5755
5756         struct mlx5_ifc_sqc_bits ctx;
5757 };
5758
5759 struct mlx5_ifc_modify_scheduling_element_out_bits {
5760         u8         status[0x8];
5761         u8         reserved_at_8[0x18];
5762
5763         u8         syndrome[0x20];
5764
5765         u8         reserved_at_40[0x1c0];
5766 };
5767
5768 enum {
5769         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5770         MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5771 };
5772
5773 struct mlx5_ifc_modify_scheduling_element_in_bits {
5774         u8         opcode[0x10];
5775         u8         reserved_at_10[0x10];
5776
5777         u8         reserved_at_20[0x10];
5778         u8         op_mod[0x10];
5779
5780         u8         scheduling_hierarchy[0x8];
5781         u8         reserved_at_48[0x18];
5782
5783         u8         scheduling_element_id[0x20];
5784
5785         u8         reserved_at_80[0x20];
5786
5787         u8         modify_bitmask[0x20];
5788
5789         u8         reserved_at_c0[0x40];
5790
5791         struct mlx5_ifc_scheduling_context_bits scheduling_context;
5792
5793         u8         reserved_at_300[0x100];
5794 };
5795
5796 struct mlx5_ifc_modify_rqt_out_bits {
5797         u8         status[0x8];
5798         u8         reserved_at_8[0x18];
5799
5800         u8         syndrome[0x20];
5801
5802         u8         reserved_at_40[0x40];
5803 };
5804
5805 struct mlx5_ifc_rqt_bitmask_bits {
5806         u8         reserved_at_0[0x20];
5807
5808         u8         reserved_at_20[0x1f];
5809         u8         rqn_list[0x1];
5810 };
5811
5812 struct mlx5_ifc_modify_rqt_in_bits {
5813         u8         opcode[0x10];
5814         u8         uid[0x10];
5815
5816         u8         reserved_at_20[0x10];
5817         u8         op_mod[0x10];
5818
5819         u8         reserved_at_40[0x8];
5820         u8         rqtn[0x18];
5821
5822         u8         reserved_at_60[0x20];
5823
5824         struct mlx5_ifc_rqt_bitmask_bits bitmask;
5825
5826         u8         reserved_at_c0[0x40];
5827
5828         struct mlx5_ifc_rqtc_bits ctx;
5829 };
5830
5831 struct mlx5_ifc_modify_rq_out_bits {
5832         u8         status[0x8];
5833         u8         reserved_at_8[0x18];
5834
5835         u8         syndrome[0x20];
5836
5837         u8         reserved_at_40[0x40];
5838 };
5839
5840 enum {
5841         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5842         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
5843         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
5844 };
5845
5846 struct mlx5_ifc_modify_rq_in_bits {
5847         u8         opcode[0x10];
5848         u8         uid[0x10];
5849
5850         u8         reserved_at_20[0x10];
5851         u8         op_mod[0x10];
5852
5853         u8         rq_state[0x4];
5854         u8         reserved_at_44[0x4];
5855         u8         rqn[0x18];
5856
5857         u8         reserved_at_60[0x20];
5858
5859         u8         modify_bitmask[0x40];
5860
5861         u8         reserved_at_c0[0x40];
5862
5863         struct mlx5_ifc_rqc_bits ctx;
5864 };
5865
5866 struct mlx5_ifc_modify_rmp_out_bits {
5867         u8         status[0x8];
5868         u8         reserved_at_8[0x18];
5869
5870         u8         syndrome[0x20];
5871
5872         u8         reserved_at_40[0x40];
5873 };
5874
5875 struct mlx5_ifc_rmp_bitmask_bits {
5876         u8         reserved_at_0[0x20];
5877
5878         u8         reserved_at_20[0x1f];
5879         u8         lwm[0x1];
5880 };
5881
5882 struct mlx5_ifc_modify_rmp_in_bits {
5883         u8         opcode[0x10];
5884         u8         uid[0x10];
5885
5886         u8         reserved_at_20[0x10];
5887         u8         op_mod[0x10];
5888
5889         u8         rmp_state[0x4];
5890         u8         reserved_at_44[0x4];
5891         u8         rmpn[0x18];
5892
5893         u8         reserved_at_60[0x20];
5894
5895         struct mlx5_ifc_rmp_bitmask_bits bitmask;
5896
5897         u8         reserved_at_c0[0x40];
5898
5899         struct mlx5_ifc_rmpc_bits ctx;
5900 };
5901
5902 struct mlx5_ifc_modify_nic_vport_context_out_bits {
5903         u8         status[0x8];
5904         u8         reserved_at_8[0x18];
5905
5906         u8         syndrome[0x20];
5907
5908         u8         reserved_at_40[0x40];
5909 };
5910
5911 struct mlx5_ifc_modify_nic_vport_field_select_bits {
5912         u8         reserved_at_0[0x12];
5913         u8         affiliation[0x1];
5914         u8         reserved_at_13[0x1];
5915         u8         disable_uc_local_lb[0x1];
5916         u8         disable_mc_local_lb[0x1];
5917         u8         node_guid[0x1];
5918         u8         port_guid[0x1];
5919         u8         min_inline[0x1];
5920         u8         mtu[0x1];
5921         u8         change_event[0x1];
5922         u8         promisc[0x1];
5923         u8         permanent_address[0x1];
5924         u8         addresses_list[0x1];
5925         u8         roce_en[0x1];
5926         u8         reserved_at_1f[0x1];
5927 };
5928
5929 struct mlx5_ifc_modify_nic_vport_context_in_bits {
5930         u8         opcode[0x10];
5931         u8         reserved_at_10[0x10];
5932
5933         u8         reserved_at_20[0x10];
5934         u8         op_mod[0x10];
5935
5936         u8         other_vport[0x1];
5937         u8         reserved_at_41[0xf];
5938         u8         vport_number[0x10];
5939
5940         struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5941
5942         u8         reserved_at_80[0x780];
5943
5944         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5945 };
5946
5947 struct mlx5_ifc_modify_hca_vport_context_out_bits {
5948         u8         status[0x8];
5949         u8         reserved_at_8[0x18];
5950
5951         u8         syndrome[0x20];
5952
5953         u8         reserved_at_40[0x40];
5954 };
5955
5956 struct mlx5_ifc_modify_hca_vport_context_in_bits {
5957         u8         opcode[0x10];
5958         u8         reserved_at_10[0x10];
5959
5960         u8         reserved_at_20[0x10];
5961         u8         op_mod[0x10];
5962
5963         u8         other_vport[0x1];
5964         u8         reserved_at_41[0xb];
5965         u8         port_num[0x4];
5966         u8         vport_number[0x10];
5967
5968         u8         reserved_at_60[0x20];
5969
5970         struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5971 };
5972
5973 struct mlx5_ifc_modify_cq_out_bits {
5974         u8         status[0x8];
5975         u8         reserved_at_8[0x18];
5976
5977         u8         syndrome[0x20];
5978
5979         u8         reserved_at_40[0x40];
5980 };
5981
5982 enum {
5983         MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ  = 0x0,
5984         MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ  = 0x1,
5985 };
5986
5987 struct mlx5_ifc_modify_cq_in_bits {
5988         u8         opcode[0x10];
5989         u8         uid[0x10];
5990
5991         u8         reserved_at_20[0x10];
5992         u8         op_mod[0x10];
5993
5994         u8         reserved_at_40[0x8];
5995         u8         cqn[0x18];
5996
5997         union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5998
5999         struct mlx5_ifc_cqc_bits cq_context;
6000
6001         u8         reserved_at_280[0x60];
6002
6003         u8         cq_umem_valid[0x1];
6004         u8         reserved_at_2e1[0x1f];
6005
6006         u8         reserved_at_300[0x580];
6007
6008         u8         pas[0][0x40];
6009 };
6010
6011 struct mlx5_ifc_modify_cong_status_out_bits {
6012         u8         status[0x8];
6013         u8         reserved_at_8[0x18];
6014
6015         u8         syndrome[0x20];
6016
6017         u8         reserved_at_40[0x40];
6018 };
6019
6020 struct mlx5_ifc_modify_cong_status_in_bits {
6021         u8         opcode[0x10];
6022         u8         reserved_at_10[0x10];
6023
6024         u8         reserved_at_20[0x10];
6025         u8         op_mod[0x10];
6026
6027         u8         reserved_at_40[0x18];
6028         u8         priority[0x4];
6029         u8         cong_protocol[0x4];
6030
6031         u8         enable[0x1];
6032         u8         tag_enable[0x1];
6033         u8         reserved_at_62[0x1e];
6034 };
6035
6036 struct mlx5_ifc_modify_cong_params_out_bits {
6037         u8         status[0x8];
6038         u8         reserved_at_8[0x18];
6039
6040         u8         syndrome[0x20];
6041
6042         u8         reserved_at_40[0x40];
6043 };
6044
6045 struct mlx5_ifc_modify_cong_params_in_bits {
6046         u8         opcode[0x10];
6047         u8         reserved_at_10[0x10];
6048
6049         u8         reserved_at_20[0x10];
6050         u8         op_mod[0x10];
6051
6052         u8         reserved_at_40[0x1c];
6053         u8         cong_protocol[0x4];
6054
6055         union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
6056
6057         u8         reserved_at_80[0x80];
6058
6059         union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
6060 };
6061
6062 struct mlx5_ifc_manage_pages_out_bits {
6063         u8         status[0x8];
6064         u8         reserved_at_8[0x18];
6065
6066         u8         syndrome[0x20];
6067
6068         u8         output_num_entries[0x20];
6069
6070         u8         reserved_at_60[0x20];
6071
6072         u8         pas[0][0x40];
6073 };
6074
6075 enum {
6076         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL     = 0x0,
6077         MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS  = 0x1,
6078         MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES    = 0x2,
6079 };
6080
6081 struct mlx5_ifc_manage_pages_in_bits {
6082         u8         opcode[0x10];
6083         u8         reserved_at_10[0x10];
6084
6085         u8         reserved_at_20[0x10];
6086         u8         op_mod[0x10];
6087
6088         u8         embedded_cpu_function[0x1];
6089         u8         reserved_at_41[0xf];
6090         u8         function_id[0x10];
6091
6092         u8         input_num_entries[0x20];
6093
6094         u8         pas[0][0x40];
6095 };
6096
6097 struct mlx5_ifc_mad_ifc_out_bits {
6098         u8         status[0x8];
6099         u8         reserved_at_8[0x18];
6100
6101         u8         syndrome[0x20];
6102
6103         u8         reserved_at_40[0x40];
6104
6105         u8         response_mad_packet[256][0x8];
6106 };
6107
6108 struct mlx5_ifc_mad_ifc_in_bits {
6109         u8         opcode[0x10];
6110         u8         reserved_at_10[0x10];
6111
6112         u8         reserved_at_20[0x10];
6113         u8         op_mod[0x10];
6114
6115         u8         remote_lid[0x10];
6116         u8         reserved_at_50[0x8];
6117         u8         port[0x8];
6118
6119         u8         reserved_at_60[0x20];
6120
6121         u8         mad[256][0x8];
6122 };
6123
6124 struct mlx5_ifc_init_hca_out_bits {
6125         u8         status[0x8];
6126         u8         reserved_at_8[0x18];
6127
6128         u8         syndrome[0x20];
6129
6130         u8         reserved_at_40[0x40];
6131 };
6132
6133 struct mlx5_ifc_init_hca_in_bits {
6134         u8         opcode[0x10];
6135         u8         reserved_at_10[0x10];
6136
6137         u8         reserved_at_20[0x10];
6138         u8         op_mod[0x10];
6139
6140         u8         reserved_at_40[0x40];
6141         u8         sw_owner_id[4][0x20];
6142 };
6143
6144 struct mlx5_ifc_init2rtr_qp_out_bits {
6145         u8         status[0x8];
6146         u8         reserved_at_8[0x18];
6147
6148         u8         syndrome[0x20];
6149
6150         u8         reserved_at_40[0x40];
6151 };
6152
6153 struct mlx5_ifc_init2rtr_qp_in_bits {
6154         u8         opcode[0x10];
6155         u8         uid[0x10];
6156
6157         u8         reserved_at_20[0x10];
6158         u8         op_mod[0x10];
6159
6160         u8         reserved_at_40[0x8];
6161         u8         qpn[0x18];
6162
6163         u8         reserved_at_60[0x20];
6164
6165         u8         opt_param_mask[0x20];
6166
6167         u8         reserved_at_a0[0x20];
6168
6169         struct mlx5_ifc_qpc_bits qpc;
6170
6171         u8         reserved_at_800[0x80];
6172 };
6173
6174 struct mlx5_ifc_init2init_qp_out_bits {
6175         u8         status[0x8];
6176         u8         reserved_at_8[0x18];
6177
6178         u8         syndrome[0x20];
6179
6180         u8         reserved_at_40[0x40];
6181 };
6182
6183 struct mlx5_ifc_init2init_qp_in_bits {
6184         u8         opcode[0x10];
6185         u8         uid[0x10];
6186
6187         u8         reserved_at_20[0x10];
6188         u8         op_mod[0x10];
6189
6190         u8         reserved_at_40[0x8];
6191         u8         qpn[0x18];
6192
6193         u8         reserved_at_60[0x20];
6194
6195         u8         opt_param_mask[0x20];
6196
6197         u8         reserved_at_a0[0x20];
6198
6199         struct mlx5_ifc_qpc_bits qpc;
6200
6201         u8         reserved_at_800[0x80];
6202 };
6203
6204 struct mlx5_ifc_get_dropped_packet_log_out_bits {
6205         u8         status[0x8];
6206         u8         reserved_at_8[0x18];
6207
6208         u8         syndrome[0x20];
6209
6210         u8         reserved_at_40[0x40];
6211
6212         u8         packet_headers_log[128][0x8];
6213
6214         u8         packet_syndrome[64][0x8];
6215 };
6216
6217 struct mlx5_ifc_get_dropped_packet_log_in_bits {
6218         u8         opcode[0x10];
6219         u8         reserved_at_10[0x10];
6220
6221         u8         reserved_at_20[0x10];
6222         u8         op_mod[0x10];
6223
6224         u8         reserved_at_40[0x40];
6225 };
6226
6227 struct mlx5_ifc_gen_eqe_in_bits {
6228         u8         opcode[0x10];
6229         u8         reserved_at_10[0x10];
6230
6231         u8         reserved_at_20[0x10];
6232         u8         op_mod[0x10];
6233
6234         u8         reserved_at_40[0x18];
6235         u8         eq_number[0x8];
6236
6237         u8         reserved_at_60[0x20];
6238
6239         u8         eqe[64][0x8];
6240 };
6241
6242 struct mlx5_ifc_gen_eq_out_bits {
6243         u8         status[0x8];
6244         u8         reserved_at_8[0x18];
6245
6246         u8         syndrome[0x20];
6247
6248         u8         reserved_at_40[0x40];
6249 };
6250
6251 struct mlx5_ifc_enable_hca_out_bits {
6252         u8         status[0x8];
6253         u8         reserved_at_8[0x18];
6254
6255         u8         syndrome[0x20];
6256
6257         u8         reserved_at_40[0x20];
6258 };
6259
6260 struct mlx5_ifc_enable_hca_in_bits {
6261         u8         opcode[0x10];
6262         u8         reserved_at_10[0x10];
6263
6264         u8         reserved_at_20[0x10];
6265         u8         op_mod[0x10];
6266
6267         u8         embedded_cpu_function[0x1];
6268         u8         reserved_at_41[0xf];
6269         u8         function_id[0x10];
6270
6271         u8         reserved_at_60[0x20];
6272 };
6273
6274 struct mlx5_ifc_drain_dct_out_bits {
6275         u8         status[0x8];
6276         u8         reserved_at_8[0x18];
6277
6278         u8         syndrome[0x20];
6279
6280         u8         reserved_at_40[0x40];
6281 };
6282
6283 struct mlx5_ifc_drain_dct_in_bits {
6284         u8         opcode[0x10];
6285         u8         uid[0x10];
6286
6287         u8         reserved_at_20[0x10];
6288         u8         op_mod[0x10];
6289
6290         u8         reserved_at_40[0x8];
6291         u8         dctn[0x18];
6292
6293         u8         reserved_at_60[0x20];
6294 };
6295
6296 struct mlx5_ifc_disable_hca_out_bits {
6297         u8         status[0x8];
6298         u8         reserved_at_8[0x18];
6299
6300         u8         syndrome[0x20];
6301
6302         u8         reserved_at_40[0x20];
6303 };
6304
6305 struct mlx5_ifc_disable_hca_in_bits {
6306         u8         opcode[0x10];
6307         u8         reserved_at_10[0x10];
6308
6309         u8         reserved_at_20[0x10];
6310         u8         op_mod[0x10];
6311
6312         u8         embedded_cpu_function[0x1];
6313         u8         reserved_at_41[0xf];
6314         u8         function_id[0x10];
6315
6316         u8         reserved_at_60[0x20];
6317 };
6318
6319 struct mlx5_ifc_detach_from_mcg_out_bits {
6320         u8         status[0x8];
6321         u8         reserved_at_8[0x18];
6322
6323         u8         syndrome[0x20];
6324
6325         u8         reserved_at_40[0x40];
6326 };
6327
6328 struct mlx5_ifc_detach_from_mcg_in_bits {
6329         u8         opcode[0x10];
6330         u8         uid[0x10];
6331
6332         u8         reserved_at_20[0x10];
6333         u8         op_mod[0x10];
6334
6335         u8         reserved_at_40[0x8];
6336         u8         qpn[0x18];
6337
6338         u8         reserved_at_60[0x20];
6339
6340         u8         multicast_gid[16][0x8];
6341 };
6342
6343 struct mlx5_ifc_destroy_xrq_out_bits {
6344         u8         status[0x8];
6345         u8         reserved_at_8[0x18];
6346
6347         u8         syndrome[0x20];
6348
6349         u8         reserved_at_40[0x40];
6350 };
6351
6352 struct mlx5_ifc_destroy_xrq_in_bits {
6353         u8         opcode[0x10];
6354         u8         uid[0x10];
6355
6356         u8         reserved_at_20[0x10];
6357         u8         op_mod[0x10];
6358
6359         u8         reserved_at_40[0x8];
6360         u8         xrqn[0x18];
6361
6362         u8         reserved_at_60[0x20];
6363 };
6364
6365 struct mlx5_ifc_destroy_xrc_srq_out_bits {
6366         u8         status[0x8];
6367         u8         reserved_at_8[0x18];
6368
6369         u8         syndrome[0x20];
6370
6371         u8         reserved_at_40[0x40];
6372 };
6373
6374 struct mlx5_ifc_destroy_xrc_srq_in_bits {
6375         u8         opcode[0x10];
6376         u8         uid[0x10];
6377
6378         u8         reserved_at_20[0x10];
6379         u8         op_mod[0x10];
6380
6381         u8         reserved_at_40[0x8];
6382         u8         xrc_srqn[0x18];
6383
6384         u8         reserved_at_60[0x20];
6385 };
6386
6387 struct mlx5_ifc_destroy_tis_out_bits {
6388         u8         status[0x8];
6389         u8         reserved_at_8[0x18];
6390
6391         u8         syndrome[0x20];
6392
6393         u8         reserved_at_40[0x40];
6394 };
6395
6396 struct mlx5_ifc_destroy_tis_in_bits {
6397         u8         opcode[0x10];
6398         u8         uid[0x10];
6399
6400         u8         reserved_at_20[0x10];
6401         u8         op_mod[0x10];
6402
6403         u8         reserved_at_40[0x8];
6404         u8         tisn[0x18];
6405
6406         u8         reserved_at_60[0x20];
6407 };
6408
6409 struct mlx5_ifc_destroy_tir_out_bits {
6410         u8         status[0x8];
6411         u8         reserved_at_8[0x18];
6412
6413         u8         syndrome[0x20];
6414
6415         u8         reserved_at_40[0x40];
6416 };
6417
6418 struct mlx5_ifc_destroy_tir_in_bits {
6419         u8         opcode[0x10];
6420         u8         uid[0x10];
6421
6422         u8         reserved_at_20[0x10];
6423         u8         op_mod[0x10];
6424
6425         u8         reserved_at_40[0x8];
6426         u8         tirn[0x18];
6427
6428         u8         reserved_at_60[0x20];
6429 };
6430
6431 struct mlx5_ifc_destroy_srq_out_bits {
6432         u8         status[0x8];
6433         u8         reserved_at_8[0x18];
6434
6435         u8         syndrome[0x20];
6436
6437         u8         reserved_at_40[0x40];
6438 };
6439
6440 struct mlx5_ifc_destroy_srq_in_bits {
6441         u8         opcode[0x10];
6442         u8         uid[0x10];
6443
6444         u8         reserved_at_20[0x10];
6445         u8         op_mod[0x10];
6446
6447         u8         reserved_at_40[0x8];
6448         u8         srqn[0x18];
6449
6450         u8         reserved_at_60[0x20];
6451 };
6452
6453 struct mlx5_ifc_destroy_sq_out_bits {
6454         u8         status[0x8];
6455         u8         reserved_at_8[0x18];
6456
6457         u8         syndrome[0x20];
6458
6459         u8         reserved_at_40[0x40];
6460 };
6461
6462 struct mlx5_ifc_destroy_sq_in_bits {
6463         u8         opcode[0x10];
6464         u8         uid[0x10];
6465
6466         u8         reserved_at_20[0x10];
6467         u8         op_mod[0x10];
6468
6469         u8         reserved_at_40[0x8];
6470         u8         sqn[0x18];
6471
6472         u8         reserved_at_60[0x20];
6473 };
6474
6475 struct mlx5_ifc_destroy_scheduling_element_out_bits {
6476         u8         status[0x8];
6477         u8         reserved_at_8[0x18];
6478
6479         u8         syndrome[0x20];
6480
6481         u8         reserved_at_40[0x1c0];
6482 };
6483
6484 struct mlx5_ifc_destroy_scheduling_element_in_bits {
6485         u8         opcode[0x10];
6486         u8         reserved_at_10[0x10];
6487
6488         u8         reserved_at_20[0x10];
6489         u8         op_mod[0x10];
6490
6491         u8         scheduling_hierarchy[0x8];
6492         u8         reserved_at_48[0x18];
6493
6494         u8         scheduling_element_id[0x20];
6495
6496         u8         reserved_at_80[0x180];
6497 };
6498
6499 struct mlx5_ifc_destroy_rqt_out_bits {
6500         u8         status[0x8];
6501         u8         reserved_at_8[0x18];
6502
6503         u8         syndrome[0x20];
6504
6505         u8         reserved_at_40[0x40];
6506 };
6507
6508 struct mlx5_ifc_destroy_rqt_in_bits {
6509         u8         opcode[0x10];
6510         u8         uid[0x10];
6511
6512         u8         reserved_at_20[0x10];
6513         u8         op_mod[0x10];
6514
6515         u8         reserved_at_40[0x8];
6516         u8         rqtn[0x18];
6517
6518         u8         reserved_at_60[0x20];
6519 };
6520
6521 struct mlx5_ifc_destroy_rq_out_bits {
6522         u8         status[0x8];
6523         u8         reserved_at_8[0x18];
6524
6525         u8         syndrome[0x20];
6526
6527         u8         reserved_at_40[0x40];
6528 };
6529
6530 struct mlx5_ifc_destroy_rq_in_bits {
6531         u8         opcode[0x10];
6532         u8         uid[0x10];
6533
6534         u8         reserved_at_20[0x10];
6535         u8         op_mod[0x10];
6536
6537         u8         reserved_at_40[0x8];
6538         u8         rqn[0x18];
6539
6540         u8         reserved_at_60[0x20];
6541 };
6542
6543 struct mlx5_ifc_set_delay_drop_params_in_bits {
6544         u8         opcode[0x10];
6545         u8         reserved_at_10[0x10];
6546
6547         u8         reserved_at_20[0x10];
6548         u8         op_mod[0x10];
6549
6550         u8         reserved_at_40[0x20];
6551
6552         u8         reserved_at_60[0x10];
6553         u8         delay_drop_timeout[0x10];
6554 };
6555
6556 struct mlx5_ifc_set_delay_drop_params_out_bits {
6557         u8         status[0x8];
6558         u8         reserved_at_8[0x18];
6559
6560         u8         syndrome[0x20];
6561
6562         u8         reserved_at_40[0x40];
6563 };
6564
6565 struct mlx5_ifc_destroy_rmp_out_bits {
6566         u8         status[0x8];
6567         u8         reserved_at_8[0x18];
6568
6569         u8         syndrome[0x20];
6570
6571         u8         reserved_at_40[0x40];
6572 };
6573
6574 struct mlx5_ifc_destroy_rmp_in_bits {
6575         u8         opcode[0x10];
6576         u8         uid[0x10];
6577
6578         u8         reserved_at_20[0x10];
6579         u8         op_mod[0x10];
6580
6581         u8         reserved_at_40[0x8];
6582         u8         rmpn[0x18];
6583
6584         u8         reserved_at_60[0x20];
6585 };
6586
6587 struct mlx5_ifc_destroy_qp_out_bits {
6588         u8         status[0x8];
6589         u8         reserved_at_8[0x18];
6590
6591         u8         syndrome[0x20];
6592
6593         u8         reserved_at_40[0x40];
6594 };
6595
6596 struct mlx5_ifc_destroy_qp_in_bits {
6597         u8         opcode[0x10];
6598         u8         uid[0x10];
6599
6600         u8         reserved_at_20[0x10];
6601         u8         op_mod[0x10];
6602
6603         u8         reserved_at_40[0x8];
6604         u8         qpn[0x18];
6605
6606         u8         reserved_at_60[0x20];
6607 };
6608
6609 struct mlx5_ifc_destroy_psv_out_bits {
6610         u8         status[0x8];
6611         u8         reserved_at_8[0x18];
6612
6613         u8         syndrome[0x20];
6614
6615         u8         reserved_at_40[0x40];
6616 };
6617
6618 struct mlx5_ifc_destroy_psv_in_bits {
6619         u8         opcode[0x10];
6620         u8         reserved_at_10[0x10];
6621
6622         u8         reserved_at_20[0x10];
6623         u8         op_mod[0x10];
6624
6625         u8         reserved_at_40[0x8];
6626         u8         psvn[0x18];
6627
6628         u8         reserved_at_60[0x20];
6629 };
6630
6631 struct mlx5_ifc_destroy_mkey_out_bits {
6632         u8         status[0x8];
6633         u8         reserved_at_8[0x18];
6634
6635         u8         syndrome[0x20];
6636
6637         u8         reserved_at_40[0x40];
6638 };
6639
6640 struct mlx5_ifc_destroy_mkey_in_bits {
6641         u8         opcode[0x10];
6642         u8         reserved_at_10[0x10];
6643
6644         u8         reserved_at_20[0x10];
6645         u8         op_mod[0x10];
6646
6647         u8         reserved_at_40[0x8];
6648         u8         mkey_index[0x18];
6649
6650         u8         reserved_at_60[0x20];
6651 };
6652
6653 struct mlx5_ifc_destroy_flow_table_out_bits {
6654         u8         status[0x8];
6655         u8         reserved_at_8[0x18];
6656
6657         u8         syndrome[0x20];
6658
6659         u8         reserved_at_40[0x40];
6660 };
6661
6662 struct mlx5_ifc_destroy_flow_table_in_bits {
6663         u8         opcode[0x10];
6664         u8         reserved_at_10[0x10];
6665
6666         u8         reserved_at_20[0x10];
6667         u8         op_mod[0x10];
6668
6669         u8         other_vport[0x1];
6670         u8         reserved_at_41[0xf];
6671         u8         vport_number[0x10];
6672
6673         u8         reserved_at_60[0x20];
6674
6675         u8         table_type[0x8];
6676         u8         reserved_at_88[0x18];
6677
6678         u8         reserved_at_a0[0x8];
6679         u8         table_id[0x18];
6680
6681         u8         reserved_at_c0[0x140];
6682 };
6683
6684 struct mlx5_ifc_destroy_flow_group_out_bits {
6685         u8         status[0x8];
6686         u8         reserved_at_8[0x18];
6687
6688         u8         syndrome[0x20];
6689
6690         u8         reserved_at_40[0x40];
6691 };
6692
6693 struct mlx5_ifc_destroy_flow_group_in_bits {
6694         u8         opcode[0x10];
6695         u8         reserved_at_10[0x10];
6696
6697         u8         reserved_at_20[0x10];
6698         u8         op_mod[0x10];
6699
6700         u8         other_vport[0x1];
6701         u8         reserved_at_41[0xf];
6702         u8         vport_number[0x10];
6703
6704         u8         reserved_at_60[0x20];
6705
6706         u8         table_type[0x8];
6707         u8         reserved_at_88[0x18];
6708
6709         u8         reserved_at_a0[0x8];
6710         u8         table_id[0x18];
6711
6712         u8         group_id[0x20];
6713
6714         u8         reserved_at_e0[0x120];
6715 };
6716
6717 struct mlx5_ifc_destroy_eq_out_bits {
6718         u8         status[0x8];
6719         u8         reserved_at_8[0x18];
6720
6721         u8         syndrome[0x20];
6722
6723         u8         reserved_at_40[0x40];
6724 };
6725
6726 struct mlx5_ifc_destroy_eq_in_bits {
6727         u8         opcode[0x10];
6728         u8         reserved_at_10[0x10];
6729
6730         u8         reserved_at_20[0x10];
6731         u8         op_mod[0x10];
6732
6733         u8         reserved_at_40[0x18];
6734         u8         eq_number[0x8];
6735
6736         u8         reserved_at_60[0x20];
6737 };
6738
6739 struct mlx5_ifc_destroy_dct_out_bits {
6740         u8         status[0x8];
6741         u8         reserved_at_8[0x18];
6742
6743         u8         syndrome[0x20];
6744
6745         u8         reserved_at_40[0x40];
6746 };
6747
6748 struct mlx5_ifc_destroy_dct_in_bits {
6749         u8         opcode[0x10];
6750         u8         uid[0x10];
6751
6752         u8         reserved_at_20[0x10];
6753         u8         op_mod[0x10];
6754
6755         u8         reserved_at_40[0x8];
6756         u8         dctn[0x18];
6757
6758         u8         reserved_at_60[0x20];
6759 };
6760
6761 struct mlx5_ifc_destroy_cq_out_bits {
6762         u8         status[0x8];
6763         u8         reserved_at_8[0x18];
6764
6765         u8         syndrome[0x20];
6766
6767         u8         reserved_at_40[0x40];
6768 };
6769
6770 struct mlx5_ifc_destroy_cq_in_bits {
6771         u8         opcode[0x10];
6772         u8         uid[0x10];
6773
6774         u8         reserved_at_20[0x10];
6775         u8         op_mod[0x10];
6776
6777         u8         reserved_at_40[0x8];
6778         u8         cqn[0x18];
6779
6780         u8         reserved_at_60[0x20];
6781 };
6782
6783 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6784         u8         status[0x8];
6785         u8         reserved_at_8[0x18];
6786
6787         u8         syndrome[0x20];
6788
6789         u8         reserved_at_40[0x40];
6790 };
6791
6792 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6793         u8         opcode[0x10];
6794         u8         reserved_at_10[0x10];
6795
6796         u8         reserved_at_20[0x10];
6797         u8         op_mod[0x10];
6798
6799         u8         reserved_at_40[0x20];
6800
6801         u8         reserved_at_60[0x10];
6802         u8         vxlan_udp_port[0x10];
6803 };
6804
6805 struct mlx5_ifc_delete_l2_table_entry_out_bits {
6806         u8         status[0x8];
6807         u8         reserved_at_8[0x18];
6808
6809         u8         syndrome[0x20];
6810
6811         u8         reserved_at_40[0x40];
6812 };
6813
6814 struct mlx5_ifc_delete_l2_table_entry_in_bits {
6815         u8         opcode[0x10];
6816         u8         reserved_at_10[0x10];
6817
6818         u8         reserved_at_20[0x10];
6819         u8         op_mod[0x10];
6820
6821         u8         reserved_at_40[0x60];
6822
6823         u8         reserved_at_a0[0x8];
6824         u8         table_index[0x18];
6825
6826         u8         reserved_at_c0[0x140];
6827 };
6828
6829 struct mlx5_ifc_delete_fte_out_bits {
6830         u8         status[0x8];
6831         u8         reserved_at_8[0x18];
6832
6833         u8         syndrome[0x20];
6834
6835         u8         reserved_at_40[0x40];
6836 };
6837
6838 struct mlx5_ifc_delete_fte_in_bits {
6839         u8         opcode[0x10];
6840         u8         reserved_at_10[0x10];
6841
6842         u8         reserved_at_20[0x10];
6843         u8         op_mod[0x10];
6844
6845         u8         other_vport[0x1];
6846         u8         reserved_at_41[0xf];
6847         u8         vport_number[0x10];
6848
6849         u8         reserved_at_60[0x20];
6850
6851         u8         table_type[0x8];
6852         u8         reserved_at_88[0x18];
6853
6854         u8         reserved_at_a0[0x8];
6855         u8         table_id[0x18];
6856
6857         u8         reserved_at_c0[0x40];
6858
6859         u8         flow_index[0x20];
6860
6861         u8         reserved_at_120[0xe0];
6862 };
6863
6864 struct mlx5_ifc_dealloc_xrcd_out_bits {
6865         u8         status[0x8];
6866         u8         reserved_at_8[0x18];
6867
6868         u8         syndrome[0x20];
6869
6870         u8         reserved_at_40[0x40];
6871 };
6872
6873 struct mlx5_ifc_dealloc_xrcd_in_bits {
6874         u8         opcode[0x10];
6875         u8         uid[0x10];
6876
6877         u8         reserved_at_20[0x10];
6878         u8         op_mod[0x10];
6879
6880         u8         reserved_at_40[0x8];
6881         u8         xrcd[0x18];
6882
6883         u8         reserved_at_60[0x20];
6884 };
6885
6886 struct mlx5_ifc_dealloc_uar_out_bits {
6887         u8         status[0x8];
6888         u8         reserved_at_8[0x18];
6889
6890         u8         syndrome[0x20];
6891
6892         u8         reserved_at_40[0x40];
6893 };
6894
6895 struct mlx5_ifc_dealloc_uar_in_bits {
6896         u8         opcode[0x10];
6897         u8         reserved_at_10[0x10];
6898
6899         u8         reserved_at_20[0x10];
6900         u8         op_mod[0x10];
6901
6902         u8         reserved_at_40[0x8];
6903         u8         uar[0x18];
6904
6905         u8         reserved_at_60[0x20];
6906 };
6907
6908 struct mlx5_ifc_dealloc_transport_domain_out_bits {
6909         u8         status[0x8];
6910         u8         reserved_at_8[0x18];
6911
6912         u8         syndrome[0x20];
6913
6914         u8         reserved_at_40[0x40];
6915 };
6916
6917 struct mlx5_ifc_dealloc_transport_domain_in_bits {
6918         u8         opcode[0x10];
6919         u8         uid[0x10];
6920
6921         u8         reserved_at_20[0x10];
6922         u8         op_mod[0x10];
6923
6924         u8         reserved_at_40[0x8];
6925         u8         transport_domain[0x18];
6926
6927         u8         reserved_at_60[0x20];
6928 };
6929
6930 struct mlx5_ifc_dealloc_q_counter_out_bits {
6931         u8         status[0x8];
6932         u8         reserved_at_8[0x18];
6933
6934         u8         syndrome[0x20];
6935
6936         u8         reserved_at_40[0x40];
6937 };
6938
6939 struct mlx5_ifc_dealloc_q_counter_in_bits {
6940         u8         opcode[0x10];
6941         u8         reserved_at_10[0x10];
6942
6943         u8         reserved_at_20[0x10];
6944         u8         op_mod[0x10];
6945
6946         u8         reserved_at_40[0x18];
6947         u8         counter_set_id[0x8];
6948
6949         u8         reserved_at_60[0x20];
6950 };
6951
6952 struct mlx5_ifc_dealloc_pd_out_bits {
6953         u8         status[0x8];
6954         u8         reserved_at_8[0x18];
6955
6956         u8         syndrome[0x20];
6957
6958         u8         reserved_at_40[0x40];
6959 };
6960
6961 struct mlx5_ifc_dealloc_pd_in_bits {
6962         u8         opcode[0x10];
6963         u8         uid[0x10];
6964
6965         u8         reserved_at_20[0x10];
6966         u8         op_mod[0x10];
6967
6968         u8         reserved_at_40[0x8];
6969         u8         pd[0x18];
6970
6971         u8         reserved_at_60[0x20];
6972 };
6973
6974 struct mlx5_ifc_dealloc_flow_counter_out_bits {
6975         u8         status[0x8];
6976         u8         reserved_at_8[0x18];
6977
6978         u8         syndrome[0x20];
6979
6980         u8         reserved_at_40[0x40];
6981 };
6982
6983 struct mlx5_ifc_dealloc_flow_counter_in_bits {
6984         u8         opcode[0x10];
6985         u8         reserved_at_10[0x10];
6986
6987         u8         reserved_at_20[0x10];
6988         u8         op_mod[0x10];
6989
6990         u8         flow_counter_id[0x20];
6991
6992         u8         reserved_at_60[0x20];
6993 };
6994
6995 struct mlx5_ifc_create_xrq_out_bits {
6996         u8         status[0x8];
6997         u8         reserved_at_8[0x18];
6998
6999         u8         syndrome[0x20];
7000
7001         u8         reserved_at_40[0x8];
7002         u8         xrqn[0x18];
7003
7004         u8         reserved_at_60[0x20];
7005 };
7006
7007 struct mlx5_ifc_create_xrq_in_bits {
7008         u8         opcode[0x10];
7009         u8         uid[0x10];
7010
7011         u8         reserved_at_20[0x10];
7012         u8         op_mod[0x10];
7013
7014         u8         reserved_at_40[0x40];
7015
7016         struct mlx5_ifc_xrqc_bits xrq_context;
7017 };
7018
7019 struct mlx5_ifc_create_xrc_srq_out_bits {
7020         u8         status[0x8];
7021         u8         reserved_at_8[0x18];
7022
7023         u8         syndrome[0x20];
7024
7025         u8         reserved_at_40[0x8];
7026         u8         xrc_srqn[0x18];
7027
7028         u8         reserved_at_60[0x20];
7029 };
7030
7031 struct mlx5_ifc_create_xrc_srq_in_bits {
7032         u8         opcode[0x10];
7033         u8         uid[0x10];
7034
7035         u8         reserved_at_20[0x10];
7036         u8         op_mod[0x10];
7037
7038         u8         reserved_at_40[0x40];
7039
7040         struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
7041
7042         u8         reserved_at_280[0x60];
7043
7044         u8         xrc_srq_umem_valid[0x1];
7045         u8         reserved_at_2e1[0x1f];
7046
7047         u8         reserved_at_300[0x580];
7048
7049         u8         pas[0][0x40];
7050 };
7051
7052 struct mlx5_ifc_create_tis_out_bits {
7053         u8         status[0x8];
7054         u8         reserved_at_8[0x18];
7055
7056         u8         syndrome[0x20];
7057
7058         u8         reserved_at_40[0x8];
7059         u8         tisn[0x18];
7060
7061         u8         reserved_at_60[0x20];
7062 };
7063
7064 struct mlx5_ifc_create_tis_in_bits {
7065         u8         opcode[0x10];
7066         u8         uid[0x10];
7067
7068         u8         reserved_at_20[0x10];
7069         u8         op_mod[0x10];
7070
7071         u8         reserved_at_40[0xc0];
7072
7073         struct mlx5_ifc_tisc_bits ctx;
7074 };
7075
7076 struct mlx5_ifc_create_tir_out_bits {
7077         u8         status[0x8];
7078         u8         icm_address_63_40[0x18];
7079
7080         u8         syndrome[0x20];
7081
7082         u8         icm_address_39_32[0x8];
7083         u8         tirn[0x18];
7084
7085         u8         icm_address_31_0[0x20];
7086 };
7087
7088 struct mlx5_ifc_create_tir_in_bits {
7089         u8         opcode[0x10];
7090         u8         uid[0x10];
7091
7092         u8         reserved_at_20[0x10];
7093         u8         op_mod[0x10];
7094
7095         u8         reserved_at_40[0xc0];
7096
7097         struct mlx5_ifc_tirc_bits ctx;
7098 };
7099
7100 struct mlx5_ifc_create_srq_out_bits {
7101         u8         status[0x8];
7102         u8         reserved_at_8[0x18];
7103
7104         u8         syndrome[0x20];
7105
7106         u8         reserved_at_40[0x8];
7107         u8         srqn[0x18];
7108
7109         u8         reserved_at_60[0x20];
7110 };
7111
7112 struct mlx5_ifc_create_srq_in_bits {
7113         u8         opcode[0x10];
7114         u8         uid[0x10];
7115
7116         u8         reserved_at_20[0x10];
7117         u8         op_mod[0x10];
7118
7119         u8         reserved_at_40[0x40];
7120
7121         struct mlx5_ifc_srqc_bits srq_context_entry;
7122
7123         u8         reserved_at_280[0x600];
7124
7125         u8         pas[0][0x40];
7126 };
7127
7128 struct mlx5_ifc_create_sq_out_bits {
7129         u8         status[0x8];
7130         u8         reserved_at_8[0x18];
7131
7132         u8         syndrome[0x20];
7133
7134         u8         reserved_at_40[0x8];
7135         u8         sqn[0x18];
7136
7137         u8         reserved_at_60[0x20];
7138 };
7139
7140 struct mlx5_ifc_create_sq_in_bits {
7141         u8         opcode[0x10];
7142         u8         uid[0x10];
7143
7144         u8         reserved_at_20[0x10];
7145         u8         op_mod[0x10];
7146
7147         u8         reserved_at_40[0xc0];
7148
7149         struct mlx5_ifc_sqc_bits ctx;
7150 };
7151
7152 struct mlx5_ifc_create_scheduling_element_out_bits {
7153         u8         status[0x8];
7154         u8         reserved_at_8[0x18];
7155
7156         u8         syndrome[0x20];
7157
7158         u8         reserved_at_40[0x40];
7159
7160         u8         scheduling_element_id[0x20];
7161
7162         u8         reserved_at_a0[0x160];
7163 };
7164
7165 struct mlx5_ifc_create_scheduling_element_in_bits {
7166         u8         opcode[0x10];
7167         u8         reserved_at_10[0x10];
7168
7169         u8         reserved_at_20[0x10];
7170         u8         op_mod[0x10];
7171
7172         u8         scheduling_hierarchy[0x8];
7173         u8         reserved_at_48[0x18];
7174
7175         u8         reserved_at_60[0xa0];
7176
7177         struct mlx5_ifc_scheduling_context_bits scheduling_context;
7178
7179         u8         reserved_at_300[0x100];
7180 };
7181
7182 struct mlx5_ifc_create_rqt_out_bits {
7183         u8         status[0x8];
7184         u8         reserved_at_8[0x18];
7185
7186         u8         syndrome[0x20];
7187
7188         u8         reserved_at_40[0x8];
7189         u8         rqtn[0x18];
7190
7191         u8         reserved_at_60[0x20];
7192 };
7193
7194 struct mlx5_ifc_create_rqt_in_bits {
7195         u8         opcode[0x10];
7196         u8         uid[0x10];
7197
7198         u8         reserved_at_20[0x10];
7199         u8         op_mod[0x10];
7200
7201         u8         reserved_at_40[0xc0];
7202
7203         struct mlx5_ifc_rqtc_bits rqt_context;
7204 };
7205
7206 struct mlx5_ifc_create_rq_out_bits {
7207         u8         status[0x8];
7208         u8         reserved_at_8[0x18];
7209
7210         u8         syndrome[0x20];
7211
7212         u8         reserved_at_40[0x8];
7213         u8         rqn[0x18];
7214
7215         u8         reserved_at_60[0x20];
7216 };
7217
7218 struct mlx5_ifc_create_rq_in_bits {
7219         u8         opcode[0x10];
7220         u8         uid[0x10];
7221
7222         u8         reserved_at_20[0x10];
7223         u8         op_mod[0x10];
7224
7225         u8         reserved_at_40[0xc0];
7226
7227         struct mlx5_ifc_rqc_bits ctx;
7228 };
7229
7230 struct mlx5_ifc_create_rmp_out_bits {
7231         u8         status[0x8];
7232         u8         reserved_at_8[0x18];
7233
7234         u8         syndrome[0x20];
7235
7236         u8         reserved_at_40[0x8];
7237         u8         rmpn[0x18];
7238
7239         u8         reserved_at_60[0x20];
7240 };
7241
7242 struct mlx5_ifc_create_rmp_in_bits {
7243         u8         opcode[0x10];
7244         u8         uid[0x10];
7245
7246         u8         reserved_at_20[0x10];
7247         u8         op_mod[0x10];
7248
7249         u8         reserved_at_40[0xc0];
7250
7251         struct mlx5_ifc_rmpc_bits ctx;
7252 };
7253
7254 struct mlx5_ifc_create_qp_out_bits {
7255         u8         status[0x8];
7256         u8         reserved_at_8[0x18];
7257
7258         u8         syndrome[0x20];
7259
7260         u8         reserved_at_40[0x8];
7261         u8         qpn[0x18];
7262
7263         u8         reserved_at_60[0x20];
7264 };
7265
7266 struct mlx5_ifc_create_qp_in_bits {
7267         u8         opcode[0x10];
7268         u8         uid[0x10];
7269
7270         u8         reserved_at_20[0x10];
7271         u8         op_mod[0x10];
7272
7273         u8         reserved_at_40[0x40];
7274
7275         u8         opt_param_mask[0x20];
7276
7277         u8         reserved_at_a0[0x20];
7278
7279         struct mlx5_ifc_qpc_bits qpc;
7280
7281         u8         reserved_at_800[0x60];
7282
7283         u8         wq_umem_valid[0x1];
7284         u8         reserved_at_861[0x1f];
7285
7286         u8         pas[0][0x40];
7287 };
7288
7289 struct mlx5_ifc_create_psv_out_bits {
7290         u8         status[0x8];
7291         u8         reserved_at_8[0x18];
7292
7293         u8         syndrome[0x20];
7294
7295         u8         reserved_at_40[0x40];
7296
7297         u8         reserved_at_80[0x8];
7298         u8         psv0_index[0x18];
7299
7300         u8         reserved_at_a0[0x8];
7301         u8         psv1_index[0x18];
7302
7303         u8         reserved_at_c0[0x8];
7304         u8         psv2_index[0x18];
7305
7306         u8         reserved_at_e0[0x8];
7307         u8         psv3_index[0x18];
7308 };
7309
7310 struct mlx5_ifc_create_psv_in_bits {
7311         u8         opcode[0x10];
7312         u8         reserved_at_10[0x10];
7313
7314         u8         reserved_at_20[0x10];
7315         u8         op_mod[0x10];
7316
7317         u8         num_psv[0x4];
7318         u8         reserved_at_44[0x4];
7319         u8         pd[0x18];
7320
7321         u8         reserved_at_60[0x20];
7322 };
7323
7324 struct mlx5_ifc_create_mkey_out_bits {
7325         u8         status[0x8];
7326         u8         reserved_at_8[0x18];
7327
7328         u8         syndrome[0x20];
7329
7330         u8         reserved_at_40[0x8];
7331         u8         mkey_index[0x18];
7332
7333         u8         reserved_at_60[0x20];
7334 };
7335
7336 struct mlx5_ifc_create_mkey_in_bits {
7337         u8         opcode[0x10];
7338         u8         reserved_at_10[0x10];
7339
7340         u8         reserved_at_20[0x10];
7341         u8         op_mod[0x10];
7342
7343         u8         reserved_at_40[0x20];
7344
7345         u8         pg_access[0x1];
7346         u8         mkey_umem_valid[0x1];
7347         u8         reserved_at_62[0x1e];
7348
7349         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
7350
7351         u8         reserved_at_280[0x80];
7352
7353         u8         translations_octword_actual_size[0x20];
7354
7355         u8         reserved_at_320[0x560];
7356
7357         u8         klm_pas_mtt[0][0x20];
7358 };
7359
7360 struct mlx5_ifc_create_flow_table_out_bits {
7361         u8         status[0x8];
7362         u8         reserved_at_8[0x18];
7363
7364         u8         syndrome[0x20];
7365
7366         u8         reserved_at_40[0x8];
7367         u8         table_id[0x18];
7368
7369         u8         reserved_at_60[0x20];
7370 };
7371
7372 struct mlx5_ifc_flow_table_context_bits {
7373         u8         reformat_en[0x1];
7374         u8         decap_en[0x1];
7375         u8         reserved_at_2[0x1];
7376         u8         termination_table[0x1];
7377         u8         table_miss_action[0x4];
7378         u8         level[0x8];
7379         u8         reserved_at_10[0x8];
7380         u8         log_size[0x8];
7381
7382         u8         reserved_at_20[0x8];
7383         u8         table_miss_id[0x18];
7384
7385         u8         reserved_at_40[0x8];
7386         u8         lag_master_next_table_id[0x18];
7387
7388         u8         reserved_at_60[0xe0];
7389 };
7390
7391 struct mlx5_ifc_create_flow_table_in_bits {
7392         u8         opcode[0x10];
7393         u8         reserved_at_10[0x10];
7394
7395         u8         reserved_at_20[0x10];
7396         u8         op_mod[0x10];
7397
7398         u8         other_vport[0x1];
7399         u8         reserved_at_41[0xf];
7400         u8         vport_number[0x10];
7401
7402         u8         reserved_at_60[0x20];
7403
7404         u8         table_type[0x8];
7405         u8         reserved_at_88[0x18];
7406
7407         u8         reserved_at_a0[0x20];
7408
7409         struct mlx5_ifc_flow_table_context_bits flow_table_context;
7410 };
7411
7412 struct mlx5_ifc_create_flow_group_out_bits {
7413         u8         status[0x8];
7414         u8         reserved_at_8[0x18];
7415
7416         u8         syndrome[0x20];
7417
7418         u8         reserved_at_40[0x8];
7419         u8         group_id[0x18];
7420
7421         u8         reserved_at_60[0x20];
7422 };
7423
7424 enum {
7425         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS     = 0x0,
7426         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS   = 0x1,
7427         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS     = 0x2,
7428         MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
7429 };
7430
7431 struct mlx5_ifc_create_flow_group_in_bits {
7432         u8         opcode[0x10];
7433         u8         reserved_at_10[0x10];
7434
7435         u8         reserved_at_20[0x10];
7436         u8         op_mod[0x10];
7437
7438         u8         other_vport[0x1];
7439         u8         reserved_at_41[0xf];
7440         u8         vport_number[0x10];
7441
7442         u8         reserved_at_60[0x20];
7443
7444         u8         table_type[0x8];
7445         u8         reserved_at_88[0x18];
7446
7447         u8         reserved_at_a0[0x8];
7448         u8         table_id[0x18];
7449
7450         u8         source_eswitch_owner_vhca_id_valid[0x1];
7451
7452         u8         reserved_at_c1[0x1f];
7453
7454         u8         start_flow_index[0x20];
7455
7456         u8         reserved_at_100[0x20];
7457
7458         u8         end_flow_index[0x20];
7459
7460         u8         reserved_at_140[0xa0];
7461
7462         u8         reserved_at_1e0[0x18];
7463         u8         match_criteria_enable[0x8];
7464
7465         struct mlx5_ifc_fte_match_param_bits match_criteria;
7466
7467         u8         reserved_at_1200[0xe00];
7468 };
7469
7470 struct mlx5_ifc_create_eq_out_bits {
7471         u8         status[0x8];
7472         u8         reserved_at_8[0x18];
7473
7474         u8         syndrome[0x20];
7475
7476         u8         reserved_at_40[0x18];
7477         u8         eq_number[0x8];
7478
7479         u8         reserved_at_60[0x20];
7480 };
7481
7482 struct mlx5_ifc_create_eq_in_bits {
7483         u8         opcode[0x10];
7484         u8         uid[0x10];
7485
7486         u8         reserved_at_20[0x10];
7487         u8         op_mod[0x10];
7488
7489         u8         reserved_at_40[0x40];
7490
7491         struct mlx5_ifc_eqc_bits eq_context_entry;
7492
7493         u8         reserved_at_280[0x40];
7494
7495         u8         event_bitmask[4][0x40];
7496
7497         u8         reserved_at_3c0[0x4c0];
7498
7499         u8         pas[0][0x40];
7500 };
7501
7502 struct mlx5_ifc_create_dct_out_bits {
7503         u8         status[0x8];
7504         u8         reserved_at_8[0x18];
7505
7506         u8         syndrome[0x20];
7507
7508         u8         reserved_at_40[0x8];
7509         u8         dctn[0x18];
7510
7511         u8         reserved_at_60[0x20];
7512 };
7513
7514 struct mlx5_ifc_create_dct_in_bits {
7515         u8         opcode[0x10];
7516         u8         uid[0x10];
7517
7518         u8         reserved_at_20[0x10];
7519         u8         op_mod[0x10];
7520
7521         u8         reserved_at_40[0x40];
7522
7523         struct mlx5_ifc_dctc_bits dct_context_entry;
7524
7525         u8         reserved_at_280[0x180];
7526 };
7527
7528 struct mlx5_ifc_create_cq_out_bits {
7529         u8         status[0x8];
7530         u8         reserved_at_8[0x18];
7531
7532         u8         syndrome[0x20];
7533
7534         u8         reserved_at_40[0x8];
7535         u8         cqn[0x18];
7536
7537         u8         reserved_at_60[0x20];
7538 };
7539
7540 struct mlx5_ifc_create_cq_in_bits {
7541         u8         opcode[0x10];
7542         u8         uid[0x10];
7543
7544         u8         reserved_at_20[0x10];
7545         u8         op_mod[0x10];
7546
7547         u8         reserved_at_40[0x40];
7548
7549         struct mlx5_ifc_cqc_bits cq_context;
7550
7551         u8         reserved_at_280[0x60];
7552
7553         u8         cq_umem_valid[0x1];
7554         u8         reserved_at_2e1[0x59f];
7555
7556         u8         pas[0][0x40];
7557 };
7558
7559 struct mlx5_ifc_config_int_moderation_out_bits {
7560         u8         status[0x8];
7561         u8         reserved_at_8[0x18];
7562
7563         u8         syndrome[0x20];
7564
7565         u8         reserved_at_40[0x4];
7566         u8         min_delay[0xc];
7567         u8         int_vector[0x10];
7568
7569         u8         reserved_at_60[0x20];
7570 };
7571
7572 enum {
7573         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE  = 0x0,
7574         MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ   = 0x1,
7575 };
7576
7577 struct mlx5_ifc_config_int_moderation_in_bits {
7578         u8         opcode[0x10];
7579         u8         reserved_at_10[0x10];
7580
7581         u8         reserved_at_20[0x10];
7582         u8         op_mod[0x10];
7583
7584         u8         reserved_at_40[0x4];
7585         u8         min_delay[0xc];
7586         u8         int_vector[0x10];
7587
7588         u8         reserved_at_60[0x20];
7589 };
7590
7591 struct mlx5_ifc_attach_to_mcg_out_bits {
7592         u8         status[0x8];
7593         u8         reserved_at_8[0x18];
7594
7595         u8         syndrome[0x20];
7596
7597         u8         reserved_at_40[0x40];
7598 };
7599
7600 struct mlx5_ifc_attach_to_mcg_in_bits {
7601         u8         opcode[0x10];
7602         u8         uid[0x10];
7603
7604         u8         reserved_at_20[0x10];
7605         u8         op_mod[0x10];
7606
7607         u8         reserved_at_40[0x8];
7608         u8         qpn[0x18];
7609
7610         u8         reserved_at_60[0x20];
7611
7612         u8         multicast_gid[16][0x8];
7613 };
7614
7615 struct mlx5_ifc_arm_xrq_out_bits {
7616         u8         status[0x8];
7617         u8         reserved_at_8[0x18];
7618
7619         u8         syndrome[0x20];
7620
7621         u8         reserved_at_40[0x40];
7622 };
7623
7624 struct mlx5_ifc_arm_xrq_in_bits {
7625         u8         opcode[0x10];
7626         u8         reserved_at_10[0x10];
7627
7628         u8         reserved_at_20[0x10];
7629         u8         op_mod[0x10];
7630
7631         u8         reserved_at_40[0x8];
7632         u8         xrqn[0x18];
7633
7634         u8         reserved_at_60[0x10];
7635         u8         lwm[0x10];
7636 };
7637
7638 struct mlx5_ifc_arm_xrc_srq_out_bits {
7639         u8         status[0x8];
7640         u8         reserved_at_8[0x18];
7641
7642         u8         syndrome[0x20];
7643
7644         u8         reserved_at_40[0x40];
7645 };
7646
7647 enum {
7648         MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ  = 0x1,
7649 };
7650
7651 struct mlx5_ifc_arm_xrc_srq_in_bits {
7652         u8         opcode[0x10];
7653         u8         uid[0x10];
7654
7655         u8         reserved_at_20[0x10];
7656         u8         op_mod[0x10];
7657
7658         u8         reserved_at_40[0x8];
7659         u8         xrc_srqn[0x18];
7660
7661         u8         reserved_at_60[0x10];
7662         u8         lwm[0x10];
7663 };
7664
7665 struct mlx5_ifc_arm_rq_out_bits {
7666         u8         status[0x8];
7667         u8         reserved_at_8[0x18];
7668
7669         u8         syndrome[0x20];
7670
7671         u8         reserved_at_40[0x40];
7672 };
7673
7674 enum {
7675         MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7676         MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
7677 };
7678
7679 struct mlx5_ifc_arm_rq_in_bits {
7680         u8         opcode[0x10];
7681         u8         uid[0x10];
7682
7683         u8         reserved_at_20[0x10];
7684         u8         op_mod[0x10];
7685
7686         u8         reserved_at_40[0x8];
7687         u8         srq_number[0x18];
7688
7689         u8         reserved_at_60[0x10];
7690         u8         lwm[0x10];
7691 };
7692
7693 struct mlx5_ifc_arm_dct_out_bits {
7694         u8         status[0x8];
7695         u8         reserved_at_8[0x18];
7696
7697         u8         syndrome[0x20];
7698
7699         u8         reserved_at_40[0x40];
7700 };
7701
7702 struct mlx5_ifc_arm_dct_in_bits {
7703         u8         opcode[0x10];
7704         u8         reserved_at_10[0x10];
7705
7706         u8         reserved_at_20[0x10];
7707         u8         op_mod[0x10];
7708
7709         u8         reserved_at_40[0x8];
7710         u8         dct_number[0x18];
7711
7712         u8         reserved_at_60[0x20];
7713 };
7714
7715 struct mlx5_ifc_alloc_xrcd_out_bits {
7716         u8         status[0x8];
7717         u8         reserved_at_8[0x18];
7718
7719         u8         syndrome[0x20];
7720
7721         u8         reserved_at_40[0x8];
7722         u8         xrcd[0x18];
7723
7724         u8         reserved_at_60[0x20];
7725 };
7726
7727 struct mlx5_ifc_alloc_xrcd_in_bits {
7728         u8         opcode[0x10];
7729         u8         uid[0x10];
7730
7731         u8         reserved_at_20[0x10];
7732         u8         op_mod[0x10];
7733
7734         u8         reserved_at_40[0x40];
7735 };
7736
7737 struct mlx5_ifc_alloc_uar_out_bits {
7738         u8         status[0x8];
7739         u8         reserved_at_8[0x18];
7740
7741         u8         syndrome[0x20];
7742
7743         u8         reserved_at_40[0x8];
7744         u8         uar[0x18];
7745
7746         u8         reserved_at_60[0x20];
7747 };
7748
7749 struct mlx5_ifc_alloc_uar_in_bits {
7750         u8         opcode[0x10];
7751         u8         reserved_at_10[0x10];
7752
7753         u8         reserved_at_20[0x10];
7754         u8         op_mod[0x10];
7755
7756         u8         reserved_at_40[0x40];
7757 };
7758
7759 struct mlx5_ifc_alloc_transport_domain_out_bits {
7760         u8         status[0x8];
7761         u8         reserved_at_8[0x18];
7762
7763         u8         syndrome[0x20];
7764
7765         u8         reserved_at_40[0x8];
7766         u8         transport_domain[0x18];
7767
7768         u8         reserved_at_60[0x20];
7769 };
7770
7771 struct mlx5_ifc_alloc_transport_domain_in_bits {
7772         u8         opcode[0x10];
7773         u8         uid[0x10];
7774
7775         u8         reserved_at_20[0x10];
7776         u8         op_mod[0x10];
7777
7778         u8         reserved_at_40[0x40];
7779 };
7780
7781 struct mlx5_ifc_alloc_q_counter_out_bits {
7782         u8         status[0x8];
7783         u8         reserved_at_8[0x18];
7784
7785         u8         syndrome[0x20];
7786
7787         u8         reserved_at_40[0x18];
7788         u8         counter_set_id[0x8];
7789
7790         u8         reserved_at_60[0x20];
7791 };
7792
7793 struct mlx5_ifc_alloc_q_counter_in_bits {
7794         u8         opcode[0x10];
7795         u8         uid[0x10];
7796
7797         u8         reserved_at_20[0x10];
7798         u8         op_mod[0x10];
7799
7800         u8         reserved_at_40[0x40];
7801 };
7802
7803 struct mlx5_ifc_alloc_pd_out_bits {
7804         u8         status[0x8];
7805         u8         reserved_at_8[0x18];
7806
7807         u8         syndrome[0x20];
7808
7809         u8         reserved_at_40[0x8];
7810         u8         pd[0x18];
7811
7812         u8         reserved_at_60[0x20];
7813 };
7814
7815 struct mlx5_ifc_alloc_pd_in_bits {
7816         u8         opcode[0x10];
7817         u8         uid[0x10];
7818
7819         u8         reserved_at_20[0x10];
7820         u8         op_mod[0x10];
7821
7822         u8         reserved_at_40[0x40];
7823 };
7824
7825 struct mlx5_ifc_alloc_flow_counter_out_bits {
7826         u8         status[0x8];
7827         u8         reserved_at_8[0x18];
7828
7829         u8         syndrome[0x20];
7830
7831         u8         flow_counter_id[0x20];
7832
7833         u8         reserved_at_60[0x20];
7834 };
7835
7836 struct mlx5_ifc_alloc_flow_counter_in_bits {
7837         u8         opcode[0x10];
7838         u8         reserved_at_10[0x10];
7839
7840         u8         reserved_at_20[0x10];
7841         u8         op_mod[0x10];
7842
7843         u8         reserved_at_40[0x38];
7844         u8         flow_counter_bulk[0x8];
7845 };
7846
7847 struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7848         u8         status[0x8];
7849         u8         reserved_at_8[0x18];
7850
7851         u8         syndrome[0x20];
7852
7853         u8         reserved_at_40[0x40];
7854 };
7855
7856 struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7857         u8         opcode[0x10];
7858         u8         reserved_at_10[0x10];
7859
7860         u8         reserved_at_20[0x10];
7861         u8         op_mod[0x10];
7862
7863         u8         reserved_at_40[0x20];
7864
7865         u8         reserved_at_60[0x10];
7866         u8         vxlan_udp_port[0x10];
7867 };
7868
7869 struct mlx5_ifc_set_pp_rate_limit_out_bits {
7870         u8         status[0x8];
7871         u8         reserved_at_8[0x18];
7872
7873         u8         syndrome[0x20];
7874
7875         u8         reserved_at_40[0x40];
7876 };
7877
7878 struct mlx5_ifc_set_pp_rate_limit_in_bits {
7879         u8         opcode[0x10];
7880         u8         reserved_at_10[0x10];
7881
7882         u8         reserved_at_20[0x10];
7883         u8         op_mod[0x10];
7884
7885         u8         reserved_at_40[0x10];
7886         u8         rate_limit_index[0x10];
7887
7888         u8         reserved_at_60[0x20];
7889
7890         u8         rate_limit[0x20];
7891
7892         u8         burst_upper_bound[0x20];
7893
7894         u8         reserved_at_c0[0x10];
7895         u8         typical_packet_size[0x10];
7896
7897         u8         reserved_at_e0[0x120];
7898 };
7899
7900 struct mlx5_ifc_access_register_out_bits {
7901         u8         status[0x8];
7902         u8         reserved_at_8[0x18];
7903
7904         u8         syndrome[0x20];
7905
7906         u8         reserved_at_40[0x40];
7907
7908         u8         register_data[0][0x20];
7909 };
7910
7911 enum {
7912         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
7913         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
7914 };
7915
7916 struct mlx5_ifc_access_register_in_bits {
7917         u8         opcode[0x10];
7918         u8         reserved_at_10[0x10];
7919
7920         u8         reserved_at_20[0x10];
7921         u8         op_mod[0x10];
7922
7923         u8         reserved_at_40[0x10];
7924         u8         register_id[0x10];
7925
7926         u8         argument[0x20];
7927
7928         u8         register_data[0][0x20];
7929 };
7930
7931 struct mlx5_ifc_sltp_reg_bits {
7932         u8         status[0x4];
7933         u8         version[0x4];
7934         u8         local_port[0x8];
7935         u8         pnat[0x2];
7936         u8         reserved_at_12[0x2];
7937         u8         lane[0x4];
7938         u8         reserved_at_18[0x8];
7939
7940         u8         reserved_at_20[0x20];
7941
7942         u8         reserved_at_40[0x7];
7943         u8         polarity[0x1];
7944         u8         ob_tap0[0x8];
7945         u8         ob_tap1[0x8];
7946         u8         ob_tap2[0x8];
7947
7948         u8         reserved_at_60[0xc];
7949         u8         ob_preemp_mode[0x4];
7950         u8         ob_reg[0x8];
7951         u8         ob_bias[0x8];
7952
7953         u8         reserved_at_80[0x20];
7954 };
7955
7956 struct mlx5_ifc_slrg_reg_bits {
7957         u8         status[0x4];
7958         u8         version[0x4];
7959         u8         local_port[0x8];
7960         u8         pnat[0x2];
7961         u8         reserved_at_12[0x2];
7962         u8         lane[0x4];
7963         u8         reserved_at_18[0x8];
7964
7965         u8         time_to_link_up[0x10];
7966         u8         reserved_at_30[0xc];
7967         u8         grade_lane_speed[0x4];
7968
7969         u8         grade_version[0x8];
7970         u8         grade[0x18];
7971
7972         u8         reserved_at_60[0x4];
7973         u8         height_grade_type[0x4];
7974         u8         height_grade[0x18];
7975
7976         u8         height_dz[0x10];
7977         u8         height_dv[0x10];
7978
7979         u8         reserved_at_a0[0x10];
7980         u8         height_sigma[0x10];
7981
7982         u8         reserved_at_c0[0x20];
7983
7984         u8         reserved_at_e0[0x4];
7985         u8         phase_grade_type[0x4];
7986         u8         phase_grade[0x18];
7987
7988         u8         reserved_at_100[0x8];
7989         u8         phase_eo_pos[0x8];
7990         u8         reserved_at_110[0x8];
7991         u8         phase_eo_neg[0x8];
7992
7993         u8         ffe_set_tested[0x10];
7994         u8         test_errors_per_lane[0x10];
7995 };
7996
7997 struct mlx5_ifc_pvlc_reg_bits {
7998         u8         reserved_at_0[0x8];
7999         u8         local_port[0x8];
8000         u8         reserved_at_10[0x10];
8001
8002         u8         reserved_at_20[0x1c];
8003         u8         vl_hw_cap[0x4];
8004
8005         u8         reserved_at_40[0x1c];
8006         u8         vl_admin[0x4];
8007
8008         u8         reserved_at_60[0x1c];
8009         u8         vl_operational[0x4];
8010 };
8011
8012 struct mlx5_ifc_pude_reg_bits {
8013         u8         swid[0x8];
8014         u8         local_port[0x8];
8015         u8         reserved_at_10[0x4];
8016         u8         admin_status[0x4];
8017         u8         reserved_at_18[0x4];
8018         u8         oper_status[0x4];
8019
8020         u8         reserved_at_20[0x60];
8021 };
8022
8023 struct mlx5_ifc_ptys_reg_bits {
8024         u8         reserved_at_0[0x1];
8025         u8         an_disable_admin[0x1];
8026         u8         an_disable_cap[0x1];
8027         u8         reserved_at_3[0x5];
8028         u8         local_port[0x8];
8029         u8         reserved_at_10[0xd];
8030         u8         proto_mask[0x3];
8031
8032         u8         an_status[0x4];
8033         u8         reserved_at_24[0x1c];
8034
8035         u8         ext_eth_proto_capability[0x20];
8036
8037         u8         eth_proto_capability[0x20];
8038
8039         u8         ib_link_width_capability[0x10];
8040         u8         ib_proto_capability[0x10];
8041
8042         u8         ext_eth_proto_admin[0x20];
8043
8044         u8         eth_proto_admin[0x20];
8045
8046         u8         ib_link_width_admin[0x10];
8047         u8         ib_proto_admin[0x10];
8048
8049         u8         ext_eth_proto_oper[0x20];
8050
8051         u8         eth_proto_oper[0x20];
8052
8053         u8         ib_link_width_oper[0x10];
8054         u8         ib_proto_oper[0x10];
8055
8056         u8         reserved_at_160[0x1c];
8057         u8         connector_type[0x4];
8058
8059         u8         eth_proto_lp_advertise[0x20];
8060
8061         u8         reserved_at_1a0[0x60];
8062 };
8063
8064 struct mlx5_ifc_mlcr_reg_bits {
8065         u8         reserved_at_0[0x8];
8066         u8         local_port[0x8];
8067         u8         reserved_at_10[0x20];
8068
8069         u8         beacon_duration[0x10];
8070         u8         reserved_at_40[0x10];
8071
8072         u8         beacon_remain[0x10];
8073 };
8074
8075 struct mlx5_ifc_ptas_reg_bits {
8076         u8         reserved_at_0[0x20];
8077
8078         u8         algorithm_options[0x10];
8079         u8         reserved_at_30[0x4];
8080         u8         repetitions_mode[0x4];
8081         u8         num_of_repetitions[0x8];
8082
8083         u8         grade_version[0x8];
8084         u8         height_grade_type[0x4];
8085         u8         phase_grade_type[0x4];
8086         u8         height_grade_weight[0x8];
8087         u8         phase_grade_weight[0x8];
8088
8089         u8         gisim_measure_bits[0x10];
8090         u8         adaptive_tap_measure_bits[0x10];
8091
8092         u8         ber_bath_high_error_threshold[0x10];
8093         u8         ber_bath_mid_error_threshold[0x10];
8094
8095         u8         ber_bath_low_error_threshold[0x10];
8096         u8         one_ratio_high_threshold[0x10];
8097
8098         u8         one_ratio_high_mid_threshold[0x10];
8099         u8         one_ratio_low_mid_threshold[0x10];
8100
8101         u8         one_ratio_low_threshold[0x10];
8102         u8         ndeo_error_threshold[0x10];
8103
8104         u8         mixer_offset_step_size[0x10];
8105         u8         reserved_at_110[0x8];
8106         u8         mix90_phase_for_voltage_bath[0x8];
8107
8108         u8         mixer_offset_start[0x10];
8109         u8         mixer_offset_end[0x10];
8110
8111         u8         reserved_at_140[0x15];
8112         u8         ber_test_time[0xb];
8113 };
8114
8115 struct mlx5_ifc_pspa_reg_bits {
8116         u8         swid[0x8];
8117         u8         local_port[0x8];
8118         u8         sub_port[0x8];
8119         u8         reserved_at_18[0x8];
8120
8121         u8         reserved_at_20[0x20];
8122 };
8123
8124 struct mlx5_ifc_pqdr_reg_bits {
8125         u8         reserved_at_0[0x8];
8126         u8         local_port[0x8];
8127         u8         reserved_at_10[0x5];
8128         u8         prio[0x3];
8129         u8         reserved_at_18[0x6];
8130         u8         mode[0x2];
8131
8132         u8         reserved_at_20[0x20];
8133
8134         u8         reserved_at_40[0x10];
8135         u8         min_threshold[0x10];
8136
8137         u8         reserved_at_60[0x10];
8138         u8         max_threshold[0x10];
8139
8140         u8         reserved_at_80[0x10];
8141         u8         mark_probability_denominator[0x10];
8142
8143         u8         reserved_at_a0[0x60];
8144 };
8145
8146 struct mlx5_ifc_ppsc_reg_bits {
8147         u8         reserved_at_0[0x8];
8148         u8         local_port[0x8];
8149         u8         reserved_at_10[0x10];
8150
8151         u8         reserved_at_20[0x60];
8152
8153         u8         reserved_at_80[0x1c];
8154         u8         wrps_admin[0x4];
8155
8156         u8         reserved_at_a0[0x1c];
8157         u8         wrps_status[0x4];
8158
8159         u8         reserved_at_c0[0x8];
8160         u8         up_threshold[0x8];
8161         u8         reserved_at_d0[0x8];
8162         u8         down_threshold[0x8];
8163
8164         u8         reserved_at_e0[0x20];
8165
8166         u8         reserved_at_100[0x1c];
8167         u8         srps_admin[0x4];
8168
8169         u8         reserved_at_120[0x1c];
8170         u8         srps_status[0x4];
8171
8172         u8         reserved_at_140[0x40];
8173 };
8174
8175 struct mlx5_ifc_pplr_reg_bits {
8176         u8         reserved_at_0[0x8];
8177         u8         local_port[0x8];
8178         u8         reserved_at_10[0x10];
8179
8180         u8         reserved_at_20[0x8];
8181         u8         lb_cap[0x8];
8182         u8         reserved_at_30[0x8];
8183         u8         lb_en[0x8];
8184 };
8185
8186 struct mlx5_ifc_pplm_reg_bits {
8187         u8         reserved_at_0[0x8];
8188         u8         local_port[0x8];
8189         u8         reserved_at_10[0x10];
8190
8191         u8         reserved_at_20[0x20];
8192
8193         u8         port_profile_mode[0x8];
8194         u8         static_port_profile[0x8];
8195         u8         active_port_profile[0x8];
8196         u8         reserved_at_58[0x8];
8197
8198         u8         retransmission_active[0x8];
8199         u8         fec_mode_active[0x18];
8200
8201         u8         rs_fec_correction_bypass_cap[0x4];
8202         u8         reserved_at_84[0x8];
8203         u8         fec_override_cap_56g[0x4];
8204         u8         fec_override_cap_100g[0x4];
8205         u8         fec_override_cap_50g[0x4];
8206         u8         fec_override_cap_25g[0x4];
8207         u8         fec_override_cap_10g_40g[0x4];
8208
8209         u8         rs_fec_correction_bypass_admin[0x4];
8210         u8         reserved_at_a4[0x8];
8211         u8         fec_override_admin_56g[0x4];
8212         u8         fec_override_admin_100g[0x4];
8213         u8         fec_override_admin_50g[0x4];
8214         u8         fec_override_admin_25g[0x4];
8215         u8         fec_override_admin_10g_40g[0x4];
8216 };
8217
8218 struct mlx5_ifc_ppcnt_reg_bits {
8219         u8         swid[0x8];
8220         u8         local_port[0x8];
8221         u8         pnat[0x2];
8222         u8         reserved_at_12[0x8];
8223         u8         grp[0x6];
8224
8225         u8         clr[0x1];
8226         u8         reserved_at_21[0x1c];
8227         u8         prio_tc[0x3];
8228
8229         union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
8230 };
8231
8232 struct mlx5_ifc_mpein_reg_bits {
8233         u8         reserved_at_0[0x2];
8234         u8         depth[0x6];
8235         u8         pcie_index[0x8];
8236         u8         node[0x8];
8237         u8         reserved_at_18[0x8];
8238
8239         u8         capability_mask[0x20];
8240
8241         u8         reserved_at_40[0x8];
8242         u8         link_width_enabled[0x8];
8243         u8         link_speed_enabled[0x10];
8244
8245         u8         lane0_physical_position[0x8];
8246         u8         link_width_active[0x8];
8247         u8         link_speed_active[0x10];
8248
8249         u8         num_of_pfs[0x10];
8250         u8         num_of_vfs[0x10];
8251
8252         u8         bdf0[0x10];
8253         u8         reserved_at_b0[0x10];
8254
8255         u8         max_read_request_size[0x4];
8256         u8         max_payload_size[0x4];
8257         u8         reserved_at_c8[0x5];
8258         u8         pwr_status[0x3];
8259         u8         port_type[0x4];
8260         u8         reserved_at_d4[0xb];
8261         u8         lane_reversal[0x1];
8262
8263         u8         reserved_at_e0[0x14];
8264         u8         pci_power[0xc];
8265
8266         u8         reserved_at_100[0x20];
8267
8268         u8         device_status[0x10];
8269         u8         port_state[0x8];
8270         u8         reserved_at_138[0x8];
8271
8272         u8         reserved_at_140[0x10];
8273         u8         receiver_detect_result[0x10];
8274
8275         u8         reserved_at_160[0x20];
8276 };
8277
8278 struct mlx5_ifc_mpcnt_reg_bits {
8279         u8         reserved_at_0[0x8];
8280         u8         pcie_index[0x8];
8281         u8         reserved_at_10[0xa];
8282         u8         grp[0x6];
8283
8284         u8         clr[0x1];
8285         u8         reserved_at_21[0x1f];
8286
8287         union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
8288 };
8289
8290 struct mlx5_ifc_ppad_reg_bits {
8291         u8         reserved_at_0[0x3];
8292         u8         single_mac[0x1];
8293         u8         reserved_at_4[0x4];
8294         u8         local_port[0x8];
8295         u8         mac_47_32[0x10];
8296
8297         u8         mac_31_0[0x20];
8298
8299         u8         reserved_at_40[0x40];
8300 };
8301
8302 struct mlx5_ifc_pmtu_reg_bits {
8303         u8         reserved_at_0[0x8];
8304         u8         local_port[0x8];
8305         u8         reserved_at_10[0x10];
8306
8307         u8         max_mtu[0x10];
8308         u8         reserved_at_30[0x10];
8309
8310         u8         admin_mtu[0x10];
8311         u8         reserved_at_50[0x10];
8312
8313         u8         oper_mtu[0x10];
8314         u8         reserved_at_70[0x10];
8315 };
8316
8317 struct mlx5_ifc_pmpr_reg_bits {
8318         u8         reserved_at_0[0x8];
8319         u8         module[0x8];
8320         u8         reserved_at_10[0x10];
8321
8322         u8         reserved_at_20[0x18];
8323         u8         attenuation_5g[0x8];
8324
8325         u8         reserved_at_40[0x18];
8326         u8         attenuation_7g[0x8];
8327
8328         u8         reserved_at_60[0x18];
8329         u8         attenuation_12g[0x8];
8330 };
8331
8332 struct mlx5_ifc_pmpe_reg_bits {
8333         u8         reserved_at_0[0x8];
8334         u8         module[0x8];
8335         u8         reserved_at_10[0xc];
8336         u8         module_status[0x4];
8337
8338         u8         reserved_at_20[0x60];
8339 };
8340
8341 struct mlx5_ifc_pmpc_reg_bits {
8342         u8         module_state_updated[32][0x8];
8343 };
8344
8345 struct mlx5_ifc_pmlpn_reg_bits {
8346         u8         reserved_at_0[0x4];
8347         u8         mlpn_status[0x4];
8348         u8         local_port[0x8];
8349         u8         reserved_at_10[0x10];
8350
8351         u8         e[0x1];
8352         u8         reserved_at_21[0x1f];
8353 };
8354
8355 struct mlx5_ifc_pmlp_reg_bits {
8356         u8         rxtx[0x1];
8357         u8         reserved_at_1[0x7];
8358         u8         local_port[0x8];
8359         u8         reserved_at_10[0x8];
8360         u8         width[0x8];
8361
8362         u8         lane0_module_mapping[0x20];
8363
8364         u8         lane1_module_mapping[0x20];
8365
8366         u8         lane2_module_mapping[0x20];
8367
8368         u8         lane3_module_mapping[0x20];
8369
8370         u8         reserved_at_a0[0x160];
8371 };
8372
8373 struct mlx5_ifc_pmaos_reg_bits {
8374         u8         reserved_at_0[0x8];
8375         u8         module[0x8];
8376         u8         reserved_at_10[0x4];
8377         u8         admin_status[0x4];
8378         u8         reserved_at_18[0x4];
8379         u8         oper_status[0x4];
8380
8381         u8         ase[0x1];
8382         u8         ee[0x1];
8383         u8         reserved_at_22[0x1c];
8384         u8         e[0x2];
8385
8386         u8         reserved_at_40[0x40];
8387 };
8388
8389 struct mlx5_ifc_plpc_reg_bits {
8390         u8         reserved_at_0[0x4];
8391         u8         profile_id[0xc];
8392         u8         reserved_at_10[0x4];
8393         u8         proto_mask[0x4];
8394         u8         reserved_at_18[0x8];
8395
8396         u8         reserved_at_20[0x10];
8397         u8         lane_speed[0x10];
8398
8399         u8         reserved_at_40[0x17];
8400         u8         lpbf[0x1];
8401         u8         fec_mode_policy[0x8];
8402
8403         u8         retransmission_capability[0x8];
8404         u8         fec_mode_capability[0x18];
8405
8406         u8         retransmission_support_admin[0x8];
8407         u8         fec_mode_support_admin[0x18];
8408
8409         u8         retransmission_request_admin[0x8];
8410         u8         fec_mode_request_admin[0x18];
8411
8412         u8         reserved_at_c0[0x80];
8413 };
8414
8415 struct mlx5_ifc_plib_reg_bits {
8416         u8         reserved_at_0[0x8];
8417         u8         local_port[0x8];
8418         u8         reserved_at_10[0x8];
8419         u8         ib_port[0x8];
8420
8421         u8         reserved_at_20[0x60];
8422 };
8423
8424 struct mlx5_ifc_plbf_reg_bits {
8425         u8         reserved_at_0[0x8];
8426         u8         local_port[0x8];
8427         u8         reserved_at_10[0xd];
8428         u8         lbf_mode[0x3];
8429
8430         u8         reserved_at_20[0x20];
8431 };
8432
8433 struct mlx5_ifc_pipg_reg_bits {
8434         u8         reserved_at_0[0x8];
8435         u8         local_port[0x8];
8436         u8         reserved_at_10[0x10];
8437
8438         u8         dic[0x1];
8439         u8         reserved_at_21[0x19];
8440         u8         ipg[0x4];
8441         u8         reserved_at_3e[0x2];
8442 };
8443
8444 struct mlx5_ifc_pifr_reg_bits {
8445         u8         reserved_at_0[0x8];
8446         u8         local_port[0x8];
8447         u8         reserved_at_10[0x10];
8448
8449         u8         reserved_at_20[0xe0];
8450
8451         u8         port_filter[8][0x20];
8452
8453         u8         port_filter_update_en[8][0x20];
8454 };
8455
8456 struct mlx5_ifc_pfcc_reg_bits {
8457         u8         reserved_at_0[0x8];
8458         u8         local_port[0x8];
8459         u8         reserved_at_10[0xb];
8460         u8         ppan_mask_n[0x1];
8461         u8         minor_stall_mask[0x1];
8462         u8         critical_stall_mask[0x1];
8463         u8         reserved_at_1e[0x2];
8464
8465         u8         ppan[0x4];
8466         u8         reserved_at_24[0x4];
8467         u8         prio_mask_tx[0x8];
8468         u8         reserved_at_30[0x8];
8469         u8         prio_mask_rx[0x8];
8470
8471         u8         pptx[0x1];
8472         u8         aptx[0x1];
8473         u8         pptx_mask_n[0x1];
8474         u8         reserved_at_43[0x5];
8475         u8         pfctx[0x8];
8476         u8         reserved_at_50[0x10];
8477
8478         u8         pprx[0x1];
8479         u8         aprx[0x1];
8480         u8         pprx_mask_n[0x1];
8481         u8         reserved_at_63[0x5];
8482         u8         pfcrx[0x8];
8483         u8         reserved_at_70[0x10];
8484
8485         u8         device_stall_minor_watermark[0x10];
8486         u8         device_stall_critical_watermark[0x10];
8487
8488         u8         reserved_at_a0[0x60];
8489 };
8490
8491 struct mlx5_ifc_pelc_reg_bits {
8492         u8         op[0x4];
8493         u8         reserved_at_4[0x4];
8494         u8         local_port[0x8];
8495         u8         reserved_at_10[0x10];
8496
8497         u8         op_admin[0x8];
8498         u8         op_capability[0x8];
8499         u8         op_request[0x8];
8500         u8         op_active[0x8];
8501
8502         u8         admin[0x40];
8503
8504         u8         capability[0x40];
8505
8506         u8         request[0x40];
8507
8508         u8         active[0x40];
8509
8510         u8         reserved_at_140[0x80];
8511 };
8512
8513 struct mlx5_ifc_peir_reg_bits {
8514         u8         reserved_at_0[0x8];
8515         u8         local_port[0x8];
8516         u8         reserved_at_10[0x10];
8517
8518         u8         reserved_at_20[0xc];
8519         u8         error_count[0x4];
8520         u8         reserved_at_30[0x10];
8521
8522         u8         reserved_at_40[0xc];
8523         u8         lane[0x4];
8524         u8         reserved_at_50[0x8];
8525         u8         error_type[0x8];
8526 };
8527
8528 struct mlx5_ifc_mpegc_reg_bits {
8529         u8         reserved_at_0[0x30];
8530         u8         field_select[0x10];
8531
8532         u8         tx_overflow_sense[0x1];
8533         u8         mark_cqe[0x1];
8534         u8         mark_cnp[0x1];
8535         u8         reserved_at_43[0x1b];
8536         u8         tx_lossy_overflow_oper[0x2];
8537
8538         u8         reserved_at_60[0x100];
8539 };
8540
8541 struct mlx5_ifc_pcam_enhanced_features_bits {
8542         u8         reserved_at_0[0x6d];
8543         u8         rx_icrc_encapsulated_counter[0x1];
8544         u8         reserved_at_6e[0x4];
8545         u8         ptys_extended_ethernet[0x1];
8546         u8         reserved_at_73[0x3];
8547         u8         pfcc_mask[0x1];
8548         u8         reserved_at_77[0x3];
8549         u8         per_lane_error_counters[0x1];
8550         u8         rx_buffer_fullness_counters[0x1];
8551         u8         ptys_connector_type[0x1];
8552         u8         reserved_at_7d[0x1];
8553         u8         ppcnt_discard_group[0x1];
8554         u8         ppcnt_statistical_group[0x1];
8555 };
8556
8557 struct mlx5_ifc_pcam_regs_5000_to_507f_bits {
8558         u8         port_access_reg_cap_mask_127_to_96[0x20];
8559         u8         port_access_reg_cap_mask_95_to_64[0x20];
8560
8561         u8         port_access_reg_cap_mask_63_to_36[0x1c];
8562         u8         pplm[0x1];
8563         u8         port_access_reg_cap_mask_34_to_32[0x3];
8564
8565         u8         port_access_reg_cap_mask_31_to_13[0x13];
8566         u8         pbmc[0x1];
8567         u8         pptb[0x1];
8568         u8         port_access_reg_cap_mask_10_to_09[0x2];
8569         u8         ppcnt[0x1];
8570         u8         port_access_reg_cap_mask_07_to_00[0x8];
8571 };
8572
8573 struct mlx5_ifc_pcam_reg_bits {
8574         u8         reserved_at_0[0x8];
8575         u8         feature_group[0x8];
8576         u8         reserved_at_10[0x8];
8577         u8         access_reg_group[0x8];
8578
8579         u8         reserved_at_20[0x20];
8580
8581         union {
8582                 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f;
8583                 u8         reserved_at_0[0x80];
8584         } port_access_reg_cap_mask;
8585
8586         u8         reserved_at_c0[0x80];
8587
8588         union {
8589                 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
8590                 u8         reserved_at_0[0x80];
8591         } feature_cap_mask;
8592
8593         u8         reserved_at_1c0[0xc0];
8594 };
8595
8596 struct mlx5_ifc_mcam_enhanced_features_bits {
8597         u8         reserved_at_0[0x6e];
8598         u8         pci_status_and_power[0x1];
8599         u8         reserved_at_6f[0x5];
8600         u8         mark_tx_action_cnp[0x1];
8601         u8         mark_tx_action_cqe[0x1];
8602         u8         dynamic_tx_overflow[0x1];
8603         u8         reserved_at_77[0x4];
8604         u8         pcie_outbound_stalled[0x1];
8605         u8         tx_overflow_buffer_pkt[0x1];
8606         u8         mtpps_enh_out_per_adj[0x1];
8607         u8         mtpps_fs[0x1];
8608         u8         pcie_performance_group[0x1];
8609 };
8610
8611 struct mlx5_ifc_mcam_access_reg_bits {
8612         u8         reserved_at_0[0x1c];
8613         u8         mcda[0x1];
8614         u8         mcc[0x1];
8615         u8         mcqi[0x1];
8616         u8         mcqs[0x1];
8617
8618         u8         regs_95_to_87[0x9];
8619         u8         mpegc[0x1];
8620         u8         regs_85_to_68[0x12];
8621         u8         tracer_registers[0x4];
8622
8623         u8         regs_63_to_32[0x20];
8624         u8         regs_31_to_0[0x20];
8625 };
8626
8627 struct mlx5_ifc_mcam_reg_bits {
8628         u8         reserved_at_0[0x8];
8629         u8         feature_group[0x8];
8630         u8         reserved_at_10[0x8];
8631         u8         access_reg_group[0x8];
8632
8633         u8         reserved_at_20[0x20];
8634
8635         union {
8636                 struct mlx5_ifc_mcam_access_reg_bits access_regs;
8637                 u8         reserved_at_0[0x80];
8638         } mng_access_reg_cap_mask;
8639
8640         u8         reserved_at_c0[0x80];
8641
8642         union {
8643                 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
8644                 u8         reserved_at_0[0x80];
8645         } mng_feature_cap_mask;
8646
8647         u8         reserved_at_1c0[0x80];
8648 };
8649
8650 struct mlx5_ifc_qcam_access_reg_cap_mask {
8651         u8         qcam_access_reg_cap_mask_127_to_20[0x6C];
8652         u8         qpdpm[0x1];
8653         u8         qcam_access_reg_cap_mask_18_to_4[0x0F];
8654         u8         qdpm[0x1];
8655         u8         qpts[0x1];
8656         u8         qcap[0x1];
8657         u8         qcam_access_reg_cap_mask_0[0x1];
8658 };
8659
8660 struct mlx5_ifc_qcam_qos_feature_cap_mask {
8661         u8         qcam_qos_feature_cap_mask_127_to_1[0x7F];
8662         u8         qpts_trust_both[0x1];
8663 };
8664
8665 struct mlx5_ifc_qcam_reg_bits {
8666         u8         reserved_at_0[0x8];
8667         u8         feature_group[0x8];
8668         u8         reserved_at_10[0x8];
8669         u8         access_reg_group[0x8];
8670         u8         reserved_at_20[0x20];
8671
8672         union {
8673                 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
8674                 u8  reserved_at_0[0x80];
8675         } qos_access_reg_cap_mask;
8676
8677         u8         reserved_at_c0[0x80];
8678
8679         union {
8680                 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
8681                 u8  reserved_at_0[0x80];
8682         } qos_feature_cap_mask;
8683
8684         u8         reserved_at_1c0[0x80];
8685 };
8686
8687 struct mlx5_ifc_core_dump_reg_bits {
8688         u8         reserved_at_0[0x18];
8689         u8         core_dump_type[0x8];
8690
8691         u8         reserved_at_20[0x30];
8692         u8         vhca_id[0x10];
8693
8694         u8         reserved_at_60[0x8];
8695         u8         qpn[0x18];
8696         u8         reserved_at_80[0x180];
8697 };
8698
8699 struct mlx5_ifc_pcap_reg_bits {
8700         u8         reserved_at_0[0x8];
8701         u8         local_port[0x8];
8702         u8         reserved_at_10[0x10];
8703
8704         u8         port_capability_mask[4][0x20];
8705 };
8706
8707 struct mlx5_ifc_paos_reg_bits {
8708         u8         swid[0x8];
8709         u8         local_port[0x8];
8710         u8         reserved_at_10[0x4];
8711         u8         admin_status[0x4];
8712         u8         reserved_at_18[0x4];
8713         u8         oper_status[0x4];
8714
8715         u8         ase[0x1];
8716         u8         ee[0x1];
8717         u8         reserved_at_22[0x1c];
8718         u8         e[0x2];
8719
8720         u8         reserved_at_40[0x40];
8721 };
8722
8723 struct mlx5_ifc_pamp_reg_bits {
8724         u8         reserved_at_0[0x8];
8725         u8         opamp_group[0x8];
8726         u8         reserved_at_10[0xc];
8727         u8         opamp_group_type[0x4];
8728
8729         u8         start_index[0x10];
8730         u8         reserved_at_30[0x4];
8731         u8         num_of_indices[0xc];
8732
8733         u8         index_data[18][0x10];
8734 };
8735
8736 struct mlx5_ifc_pcmr_reg_bits {
8737         u8         reserved_at_0[0x8];
8738         u8         local_port[0x8];
8739         u8         reserved_at_10[0x10];
8740         u8         entropy_force_cap[0x1];
8741         u8         entropy_calc_cap[0x1];
8742         u8         entropy_gre_calc_cap[0x1];
8743         u8         reserved_at_23[0x1b];
8744         u8         fcs_cap[0x1];
8745         u8         reserved_at_3f[0x1];
8746         u8         entropy_force[0x1];
8747         u8         entropy_calc[0x1];
8748         u8         entropy_gre_calc[0x1];
8749         u8         reserved_at_43[0x1b];
8750         u8         fcs_chk[0x1];
8751         u8         reserved_at_5f[0x1];
8752 };
8753
8754 struct mlx5_ifc_lane_2_module_mapping_bits {
8755         u8         reserved_at_0[0x6];
8756         u8         rx_lane[0x2];
8757         u8         reserved_at_8[0x6];
8758         u8         tx_lane[0x2];
8759         u8         reserved_at_10[0x8];
8760         u8         module[0x8];
8761 };
8762
8763 struct mlx5_ifc_bufferx_reg_bits {
8764         u8         reserved_at_0[0x6];
8765         u8         lossy[0x1];
8766         u8         epsb[0x1];
8767         u8         reserved_at_8[0xc];
8768         u8         size[0xc];
8769
8770         u8         xoff_threshold[0x10];
8771         u8         xon_threshold[0x10];
8772 };
8773
8774 struct mlx5_ifc_set_node_in_bits {
8775         u8         node_description[64][0x8];
8776 };
8777
8778 struct mlx5_ifc_register_power_settings_bits {
8779         u8         reserved_at_0[0x18];
8780         u8         power_settings_level[0x8];
8781
8782         u8         reserved_at_20[0x60];
8783 };
8784
8785 struct mlx5_ifc_register_host_endianness_bits {
8786         u8         he[0x1];
8787         u8         reserved_at_1[0x1f];
8788
8789         u8         reserved_at_20[0x60];
8790 };
8791
8792 struct mlx5_ifc_umr_pointer_desc_argument_bits {
8793         u8         reserved_at_0[0x20];
8794
8795         u8         mkey[0x20];
8796
8797         u8         addressh_63_32[0x20];
8798
8799         u8         addressl_31_0[0x20];
8800 };
8801
8802 struct mlx5_ifc_ud_adrs_vector_bits {
8803         u8         dc_key[0x40];
8804
8805         u8         ext[0x1];
8806         u8         reserved_at_41[0x7];
8807         u8         destination_qp_dct[0x18];
8808
8809         u8         static_rate[0x4];
8810         u8         sl_eth_prio[0x4];
8811         u8         fl[0x1];
8812         u8         mlid[0x7];
8813         u8         rlid_udp_sport[0x10];
8814
8815         u8         reserved_at_80[0x20];
8816
8817         u8         rmac_47_16[0x20];
8818
8819         u8         rmac_15_0[0x10];
8820         u8         tclass[0x8];
8821         u8         hop_limit[0x8];
8822
8823         u8         reserved_at_e0[0x1];
8824         u8         grh[0x1];
8825         u8         reserved_at_e2[0x2];
8826         u8         src_addr_index[0x8];
8827         u8         flow_label[0x14];
8828
8829         u8         rgid_rip[16][0x8];
8830 };
8831
8832 struct mlx5_ifc_pages_req_event_bits {
8833         u8         reserved_at_0[0x10];
8834         u8         function_id[0x10];
8835
8836         u8         num_pages[0x20];
8837
8838         u8         reserved_at_40[0xa0];
8839 };
8840
8841 struct mlx5_ifc_eqe_bits {
8842         u8         reserved_at_0[0x8];
8843         u8         event_type[0x8];
8844         u8         reserved_at_10[0x8];
8845         u8         event_sub_type[0x8];
8846
8847         u8         reserved_at_20[0xe0];
8848
8849         union mlx5_ifc_event_auto_bits event_data;
8850
8851         u8         reserved_at_1e0[0x10];
8852         u8         signature[0x8];
8853         u8         reserved_at_1f8[0x7];
8854         u8         owner[0x1];
8855 };
8856
8857 enum {
8858         MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT  = 0x7,
8859 };
8860
8861 struct mlx5_ifc_cmd_queue_entry_bits {
8862         u8         type[0x8];
8863         u8         reserved_at_8[0x18];
8864
8865         u8         input_length[0x20];
8866
8867         u8         input_mailbox_pointer_63_32[0x20];
8868
8869         u8         input_mailbox_pointer_31_9[0x17];
8870         u8         reserved_at_77[0x9];
8871
8872         u8         command_input_inline_data[16][0x8];
8873
8874         u8         command_output_inline_data[16][0x8];
8875
8876         u8         output_mailbox_pointer_63_32[0x20];
8877
8878         u8         output_mailbox_pointer_31_9[0x17];
8879         u8         reserved_at_1b7[0x9];
8880
8881         u8         output_length[0x20];
8882
8883         u8         token[0x8];
8884         u8         signature[0x8];
8885         u8         reserved_at_1f0[0x8];
8886         u8         status[0x7];
8887         u8         ownership[0x1];
8888 };
8889
8890 struct mlx5_ifc_cmd_out_bits {
8891         u8         status[0x8];
8892         u8         reserved_at_8[0x18];
8893
8894         u8         syndrome[0x20];
8895
8896         u8         command_output[0x20];
8897 };
8898
8899 struct mlx5_ifc_cmd_in_bits {
8900         u8         opcode[0x10];
8901         u8         reserved_at_10[0x10];
8902
8903         u8         reserved_at_20[0x10];
8904         u8         op_mod[0x10];
8905
8906         u8         command[0][0x20];
8907 };
8908
8909 struct mlx5_ifc_cmd_if_box_bits {
8910         u8         mailbox_data[512][0x8];
8911
8912         u8         reserved_at_1000[0x180];
8913
8914         u8         next_pointer_63_32[0x20];
8915
8916         u8         next_pointer_31_10[0x16];
8917         u8         reserved_at_11b6[0xa];
8918
8919         u8         block_number[0x20];
8920
8921         u8         reserved_at_11e0[0x8];
8922         u8         token[0x8];
8923         u8         ctrl_signature[0x8];
8924         u8         signature[0x8];
8925 };
8926
8927 struct mlx5_ifc_mtt_bits {
8928         u8         ptag_63_32[0x20];
8929
8930         u8         ptag_31_8[0x18];
8931         u8         reserved_at_38[0x6];
8932         u8         wr_en[0x1];
8933         u8         rd_en[0x1];
8934 };
8935
8936 struct mlx5_ifc_query_wol_rol_out_bits {
8937         u8         status[0x8];
8938         u8         reserved_at_8[0x18];
8939
8940         u8         syndrome[0x20];
8941
8942         u8         reserved_at_40[0x10];
8943         u8         rol_mode[0x8];
8944         u8         wol_mode[0x8];
8945
8946         u8         reserved_at_60[0x20];
8947 };
8948
8949 struct mlx5_ifc_query_wol_rol_in_bits {
8950         u8         opcode[0x10];
8951         u8         reserved_at_10[0x10];
8952
8953         u8         reserved_at_20[0x10];
8954         u8         op_mod[0x10];
8955
8956         u8         reserved_at_40[0x40];
8957 };
8958
8959 struct mlx5_ifc_set_wol_rol_out_bits {
8960         u8         status[0x8];
8961         u8         reserved_at_8[0x18];
8962
8963         u8         syndrome[0x20];
8964
8965         u8         reserved_at_40[0x40];
8966 };
8967
8968 struct mlx5_ifc_set_wol_rol_in_bits {
8969         u8         opcode[0x10];
8970         u8         reserved_at_10[0x10];
8971
8972         u8         reserved_at_20[0x10];
8973         u8         op_mod[0x10];
8974
8975         u8         rol_mode_valid[0x1];
8976         u8         wol_mode_valid[0x1];
8977         u8         reserved_at_42[0xe];
8978         u8         rol_mode[0x8];
8979         u8         wol_mode[0x8];
8980
8981         u8         reserved_at_60[0x20];
8982 };
8983
8984 enum {
8985         MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER  = 0x0,
8986         MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED     = 0x1,
8987         MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC  = 0x2,
8988 };
8989
8990 enum {
8991         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER  = 0x0,
8992         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED     = 0x1,
8993         MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC  = 0x2,
8994 };
8995
8996 enum {
8997         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR              = 0x1,
8998         MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC                   = 0x7,
8999         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR                 = 0x8,
9000         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR                   = 0x9,
9001         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR            = 0xa,
9002         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR                 = 0xb,
9003         MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN  = 0xc,
9004         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR                    = 0xd,
9005         MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV                       = 0xe,
9006         MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR                    = 0xf,
9007         MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR                = 0x10,
9008 };
9009
9010 struct mlx5_ifc_initial_seg_bits {
9011         u8         fw_rev_minor[0x10];
9012         u8         fw_rev_major[0x10];
9013
9014         u8         cmd_interface_rev[0x10];
9015         u8         fw_rev_subminor[0x10];
9016
9017         u8         reserved_at_40[0x40];
9018
9019         u8         cmdq_phy_addr_63_32[0x20];
9020
9021         u8         cmdq_phy_addr_31_12[0x14];
9022         u8         reserved_at_b4[0x2];
9023         u8         nic_interface[0x2];
9024         u8         log_cmdq_size[0x4];
9025         u8         log_cmdq_stride[0x4];
9026
9027         u8         command_doorbell_vector[0x20];
9028
9029         u8         reserved_at_e0[0xf00];
9030
9031         u8         initializing[0x1];
9032         u8         reserved_at_fe1[0x4];
9033         u8         nic_interface_supported[0x3];
9034         u8         embedded_cpu[0x1];
9035         u8         reserved_at_fe9[0x17];
9036
9037         struct mlx5_ifc_health_buffer_bits health_buffer;
9038
9039         u8         no_dram_nic_offset[0x20];
9040
9041         u8         reserved_at_1220[0x6e40];
9042
9043         u8         reserved_at_8060[0x1f];
9044         u8         clear_int[0x1];
9045
9046         u8         health_syndrome[0x8];
9047         u8         health_counter[0x18];
9048
9049         u8         reserved_at_80a0[0x17fc0];
9050 };
9051
9052 struct mlx5_ifc_mtpps_reg_bits {
9053         u8         reserved_at_0[0xc];
9054         u8         cap_number_of_pps_pins[0x4];
9055         u8         reserved_at_10[0x4];
9056         u8         cap_max_num_of_pps_in_pins[0x4];
9057         u8         reserved_at_18[0x4];
9058         u8         cap_max_num_of_pps_out_pins[0x4];
9059
9060         u8         reserved_at_20[0x24];
9061         u8         cap_pin_3_mode[0x4];
9062         u8         reserved_at_48[0x4];
9063         u8         cap_pin_2_mode[0x4];
9064         u8         reserved_at_50[0x4];
9065         u8         cap_pin_1_mode[0x4];
9066         u8         reserved_at_58[0x4];
9067         u8         cap_pin_0_mode[0x4];
9068
9069         u8         reserved_at_60[0x4];
9070         u8         cap_pin_7_mode[0x4];
9071         u8         reserved_at_68[0x4];
9072         u8         cap_pin_6_mode[0x4];
9073         u8         reserved_at_70[0x4];
9074         u8         cap_pin_5_mode[0x4];
9075         u8         reserved_at_78[0x4];
9076         u8         cap_pin_4_mode[0x4];
9077
9078         u8         field_select[0x20];
9079         u8         reserved_at_a0[0x60];
9080
9081         u8         enable[0x1];
9082         u8         reserved_at_101[0xb];
9083         u8         pattern[0x4];
9084         u8         reserved_at_110[0x4];
9085         u8         pin_mode[0x4];
9086         u8         pin[0x8];
9087
9088         u8         reserved_at_120[0x20];
9089
9090         u8         time_stamp[0x40];
9091
9092         u8         out_pulse_duration[0x10];
9093         u8         out_periodic_adjustment[0x10];
9094         u8         enhanced_out_periodic_adjustment[0x20];
9095
9096         u8         reserved_at_1c0[0x20];
9097 };
9098
9099 struct mlx5_ifc_mtppse_reg_bits {
9100         u8         reserved_at_0[0x18];
9101         u8         pin[0x8];
9102         u8         event_arm[0x1];
9103         u8         reserved_at_21[0x1b];
9104         u8         event_generation_mode[0x4];
9105         u8         reserved_at_40[0x40];
9106 };
9107
9108 struct mlx5_ifc_mcqs_reg_bits {
9109         u8         last_index_flag[0x1];
9110         u8         reserved_at_1[0x7];
9111         u8         fw_device[0x8];
9112         u8         component_index[0x10];
9113
9114         u8         reserved_at_20[0x10];
9115         u8         identifier[0x10];
9116
9117         u8         reserved_at_40[0x17];
9118         u8         component_status[0x5];
9119         u8         component_update_state[0x4];
9120
9121         u8         last_update_state_changer_type[0x4];
9122         u8         last_update_state_changer_host_id[0x4];
9123         u8         reserved_at_68[0x18];
9124 };
9125
9126 struct mlx5_ifc_mcqi_cap_bits {
9127         u8         supported_info_bitmask[0x20];
9128
9129         u8         component_size[0x20];
9130
9131         u8         max_component_size[0x20];
9132
9133         u8         log_mcda_word_size[0x4];
9134         u8         reserved_at_64[0xc];
9135         u8         mcda_max_write_size[0x10];
9136
9137         u8         rd_en[0x1];
9138         u8         reserved_at_81[0x1];
9139         u8         match_chip_id[0x1];
9140         u8         match_psid[0x1];
9141         u8         check_user_timestamp[0x1];
9142         u8         match_base_guid_mac[0x1];
9143         u8         reserved_at_86[0x1a];
9144 };
9145
9146 struct mlx5_ifc_mcqi_version_bits {
9147         u8         reserved_at_0[0x2];
9148         u8         build_time_valid[0x1];
9149         u8         user_defined_time_valid[0x1];
9150         u8         reserved_at_4[0x14];
9151         u8         version_string_length[0x8];
9152
9153         u8         version[0x20];
9154
9155         u8         build_time[0x40];
9156
9157         u8         user_defined_time[0x40];
9158
9159         u8         build_tool_version[0x20];
9160
9161         u8         reserved_at_e0[0x20];
9162
9163         u8         version_string[92][0x8];
9164 };
9165
9166 struct mlx5_ifc_mcqi_activation_method_bits {
9167         u8         pending_server_ac_power_cycle[0x1];
9168         u8         pending_server_dc_power_cycle[0x1];
9169         u8         pending_server_reboot[0x1];
9170         u8         pending_fw_reset[0x1];
9171         u8         auto_activate[0x1];
9172         u8         all_hosts_sync[0x1];
9173         u8         device_hw_reset[0x1];
9174         u8         reserved_at_7[0x19];
9175 };
9176
9177 union mlx5_ifc_mcqi_reg_data_bits {
9178         struct mlx5_ifc_mcqi_cap_bits               mcqi_caps;
9179         struct mlx5_ifc_mcqi_version_bits           mcqi_version;
9180         struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod;
9181 };
9182
9183 struct mlx5_ifc_mcqi_reg_bits {
9184         u8         read_pending_component[0x1];
9185         u8         reserved_at_1[0xf];
9186         u8         component_index[0x10];
9187
9188         u8         reserved_at_20[0x20];
9189
9190         u8         reserved_at_40[0x1b];
9191         u8         info_type[0x5];
9192
9193         u8         info_size[0x20];
9194
9195         u8         offset[0x20];
9196
9197         u8         reserved_at_a0[0x10];
9198         u8         data_size[0x10];
9199
9200         union mlx5_ifc_mcqi_reg_data_bits data[0];
9201 };
9202
9203 struct mlx5_ifc_mcc_reg_bits {
9204         u8         reserved_at_0[0x4];
9205         u8         time_elapsed_since_last_cmd[0xc];
9206         u8         reserved_at_10[0x8];
9207         u8         instruction[0x8];
9208
9209         u8         reserved_at_20[0x10];
9210         u8         component_index[0x10];
9211
9212         u8         reserved_at_40[0x8];
9213         u8         update_handle[0x18];
9214
9215         u8         handle_owner_type[0x4];
9216         u8         handle_owner_host_id[0x4];
9217         u8         reserved_at_68[0x1];
9218         u8         control_progress[0x7];
9219         u8         error_code[0x8];
9220         u8         reserved_at_78[0x4];
9221         u8         control_state[0x4];
9222
9223         u8         component_size[0x20];
9224
9225         u8         reserved_at_a0[0x60];
9226 };
9227
9228 struct mlx5_ifc_mcda_reg_bits {
9229         u8         reserved_at_0[0x8];
9230         u8         update_handle[0x18];
9231
9232         u8         offset[0x20];
9233
9234         u8         reserved_at_40[0x10];
9235         u8         size[0x10];
9236
9237         u8         reserved_at_60[0x20];
9238
9239         u8         data[0][0x20];
9240 };
9241
9242 union mlx5_ifc_ports_control_registers_document_bits {
9243         struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
9244         struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
9245         struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
9246         struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
9247         struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
9248         struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
9249         struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
9250         struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
9251         struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
9252         struct mlx5_ifc_pamp_reg_bits pamp_reg;
9253         struct mlx5_ifc_paos_reg_bits paos_reg;
9254         struct mlx5_ifc_pcap_reg_bits pcap_reg;
9255         struct mlx5_ifc_peir_reg_bits peir_reg;
9256         struct mlx5_ifc_pelc_reg_bits pelc_reg;
9257         struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
9258         struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
9259         struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
9260         struct mlx5_ifc_pifr_reg_bits pifr_reg;
9261         struct mlx5_ifc_pipg_reg_bits pipg_reg;
9262         struct mlx5_ifc_plbf_reg_bits plbf_reg;
9263         struct mlx5_ifc_plib_reg_bits plib_reg;
9264         struct mlx5_ifc_plpc_reg_bits plpc_reg;
9265         struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
9266         struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
9267         struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
9268         struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
9269         struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
9270         struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
9271         struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
9272         struct mlx5_ifc_ppad_reg_bits ppad_reg;
9273         struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
9274         struct mlx5_ifc_mpein_reg_bits mpein_reg;
9275         struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
9276         struct mlx5_ifc_pplm_reg_bits pplm_reg;
9277         struct mlx5_ifc_pplr_reg_bits pplr_reg;
9278         struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
9279         struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
9280         struct mlx5_ifc_pspa_reg_bits pspa_reg;
9281         struct mlx5_ifc_ptas_reg_bits ptas_reg;
9282         struct mlx5_ifc_ptys_reg_bits ptys_reg;
9283         struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
9284         struct mlx5_ifc_pude_reg_bits pude_reg;
9285         struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
9286         struct mlx5_ifc_slrg_reg_bits slrg_reg;
9287         struct mlx5_ifc_sltp_reg_bits sltp_reg;
9288         struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
9289         struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
9290         struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
9291         struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
9292         struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
9293         struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
9294         struct mlx5_ifc_mcc_reg_bits mcc_reg;
9295         struct mlx5_ifc_mcda_reg_bits mcda_reg;
9296         u8         reserved_at_0[0x60e0];
9297 };
9298
9299 union mlx5_ifc_debug_enhancements_document_bits {
9300         struct mlx5_ifc_health_buffer_bits health_buffer;
9301         u8         reserved_at_0[0x200];
9302 };
9303
9304 union mlx5_ifc_uplink_pci_interface_document_bits {
9305         struct mlx5_ifc_initial_seg_bits initial_seg;
9306         u8         reserved_at_0[0x20060];
9307 };
9308
9309 struct mlx5_ifc_set_flow_table_root_out_bits {
9310         u8         status[0x8];
9311         u8         reserved_at_8[0x18];
9312
9313         u8         syndrome[0x20];
9314
9315         u8         reserved_at_40[0x40];
9316 };
9317
9318 struct mlx5_ifc_set_flow_table_root_in_bits {
9319         u8         opcode[0x10];
9320         u8         reserved_at_10[0x10];
9321
9322         u8         reserved_at_20[0x10];
9323         u8         op_mod[0x10];
9324
9325         u8         other_vport[0x1];
9326         u8         reserved_at_41[0xf];
9327         u8         vport_number[0x10];
9328
9329         u8         reserved_at_60[0x20];
9330
9331         u8         table_type[0x8];
9332         u8         reserved_at_88[0x18];
9333
9334         u8         reserved_at_a0[0x8];
9335         u8         table_id[0x18];
9336
9337         u8         reserved_at_c0[0x8];
9338         u8         underlay_qpn[0x18];
9339         u8         reserved_at_e0[0x120];
9340 };
9341
9342 enum {
9343         MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID     = (1UL << 0),
9344         MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
9345 };
9346
9347 struct mlx5_ifc_modify_flow_table_out_bits {
9348         u8         status[0x8];
9349         u8         reserved_at_8[0x18];
9350
9351         u8         syndrome[0x20];
9352
9353         u8         reserved_at_40[0x40];
9354 };
9355
9356 struct mlx5_ifc_modify_flow_table_in_bits {
9357         u8         opcode[0x10];
9358         u8         reserved_at_10[0x10];
9359
9360         u8         reserved_at_20[0x10];
9361         u8         op_mod[0x10];
9362
9363         u8         other_vport[0x1];
9364         u8         reserved_at_41[0xf];
9365         u8         vport_number[0x10];
9366
9367         u8         reserved_at_60[0x10];
9368         u8         modify_field_select[0x10];
9369
9370         u8         table_type[0x8];
9371         u8         reserved_at_88[0x18];
9372
9373         u8         reserved_at_a0[0x8];
9374         u8         table_id[0x18];
9375
9376         struct mlx5_ifc_flow_table_context_bits flow_table_context;
9377 };
9378
9379 struct mlx5_ifc_ets_tcn_config_reg_bits {
9380         u8         g[0x1];
9381         u8         b[0x1];
9382         u8         r[0x1];
9383         u8         reserved_at_3[0x9];
9384         u8         group[0x4];
9385         u8         reserved_at_10[0x9];
9386         u8         bw_allocation[0x7];
9387
9388         u8         reserved_at_20[0xc];
9389         u8         max_bw_units[0x4];
9390         u8         reserved_at_30[0x8];
9391         u8         max_bw_value[0x8];
9392 };
9393
9394 struct mlx5_ifc_ets_global_config_reg_bits {
9395         u8         reserved_at_0[0x2];
9396         u8         r[0x1];
9397         u8         reserved_at_3[0x1d];
9398
9399         u8         reserved_at_20[0xc];
9400         u8         max_bw_units[0x4];
9401         u8         reserved_at_30[0x8];
9402         u8         max_bw_value[0x8];
9403 };
9404
9405 struct mlx5_ifc_qetc_reg_bits {
9406         u8                                         reserved_at_0[0x8];
9407         u8                                         port_number[0x8];
9408         u8                                         reserved_at_10[0x30];
9409
9410         struct mlx5_ifc_ets_tcn_config_reg_bits    tc_configuration[0x8];
9411         struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
9412 };
9413
9414 struct mlx5_ifc_qpdpm_dscp_reg_bits {
9415         u8         e[0x1];
9416         u8         reserved_at_01[0x0b];
9417         u8         prio[0x04];
9418 };
9419
9420 struct mlx5_ifc_qpdpm_reg_bits {
9421         u8                                     reserved_at_0[0x8];
9422         u8                                     local_port[0x8];
9423         u8                                     reserved_at_10[0x10];
9424         struct mlx5_ifc_qpdpm_dscp_reg_bits    dscp[64];
9425 };
9426
9427 struct mlx5_ifc_qpts_reg_bits {
9428         u8         reserved_at_0[0x8];
9429         u8         local_port[0x8];
9430         u8         reserved_at_10[0x2d];
9431         u8         trust_state[0x3];
9432 };
9433
9434 struct mlx5_ifc_pptb_reg_bits {
9435         u8         reserved_at_0[0x2];
9436         u8         mm[0x2];
9437         u8         reserved_at_4[0x4];
9438         u8         local_port[0x8];
9439         u8         reserved_at_10[0x6];
9440         u8         cm[0x1];
9441         u8         um[0x1];
9442         u8         pm[0x8];
9443
9444         u8         prio_x_buff[0x20];
9445
9446         u8         pm_msb[0x8];
9447         u8         reserved_at_48[0x10];
9448         u8         ctrl_buff[0x4];
9449         u8         untagged_buff[0x4];
9450 };
9451
9452 struct mlx5_ifc_pbmc_reg_bits {
9453         u8         reserved_at_0[0x8];
9454         u8         local_port[0x8];
9455         u8         reserved_at_10[0x10];
9456
9457         u8         xoff_timer_value[0x10];
9458         u8         xoff_refresh[0x10];
9459
9460         u8         reserved_at_40[0x9];
9461         u8         fullness_threshold[0x7];
9462         u8         port_buffer_size[0x10];
9463
9464         struct mlx5_ifc_bufferx_reg_bits buffer[10];
9465
9466         u8         reserved_at_2e0[0x40];
9467 };
9468
9469 struct mlx5_ifc_qtct_reg_bits {
9470         u8         reserved_at_0[0x8];
9471         u8         port_number[0x8];
9472         u8         reserved_at_10[0xd];
9473         u8         prio[0x3];
9474
9475         u8         reserved_at_20[0x1d];
9476         u8         tclass[0x3];
9477 };
9478
9479 struct mlx5_ifc_mcia_reg_bits {
9480         u8         l[0x1];
9481         u8         reserved_at_1[0x7];
9482         u8         module[0x8];
9483         u8         reserved_at_10[0x8];
9484         u8         status[0x8];
9485
9486         u8         i2c_device_address[0x8];
9487         u8         page_number[0x8];
9488         u8         device_address[0x10];
9489
9490         u8         reserved_at_40[0x10];
9491         u8         size[0x10];
9492
9493         u8         reserved_at_60[0x20];
9494
9495         u8         dword_0[0x20];
9496         u8         dword_1[0x20];
9497         u8         dword_2[0x20];
9498         u8         dword_3[0x20];
9499         u8         dword_4[0x20];
9500         u8         dword_5[0x20];
9501         u8         dword_6[0x20];
9502         u8         dword_7[0x20];
9503         u8         dword_8[0x20];
9504         u8         dword_9[0x20];
9505         u8         dword_10[0x20];
9506         u8         dword_11[0x20];
9507 };
9508
9509 struct mlx5_ifc_dcbx_param_bits {
9510         u8         dcbx_cee_cap[0x1];
9511         u8         dcbx_ieee_cap[0x1];
9512         u8         dcbx_standby_cap[0x1];
9513         u8         reserved_at_3[0x5];
9514         u8         port_number[0x8];
9515         u8         reserved_at_10[0xa];
9516         u8         max_application_table_size[6];
9517         u8         reserved_at_20[0x15];
9518         u8         version_oper[0x3];
9519         u8         reserved_at_38[5];
9520         u8         version_admin[0x3];
9521         u8         willing_admin[0x1];
9522         u8         reserved_at_41[0x3];
9523         u8         pfc_cap_oper[0x4];
9524         u8         reserved_at_48[0x4];
9525         u8         pfc_cap_admin[0x4];
9526         u8         reserved_at_50[0x4];
9527         u8         num_of_tc_oper[0x4];
9528         u8         reserved_at_58[0x4];
9529         u8         num_of_tc_admin[0x4];
9530         u8         remote_willing[0x1];
9531         u8         reserved_at_61[3];
9532         u8         remote_pfc_cap[4];
9533         u8         reserved_at_68[0x14];
9534         u8         remote_num_of_tc[0x4];
9535         u8         reserved_at_80[0x18];
9536         u8         error[0x8];
9537         u8         reserved_at_a0[0x160];
9538 };
9539
9540 struct mlx5_ifc_lagc_bits {
9541         u8         reserved_at_0[0x1d];
9542         u8         lag_state[0x3];
9543
9544         u8         reserved_at_20[0x14];
9545         u8         tx_remap_affinity_2[0x4];
9546         u8         reserved_at_38[0x4];
9547         u8         tx_remap_affinity_1[0x4];
9548 };
9549
9550 struct mlx5_ifc_create_lag_out_bits {
9551         u8         status[0x8];
9552         u8         reserved_at_8[0x18];
9553
9554         u8         syndrome[0x20];
9555
9556         u8         reserved_at_40[0x40];
9557 };
9558
9559 struct mlx5_ifc_create_lag_in_bits {
9560         u8         opcode[0x10];
9561         u8         reserved_at_10[0x10];
9562
9563         u8         reserved_at_20[0x10];
9564         u8         op_mod[0x10];
9565
9566         struct mlx5_ifc_lagc_bits ctx;
9567 };
9568
9569 struct mlx5_ifc_modify_lag_out_bits {
9570         u8         status[0x8];
9571         u8         reserved_at_8[0x18];
9572
9573         u8         syndrome[0x20];
9574
9575         u8         reserved_at_40[0x40];
9576 };
9577
9578 struct mlx5_ifc_modify_lag_in_bits {
9579         u8         opcode[0x10];
9580         u8         reserved_at_10[0x10];
9581
9582         u8         reserved_at_20[0x10];
9583         u8         op_mod[0x10];
9584
9585         u8         reserved_at_40[0x20];
9586         u8         field_select[0x20];
9587
9588         struct mlx5_ifc_lagc_bits ctx;
9589 };
9590
9591 struct mlx5_ifc_query_lag_out_bits {
9592         u8         status[0x8];
9593         u8         reserved_at_8[0x18];
9594
9595         u8         syndrome[0x20];
9596
9597         u8         reserved_at_40[0x40];
9598
9599         struct mlx5_ifc_lagc_bits ctx;
9600 };
9601
9602 struct mlx5_ifc_query_lag_in_bits {
9603         u8         opcode[0x10];
9604         u8         reserved_at_10[0x10];
9605
9606         u8         reserved_at_20[0x10];
9607         u8         op_mod[0x10];
9608
9609         u8         reserved_at_40[0x40];
9610 };
9611
9612 struct mlx5_ifc_destroy_lag_out_bits {
9613         u8         status[0x8];
9614         u8         reserved_at_8[0x18];
9615
9616         u8         syndrome[0x20];
9617
9618         u8         reserved_at_40[0x40];
9619 };
9620
9621 struct mlx5_ifc_destroy_lag_in_bits {
9622         u8         opcode[0x10];
9623         u8         reserved_at_10[0x10];
9624
9625         u8         reserved_at_20[0x10];
9626         u8         op_mod[0x10];
9627
9628         u8         reserved_at_40[0x40];
9629 };
9630
9631 struct mlx5_ifc_create_vport_lag_out_bits {
9632         u8         status[0x8];
9633         u8         reserved_at_8[0x18];
9634
9635         u8         syndrome[0x20];
9636
9637         u8         reserved_at_40[0x40];
9638 };
9639
9640 struct mlx5_ifc_create_vport_lag_in_bits {
9641         u8         opcode[0x10];
9642         u8         reserved_at_10[0x10];
9643
9644         u8         reserved_at_20[0x10];
9645         u8         op_mod[0x10];
9646
9647         u8         reserved_at_40[0x40];
9648 };
9649
9650 struct mlx5_ifc_destroy_vport_lag_out_bits {
9651         u8         status[0x8];
9652         u8         reserved_at_8[0x18];
9653
9654         u8         syndrome[0x20];
9655
9656         u8         reserved_at_40[0x40];
9657 };
9658
9659 struct mlx5_ifc_destroy_vport_lag_in_bits {
9660         u8         opcode[0x10];
9661         u8         reserved_at_10[0x10];
9662
9663         u8         reserved_at_20[0x10];
9664         u8         op_mod[0x10];
9665
9666         u8         reserved_at_40[0x40];
9667 };
9668
9669 struct mlx5_ifc_alloc_memic_in_bits {
9670         u8         opcode[0x10];
9671         u8         reserved_at_10[0x10];
9672
9673         u8         reserved_at_20[0x10];
9674         u8         op_mod[0x10];
9675
9676         u8         reserved_at_30[0x20];
9677
9678         u8         reserved_at_40[0x18];
9679         u8         log_memic_addr_alignment[0x8];
9680
9681         u8         range_start_addr[0x40];
9682
9683         u8         range_size[0x20];
9684
9685         u8         memic_size[0x20];
9686 };
9687
9688 struct mlx5_ifc_alloc_memic_out_bits {
9689         u8         status[0x8];
9690         u8         reserved_at_8[0x18];
9691
9692         u8         syndrome[0x20];
9693
9694         u8         memic_start_addr[0x40];
9695 };
9696
9697 struct mlx5_ifc_dealloc_memic_in_bits {
9698         u8         opcode[0x10];
9699         u8         reserved_at_10[0x10];
9700
9701         u8         reserved_at_20[0x10];
9702         u8         op_mod[0x10];
9703
9704         u8         reserved_at_40[0x40];
9705
9706         u8         memic_start_addr[0x40];
9707
9708         u8         memic_size[0x20];
9709
9710         u8         reserved_at_e0[0x20];
9711 };
9712
9713 struct mlx5_ifc_dealloc_memic_out_bits {
9714         u8         status[0x8];
9715         u8         reserved_at_8[0x18];
9716
9717         u8         syndrome[0x20];
9718
9719         u8         reserved_at_40[0x40];
9720 };
9721
9722 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
9723         u8         opcode[0x10];
9724         u8         uid[0x10];
9725
9726         u8         vhca_tunnel_id[0x10];
9727         u8         obj_type[0x10];
9728
9729         u8         obj_id[0x20];
9730
9731         u8         reserved_at_60[0x20];
9732 };
9733
9734 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
9735         u8         status[0x8];
9736         u8         reserved_at_8[0x18];
9737
9738         u8         syndrome[0x20];
9739
9740         u8         obj_id[0x20];
9741
9742         u8         reserved_at_60[0x20];
9743 };
9744
9745 struct mlx5_ifc_umem_bits {
9746         u8         reserved_at_0[0x80];
9747
9748         u8         reserved_at_80[0x1b];
9749         u8         log_page_size[0x5];
9750
9751         u8         page_offset[0x20];
9752
9753         u8         num_of_mtt[0x40];
9754
9755         struct mlx5_ifc_mtt_bits  mtt[0];
9756 };
9757
9758 struct mlx5_ifc_uctx_bits {
9759         u8         cap[0x20];
9760
9761         u8         reserved_at_20[0x160];
9762 };
9763
9764 struct mlx5_ifc_sw_icm_bits {
9765         u8         modify_field_select[0x40];
9766
9767         u8         reserved_at_40[0x18];
9768         u8         log_sw_icm_size[0x8];
9769
9770         u8         reserved_at_60[0x20];
9771
9772         u8         sw_icm_start_addr[0x40];
9773
9774         u8         reserved_at_c0[0x140];
9775 };
9776
9777 struct mlx5_ifc_geneve_tlv_option_bits {
9778         u8         modify_field_select[0x40];
9779
9780         u8         reserved_at_40[0x18];
9781         u8         geneve_option_fte_index[0x8];
9782
9783         u8         option_class[0x10];
9784         u8         option_type[0x8];
9785         u8         reserved_at_78[0x3];
9786         u8         option_data_length[0x5];
9787
9788         u8         reserved_at_80[0x180];
9789 };
9790
9791 struct mlx5_ifc_create_umem_in_bits {
9792         u8         opcode[0x10];
9793         u8         uid[0x10];
9794
9795         u8         reserved_at_20[0x10];
9796         u8         op_mod[0x10];
9797
9798         u8         reserved_at_40[0x40];
9799
9800         struct mlx5_ifc_umem_bits  umem;
9801 };
9802
9803 struct mlx5_ifc_create_uctx_in_bits {
9804         u8         opcode[0x10];
9805         u8         reserved_at_10[0x10];
9806
9807         u8         reserved_at_20[0x10];
9808         u8         op_mod[0x10];
9809
9810         u8         reserved_at_40[0x40];
9811
9812         struct mlx5_ifc_uctx_bits  uctx;
9813 };
9814
9815 struct mlx5_ifc_destroy_uctx_in_bits {
9816         u8         opcode[0x10];
9817         u8         reserved_at_10[0x10];
9818
9819         u8         reserved_at_20[0x10];
9820         u8         op_mod[0x10];
9821
9822         u8         reserved_at_40[0x10];
9823         u8         uid[0x10];
9824
9825         u8         reserved_at_60[0x20];
9826 };
9827
9828 struct mlx5_ifc_create_sw_icm_in_bits {
9829         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9830         struct mlx5_ifc_sw_icm_bits                   sw_icm;
9831 };
9832
9833 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
9834         struct mlx5_ifc_general_obj_in_cmd_hdr_bits   hdr;
9835         struct mlx5_ifc_geneve_tlv_option_bits        geneve_tlv_opt;
9836 };
9837
9838 struct mlx5_ifc_mtrc_string_db_param_bits {
9839         u8         string_db_base_address[0x20];
9840
9841         u8         reserved_at_20[0x8];
9842         u8         string_db_size[0x18];
9843 };
9844
9845 struct mlx5_ifc_mtrc_cap_bits {
9846         u8         trace_owner[0x1];
9847         u8         trace_to_memory[0x1];
9848         u8         reserved_at_2[0x4];
9849         u8         trc_ver[0x2];
9850         u8         reserved_at_8[0x14];
9851         u8         num_string_db[0x4];
9852
9853         u8         first_string_trace[0x8];
9854         u8         num_string_trace[0x8];
9855         u8         reserved_at_30[0x28];
9856
9857         u8         log_max_trace_buffer_size[0x8];
9858
9859         u8         reserved_at_60[0x20];
9860
9861         struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8];
9862
9863         u8         reserved_at_280[0x180];
9864 };
9865
9866 struct mlx5_ifc_mtrc_conf_bits {
9867         u8         reserved_at_0[0x1c];
9868         u8         trace_mode[0x4];
9869         u8         reserved_at_20[0x18];
9870         u8         log_trace_buffer_size[0x8];
9871         u8         trace_mkey[0x20];
9872         u8         reserved_at_60[0x3a0];
9873 };
9874
9875 struct mlx5_ifc_mtrc_stdb_bits {
9876         u8         string_db_index[0x4];
9877         u8         reserved_at_4[0x4];
9878         u8         read_size[0x18];
9879         u8         start_offset[0x20];
9880         u8         string_db_data[0];
9881 };
9882
9883 struct mlx5_ifc_mtrc_ctrl_bits {
9884         u8         trace_status[0x2];
9885         u8         reserved_at_2[0x2];
9886         u8         arm_event[0x1];
9887         u8         reserved_at_5[0xb];
9888         u8         modify_field_select[0x10];
9889         u8         reserved_at_20[0x2b];
9890         u8         current_timestamp52_32[0x15];
9891         u8         current_timestamp31_0[0x20];
9892         u8         reserved_at_80[0x180];
9893 };
9894
9895 struct mlx5_ifc_host_params_context_bits {
9896         u8         host_number[0x8];
9897         u8         reserved_at_8[0x7];
9898         u8         host_pf_disabled[0x1];
9899         u8         host_num_of_vfs[0x10];
9900
9901         u8         host_total_vfs[0x10];
9902         u8         host_pci_bus[0x10];
9903
9904         u8         reserved_at_40[0x10];
9905         u8         host_pci_device[0x10];
9906
9907         u8         reserved_at_60[0x10];
9908         u8         host_pci_function[0x10];
9909
9910         u8         reserved_at_80[0x180];
9911 };
9912
9913 struct mlx5_ifc_query_esw_functions_in_bits {
9914         u8         opcode[0x10];
9915         u8         reserved_at_10[0x10];
9916
9917         u8         reserved_at_20[0x10];
9918         u8         op_mod[0x10];
9919
9920         u8         reserved_at_40[0x40];
9921 };
9922
9923 struct mlx5_ifc_query_esw_functions_out_bits {
9924         u8         status[0x8];
9925         u8         reserved_at_8[0x18];
9926
9927         u8         syndrome[0x20];
9928
9929         u8         reserved_at_40[0x40];
9930
9931         struct mlx5_ifc_host_params_context_bits host_params_context;
9932
9933         u8         reserved_at_280[0x180];
9934         u8         host_sf_enable[0][0x40];
9935 };
9936
9937 struct mlx5_ifc_sf_partition_bits {
9938         u8         reserved_at_0[0x10];
9939         u8         log_num_sf[0x8];
9940         u8         log_sf_bar_size[0x8];
9941 };
9942
9943 struct mlx5_ifc_query_sf_partitions_out_bits {
9944         u8         status[0x8];
9945         u8         reserved_at_8[0x18];
9946
9947         u8         syndrome[0x20];
9948
9949         u8         reserved_at_40[0x18];
9950         u8         num_sf_partitions[0x8];
9951
9952         u8         reserved_at_60[0x20];
9953
9954         struct mlx5_ifc_sf_partition_bits sf_partition[0];
9955 };
9956
9957 struct mlx5_ifc_query_sf_partitions_in_bits {
9958         u8         opcode[0x10];
9959         u8         reserved_at_10[0x10];
9960
9961         u8         reserved_at_20[0x10];
9962         u8         op_mod[0x10];
9963
9964         u8         reserved_at_40[0x40];
9965 };
9966
9967 struct mlx5_ifc_dealloc_sf_out_bits {
9968         u8         status[0x8];
9969         u8         reserved_at_8[0x18];
9970
9971         u8         syndrome[0x20];
9972
9973         u8         reserved_at_40[0x40];
9974 };
9975
9976 struct mlx5_ifc_dealloc_sf_in_bits {
9977         u8         opcode[0x10];
9978         u8         reserved_at_10[0x10];
9979
9980         u8         reserved_at_20[0x10];
9981         u8         op_mod[0x10];
9982
9983         u8         reserved_at_40[0x10];
9984         u8         function_id[0x10];
9985
9986         u8         reserved_at_60[0x20];
9987 };
9988
9989 struct mlx5_ifc_alloc_sf_out_bits {
9990         u8         status[0x8];
9991         u8         reserved_at_8[0x18];
9992
9993         u8         syndrome[0x20];
9994
9995         u8         reserved_at_40[0x40];
9996 };
9997
9998 struct mlx5_ifc_alloc_sf_in_bits {
9999         u8         opcode[0x10];
10000         u8         reserved_at_10[0x10];
10001
10002         u8         reserved_at_20[0x10];
10003         u8         op_mod[0x10];
10004
10005         u8         reserved_at_40[0x10];
10006         u8         function_id[0x10];
10007
10008         u8         reserved_at_60[0x20];
10009 };
10010
10011 struct mlx5_ifc_affiliated_event_header_bits {
10012         u8         reserved_at_0[0x10];
10013         u8         obj_type[0x10];
10014
10015         u8         obj_id[0x20];
10016 };
10017
10018 enum {
10019         MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT(0xc),
10020 };
10021
10022 enum {
10023         MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
10024 };
10025
10026 struct mlx5_ifc_encryption_key_obj_bits {
10027         u8         modify_field_select[0x40];
10028
10029         u8         reserved_at_40[0x14];
10030         u8         key_size[0x4];
10031         u8         reserved_at_58[0x4];
10032         u8         key_type[0x4];
10033
10034         u8         reserved_at_60[0x8];
10035         u8         pd[0x18];
10036
10037         u8         reserved_at_80[0x180];
10038         u8         key[8][0x20];
10039
10040         u8         reserved_at_300[0x500];
10041 };
10042
10043 struct mlx5_ifc_create_encryption_key_in_bits {
10044         struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
10045         struct mlx5_ifc_encryption_key_obj_bits encryption_key_object;
10046 };
10047
10048 enum {
10049         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
10050         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
10051 };
10052
10053 enum {
10054         MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_DEK = 0x1,
10055 };
10056
10057 struct mlx5_ifc_tls_static_params_bits {
10058         u8         const_2[0x2];
10059         u8         tls_version[0x4];
10060         u8         const_1[0x2];
10061         u8         reserved_at_8[0x14];
10062         u8         encryption_standard[0x4];
10063
10064         u8         reserved_at_20[0x20];
10065
10066         u8         initial_record_number[0x40];
10067
10068         u8         resync_tcp_sn[0x20];
10069
10070         u8         gcm_iv[0x20];
10071
10072         u8         implicit_iv[0x40];
10073
10074         u8         reserved_at_100[0x8];
10075         u8         dek_index[0x18];
10076
10077         u8         reserved_at_120[0xe0];
10078 };
10079
10080 struct mlx5_ifc_tls_progress_params_bits {
10081         u8         valid[0x1];
10082         u8         reserved_at_1[0x7];
10083         u8         pd[0x18];
10084
10085         u8         next_record_tcp_sn[0x20];
10086
10087         u8         hw_resync_tcp_sn[0x20];
10088
10089         u8         record_tracker_state[0x2];
10090         u8         auth_state[0x2];
10091         u8         reserved_at_64[0x4];
10092         u8         hw_offset_record_number[0x18];
10093 };
10094
10095 #endif /* MLX5_IFC_H */