1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2014 Freescale Semiconductor, Inc.
6 #ifndef __LINUX_MTD_SPI_NOR_H
7 #define __LINUX_MTD_SPI_NOR_H
9 #include <linux/bitops.h>
10 #include <linux/mtd/cfi.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/spi/spi-mem.h>
17 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
18 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
20 #define SNOR_MFR_ATMEL CFI_MFR_ATMEL
21 #define SNOR_MFR_GIGADEVICE 0xc8
22 #define SNOR_MFR_INTEL CFI_MFR_INTEL
23 #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */
24 #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */
25 #define SNOR_MFR_ISSI CFI_MFR_PMC
26 #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX
27 #define SNOR_MFR_SPANSION CFI_MFR_AMD
28 #define SNOR_MFR_SST CFI_MFR_SST
29 #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */
32 * Note on opcode nomenclature: some opcodes have a format like
33 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
34 * of I/O lines used for the opcode, address, and data (respectively). The
35 * FUNCTION has an optional suffix of '4', to represent an opcode which
36 * requires a 4-byte (32-bit) address.
40 #define SPINOR_OP_WREN 0x06 /* Write enable */
41 #define SPINOR_OP_RDSR 0x05 /* Read status register */
42 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
43 #define SPINOR_OP_RDSR2 0x3f /* Read status register 2 */
44 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
45 #define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
46 #define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
47 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
48 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
49 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
50 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
51 #define SPINOR_OP_READ_1_1_8 0x8b /* Read data bytes (Octal Output SPI) */
52 #define SPINOR_OP_READ_1_8_8 0xcb /* Read data bytes (Octal I/O SPI) */
53 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
54 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
55 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
56 #define SPINOR_OP_PP_1_1_8 0x82 /* Octal page program */
57 #define SPINOR_OP_PP_1_8_8 0xc2 /* Octal page program */
58 #define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
59 #define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
60 #define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
61 #define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
62 #define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
63 #define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
64 #define SPINOR_OP_RDSFDP 0x5a /* Read SFDP */
65 #define SPINOR_OP_RDCR 0x35 /* Read configuration register */
66 #define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
67 #define SPINOR_OP_CLFSR 0x50 /* Clear flag status register */
68 #define SPINOR_OP_RDEAR 0xc8 /* Read Extended Address Register */
69 #define SPINOR_OP_WREAR 0xc5 /* Write Extended Address Register */
71 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
72 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
73 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
74 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
75 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
76 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
77 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
78 #define SPINOR_OP_READ_1_1_8_4B 0x7c /* Read data bytes (Octal Output SPI) */
79 #define SPINOR_OP_READ_1_8_8_4B 0xcc /* Read data bytes (Octal I/O SPI) */
80 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
81 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
82 #define SPINOR_OP_PP_1_4_4_4B 0x3e /* Quad page program */
83 #define SPINOR_OP_PP_1_1_8_4B 0x84 /* Octal page program */
84 #define SPINOR_OP_PP_1_8_8_4B 0x8e /* Octal page program */
85 #define SPINOR_OP_BE_4K_4B 0x21 /* Erase 4KiB block */
86 #define SPINOR_OP_BE_32K_4B 0x5c /* Erase 32KiB block */
87 #define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
89 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
90 #define SPINOR_OP_READ_1_1_1_DTR 0x0d
91 #define SPINOR_OP_READ_1_2_2_DTR 0xbd
92 #define SPINOR_OP_READ_1_4_4_DTR 0xed
94 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
95 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
96 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
98 /* Used for SST flashes only. */
99 #define SPINOR_OP_BP 0x02 /* Byte program */
100 #define SPINOR_OP_WRDI 0x04 /* Write disable */
101 #define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
103 /* Used for S3AN flashes only */
104 #define SPINOR_OP_XSE 0x50 /* Sector erase */
105 #define SPINOR_OP_XPP 0x82 /* Page program */
106 #define SPINOR_OP_XRDSR 0xd7 /* Read status register */
108 #define XSR_PAGESIZE BIT(0) /* Page size in Po2 or Linear */
109 #define XSR_RDY BIT(7) /* Ready */
112 /* Used for Macronix and Winbond flashes. */
113 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
114 #define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
116 /* Used for Spansion flashes only. */
117 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
118 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
120 /* Used for Micron flashes only. */
121 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
122 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
124 /* Status Register bits. */
125 #define SR_WIP BIT(0) /* Write in progress */
126 #define SR_WEL BIT(1) /* Write enable latch */
127 /* meaning of other SR_* bits may differ between vendors */
128 #define SR_BP0 BIT(2) /* Block protect 0 */
129 #define SR_BP1 BIT(3) /* Block protect 1 */
130 #define SR_BP2 BIT(4) /* Block protect 2 */
131 #define SR_TB BIT(5) /* Top/Bottom protect */
132 #define SR_SRWD BIT(7) /* SR write protect */
133 /* Spansion/Cypress specific status bits */
134 #define SR_E_ERR BIT(5)
135 #define SR_P_ERR BIT(6)
137 #define SR1_QUAD_EN_BIT6 BIT(6)
139 /* Enhanced Volatile Configuration Register bits */
140 #define EVCR_QUAD_EN_MICRON BIT(7) /* Micron Quad I/O */
142 /* Flag Status Register bits */
143 #define FSR_READY BIT(7) /* Device status, 0 = Busy, 1 = Ready */
144 #define FSR_E_ERR BIT(5) /* Erase operation status */
145 #define FSR_P_ERR BIT(4) /* Program operation status */
146 #define FSR_PT_ERR BIT(1) /* Protection error bit */
148 /* Status Register 2 bits. */
149 #define SR2_QUAD_EN_BIT1 BIT(1)
150 #define SR2_QUAD_EN_BIT7 BIT(7)
152 /* Supported SPI protocols */
153 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)
154 #define SNOR_PROTO_INST_SHIFT 16
155 #define SNOR_PROTO_INST(_nbits) \
156 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
157 SNOR_PROTO_INST_MASK)
159 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
160 #define SNOR_PROTO_ADDR_SHIFT 8
161 #define SNOR_PROTO_ADDR(_nbits) \
162 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
163 SNOR_PROTO_ADDR_MASK)
165 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
166 #define SNOR_PROTO_DATA_SHIFT 0
167 #define SNOR_PROTO_DATA(_nbits) \
168 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
169 SNOR_PROTO_DATA_MASK)
171 #define SNOR_PROTO_IS_DTR BIT(24) /* Double Transfer Rate */
173 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
174 (SNOR_PROTO_INST(_inst_nbits) | \
175 SNOR_PROTO_ADDR(_addr_nbits) | \
176 SNOR_PROTO_DATA(_data_nbits))
177 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
178 (SNOR_PROTO_IS_DTR | \
179 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
181 enum spi_nor_protocol {
182 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
183 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
184 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
185 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
186 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
187 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
188 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
189 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
190 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
191 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
193 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
194 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
195 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
196 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
199 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
201 return !!(proto & SNOR_PROTO_IS_DTR);
204 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
206 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
207 SNOR_PROTO_INST_SHIFT;
210 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
212 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
213 SNOR_PROTO_ADDR_SHIFT;
216 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
218 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
219 SNOR_PROTO_DATA_SHIFT;
222 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
224 return spi_nor_get_protocol_data_nbits(proto);
228 SPI_NOR_OPS_READ = 0,
235 enum spi_nor_option_flags {
236 SNOR_F_USE_FSR = BIT(0),
237 SNOR_F_HAS_SR_TB = BIT(1),
238 SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
239 SNOR_F_READY_XSR_RDY = BIT(3),
240 SNOR_F_USE_CLSR = BIT(4),
241 SNOR_F_BROKEN_RESET = BIT(5),
242 SNOR_F_4B_OPCODES = BIT(6),
243 SNOR_F_HAS_4BAIT = BIT(7),
244 SNOR_F_HAS_LOCK = BIT(8),
245 SNOR_F_HAS_16BIT_SR = BIT(9),
246 SNOR_F_NO_READ_CR = BIT(10),
251 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
252 * @size: the size of the sector/block erased by the erase type.
253 * JEDEC JESD216B imposes erase sizes to be a power of 2.
254 * @size_shift: @size is a power of 2, the shift is stored in
256 * @size_mask: the size mask based on @size_shift.
257 * @opcode: the SPI command op code to erase the sector/block.
258 * @idx: Erase Type index as sorted in the Basic Flash Parameter
259 * Table. It will be used to synchronize the supported
260 * Erase Types with the ones identified in the SFDP
263 struct spi_nor_erase_type {
272 * struct spi_nor_erase_command - Used for non-uniform erases
273 * The structure is used to describe a list of erase commands to be executed
274 * once we validate that the erase can be performed. The elements in the list
275 * are run-length encoded.
276 * @list: for inclusion into the list of erase commands.
277 * @count: how many times the same erase command should be
278 * consecutively used.
279 * @size: the size of the sector/block erased by the command.
280 * @opcode: the SPI command op code to erase the sector/block.
282 struct spi_nor_erase_command {
283 struct list_head list;
290 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
291 * @offset: the offset in the data array of erase region start.
292 * LSB bits are used as a bitmask encoding flags to
293 * determine if this region is overlaid, if this region is
294 * the last in the SPI NOR flash memory and to indicate
295 * all the supported erase commands inside this region.
296 * The erase types are sorted in ascending order with the
297 * smallest Erase Type size being at BIT(0).
298 * @size: the size of the region in bytes.
300 struct spi_nor_erase_region {
305 #define SNOR_ERASE_TYPE_MAX 4
306 #define SNOR_ERASE_TYPE_MASK GENMASK_ULL(SNOR_ERASE_TYPE_MAX - 1, 0)
308 #define SNOR_LAST_REGION BIT(4)
309 #define SNOR_OVERLAID_REGION BIT(5)
311 #define SNOR_ERASE_FLAGS_MAX 6
312 #define SNOR_ERASE_FLAGS_MASK GENMASK_ULL(SNOR_ERASE_FLAGS_MAX - 1, 0)
315 * struct spi_nor_erase_map - Structure to describe the SPI NOR erase map
316 * @regions: array of erase regions. The regions are consecutive in
317 * address space. Walking through the regions is done
319 * @uniform_region: a pre-allocated erase region for SPI NOR with a uniform
320 * sector size (legacy implementation).
321 * @erase_type: an array of erase types shared by all the regions.
322 * The erase types are sorted in ascending order, with the
323 * smallest Erase Type size being the first member in the
325 * @uniform_erase_type: bitmask encoding erase types that can erase the
326 * entire memory. This member is completed at init by
327 * uniform and non-uniform SPI NOR flash memories if they
328 * support at least one erase type that can erase the
331 struct spi_nor_erase_map {
332 struct spi_nor_erase_region *regions;
333 struct spi_nor_erase_region uniform_region;
334 struct spi_nor_erase_type erase_type[SNOR_ERASE_TYPE_MAX];
335 u8 uniform_erase_type;
339 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
340 * supported by the SPI controller (bus master).
341 * @mask: the bitmask listing all the supported hw capabilies
343 struct spi_nor_hwcaps {
348 *(Fast) Read capabilities.
349 * MUST be ordered by priority: the higher bit position, the higher priority.
350 * As a matter of performances, it is relevant to use Octal SPI protocols first,
351 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
354 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
355 #define SNOR_HWCAPS_READ BIT(0)
356 #define SNOR_HWCAPS_READ_FAST BIT(1)
357 #define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
359 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
360 #define SNOR_HWCAPS_READ_1_1_2 BIT(3)
361 #define SNOR_HWCAPS_READ_1_2_2 BIT(4)
362 #define SNOR_HWCAPS_READ_2_2_2 BIT(5)
363 #define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
365 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
366 #define SNOR_HWCAPS_READ_1_1_4 BIT(7)
367 #define SNOR_HWCAPS_READ_1_4_4 BIT(8)
368 #define SNOR_HWCAPS_READ_4_4_4 BIT(9)
369 #define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
371 #define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
372 #define SNOR_HWCAPS_READ_1_1_8 BIT(11)
373 #define SNOR_HWCAPS_READ_1_8_8 BIT(12)
374 #define SNOR_HWCAPS_READ_8_8_8 BIT(13)
375 #define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
378 * Page Program capabilities.
379 * MUST be ordered by priority: the higher bit position, the higher priority.
380 * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
381 * legacy SPI 1-1-1 protocol.
382 * Note that Dual Page Programs are not supported because there is no existing
383 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
384 * implements such commands.
386 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
387 #define SNOR_HWCAPS_PP BIT(16)
389 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
390 #define SNOR_HWCAPS_PP_1_1_4 BIT(17)
391 #define SNOR_HWCAPS_PP_1_4_4 BIT(18)
392 #define SNOR_HWCAPS_PP_4_4_4 BIT(19)
394 #define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
395 #define SNOR_HWCAPS_PP_1_1_8 BIT(20)
396 #define SNOR_HWCAPS_PP_1_8_8 BIT(21)
397 #define SNOR_HWCAPS_PP_8_8_8 BIT(22)
399 #define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
400 SNOR_HWCAPS_READ_4_4_4 | \
401 SNOR_HWCAPS_READ_8_8_8 | \
402 SNOR_HWCAPS_PP_4_4_4 | \
403 SNOR_HWCAPS_PP_8_8_8)
405 #define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
406 SNOR_HWCAPS_READ_1_2_2_DTR | \
407 SNOR_HWCAPS_READ_1_4_4_DTR | \
408 SNOR_HWCAPS_READ_1_8_8_DTR)
410 #define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
413 struct spi_nor_read_command {
417 enum spi_nor_protocol proto;
420 struct spi_nor_pp_command {
422 enum spi_nor_protocol proto;
425 enum spi_nor_read_command_index {
428 SNOR_CMD_READ_1_1_1_DTR,
434 SNOR_CMD_READ_1_2_2_DTR,
440 SNOR_CMD_READ_1_4_4_DTR,
446 SNOR_CMD_READ_1_8_8_DTR,
451 enum spi_nor_pp_command_index {
467 /* Forward declaration that will be used in 'struct spi_nor_flash_parameter' */
471 * struct spi_nor_controller_ops - SPI NOR controller driver specific
473 * @prepare: [OPTIONAL] do some preparations for the
474 * read/write/erase/lock/unlock operations.
475 * @unprepare: [OPTIONAL] do some post work after the
476 * read/write/erase/lock/unlock operations.
477 * @read_reg: read out the register.
478 * @write_reg: write data to the register.
479 * @read: read data from the SPI NOR.
480 * @write: write data to the SPI NOR.
481 * @erase: erase a sector of the SPI NOR at the offset @offs; if
482 * not provided by the driver, spi-nor will send the erase
483 * opcode via write_reg().
485 struct spi_nor_controller_ops {
486 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
487 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
488 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
489 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
492 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
493 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
495 int (*erase)(struct spi_nor *nor, loff_t offs);
499 * struct spi_nor_locking_ops - SPI NOR locking methods
500 * @lock: lock a region of the SPI NOR.
501 * @unlock: unlock a region of the SPI NOR.
502 * @is_locked: check if a region of the SPI NOR is completely locked
504 struct spi_nor_locking_ops {
505 int (*lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
506 int (*unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
507 int (*is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
511 * struct spi_nor_flash_parameter - SPI NOR flash parameters and settings.
512 * Includes legacy flash parameters and settings that can be overwritten
513 * by the spi_nor_fixups hooks, or dynamically when parsing the JESD216
514 * Serial Flash Discoverable Parameters (SFDP) tables.
516 * @size: the flash memory density in bytes.
517 * @page_size: the page size of the SPI NOR flash memory.
518 * @hwcaps: describes the read and page program hardware
520 * @reads: read capabilities ordered by priority: the higher index
521 * in the array, the higher priority.
522 * @page_programs: page program capabilities ordered by priority: the
523 * higher index in the array, the higher priority.
524 * @erase_map: the erase map parsed from the SFDP Sector Map Parameter
526 * @quad_enable: enables SPI NOR quad mode.
527 * @set_4byte: puts the SPI NOR in 4 byte addressing mode.
528 * @convert_addr: converts an absolute address into something the flash
529 * will understand. Particularly useful when pagesize is
531 * @setup: configures the SPI NOR memory. Useful for SPI NOR
532 * flashes that have peculiarities to the SPI NOR standard
533 * e.g. different opcodes, specific address calculation,
535 * @locking_ops: SPI NOR locking methods.
537 struct spi_nor_flash_parameter {
541 struct spi_nor_hwcaps hwcaps;
542 struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
543 struct spi_nor_pp_command page_programs[SNOR_CMD_PP_MAX];
545 struct spi_nor_erase_map erase_map;
547 int (*quad_enable)(struct spi_nor *nor);
548 int (*set_4byte)(struct spi_nor *nor, bool enable);
549 u32 (*convert_addr)(struct spi_nor *nor, u32 addr);
550 int (*setup)(struct spi_nor *nor, const struct spi_nor_hwcaps *hwcaps);
552 const struct spi_nor_locking_ops *locking_ops;
556 * struct flash_info - Forward declaration of a structure used internally by
562 * struct spi_nor - Structure for defining a the SPI NOR layer
563 * @mtd: point to a mtd_info structure
564 * @lock: the lock for the read/write/erase/lock/unlock operations
565 * @dev: point to a spi device, or a spi nor controller device.
566 * @spimem: point to the spi mem device
567 * @bouncebuf: bounce buffer used when the buffer passed by the MTD
568 * layer is not DMA-able
569 * @bouncebuf_size: size of the bounce buffer
570 * @info: spi-nor part JDEC MFR id and other info
571 * @page_size: the page size of the SPI NOR
572 * @addr_width: number of address bytes
573 * @erase_opcode: the opcode for erasing a sector
574 * @read_opcode: the read opcode
575 * @read_dummy: the dummy needed by the read operation
576 * @program_opcode: the program opcode
577 * @sst_write_second: used by the SST write operation
578 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
579 * @read_proto: the SPI protocol for read operations
580 * @write_proto: the SPI protocol for write operations
581 * @reg_proto the SPI protocol for read_reg/write_reg/erase operations
582 * @controller_ops: SPI NOR controller driver specific operations.
583 * @params: [FLASH-SPECIFIC] SPI-NOR flash parameters and settings.
584 * The structure includes legacy flash parameters and
585 * settings that can be overwritten by the spi_nor_fixups
586 * hooks, or dynamically when parsing the SFDP tables.
587 * @priv: the private data
593 struct spi_mem *spimem;
595 size_t bouncebuf_size;
596 const struct flash_info *info;
603 enum spi_nor_protocol read_proto;
604 enum spi_nor_protocol write_proto;
605 enum spi_nor_protocol reg_proto;
606 bool sst_write_second;
609 const struct spi_nor_controller_ops *controller_ops;
611 struct spi_nor_flash_parameter params;
616 static u64 __maybe_unused
617 spi_nor_region_is_last(const struct spi_nor_erase_region *region)
619 return region->offset & SNOR_LAST_REGION;
622 static u64 __maybe_unused
623 spi_nor_region_end(const struct spi_nor_erase_region *region)
625 return (region->offset & ~SNOR_ERASE_FLAGS_MASK) + region->size;
628 static void __maybe_unused
629 spi_nor_region_mark_end(struct spi_nor_erase_region *region)
631 region->offset |= SNOR_LAST_REGION;
634 static void __maybe_unused
635 spi_nor_region_mark_overlay(struct spi_nor_erase_region *region)
637 region->offset |= SNOR_OVERLAID_REGION;
640 static bool __maybe_unused spi_nor_has_uniform_erase(const struct spi_nor *nor)
642 return !!nor->params.erase_map.uniform_erase_type;
645 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
646 struct device_node *np)
648 mtd_set_of_node(&nor->mtd, np);
651 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
653 return mtd_get_of_node(&nor->mtd);
657 * spi_nor_scan() - scan the SPI NOR
658 * @nor: the spi_nor structure
659 * @name: the chip type name
660 * @hwcaps: the hardware capabilities supported by the controller driver
662 * The drivers can use this fuction to scan the SPI NOR.
663 * In the scanning, it will try to get all the necessary information to
664 * fill the mtd_info{} and the spi_nor{}.
666 * The chip type name can be provided through the @name parameter.
668 * Return: 0 for success, others for failure.
670 int spi_nor_scan(struct spi_nor *nor, const char *name,
671 const struct spi_nor_hwcaps *hwcaps);
674 * spi_nor_restore_addr_mode() - restore the status of SPI NOR
675 * @nor: the spi_nor structure
677 void spi_nor_restore(struct spi_nor *nor);